1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "mvs_if.h" 30 31/* Chip registers */ 32#define CHIP_PCIEIC 0x1900 /* PCIe Interrupt Cause */ 33#define CHIP_PCIEIM 0x1910 /* PCIe Interrupt Mask */ 34#define CHIP_PCIIC 0x1d58 /* PCI Interrupt Cause */ 35#define CHIP_PCIIM 0x1d5c /* PCI Interrupt Mask */ 36#define CHIP_MIC 0x1d60 /* Main Interrupt Cause */ 37#define CHIP_MIM 0x1d64 /* Main Interrupt Mask */ 38#define CHIP_SOC_MIC 0x20 /* SoC Main Interrupt Cause */ 39#define CHIP_SOC_MIM 0x24 /* SoC Main Interrupt Mask */ 40#define IC_ERR_IRQ (1 << 0) /* shift by (2 * port #) */ 41#define IC_DONE_IRQ (1 << 1) /* shift by (2 * port #) */ 42#define IC_HC0 0x000001ff /* bits 0-8 = HC0 */ 43#define IC_HC_SHIFT 9 /* HC1 shift */ 44#define IC_HC1 (IC_HC0 << IC_HC_SHIFT) /* 9-17 = HC1 */ 45#define IC_ERR_HC0 0x00000055 /* HC0 ERR_IRQ */ 46#define IC_DONE_HC0 0x000000aa /* HC0 DONE_IRQ */ 47#define IC_ERR_HC1 (IC_ERR_HC0 << IC_HC_SHIFT) /* HC1 ERR_IRQ */ 48#define IC_DONE_HC1 (IC_DONE_HC0 << IC_HC_SHIFT) /* HC1 DONE_IRQ */ 49#define IC_HC0_COAL_DONE (1 << 8) /* HC0 IRQ coalescing */ 50#define IC_HC1_COAL_DONE (1 << 17) /* HC1 IRQ coalescing */ 51#define IC_PCI_ERR (1 << 18) 52#define IC_TRAN_COAL_LO_DONE (1 << 19) /* transaction coalescing */ 53#define IC_TRAN_COAL_HI_DONE (1 << 20) /* transaction coalescing */ 54#define IC_ALL_PORTS_COAL_DONE (1 << 21) /* GEN_II(E) IRQ coalescing */ 55#define IC_GPIO_INT (1 << 22) 56#define IC_SELF_INT (1 << 23) 57#define IC_TWSI_INT (1 << 24) 58#define IC_MAIN_RSVD (0xfe000000) /* bits 31-25 */ 59#define IC_MAIN_RSVD_5 (0xfff10000) /* bits 31-19 */ 60#define IC_MAIN_RSVD_SOC (0xfffffec0) /* bits 31-9, 7-6 */ 61 62#define CHIP_SOC_LED 0x2C /* SoC LED Configuration */ 63 64/* Additional mask for SoC devices with less than 4 channels */ 65#define CHIP_SOC_HC0_MASK(num) (0xff >> ((4 - (num)) * 2)) 66 67/* Chip CCC registers */ 68#define CHIP_ICC 0x18008 69#define CHIP_ICC_ALL_PORTS (1 << 4) /* all ports irq event */ 70#define CHIP_ICT 0x180cc 71#define CHIP_ITT 0x180d0 72#define CHIP_TRAN_COAL_CAUSE_LO 0x18088 73#define CHIP_TRAN_COAL_CAUSE_HI 0x1808c 74 75/* Host Controller registers */ 76#define HC_SIZE 0x10000 77#define HC_OFFSET 0x20000 78#define HC_BASE(hc) ((hc) * HC_SIZE + HC_OFFSET) 79 80#define HC_CFG 0x0 /* Configuration */ 81#define HC_CFG_TIMEOUT_MASK (0xff << 0) 82#define HC_CFG_NODMABS (1 << 8) 83#define HC_CFG_NOEDMABS (1 << 9) 84#define HC_CFG_NOPRDBS (1 << 10) 85#define HC_CFG_TIMEOUTEN (1 << 16) /* Timer Enable */ 86#define HC_CFG_COALDIS(p) (1 << ((p) + 24))/* Coalescing Disable*/ 87#define HC_RQOP 0x4 /* Request Queue Out-Pointer */ 88#define HC_RQIP 0x8 /* Response Queue In-Pointer */ 89#define HC_ICT 0xc /* Interrupt Coalescing Threshold */ 90#define HC_ICT_SAICOALT_MASK 0x000000ff 91#define HC_ITT 0x10 /* Interrupt Time Threshold */ 92#define HC_ITT_SAITMTH_MASK 0x00ffffff 93#define HC_IC 0x14 /* Interrupt Cause */ 94#define HC_IC_DONE(p) (1 << (p)) /* SaCrpb/DMA Done */ 95#define HC_IC_COAL (1 << 4) /* Intr Coalescing */ 96#define HC_IC_DEV(p) (1 << ((p) + 8)) /* Device Intr */ 97 98/* Port registers */ 99#define PORT_SIZE 0x2000 100#define PORT_OFFSET 0x2000 101#define PORT_BASE(hc) ((hc) * PORT_SIZE + PORT_OFFSET) 102 103#define EDMA_CFG 0x0 /* Configuration */ 104#define EDMA_CFG_RESERVED (0x1f << 0) /* Queue len ? */ 105#define EDMA_CFG_ESATANATVCMDQUE (1 << 5) 106#define EDMA_CFG_ERDBSZ (1 << 8) 107#define EDMA_CFG_EQUE (1 << 9) 108#define EDMA_CFG_ERDBSZEXT (1 << 11) 109#define EDMA_CFG_RESERVED2 (1 << 12) 110#define EDMA_CFG_EWRBUFFERLEN (1 << 13) 111#define EDMA_CFG_EDEVERR (1 << 14) 112#define EDMA_CFG_EEDMAFBS (1 << 16) 113#define EDMA_CFG_ECUTTHROUGHEN (1 << 17) 114#define EDMA_CFG_EEARLYCOMPLETIONEN (1 << 18) 115#define EDMA_CFG_EEDMAQUELEN (1 << 19) 116#define EDMA_CFG_EHOSTQUEUECACHEEN (1 << 22) 117#define EDMA_CFG_EMASKRXPM (1 << 23) 118#define EDMA_CFG_RESUMEDIS (1 << 24) 119#define EDMA_CFG_EDMAFBS (1 << 26) 120#define EDMA_T 0x4 /* Timer */ 121#define EDMA_IEC 0x8 /* Interrupt Error Cause */ 122#define EDMA_IEM 0xc /* Interrupt Error Mask */ 123#define EDMA_IE_EDEVERR (1 << 2) /* EDMA Device Error */ 124#define EDMA_IE_EDEVDIS (1 << 3) /* EDMA Dev Disconn */ 125#define EDMA_IE_EDEVCON (1 << 4) /* EDMA Dev Conn */ 126#define EDMA_IE_SERRINT (1 << 5) 127#define EDMA_IE_ESELFDIS (1 << 7) /* EDMA Self Disable */ 128#define EDMA_IE_ETRANSINT (1 << 8) /* Transport Layer */ 129#define EDMA_IE_EIORDYERR (1 << 12) /* EDMA IORdy Error */ 130#define EDMA_IE_LINKXERR_SATACRC (1 << 0) /* SATA CRC error */ 131#define EDMA_IE_LINKXERR_INTERNALFIFO (1 << 1) /* internal FIFO err */ 132#define EDMA_IE_LINKXERR_LINKLAYERRESET (1 << 2) 133 /* Link Layer is reset by the reception of SYNC primitive from device */ 134#define EDMA_IE_LINKXERR_OTHERERRORS (1 << 3) 135 /* 136 * Link state errors, coding errors, or running disparity errors occur 137 * during FIS reception. 138 */ 139#define EDMA_IE_LINKTXERR_FISTXABORTED (1 << 4) /* FIS Tx is aborted */ 140#define EDMA_IE_LINKCTLRXERR(x) ((x) << 13) /* Link Ctrl Recv Err */ 141#define EDMA_IE_LINKDATARXERR(x) ((x) << 17) /* Link Data Recv Err */ 142#define EDMA_IE_LINKCTLTXERR(x) ((x) << 21) /* Link Ctrl Tx Error */ 143#define EDMA_IE_LINKDATATXERR(x) ((x) << 26) /* Link Data Tx Error */ 144#define EDMA_IE_TRANSPROTERR (1U << 31) /* Transport Proto E */ 145#define EDMA_IE_TRANSIENT (EDMA_IE_LINKCTLRXERR(0x0b) | \ 146 EDMA_IE_LINKCTLTXERR(0x1f)) 147 /* Non-fatal Errors */ 148#define EDMA_REQQBAH 0x10 /* Request Queue Base Address High */ 149#define EDMA_REQQIP 0x14 /* Request Queue In-Pointer */ 150#define EDMA_REQQOP 0x18 /* Request Queue Out-Pointer */ 151#define EDMA_REQQP_ERQQP_SHIFT 5 152#define EDMA_REQQP_ERQQP_MASK 0x000003e0 153#define EDMA_REQQP_ERQQBAP_MASK 0x00000c00 154#define EDMA_REQQP_ERQQBA_MASK 0xfffff000 155#define EDMA_RESQBAH 0x1c /* Response Queue Base Address High */ 156#define EDMA_RESQIP 0x20 /* Response Queue In-Pointer */ 157#define EDMA_RESQOP 0x24 /* Response Queue Out-Pointer */ 158#define EDMA_RESQP_ERPQP_SHIFT 3 159#define EDMA_RESQP_ERPQP_MASK 0x000000f8 160#define EDMA_RESQP_ERPQBAP_MASK 0x00000300 161#define EDMA_RESQP_ERPQBA_MASK 0xfffffc00 162#define EDMA_CMD 0x28 /* Command */ 163#define EDMA_CMD_EENEDMA (1 << 0) /* Enable EDMA */ 164#define EDMA_CMD_EDSEDMA (1 << 1) /* Disable EDMA */ 165#define EDMA_CMD_EATARST (1 << 2) /* ATA Device Reset */ 166#define EDMA_CMD_EEDMAFRZ (1 << 4) /* EDMA Freeze */ 167#define EDMA_TC 0x2c /* Test Control */ 168#define EDMA_S 0x30 /* Status */ 169#define EDMA_S_EDEVQUETAG(s) ((s) & 0x0000001f) 170#define EDMA_S_EDEVDIR_WRITE (0 << 5) 171#define EDMA_S_EDEVDIR_READ (1 << 5) 172#define EDMA_S_ECACHEEMPTY (1 << 6) 173#define EDMA_S_EDMAIDLE (1 << 7) 174#define EDMA_S_ESTATE(s) (((s) & 0x0000ff00) >> 8) 175#define EDMA_S_EIOID(s) (((s) & 0x003f0000) >> 16) 176#define EDMA_IORT 0x34 /* IORdy Timeout */ 177#define EDMA_CDT 0x40 /* Command Delay Threshold */ 178#define EDMA_HC 0x60 /* Halt Condition */ 179#define EDMA_UNKN_RESD 0x6C /* Unknown register */ 180#define EDMA_CQDCQOS(x) (0x90 + ((x) << 2) 181 /* NCQ Done/TCQ Outstanding Status */ 182 183/* ATA register defines */ 184#define ATA_DATA 0x100 /* (RW) data */ 185#define ATA_FEATURE 0x104 /* (W) feature */ 186#define ATA_F_DMA 0x01 /* enable DMA */ 187#define ATA_F_OVL 0x02 /* enable overlap */ 188#define ATA_ERROR 0x104 /* (R) error */ 189#define ATA_E_ILI 0x01 /* illegal length */ 190#define ATA_E_NM 0x02 /* no media */ 191#define ATA_E_ABORT 0x04 /* command aborted */ 192#define ATA_E_MCR 0x08 /* media change request */ 193#define ATA_E_IDNF 0x10 /* ID not found */ 194#define ATA_E_MC 0x20 /* media changed */ 195#define ATA_E_UNC 0x40 /* uncorrectable data */ 196#define ATA_E_ICRC 0x80 /* UDMA crc error */ 197#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 198#define ATA_COUNT 0x108 /* (W) sector count */ 199#define ATA_IREASON 0x108 /* (R) interrupt reason */ 200#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 201#define ATA_I_IN 0x02 /* read (1) | write (0) */ 202#define ATA_I_RELEASE 0x04 /* released bus (1) */ 203#define ATA_I_TAGMASK 0xf8 /* tag mask */ 204#define ATA_SECTOR 0x10c /* (RW) sector # */ 205#define ATA_CYL_LSB 0x110 /* (RW) cylinder# LSB */ 206#define ATA_CYL_MSB 0x114 /* (RW) cylinder# MSB */ 207#define ATA_DRIVE 0x118 /* (W) Sector/Drive/Head */ 208#define ATA_D_LBA 0x40 /* use LBA addressing */ 209#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 210#define ATA_COMMAND 0x11c /* (W) command */ 211#define ATA_STATUS 0x11c /* (R) status */ 212#define ATA_S_ERROR 0x01 /* error */ 213#define ATA_S_INDEX 0x02 /* index */ 214#define ATA_S_CORR 0x04 /* data corrected */ 215#define ATA_S_DRQ 0x08 /* data request */ 216#define ATA_S_DSC 0x10 /* drive seek completed */ 217#define ATA_S_SERVICE 0x10 /* drive needs service */ 218#define ATA_S_DWF 0x20 /* drive write fault */ 219#define ATA_S_DMA 0x20 /* DMA ready */ 220#define ATA_S_READY 0x40 /* drive ready */ 221#define ATA_S_BUSY 0x80 /* busy */ 222#define ATA_CONTROL 0x120 /* (W) control */ 223#define ATA_A_IDS 0x02 /* disable interrupts */ 224#define ATA_A_RESET 0x04 /* RESET controller */ 225#define ATA_A_4BIT 0x08 /* 4 head bits */ 226#define ATA_A_HOB 0x80 /* High Order Byte enable */ 227#define ATA_ALTSTAT 0x120 /* (R) alternate status */ 228#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 229#define ATAPI_P_WRITE (ATA_S_DRQ) 230#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 231#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 232#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 233#define ATAPI_P_ABORT 0 234 235/* Basic DMA Registers */ 236#define DMA_C 0x224 /* Basic DMA Command */ 237#define DMA_C_START (1 << 0) 238#define DMA_C_READ (1 << 3) 239#define DMA_C_DREGIONVALID (1 << 8) 240#define DMA_C_DREGIONLAST (1 << 9) 241#define DMA_C_CONTFROMPREV (1 << 10) 242#define DMA_C_DRBC(n) (((n) & 0xffff) << 16) 243#define DMA_S 0x228 /* Basic DMA Status */ 244#define DMA_S_ACT (1 << 0) /* Active */ 245#define DMA_S_ERR (1 << 1) /* Error */ 246#define DMA_S_PAUSED (1 << 2) /* Paused */ 247#define DMA_S_LAST (1 << 3) /* Last */ 248#define DMA_DTLBA 0x22c /* Descriptor Table Low Base Address */ 249#define DMA_DTLBA_MASK 0xfffffff0 250#define DMA_DTHBA 0x230 /* Descriptor Table High Base Address */ 251#define DMA_DRLA 0x234 /* Data Region Low Address */ 252#define DMA_DRHA 0x238 /* Data Region High Address */ 253 254/* Serial-ATA Registers */ 255#define SATA_SS 0x300 /* SStatus */ 256#define SATA_SS_DET_MASK 0x0000000f 257#define SATA_SS_DET_NO_DEVICE 0x00000000 258#define SATA_SS_DET_DEV_PRESENT 0x00000001 259#define SATA_SS_DET_PHY_ONLINE 0x00000003 260#define SATA_SS_DET_PHY_OFFLINE 0x00000004 261 262#define SATA_SS_SPD_MASK 0x000000f0 263#define SATA_SS_SPD_NO_SPEED 0x00000000 264#define SATA_SS_SPD_GEN1 0x00000010 265#define SATA_SS_SPD_GEN2 0x00000020 266#define SATA_SS_SPD_GEN3 0x00000030 267 268#define SATA_SS_IPM_MASK 0x00000f00 269#define SATA_SS_IPM_NO_DEVICE 0x00000000 270#define SATA_SS_IPM_ACTIVE 0x00000100 271#define SATA_SS_IPM_PARTIAL 0x00000200 272#define SATA_SS_IPM_SLUMBER 0x00000600 273#define SATA_SE 0x304 /* SError */ 274#define SATA_SEIM 0x340 /* SError Interrupt Mask */ 275#define SATA_SE_DATA_CORRECTED 0x00000001 276#define SATA_SE_COMM_CORRECTED 0x00000002 277#define SATA_SE_DATA_ERR 0x00000100 278#define SATA_SE_COMM_ERR 0x00000200 279#define SATA_SE_PROT_ERR 0x00000400 280#define SATA_SE_HOST_ERR 0x00000800 281#define SATA_SE_PHY_CHANGED 0x00010000 282#define SATA_SE_PHY_IERROR 0x00020000 283#define SATA_SE_COMM_WAKE 0x00040000 284#define SATA_SE_DECODE_ERR 0x00080000 285#define SATA_SE_PARITY_ERR 0x00100000 286#define SATA_SE_CRC_ERR 0x00200000 287#define SATA_SE_HANDSHAKE_ERR 0x00400000 288#define SATA_SE_LINKSEQ_ERR 0x00800000 289#define SATA_SE_TRANSPORT_ERR 0x01000000 290#define SATA_SE_UNKNOWN_FIS 0x02000000 291#define SATA_SC 0x308 /* SControl */ 292#define SATA_SC_DET_MASK 0x0000000f 293#define SATA_SC_DET_IDLE 0x00000000 294#define SATA_SC_DET_RESET 0x00000001 295#define SATA_SC_DET_DISABLE 0x00000004 296 297#define SATA_SC_SPD_MASK 0x000000f0 298#define SATA_SC_SPD_NO_SPEED 0x00000000 299#define SATA_SC_SPD_SPEED_GEN1 0x00000010 300#define SATA_SC_SPD_SPEED_GEN2 0x00000020 301#define SATA_SC_SPD_SPEED_GEN3 0x00000030 302 303#define SATA_SC_IPM_MASK 0x00000f00 304#define SATA_SC_IPM_NONE 0x00000000 305#define SATA_SC_IPM_DIS_PARTIAL 0x00000100 306#define SATA_SC_IPM_DIS_SLUMBER 0x00000200 307 308#define SATA_SC_SPM_MASK 0x0000f000 309#define SATA_SC_SPM_NONE 0x00000000 310#define SATA_SC_SPM_PARTIAL 0x00001000 311#define SATA_SC_SPM_SLUMBER 0x00002000 312#define SATA_SC_SPM_ACTIVE 0x00004000 313#define SATA_LTM 0x30c /* LTMode */ 314#define SATA_PHYM3 0x310 /* PHY Mode 3 */ 315#define SATA_PHYM4 0x314 /* PHY Mode 4 */ 316#define SATA_PHYM1 0x32c /* PHY Mode 1 */ 317#define SATA_PHYM2 0x330 /* PHY Mode 2 */ 318#define SATA_BISTC 0x334 /* BIST Control */ 319#define SATA_BISTDW1 0x338 /* BIST DW1 */ 320#define SATA_BISTDW2 0x33c /* BIST DW2 */ 321#define SATA_SATAICFG 0x050 /* Serial-ATA Interface Configuration */ 322#define SATA_SATAICFG_REFCLKCNF_20MHZ (0 << 0) 323#define SATA_SATAICFG_REFCLKCNF_25MHZ (1 << 0) 324#define SATA_SATAICFG_REFCLKCNF_30MHZ (2 << 0) 325#define SATA_SATAICFG_REFCLKCNF_40MHZ (3 << 0) 326#define SATA_SATAICFG_REFCLKCNF_MASK (3 << 0) 327#define SATA_SATAICFG_REFCLKDIV_1 (0 << 2) 328#define SATA_SATAICFG_REFCLKDIV_2 (1 << 2) /* Used 20 or 25MHz */ 329#define SATA_SATAICFG_REFCLKDIV_4 (2 << 2) /* Used 40MHz */ 330#define SATA_SATAICFG_REFCLKDIV_3 (3 << 2) /* Used 30MHz */ 331#define SATA_SATAICFG_REFCLKDIV_MASK (3 << 2) 332#define SATA_SATAICFG_REFCLKFEEDDIV_50 (0 << 4) /* or 100, when Gen2En is 1 */ 333#define SATA_SATAICFG_REFCLKFEEDDIV_60 (1 << 4) /* or 120. Used 25MHz */ 334#define SATA_SATAICFG_REFCLKFEEDDIV_75 (2 << 4) /* or 150. Used 20MHz */ 335#define SATA_SATAICFG_REFCLKFEEDDIV_90 (3 << 4) /* or 180 */ 336#define SATA_SATAICFG_REFCLKFEEDDIV_MASK (3 << 4) 337#define SATA_SATAICFG_PHYSSCEN (1 << 6) 338#define SATA_SATAICFG_GEN2EN (1 << 7) 339#define SATA_SATAICFG_COMMEN (1 << 8) 340#define SATA_SATAICFG_PHYSHUTDOWN (1 << 9) 341#define SATA_SATAICFG_TARGETMODE (1 << 10) /* 1 = Initiator */ 342#define SATA_SATAICFG_COMCHANNEL (1 << 11) 343#define SATA_SATAICFG_IGNOREBSY (1 << 24) 344#define SATA_SATAICFG_LINKRSTEN (1 << 25) 345#define SATA_SATAICFG_CMDRETXDS (1 << 26) 346#define SATA_SATAICTL 0x344 /* Serial-ATA Interface Control */ 347#define SATA_SATAICTL_PMPTX_MASK 0x0000000f 348#define SATA_SATAICTL_PMPTX_SHIFT 0 349#define SATA_SATAICTL_VUM (1 << 8) 350#define SATA_SATAICTL_VUS (1 << 9) 351#define SATA_SATAICTL_EDMAACT (1 << 16) 352#define SATA_SATAICTL_CLEARSTAT (1 << 24) 353#define SATA_SATAICTL_SRST (1 << 25) 354#define SATA_SATAITC 0x348 /* Serial-ATA Interface Test Control */ 355#define SATA_SATAIS 0x34c /* Serial-ATA Interface Status */ 356#define SATA_VU 0x35c /* Vendor Unique */ 357#define SATA_FISC 0x360 /* FIS Configuration */ 358#define SATA_FISC_FISWAIT4RDYEN_B0 (1 << 0) /* Device to Host FIS */ 359#define SATA_FISC_FISWAIT4RDYEN_B1 (1 << 1) /* SDB FIS rcv with <N>bit 0 */ 360#define SATA_FISC_FISWAIT4RDYEN_B2 (1 << 2) /* DMA Activate FIS */ 361#define SATA_FISC_FISWAIT4RDYEN_B3 (1 << 3) /* DMA Setup FIS */ 362#define SATA_FISC_FISWAIT4RDYEN_B4 (1 << 4) /* Data FIS first DW */ 363#define SATA_FISC_FISWAIT4RDYEN_B5 (1 << 5) /* Data FIS entire FIS */ 364#define SATA_FISC_FISWAIT4HOSTRDYEN_B0 (1 << 8) 365 /* Device to Host FIS with <ERR> or <DF> */ 366#define SATA_FISC_FISWAIT4HOSTRDYEN_B1 (1 << 9) /* SDB FIS rcv with <N>bit */ 367#define SATA_FISC_FISWAIT4HOSTRDYEN_B2 (1 << 10) /* SDB FIS rcv with <ERR> */ 368#define SATA_FISC_FISWAIT4HOSTRDYEN_B3 (1 << 11) /* BIST Acivate FIS */ 369#define SATA_FISC_FISWAIT4HOSTRDYEN_B4 (1 << 12) /* PIO Setup FIS */ 370#define SATA_FISC_FISWAIT4HOSTRDYEN_B5 (1 << 13) /* Data FIS with Link error */ 371#define SATA_FISC_FISWAIT4HOSTRDYEN_B6 (1 << 14) /* Unrecognized FIS type */ 372#define SATA_FISC_FISWAIT4HOSTRDYEN_B7 (1 << 15) /* Any FIS */ 373#define SATA_FISC_FISDMAACTIVATESYNCRESP (1 << 16) 374#define SATA_FISC_FISUNRECTYPECONT (1 << 17) 375#define SATA_FISIC 0x364 /* FIS Interrupt Cause */ 376#define SATA_FISIM 0x368 /* FIS Interrupt Mask */ 377#define SATA_FISDW0 0x370 /* FIS DW0 */ 378#define SATA_FISDW1 0x374 /* FIS DW1 */ 379#define SATA_FISDW2 0x378 /* FIS DW2 */ 380#define SATA_FISDW3 0x37c /* FIS DW3 */ 381#define SATA_FISDW4 0x380 /* FIS DW4 */ 382#define SATA_FISDW5 0x384 /* FIS DW5 */ 383#define SATA_FISDW6 0x388 /* FIS DW6 */ 384 385#define SATA_PHYM9_GEN2 0x398 386#define SATA_PHYM9_GEN1 0x39c 387#define SATA_PHYCFG_OFS 0x3a0 /* 65nm SoCs only */ 388 389#define MVS_MAX_PORTS 8 390#define MVS_MAX_SLOTS 32 391 392/* Pessimistic prognosis on number of required S/G entries */ 393#define MVS_SG_ENTRIES (btoc(maxphys) + 1) 394 395/* EDMA Command Request Block (CRQB) Data */ 396struct mvs_crqb { 397 uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */ 398 uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */ 399 uint16_t ctrlflg; /* Control Flags */ 400#define MVS_CRQB_READ 0x0001 401#define MVS_CRQB_TAG_MASK 0x003e 402#define MVS_CRQB_TAG_SHIFT 1 403#define MVS_CRQB_PMP_MASK 0xf000 404#define MVS_CRQB_PMP_SHIFT 12 405 uint8_t cmd[22]; 406} __packed; 407 408struct mvs_crqb_gen2e { 409 uint32_t cprdbl; /* cPRD Desriptor Table Base Low Address */ 410 uint32_t cprdbh; /* cPRD Desriptor Table Base High Address */ 411 uint32_t ctrlflg; /* Control Flags */ 412#define MVS_CRQB2E_READ 0x00000001 413#define MVS_CRQB2E_DTAG_MASK 0x0000003e 414#define MVS_CRQB2E_DTAG_SHIFT 1 415#define MVS_CRQB2E_PMP_MASK 0x0000f000 416#define MVS_CRQB2E_PMP_SHIFT 12 417#define MVS_CRQB2E_CPRD 0x00010000 418#define MVS_CRQB2E_HTAG_MASK 0x003e0000 419#define MVS_CRQB2E_HTAG_SHIFT 17 420 uint32_t drbc; /* Data Region Byte Count */ 421 uint8_t cmd[16]; 422} __packed; 423 424/* EDMA Phisical Region Descriptors (ePRD) Table Data Structure */ 425struct mvs_eprd { 426 uint32_t prdbal; /* Address bits[31:1] */ 427 uint32_t bytecount; /* Byte Count */ 428#define MVS_EPRD_MASK 0x0000ffff /* max 64KB */ 429#define MVS_EPRD_MAX (MVS_EPRD_MASK + 1) 430#define MVS_EPRD_EOF 0x80000000 431 uint32_t prdbah; /* Address bits[63:32] */ 432 uint32_t resv; 433} __packed; 434 435/* Command request blocks. 32 commands. First 1Kbyte aligned. */ 436#define MVS_CRQB_OFFSET 0 437#define MVS_CRQB_SIZE 32 /* sizeof(struct mvs_crqb) */ 438#define MVS_CRQB_MASK 0x000003e0 439#define MVS_CRQB_SHIFT 5 440#define MVS_CRQB_TO_ADDR(slot) ((slot) << MVS_CRQB_SHIFT) 441#define MVS_ADDR_TO_CRQB(addr) (((addr) & MVS_CRQB_MASK) >> MVS_CRQB_SHIFT) 442/* ePRD blocks. Up to 32 commands, Each 16byte aligned. */ 443#define MVS_EPRD_OFFSET (MVS_CRQB_OFFSET + MVS_CRQB_SIZE * MVS_MAX_SLOTS) 444#define MVS_EPRD_SIZE (MVS_SG_ENTRIES * 16) /* sizeof(struct mvs_eprd) */ 445/* Request work area. */ 446#define MVS_WORKRQ_SIZE (MVS_EPRD_OFFSET + MVS_EPRD_SIZE * MVS_MAX_SLOTS) 447 448/* EDMA Command Response Block (CRPB) Data */ 449struct mvs_crpb { 450 uint16_t id; /* CRPB ID */ 451#define MVS_CRPB_TAG_MASK 0x001F 452#define MVS_CRPB_TAG_SHIFT 0 453 uint16_t rspflg; /* CPRB Response Flags */ 454#define MVS_CRPB_EDMASTS_MASK 0x007F 455#define MVS_CRPB_EDMASTS_SHIFT 0 456#define MVS_CRPB_ATASTS_MASK 0xFF00 457#define MVS_CRPB_ATASTS_SHIFT 8 458 uint32_t ts; /* CPRB Time Stamp */ 459} __packed; 460 461/* Command response blocks. 32 commands. First 256byte aligned. */ 462#define MVS_CRPB_OFFSET 0 463#define MVS_CRPB_SIZE sizeof(struct mvs_crpb) 464#define MVS_CRPB_MASK 0x000000f8 465#define MVS_CRPB_SHIFT 3 466#define MVS_CRPB_TO_ADDR(slot) ((slot) << MVS_CRPB_SHIFT) 467#define MVS_ADDR_TO_CRPB(addr) (((addr) & MVS_CRPB_MASK) >> MVS_CRPB_SHIFT) 468/* Request work area. */ 469#define MVS_WORKRP_SIZE (MVS_CRPB_OFFSET + MVS_CRPB_SIZE * MVS_MAX_SLOTS) 470 471/* misc defines */ 472#define ATA_IRQ_RID 0 473#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 474 475struct ata_dmaslot { 476 bus_dmamap_t data_map; /* Data DMA map */ 477 bus_addr_t addr; /* Data address */ 478 uint16_t len; /* Data size */ 479}; 480 481/* structure holding DMA related information */ 482struct mvs_dma { 483 bus_dma_tag_t workrq_tag; /* Request workspace DMA tag */ 484 bus_dmamap_t workrq_map; /* Request workspace DMA map */ 485 uint8_t *workrq; /* Request workspace */ 486 bus_addr_t workrq_bus; /* Request bus address */ 487 bus_dma_tag_t workrp_tag; /* Reply workspace DMA tag */ 488 bus_dmamap_t workrp_map; /* Reply workspace DMA map */ 489 uint8_t *workrp; /* Reply workspace */ 490 bus_addr_t workrp_bus; /* Reply bus address */ 491 bus_dma_tag_t data_tag; /* Data DMA tag */ 492}; 493 494enum mvs_slot_states { 495 MVS_SLOT_EMPTY, 496 MVS_SLOT_LOADING, 497 MVS_SLOT_RUNNING, 498 MVS_SLOT_EXECUTING 499}; 500 501struct mvs_slot { 502 device_t dev; /* Device handle */ 503 int slot; /* Number of this slot */ 504 int tag; /* Used command tag */ 505 enum mvs_slot_states state; /* Slot state */ 506 u_int eprd_offset; /* EPRD offset */ 507 union ccb *ccb; /* CCB occupying slot */ 508 struct ata_dmaslot dma; /* DMA data of this slot */ 509 struct callout timeout; /* Execution timeout */ 510}; 511 512struct mvs_device { 513 int revision; 514 int mode; 515 u_int bytecount; 516 u_int atapi; 517 u_int tags; 518 u_int caps; 519}; 520 521enum mvs_edma_mode { 522 MVS_EDMA_UNKNOWN, 523 MVS_EDMA_OFF, 524 MVS_EDMA_ON, 525 MVS_EDMA_QUEUED, 526 MVS_EDMA_NCQ, 527}; 528 529/* structure describing an ATA channel */ 530struct mvs_channel { 531 device_t dev; /* Device handle */ 532 int unit; /* Physical channel */ 533 struct resource *r_mem; /* Memory of this channel */ 534 struct resource *r_irq; /* Interrupt of this channel */ 535 void *ih; /* Interrupt handle */ 536 struct mvs_dma dma; /* DMA data */ 537 struct cam_sim *sim; 538 struct cam_path *path; 539 int quirks; 540#define MVS_Q_GENI 1 541#define MVS_Q_GENII 2 542#define MVS_Q_GENIIE 4 543#define MVS_Q_SOC 8 544#define MVS_Q_CT 16 545#define MVS_Q_SOC65 32 546 int pm_level; /* power management level */ 547 548 struct mvs_slot slot[MVS_MAX_SLOTS]; 549 union ccb *hold[MVS_MAX_SLOTS]; 550 int holdtag[MVS_MAX_SLOTS]; /* Tags used for held commands. */ 551 struct mtx mtx; /* state lock */ 552 int devices; /* What is present */ 553 int pm_present; /* PM presence reported */ 554 enum mvs_edma_mode curr_mode; /* Current EDMA mode */ 555 int fbs_enabled; /* FIS-based switching enabled */ 556 uint32_t oslots; /* Occupied slots */ 557 uint32_t otagspd[16]; /* Occupied device tags */ 558 uint32_t rslots; /* Running slots */ 559 uint32_t aslots; /* Slots with atomic commands */ 560 uint32_t eslots; /* Slots in error */ 561 uint32_t toslots; /* Slots in timeout */ 562 int numrslots; /* Number of running slots */ 563 int numrslotspd[16];/* Number of running slots per dev */ 564 int numpslots; /* Number of PIO slots */ 565 int numdslots; /* Number of DMA slots */ 566 int numtslots; /* Number of NCQ slots */ 567 int numtslotspd[16];/* Number of NCQ slots per dev */ 568 int numhslots; /* Number of held slots */ 569 int recoverycmd; /* Our READ LOG active */ 570 int fatalerr; /* Fatal error happened */ 571 int lastslot; /* Last used slot */ 572 int taggedtarget; /* Last tagged target */ 573 int resetting; /* Hard-reset in progress. */ 574 int resetpolldiv; /* Hard-reset poll divider. */ 575 int out_idx; /* Next written CRQB */ 576 int in_idx; /* Next read CRPB */ 577 u_int transfersize; /* PIO transfer size */ 578 u_int donecount; /* PIO bytes sent/received */ 579 u_int basic_dma; /* Basic DMA used for ATAPI */ 580 u_int fake_busy; /* Fake busy bit after command submission */ 581 union ccb *frozen; /* Frozen command */ 582 struct callout pm_timer; /* Power management events */ 583 struct callout reset_timer; /* Hard-reset timeout */ 584 585 struct mvs_device user[16]; /* User-specified settings */ 586 struct mvs_device curr[16]; /* Current settings */ 587}; 588 589/* structure describing a MVS controller */ 590struct mvs_controller { 591 device_t dev; 592 int r_rid; 593 struct resource *r_mem; 594 struct rman sc_iomem; 595 struct mvs_controller_irq { 596 struct resource *r_irq; 597 void *handle; 598 int r_irq_rid; 599 } irq; 600 int quirks; 601 int channels; 602 int ccc; /* CCC timeout */ 603 int cccc; /* CCC commands */ 604 struct mtx mtx; /* MIM access lock */ 605 int gmim; /* Globally wanted MIM bits */ 606 int pmim; /* Port wanted MIM bits */ 607 int mim; /* Current MIM bits */ 608 int msi; /* MSI enabled */ 609 int msia; /* MSI active */ 610 struct { 611 void (*function)(void *); 612 void *argument; 613 } interrupt[MVS_MAX_PORTS]; 614}; 615 616enum mvs_err_type { 617 MVS_ERR_NONE, /* No error */ 618 MVS_ERR_INVALID, /* Error detected by us before submitting. */ 619 MVS_ERR_INNOCENT, /* Innocent victim. */ 620 MVS_ERR_TFE, /* Task File Error. */ 621 MVS_ERR_SATA, /* SATA error. */ 622 MVS_ERR_TIMEOUT, /* Command execution timeout. */ 623 MVS_ERR_NCQ, /* NCQ command error. CCB should be put on hold 624 * until READ LOG executed to reveal error. */ 625}; 626 627struct mvs_intr_arg { 628 void *arg; 629 u_int cause; 630}; 631 632/* macros to hide busspace uglyness */ 633#define ATA_INB(res, offset) \ 634 bus_read_1((res), (offset)) 635#define ATA_INW(res, offset) \ 636 bus_read_2((res), (offset)) 637#define ATA_INL(res, offset) \ 638 bus_read_4((res), (offset)) 639#define ATA_INSW(res, offset, addr, count) \ 640 bus_read_multi_2((res), (offset), (addr), (count)) 641#define ATA_INSW_STRM(res, offset, addr, count) \ 642 bus_read_multi_stream_2((res), (offset), (addr), (count)) 643#define ATA_INSL(res, offset, addr, count) \ 644 bus_read_multi_4((res), (offset), (addr), (count)) 645#define ATA_INSL_STRM(res, offset, addr, count) \ 646 bus_read_multi_stream_4((res), (offset), (addr), (count)) 647#define ATA_OUTB(res, offset, value) \ 648 bus_write_1((res), (offset), (value)) 649#define ATA_OUTW(res, offset, value) \ 650 bus_write_2((res), (offset), (value)) 651#define ATA_OUTL(res, offset, value) \ 652 bus_write_4((res), (offset), (value)); 653#define ATA_OUTSW(res, offset, addr, count) \ 654 bus_write_multi_2((res), (offset), (addr), (count)) 655#define ATA_OUTSW_STRM(res, offset, addr, count) \ 656 bus_write_multi_stream_2((res), (offset), (addr), (count)) 657#define ATA_OUTSL(res, offset, addr, count) \ 658 bus_write_multi_4((res), (offset), (addr), (count)) 659#define ATA_OUTSL_STRM(res, offset, addr, count) \ 660 bus_write_multi_stream_4((res), (offset), (addr), (count)) 661