1/****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11/****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48/*- 49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50 * 51 * Copyright (c) 1997, 1998, 1999, 2000 52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Bill Paul. 65 * 4. Neither the name of the author nor the names of any co-contributors 66 * may be used to endorse or promote products derived from this software 67 * without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 79 * THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81/*- 82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 83 * 84 * Permission to use, copy, modify, and distribute this software for any 85 * purpose with or without fee is hereby granted, provided that the above 86 * copyright notice and this permission notice appear in all copies. 87 * 88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 95 */ 96 97/* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103#include <sys/param.h> 104#include <sys/systm.h> 105#include <sys/bus.h> 106#include <sys/endian.h> 107#include <sys/mbuf.h> 108#include <sys/malloc.h> 109#include <sys/kernel.h> 110#include <sys/module.h> 111#include <sys/socket.h> 112#include <sys/sockio.h> 113#include <sys/queue.h> 114#include <sys/sysctl.h> 115 116#include <net/bpf.h> 117#include <net/ethernet.h> 118#include <net/if.h> 119#include <net/if_var.h> 120#include <net/if_arp.h> 121#include <net/if_dl.h> 122#include <net/if_media.h> 123#include <net/if_types.h> 124#include <net/if_vlan_var.h> 125 126#include <netinet/in.h> 127#include <netinet/in_systm.h> 128#include <netinet/ip.h> 129#include <netinet/tcp.h> 130#include <netinet/udp.h> 131 132#include <machine/bus.h> 133#include <machine/in_cksum.h> 134#include <machine/resource.h> 135#include <sys/rman.h> 136 137#include <dev/mii/mii.h> 138#include <dev/mii/miivar.h> 139 140#include <dev/pci/pcireg.h> 141#include <dev/pci/pcivar.h> 142 143#include <dev/msk/if_mskreg.h> 144 145MODULE_DEPEND(msk, pci, 1, 1, 1); 146MODULE_DEPEND(msk, ether, 1, 1, 1); 147MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149/* "device miibus" required. See GENERIC if you get errors here. */ 150#include "miibus_if.h" 151 152/* Tunables. */ 153static int msi_disable = 0; 154TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155static int legacy_intr = 0; 156TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157static int jumbo_disable = 0; 158TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160#define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162/* 163 * Devices supported by this driver. 164 */ 165static const struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169} msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 225 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 227 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 228 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 229 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 230 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 231 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 233 "D-Link 550SX Gigabit Ethernet" }, 234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 235 "D-Link 560SX Gigabit Ethernet" }, 236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 237 "D-Link 560T Gigabit Ethernet" } 238}; 239 240static const char *model_name[] = { 241 "Yukon XL", 242 "Yukon EC Ultra", 243 "Yukon EX", 244 "Yukon EC", 245 "Yukon FE", 246 "Yukon FE+", 247 "Yukon Supreme", 248 "Yukon Ultra 2", 249 "Yukon Unknown", 250 "Yukon Optima", 251}; 252 253static int mskc_probe(device_t); 254static int mskc_attach(device_t); 255static int mskc_detach(device_t); 256static int mskc_shutdown(device_t); 257static int mskc_setup_rambuffer(struct msk_softc *); 258static int mskc_suspend(device_t); 259static int mskc_resume(device_t); 260static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); 261static void mskc_reset(struct msk_softc *); 262 263static int msk_probe(device_t); 264static int msk_attach(device_t); 265static int msk_detach(device_t); 266 267static void msk_tick(void *); 268static void msk_intr(void *); 269static void msk_intr_phy(struct msk_if_softc *); 270static void msk_intr_gmac(struct msk_if_softc *); 271static __inline void msk_rxput(struct msk_if_softc *); 272static int msk_handle_events(struct msk_softc *); 273static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 274static void msk_intr_hwerr(struct msk_softc *); 275#ifndef __NO_STRICT_ALIGNMENT 276static __inline void msk_fixup_rx(struct mbuf *); 277#endif 278static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 279static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 280static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 281static void msk_txeof(struct msk_if_softc *, int); 282static int msk_encap(struct msk_if_softc *, struct mbuf **); 283static void msk_start(if_t); 284static void msk_start_locked(if_t); 285static int msk_ioctl(if_t, u_long, caddr_t); 286static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 287static void msk_set_rambuffer(struct msk_if_softc *); 288static void msk_set_tx_stfwd(struct msk_if_softc *); 289static void msk_init(void *); 290static void msk_init_locked(struct msk_if_softc *); 291static void msk_stop(struct msk_if_softc *); 292static void msk_watchdog(struct msk_if_softc *); 293static int msk_mediachange(if_t); 294static void msk_mediastatus(if_t, struct ifmediareq *); 295static void msk_phy_power(struct msk_softc *, int); 296static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 297static int msk_status_dma_alloc(struct msk_softc *); 298static void msk_status_dma_free(struct msk_softc *); 299static int msk_txrx_dma_alloc(struct msk_if_softc *); 300static int msk_rx_dma_jalloc(struct msk_if_softc *); 301static void msk_txrx_dma_free(struct msk_if_softc *); 302static void msk_rx_dma_jfree(struct msk_if_softc *); 303static int msk_rx_fill(struct msk_if_softc *, int); 304static int msk_init_rx_ring(struct msk_if_softc *); 305static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 306static void msk_init_tx_ring(struct msk_if_softc *); 307static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 308static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 309static int msk_newbuf(struct msk_if_softc *, int); 310static int msk_jumbo_newbuf(struct msk_if_softc *, int); 311 312static int msk_phy_readreg(struct msk_if_softc *, int, int); 313static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 314static int msk_miibus_readreg(device_t, int, int); 315static int msk_miibus_writereg(device_t, int, int, int); 316static void msk_miibus_statchg(device_t); 317 318static void msk_rxfilter(struct msk_if_softc *); 319static void msk_setvlan(struct msk_if_softc *, if_t); 320 321static void msk_stats_clear(struct msk_if_softc *); 322static void msk_stats_update(struct msk_if_softc *); 323static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 324static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 325static void msk_sysctl_node(struct msk_if_softc *); 326static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 327static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 328 329static device_method_t mskc_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, mskc_probe), 332 DEVMETHOD(device_attach, mskc_attach), 333 DEVMETHOD(device_detach, mskc_detach), 334 DEVMETHOD(device_suspend, mskc_suspend), 335 DEVMETHOD(device_resume, mskc_resume), 336 DEVMETHOD(device_shutdown, mskc_shutdown), 337 338 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), 339 340 DEVMETHOD_END 341}; 342 343static driver_t mskc_driver = { 344 "mskc", 345 mskc_methods, 346 sizeof(struct msk_softc) 347}; 348 349static device_method_t msk_methods[] = { 350 /* Device interface */ 351 DEVMETHOD(device_probe, msk_probe), 352 DEVMETHOD(device_attach, msk_attach), 353 DEVMETHOD(device_detach, msk_detach), 354 DEVMETHOD(device_shutdown, bus_generic_shutdown), 355 356 /* MII interface */ 357 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 358 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 359 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 360 361 DEVMETHOD_END 362}; 363 364static driver_t msk_driver = { 365 "msk", 366 msk_methods, 367 sizeof(struct msk_if_softc) 368}; 369 370DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL); 371DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL); 372DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL); 373 374static struct resource_spec msk_res_spec_io[] = { 375 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 376 { -1, 0, 0 } 377}; 378 379static struct resource_spec msk_res_spec_mem[] = { 380 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 381 { -1, 0, 0 } 382}; 383 384static struct resource_spec msk_irq_spec_legacy[] = { 385 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 386 { -1, 0, 0 } 387}; 388 389static struct resource_spec msk_irq_spec_msi[] = { 390 { SYS_RES_IRQ, 1, RF_ACTIVE }, 391 { -1, 0, 0 } 392}; 393 394static int 395msk_miibus_readreg(device_t dev, int phy, int reg) 396{ 397 struct msk_if_softc *sc_if; 398 399 sc_if = device_get_softc(dev); 400 401 return (msk_phy_readreg(sc_if, phy, reg)); 402} 403 404static int 405msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 406{ 407 struct msk_softc *sc; 408 int i, val; 409 410 sc = sc_if->msk_softc; 411 412 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 413 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 414 415 for (i = 0; i < MSK_TIMEOUT; i++) { 416 DELAY(1); 417 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 418 if ((val & GM_SMI_CT_RD_VAL) != 0) { 419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 420 break; 421 } 422 } 423 424 if (i == MSK_TIMEOUT) { 425 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 426 val = 0; 427 } 428 429 return (val); 430} 431 432static int 433msk_miibus_writereg(device_t dev, int phy, int reg, int val) 434{ 435 struct msk_if_softc *sc_if; 436 437 sc_if = device_get_softc(dev); 438 439 return (msk_phy_writereg(sc_if, phy, reg, val)); 440} 441 442static int 443msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 444{ 445 struct msk_softc *sc; 446 int i; 447 448 sc = sc_if->msk_softc; 449 450 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 451 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 452 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 453 for (i = 0; i < MSK_TIMEOUT; i++) { 454 DELAY(1); 455 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 456 GM_SMI_CT_BUSY) == 0) 457 break; 458 } 459 if (i == MSK_TIMEOUT) 460 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 461 462 return (0); 463} 464 465static void 466msk_miibus_statchg(device_t dev) 467{ 468 struct msk_softc *sc; 469 struct msk_if_softc *sc_if; 470 struct mii_data *mii; 471 if_t ifp; 472 uint32_t gmac; 473 474 sc_if = device_get_softc(dev); 475 sc = sc_if->msk_softc; 476 477 MSK_IF_LOCK_ASSERT(sc_if); 478 479 mii = device_get_softc(sc_if->msk_miibus); 480 ifp = sc_if->msk_ifp; 481 if (mii == NULL || ifp == NULL || 482 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 483 return; 484 485 sc_if->msk_flags &= ~MSK_FLAG_LINK; 486 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 487 (IFM_AVALID | IFM_ACTIVE)) { 488 switch (IFM_SUBTYPE(mii->mii_media_active)) { 489 case IFM_10_T: 490 case IFM_100_TX: 491 sc_if->msk_flags |= MSK_FLAG_LINK; 492 break; 493 case IFM_1000_T: 494 case IFM_1000_SX: 495 case IFM_1000_LX: 496 case IFM_1000_CX: 497 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 498 sc_if->msk_flags |= MSK_FLAG_LINK; 499 break; 500 default: 501 break; 502 } 503 } 504 505 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 506 /* Enable Tx FIFO Underrun. */ 507 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 508 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 509 /* 510 * Because mii(4) notify msk(4) that it detected link status 511 * change, there is no need to enable automatic 512 * speed/flow-control/duplex updates. 513 */ 514 gmac = GM_GPCR_AU_ALL_DIS; 515 switch (IFM_SUBTYPE(mii->mii_media_active)) { 516 case IFM_1000_SX: 517 case IFM_1000_T: 518 gmac |= GM_GPCR_SPEED_1000; 519 break; 520 case IFM_100_TX: 521 gmac |= GM_GPCR_SPEED_100; 522 break; 523 case IFM_10_T: 524 break; 525 } 526 527 if ((IFM_OPTIONS(mii->mii_media_active) & 528 IFM_ETH_RXPAUSE) == 0) 529 gmac |= GM_GPCR_FC_RX_DIS; 530 if ((IFM_OPTIONS(mii->mii_media_active) & 531 IFM_ETH_TXPAUSE) == 0) 532 gmac |= GM_GPCR_FC_TX_DIS; 533 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 534 gmac |= GM_GPCR_DUP_FULL; 535 else 536 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 537 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 538 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 539 /* Read again to ensure writing. */ 540 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 541 gmac = GMC_PAUSE_OFF; 542 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 543 if ((IFM_OPTIONS(mii->mii_media_active) & 544 IFM_ETH_RXPAUSE) != 0) 545 gmac = GMC_PAUSE_ON; 546 } 547 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 548 549 /* Enable PHY interrupt for FIFO underrun/overflow. */ 550 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 551 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 552 } else { 553 /* 554 * Link state changed to down. 555 * Disable PHY interrupts. 556 */ 557 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 558 /* Disable Rx/Tx MAC. */ 559 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 560 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 561 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 562 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 563 /* Read again to ensure writing. */ 564 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 565 } 566 } 567} 568 569static u_int 570msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 571{ 572 uint32_t *mchash = arg; 573 uint32_t crc; 574 575 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 576 /* Just want the 6 least significant bits. */ 577 crc &= 0x3f; 578 /* Set the corresponding bit in the hash table. */ 579 mchash[crc >> 5] |= 1 << (crc & 0x1f); 580 581 return (1); 582} 583 584static void 585msk_rxfilter(struct msk_if_softc *sc_if) 586{ 587 struct msk_softc *sc; 588 if_t ifp; 589 uint32_t mchash[2]; 590 uint16_t mode; 591 592 sc = sc_if->msk_softc; 593 594 MSK_IF_LOCK_ASSERT(sc_if); 595 596 ifp = sc_if->msk_ifp; 597 598 bzero(mchash, sizeof(mchash)); 599 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 600 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 601 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 602 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 603 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 604 mchash[0] = 0xffff; 605 mchash[1] = 0xffff; 606 } else { 607 mode |= GM_RXCR_UCF_ENA; 608 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash); 609 if (mchash[0] != 0 || mchash[1] != 0) 610 mode |= GM_RXCR_MCF_ENA; 611 } 612 613 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 614 mchash[0] & 0xffff); 615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 616 (mchash[0] >> 16) & 0xffff); 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 618 mchash[1] & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 620 (mchash[1] >> 16) & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 622} 623 624static void 625msk_setvlan(struct msk_if_softc *sc_if, if_t ifp) 626{ 627 struct msk_softc *sc; 628 629 sc = sc_if->msk_softc; 630 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 631 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 632 RX_VLAN_STRIP_ON); 633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 634 TX_VLAN_TAG_ON); 635 } else { 636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 637 RX_VLAN_STRIP_OFF); 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 639 TX_VLAN_TAG_OFF); 640 } 641} 642 643static int 644msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 645{ 646 uint16_t idx; 647 int i; 648 649 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 650 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 651 /* Wait until controller executes OP_TCPSTART command. */ 652 for (i = 100; i > 0; i--) { 653 DELAY(100); 654 idx = CSR_READ_2(sc_if->msk_softc, 655 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 656 PREF_UNIT_GET_IDX_REG)); 657 if (idx != 0) 658 break; 659 } 660 if (i == 0) { 661 device_printf(sc_if->msk_if_dev, 662 "prefetch unit stuck?\n"); 663 return (ETIMEDOUT); 664 } 665 /* 666 * Fill consumed LE with free buffer. This can be done 667 * in Rx handler but we don't want to add special code 668 * in fast handler. 669 */ 670 if (jumbo > 0) { 671 if (msk_jumbo_newbuf(sc_if, 0) != 0) 672 return (ENOBUFS); 673 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 674 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 676 } else { 677 if (msk_newbuf(sc_if, 0) != 0) 678 return (ENOBUFS); 679 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 680 sc_if->msk_cdata.msk_rx_ring_map, 681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 682 } 683 sc_if->msk_cdata.msk_rx_prod = 0; 684 CSR_WRITE_2(sc_if->msk_softc, 685 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 686 sc_if->msk_cdata.msk_rx_prod); 687 } 688 return (0); 689} 690 691static int 692msk_init_rx_ring(struct msk_if_softc *sc_if) 693{ 694 struct msk_ring_data *rd; 695 struct msk_rxdesc *rxd; 696 int i, nbuf, prod; 697 698 MSK_IF_LOCK_ASSERT(sc_if); 699 700 sc_if->msk_cdata.msk_rx_cons = 0; 701 sc_if->msk_cdata.msk_rx_prod = 0; 702 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 703 704 rd = &sc_if->msk_rdata; 705 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 706 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 707 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 708 rxd->rx_m = NULL; 709 rxd->rx_le = &rd->msk_rx_ring[prod]; 710 MSK_INC(prod, MSK_RX_RING_CNT); 711 } 712 nbuf = MSK_RX_BUF_CNT; 713 prod = 0; 714 /* Have controller know how to compute Rx checksum. */ 715 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 716 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 717#ifdef MSK_64BIT_DMA 718 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 719 rxd->rx_m = NULL; 720 rxd->rx_le = &rd->msk_rx_ring[prod]; 721 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 722 ETHER_HDR_LEN); 723 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 724 MSK_INC(prod, MSK_RX_RING_CNT); 725 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 726#endif 727 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 728 rxd->rx_m = NULL; 729 rxd->rx_le = &rd->msk_rx_ring[prod]; 730 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 731 ETHER_HDR_LEN); 732 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 733 MSK_INC(prod, MSK_RX_RING_CNT); 734 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 735 nbuf--; 736 } 737 for (i = 0; i < nbuf; i++) { 738 if (msk_newbuf(sc_if, prod) != 0) 739 return (ENOBUFS); 740 MSK_RX_INC(prod, MSK_RX_RING_CNT); 741 } 742 743 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 744 sc_if->msk_cdata.msk_rx_ring_map, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 747 /* Update prefetch unit. */ 748 sc_if->msk_cdata.msk_rx_prod = prod; 749 CSR_WRITE_2(sc_if->msk_softc, 750 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 751 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 752 MSK_RX_RING_CNT); 753 if (msk_rx_fill(sc_if, 0) != 0) 754 return (ENOBUFS); 755 return (0); 756} 757 758static int 759msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 760{ 761 struct msk_ring_data *rd; 762 struct msk_rxdesc *rxd; 763 int i, nbuf, prod; 764 765 MSK_IF_LOCK_ASSERT(sc_if); 766 767 sc_if->msk_cdata.msk_rx_cons = 0; 768 sc_if->msk_cdata.msk_rx_prod = 0; 769 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 770 771 rd = &sc_if->msk_rdata; 772 bzero(rd->msk_jumbo_rx_ring, 773 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 774 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 775 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 776 rxd->rx_m = NULL; 777 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 778 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 779 } 780 nbuf = MSK_RX_BUF_CNT; 781 prod = 0; 782 /* Have controller know how to compute Rx checksum. */ 783 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 784 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 785#ifdef MSK_64BIT_DMA 786 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 787 rxd->rx_m = NULL; 788 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 789 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 790 ETHER_HDR_LEN); 791 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 792 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 793 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 794#endif 795 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 796 rxd->rx_m = NULL; 797 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 798 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 799 ETHER_HDR_LEN); 800 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 801 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 802 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 803 nbuf--; 804 } 805 for (i = 0; i < nbuf; i++) { 806 if (msk_jumbo_newbuf(sc_if, prod) != 0) 807 return (ENOBUFS); 808 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 809 } 810 811 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 812 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 814 815 /* Update prefetch unit. */ 816 sc_if->msk_cdata.msk_rx_prod = prod; 817 CSR_WRITE_2(sc_if->msk_softc, 818 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 819 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 820 MSK_JUMBO_RX_RING_CNT); 821 if (msk_rx_fill(sc_if, 1) != 0) 822 return (ENOBUFS); 823 return (0); 824} 825 826static void 827msk_init_tx_ring(struct msk_if_softc *sc_if) 828{ 829 struct msk_ring_data *rd; 830 struct msk_txdesc *txd; 831 int i; 832 833 sc_if->msk_cdata.msk_tso_mtu = 0; 834 sc_if->msk_cdata.msk_last_csum = 0; 835 sc_if->msk_cdata.msk_tx_prod = 0; 836 sc_if->msk_cdata.msk_tx_cons = 0; 837 sc_if->msk_cdata.msk_tx_cnt = 0; 838 sc_if->msk_cdata.msk_tx_high_addr = 0; 839 840 rd = &sc_if->msk_rdata; 841 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 842 for (i = 0; i < MSK_TX_RING_CNT; i++) { 843 txd = &sc_if->msk_cdata.msk_txdesc[i]; 844 txd->tx_m = NULL; 845 txd->tx_le = &rd->msk_tx_ring[i]; 846 } 847 848 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 849 sc_if->msk_cdata.msk_tx_ring_map, 850 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 851} 852 853static __inline void 854msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 855{ 856 struct msk_rx_desc *rx_le; 857 struct msk_rxdesc *rxd; 858 struct mbuf *m; 859 860#ifdef MSK_64BIT_DMA 861 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 862 rx_le = rxd->rx_le; 863 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 864 MSK_INC(idx, MSK_RX_RING_CNT); 865#endif 866 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 867 m = rxd->rx_m; 868 rx_le = rxd->rx_le; 869 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 870} 871 872static __inline void 873msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 874{ 875 struct msk_rx_desc *rx_le; 876 struct msk_rxdesc *rxd; 877 struct mbuf *m; 878 879#ifdef MSK_64BIT_DMA 880 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 881 rx_le = rxd->rx_le; 882 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 883 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 884#endif 885 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 886 m = rxd->rx_m; 887 rx_le = rxd->rx_le; 888 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 889} 890 891static int 892msk_newbuf(struct msk_if_softc *sc_if, int idx) 893{ 894 struct msk_rx_desc *rx_le; 895 struct msk_rxdesc *rxd; 896 struct mbuf *m; 897 bus_dma_segment_t segs[1]; 898 bus_dmamap_t map; 899 int nsegs; 900 901 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 902 if (m == NULL) 903 return (ENOBUFS); 904 905 m->m_len = m->m_pkthdr.len = MCLBYTES; 906 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 907 m_adj(m, ETHER_ALIGN); 908#ifndef __NO_STRICT_ALIGNMENT 909 else 910 m_adj(m, MSK_RX_BUF_ALIGN); 911#endif 912 913 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 914 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 915 BUS_DMA_NOWAIT) != 0) { 916 m_freem(m); 917 return (ENOBUFS); 918 } 919 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 920 921 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 922#ifdef MSK_64BIT_DMA 923 rx_le = rxd->rx_le; 924 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 925 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 926 MSK_INC(idx, MSK_RX_RING_CNT); 927 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 928#endif 929 if (rxd->rx_m != NULL) { 930 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 931 BUS_DMASYNC_POSTREAD); 932 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 933 rxd->rx_m = NULL; 934 } 935 map = rxd->rx_dmamap; 936 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 937 sc_if->msk_cdata.msk_rx_sparemap = map; 938 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 939 BUS_DMASYNC_PREREAD); 940 rxd->rx_m = m; 941 rx_le = rxd->rx_le; 942 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 943 rx_le->msk_control = 944 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 945 946 return (0); 947} 948 949static int 950msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 951{ 952 struct msk_rx_desc *rx_le; 953 struct msk_rxdesc *rxd; 954 struct mbuf *m; 955 bus_dma_segment_t segs[1]; 956 bus_dmamap_t map; 957 int nsegs; 958 959 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 960 if (m == NULL) 961 return (ENOBUFS); 962 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 963 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 964 m_adj(m, ETHER_ALIGN); 965#ifndef __NO_STRICT_ALIGNMENT 966 else 967 m_adj(m, MSK_RX_BUF_ALIGN); 968#endif 969 970 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 971 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 972 BUS_DMA_NOWAIT) != 0) { 973 m_freem(m); 974 return (ENOBUFS); 975 } 976 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 977 978 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 979#ifdef MSK_64BIT_DMA 980 rx_le = rxd->rx_le; 981 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 982 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 983 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 984 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 985#endif 986 if (rxd->rx_m != NULL) { 987 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 988 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 989 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 990 rxd->rx_dmamap); 991 rxd->rx_m = NULL; 992 } 993 map = rxd->rx_dmamap; 994 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 995 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 996 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 997 BUS_DMASYNC_PREREAD); 998 rxd->rx_m = m; 999 rx_le = rxd->rx_le; 1000 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1001 rx_le->msk_control = 1002 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1003 1004 return (0); 1005} 1006 1007/* 1008 * Set media options. 1009 */ 1010static int 1011msk_mediachange(if_t ifp) 1012{ 1013 struct msk_if_softc *sc_if; 1014 struct mii_data *mii; 1015 int error; 1016 1017 sc_if = if_getsoftc(ifp); 1018 1019 MSK_IF_LOCK(sc_if); 1020 mii = device_get_softc(sc_if->msk_miibus); 1021 error = mii_mediachg(mii); 1022 MSK_IF_UNLOCK(sc_if); 1023 1024 return (error); 1025} 1026 1027/* 1028 * Report current media status. 1029 */ 1030static void 1031msk_mediastatus(if_t ifp, struct ifmediareq *ifmr) 1032{ 1033 struct msk_if_softc *sc_if; 1034 struct mii_data *mii; 1035 1036 sc_if = if_getsoftc(ifp); 1037 MSK_IF_LOCK(sc_if); 1038 if ((if_getflags(ifp) & IFF_UP) == 0) { 1039 MSK_IF_UNLOCK(sc_if); 1040 return; 1041 } 1042 mii = device_get_softc(sc_if->msk_miibus); 1043 1044 mii_pollstat(mii); 1045 ifmr->ifm_active = mii->mii_media_active; 1046 ifmr->ifm_status = mii->mii_media_status; 1047 MSK_IF_UNLOCK(sc_if); 1048} 1049 1050static int 1051msk_ioctl(if_t ifp, u_long command, caddr_t data) 1052{ 1053 struct msk_if_softc *sc_if; 1054 struct ifreq *ifr; 1055 struct mii_data *mii; 1056 int error, mask, reinit; 1057 1058 sc_if = if_getsoftc(ifp); 1059 ifr = (struct ifreq *)data; 1060 error = 0; 1061 1062 switch(command) { 1063 case SIOCSIFMTU: 1064 MSK_IF_LOCK(sc_if); 1065 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1066 error = EINVAL; 1067 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1068 if (ifr->ifr_mtu > ETHERMTU) { 1069 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1070 error = EINVAL; 1071 MSK_IF_UNLOCK(sc_if); 1072 break; 1073 } 1074 if ((sc_if->msk_flags & 1075 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1076 if_sethwassistbits(ifp, 0, 1077 MSK_CSUM_FEATURES | CSUM_TSO); 1078 if_setcapenablebit(ifp, 0, 1079 IFCAP_TSO4 | IFCAP_TXCSUM); 1080 VLAN_CAPABILITIES(ifp); 1081 } 1082 } 1083 if_setmtu(ifp, ifr->ifr_mtu); 1084 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1085 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1086 msk_init_locked(sc_if); 1087 } 1088 } 1089 MSK_IF_UNLOCK(sc_if); 1090 break; 1091 case SIOCSIFFLAGS: 1092 MSK_IF_LOCK(sc_if); 1093 if ((if_getflags(ifp) & IFF_UP) != 0) { 1094 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1095 ((if_getflags(ifp) ^ sc_if->msk_if_flags) & 1096 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1097 msk_rxfilter(sc_if); 1098 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1099 msk_init_locked(sc_if); 1100 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1101 msk_stop(sc_if); 1102 sc_if->msk_if_flags = if_getflags(ifp); 1103 MSK_IF_UNLOCK(sc_if); 1104 break; 1105 case SIOCADDMULTI: 1106 case SIOCDELMULTI: 1107 MSK_IF_LOCK(sc_if); 1108 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1109 msk_rxfilter(sc_if); 1110 MSK_IF_UNLOCK(sc_if); 1111 break; 1112 case SIOCGIFMEDIA: 1113 case SIOCSIFMEDIA: 1114 mii = device_get_softc(sc_if->msk_miibus); 1115 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1116 break; 1117 case SIOCSIFCAP: 1118 reinit = 0; 1119 MSK_IF_LOCK(sc_if); 1120 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1121 if ((mask & IFCAP_TXCSUM) != 0 && 1122 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1123 if_togglecapenable(ifp, IFCAP_TXCSUM); 1124 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1125 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0); 1126 else 1127 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES); 1128 } 1129 if ((mask & IFCAP_RXCSUM) != 0 && 1130 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 1131 if_togglecapenable(ifp, IFCAP_RXCSUM); 1132 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1133 reinit = 1; 1134 } 1135 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1136 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0) 1137 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1138 if ((mask & IFCAP_TSO4) != 0 && 1139 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 1140 if_togglecapenable(ifp, IFCAP_TSO4); 1141 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1142 if_sethwassistbits(ifp, CSUM_TSO, 0); 1143 else 1144 if_sethwassistbits(ifp, 0, CSUM_TSO); 1145 } 1146 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1147 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0) 1148 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1149 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1150 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 1151 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1152 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0) 1153 if_setcapenablebit(ifp, 0, 1154 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1155 msk_setvlan(sc_if, ifp); 1156 } 1157 if (if_getmtu(ifp) > ETHERMTU && 1158 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1159 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 1160 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 1161 } 1162 VLAN_CAPABILITIES(ifp); 1163 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1164 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1165 msk_init_locked(sc_if); 1166 } 1167 MSK_IF_UNLOCK(sc_if); 1168 break; 1169 default: 1170 error = ether_ioctl(ifp, command, data); 1171 break; 1172 } 1173 1174 return (error); 1175} 1176 1177static int 1178mskc_probe(device_t dev) 1179{ 1180 const struct msk_product *mp; 1181 uint16_t vendor, devid; 1182 int i; 1183 1184 vendor = pci_get_vendor(dev); 1185 devid = pci_get_device(dev); 1186 mp = msk_products; 1187 for (i = 0; i < nitems(msk_products); i++, mp++) { 1188 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1189 device_set_desc(dev, mp->msk_name); 1190 return (BUS_PROBE_DEFAULT); 1191 } 1192 } 1193 1194 return (ENXIO); 1195} 1196 1197static int 1198mskc_setup_rambuffer(struct msk_softc *sc) 1199{ 1200 int next; 1201 int i; 1202 1203 /* Get adapter SRAM size. */ 1204 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1205 if (bootverbose) 1206 device_printf(sc->msk_dev, 1207 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1208 if (sc->msk_ramsize == 0) 1209 return (0); 1210 1211 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1212 /* 1213 * Give receiver 2/3 of memory and round down to the multiple 1214 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1215 * of 1024. 1216 */ 1217 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1218 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1219 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1220 sc->msk_rxqstart[i] = next; 1221 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1222 next = sc->msk_rxqend[i] + 1; 1223 sc->msk_txqstart[i] = next; 1224 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1225 next = sc->msk_txqend[i] + 1; 1226 if (bootverbose) { 1227 device_printf(sc->msk_dev, 1228 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1229 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1230 sc->msk_rxqend[i]); 1231 device_printf(sc->msk_dev, 1232 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1233 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1234 sc->msk_txqend[i]); 1235 } 1236 } 1237 1238 return (0); 1239} 1240 1241static void 1242msk_phy_power(struct msk_softc *sc, int mode) 1243{ 1244 uint32_t our, val; 1245 int i; 1246 1247 switch (mode) { 1248 case MSK_PHY_POWERUP: 1249 /* Switch power to VCC (WA for VAUX problem). */ 1250 CSR_WRITE_1(sc, B0_POWER_CTRL, 1251 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1252 /* Disable Core Clock Division, set Clock Select to 0. */ 1253 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1254 1255 val = 0; 1256 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1257 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1258 /* Enable bits are inverted. */ 1259 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1262 } 1263 /* 1264 * Enable PCI & Core Clock, enable clock gating for both Links. 1265 */ 1266 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1267 1268 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1269 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1270 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1271 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1272 /* Deassert Low Power for 1st PHY. */ 1273 our |= PCI_Y2_PHY1_COMA; 1274 if (sc->msk_num_port > 1) 1275 our |= PCI_Y2_PHY2_COMA; 1276 } 1277 } 1278 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1279 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1280 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1281 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1282 val &= (PCI_FORCE_ASPM_REQUEST | 1283 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1284 PCI_ASPM_CLKRUN_REQUEST); 1285 /* Set all bits to 0 except bits 15..12. */ 1286 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1287 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1288 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1289 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1290 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1291 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1292 /* 1293 * Disable status race, workaround for 1294 * Yukon EC Ultra & Yukon EX. 1295 */ 1296 val = CSR_READ_4(sc, B2_GP_IO); 1297 val |= GLB_GPIO_STAT_RACE_DIS; 1298 CSR_WRITE_4(sc, B2_GP_IO, val); 1299 CSR_READ_4(sc, B2_GP_IO); 1300 } 1301 /* Release PHY from PowerDown/COMA mode. */ 1302 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1303 1304 for (i = 0; i < sc->msk_num_port; i++) { 1305 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1306 GMLC_RST_SET); 1307 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1308 GMLC_RST_CLR); 1309 } 1310 break; 1311 case MSK_PHY_POWERDOWN: 1312 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1313 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1314 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1315 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1316 val &= ~PCI_Y2_PHY1_COMA; 1317 if (sc->msk_num_port > 1) 1318 val &= ~PCI_Y2_PHY2_COMA; 1319 } 1320 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1321 1322 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1323 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1324 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1325 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1326 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1327 /* Enable bits are inverted. */ 1328 val = 0; 1329 } 1330 /* 1331 * Disable PCI & Core Clock, disable clock gating for 1332 * both Links. 1333 */ 1334 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1335 CSR_WRITE_1(sc, B0_POWER_CTRL, 1336 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1337 break; 1338 default: 1339 break; 1340 } 1341} 1342 1343static void 1344mskc_reset(struct msk_softc *sc) 1345{ 1346 bus_addr_t addr; 1347 uint16_t status; 1348 uint32_t val; 1349 int i, initram; 1350 1351 /* Disable ASF. */ 1352 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1353 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1354 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1355 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1356 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1357 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1358 /* Clear AHB bridge & microcontroller reset. */ 1359 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1360 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1361 /* Clear ASF microcontroller state. */ 1362 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1363 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1364 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1365 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1366 } else 1367 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1368 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1369 /* 1370 * Since we disabled ASF, S/W reset is required for 1371 * Power Management. 1372 */ 1373 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1374 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1375 } 1376 1377 /* Clear all error bits in the PCI status register. */ 1378 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1379 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1380 1381 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1382 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1383 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1384 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1385 1386 switch (sc->msk_bustype) { 1387 case MSK_PEX_BUS: 1388 /* Clear all PEX errors. */ 1389 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1390 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1391 if ((val & PEX_RX_OV) != 0) { 1392 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1393 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1394 } 1395 break; 1396 case MSK_PCI_BUS: 1397 case MSK_PCIX_BUS: 1398 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1399 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1400 if (val == 0) 1401 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1402 if (sc->msk_bustype == MSK_PCIX_BUS) { 1403 /* Set Cache Line Size opt. */ 1404 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1405 val |= PCI_CLS_OPT; 1406 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1407 } 1408 break; 1409 } 1410 /* Set PHY power state. */ 1411 msk_phy_power(sc, MSK_PHY_POWERUP); 1412 1413 /* Reset GPHY/GMAC Control */ 1414 for (i = 0; i < sc->msk_num_port; i++) { 1415 /* GPHY Control reset. */ 1416 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1417 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1418 /* GMAC Control reset. */ 1419 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1420 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1422 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1423 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1424 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1425 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1426 GMC_BYP_RETR_ON); 1427 } 1428 1429 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1430 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1431 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1432 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1433 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1434 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1435 } 1436 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1437 1438 /* LED On. */ 1439 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1440 1441 /* Clear TWSI IRQ. */ 1442 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1443 1444 /* Turn off hardware timer. */ 1445 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1446 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1447 1448 /* Turn off descriptor polling. */ 1449 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1450 1451 /* Turn off time stamps. */ 1452 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1453 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1454 1455 initram = 0; 1456 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1457 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1458 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1459 initram++; 1460 1461 /* Configure timeout values. */ 1462 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1463 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1464 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1465 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1466 MSK_RI_TO_53); 1467 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1468 MSK_RI_TO_53); 1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1470 MSK_RI_TO_53); 1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1472 MSK_RI_TO_53); 1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1474 MSK_RI_TO_53); 1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1476 MSK_RI_TO_53); 1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1478 MSK_RI_TO_53); 1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1480 MSK_RI_TO_53); 1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1482 MSK_RI_TO_53); 1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1484 MSK_RI_TO_53); 1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1486 MSK_RI_TO_53); 1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1488 MSK_RI_TO_53); 1489 } 1490 1491 /* Disable all interrupts. */ 1492 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1493 CSR_READ_4(sc, B0_HWE_IMSK); 1494 CSR_WRITE_4(sc, B0_IMSK, 0); 1495 CSR_READ_4(sc, B0_IMSK); 1496 1497 /* 1498 * On dual port PCI-X card, there is an problem where status 1499 * can be received out of order due to split transactions. 1500 */ 1501 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1502 uint16_t pcix_cmd; 1503 1504 pcix_cmd = pci_read_config(sc->msk_dev, 1505 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1506 /* Clear Max Outstanding Split Transactions. */ 1507 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1508 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1509 pci_write_config(sc->msk_dev, 1510 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1511 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1512 } 1513 if (sc->msk_expcap != 0) { 1514 /* Change Max. Read Request Size to 2048 bytes. */ 1515 if (pci_get_max_read_req(sc->msk_dev) == 512) 1516 pci_set_max_read_req(sc->msk_dev, 2048); 1517 } 1518 1519 /* Clear status list. */ 1520 bzero(sc->msk_stat_ring, 1521 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1522 sc->msk_stat_cons = 0; 1523 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1525 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1526 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1527 /* Set the status list base address. */ 1528 addr = sc->msk_stat_ring_paddr; 1529 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1530 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1531 /* Set the status list last index. */ 1532 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1533 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1534 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1535 /* WA for dev. #4.3 */ 1536 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1537 /* WA for dev. #4.18 */ 1538 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1539 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1540 } else { 1541 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1542 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1543 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1544 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1545 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1546 else 1547 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1548 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1549 } 1550 /* 1551 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1552 */ 1553 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1554 1555 /* Enable status unit. */ 1556 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1557 1558 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1559 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1560 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1561} 1562 1563static int 1564msk_probe(device_t dev) 1565{ 1566 struct msk_softc *sc; 1567 char desc[100]; 1568 1569 sc = device_get_softc(device_get_parent(dev)); 1570 /* 1571 * Not much to do here. We always know there will be 1572 * at least one GMAC present, and if there are two, 1573 * mskc_attach() will create a second device instance 1574 * for us. 1575 */ 1576 snprintf(desc, sizeof(desc), 1577 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1578 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1579 sc->msk_hw_rev); 1580 device_set_desc_copy(dev, desc); 1581 1582 return (BUS_PROBE_DEFAULT); 1583} 1584 1585static int 1586msk_attach(device_t dev) 1587{ 1588 struct msk_softc *sc; 1589 struct msk_if_softc *sc_if; 1590 if_t ifp; 1591 struct msk_mii_data *mmd; 1592 int i, port, error; 1593 uint8_t eaddr[6]; 1594 1595 if (dev == NULL) 1596 return (EINVAL); 1597 1598 error = 0; 1599 sc_if = device_get_softc(dev); 1600 sc = device_get_softc(device_get_parent(dev)); 1601 mmd = device_get_ivars(dev); 1602 port = mmd->port; 1603 1604 sc_if->msk_if_dev = dev; 1605 sc_if->msk_port = port; 1606 sc_if->msk_softc = sc; 1607 sc_if->msk_flags = sc->msk_pflags; 1608 sc->msk_if[port] = sc_if; 1609 /* Setup Tx/Rx queue register offsets. */ 1610 if (port == MSK_PORT_A) { 1611 sc_if->msk_txq = Q_XA1; 1612 sc_if->msk_txsq = Q_XS1; 1613 sc_if->msk_rxq = Q_R1; 1614 } else { 1615 sc_if->msk_txq = Q_XA2; 1616 sc_if->msk_txsq = Q_XS2; 1617 sc_if->msk_rxq = Q_R2; 1618 } 1619 1620 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1621 msk_sysctl_node(sc_if); 1622 1623 if ((error = msk_txrx_dma_alloc(sc_if)) != 0) 1624 goto fail; 1625 msk_rx_dma_jalloc(sc_if); 1626 1627 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1628 if (ifp == NULL) { 1629 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1630 error = ENOSPC; 1631 goto fail; 1632 } 1633 if_setsoftc(ifp, sc_if); 1634 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1635 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1636 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1637 /* 1638 * Enable Rx checksum offloading if controller supports 1639 * new descriptor formant and controller is not Yukon XL. 1640 */ 1641 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1642 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1643 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1644 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1645 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1646 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1647 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO); 1648 if_setcapenable(ifp, if_getcapabilities(ifp)); 1649 if_setioctlfn(ifp, msk_ioctl); 1650 if_setstartfn(ifp, msk_start); 1651 if_setinitfn(ifp, msk_init); 1652 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1); 1653 if_setsendqready(ifp); 1654 /* 1655 * Get station address for this interface. Note that 1656 * dual port cards actually come with three station 1657 * addresses: one for each port, plus an extra. The 1658 * extra one is used by the SysKonnect driver software 1659 * as a 'virtual' station address for when both ports 1660 * are operating in failover mode. Currently we don't 1661 * use this extra address. 1662 */ 1663 MSK_IF_LOCK(sc_if); 1664 for (i = 0; i < ETHER_ADDR_LEN; i++) 1665 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1666 1667 /* 1668 * Call MI attach routine. Can't hold locks when calling into ether_*. 1669 */ 1670 MSK_IF_UNLOCK(sc_if); 1671 ether_ifattach(ifp, eaddr); 1672 MSK_IF_LOCK(sc_if); 1673 1674 /* VLAN capability setup */ 1675 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1676 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1677 /* 1678 * Due to Tx checksum offload hardware bugs, msk(4) manually 1679 * computes checksum for short frames. For VLAN tagged frames 1680 * this workaround does not work so disable checksum offload 1681 * for VLAN interface. 1682 */ 1683 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0); 1684 /* 1685 * Enable Rx checksum offloading for VLAN tagged frames 1686 * if controller support new descriptor format. 1687 */ 1688 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1689 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1690 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1691 } 1692 if_setcapenable(ifp, if_getcapabilities(ifp)); 1693 /* 1694 * Disable RX checksum offloading on controllers that don't use 1695 * new descriptor format but give chance to enable it. 1696 */ 1697 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1698 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 1699 1700 /* 1701 * Tell the upper layer(s) we support long frames. 1702 * Must appear after the call to ether_ifattach() because 1703 * ether_ifattach() sets ifi_hdrlen to the default value. 1704 */ 1705 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1706 1707 /* 1708 * Do miibus setup. 1709 */ 1710 MSK_IF_UNLOCK(sc_if); 1711 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1712 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1713 mmd->mii_flags); 1714 if (error != 0) { 1715 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1716 ether_ifdetach(ifp); 1717 error = ENXIO; 1718 goto fail; 1719 } 1720 1721fail: 1722 if (error != 0) { 1723 /* Access should be ok even though lock has been dropped */ 1724 sc->msk_if[port] = NULL; 1725 msk_detach(dev); 1726 } 1727 1728 return (error); 1729} 1730 1731/* 1732 * Attach the interface. Allocate softc structures, do ifmedia 1733 * setup and ethernet/BPF attach. 1734 */ 1735static int 1736mskc_attach(device_t dev) 1737{ 1738 struct msk_softc *sc; 1739 struct msk_mii_data *mmd; 1740 int error, msic, msir, reg; 1741 1742 sc = device_get_softc(dev); 1743 sc->msk_dev = dev; 1744 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1745 MTX_DEF); 1746 1747 /* 1748 * Map control/status registers. 1749 */ 1750 pci_enable_busmaster(dev); 1751 1752 /* Allocate I/O resource */ 1753#ifdef MSK_USEIOSPACE 1754 sc->msk_res_spec = msk_res_spec_io; 1755#else 1756 sc->msk_res_spec = msk_res_spec_mem; 1757#endif 1758 sc->msk_irq_spec = msk_irq_spec_legacy; 1759 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1760 if (error) { 1761 if (sc->msk_res_spec == msk_res_spec_mem) 1762 sc->msk_res_spec = msk_res_spec_io; 1763 else 1764 sc->msk_res_spec = msk_res_spec_mem; 1765 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1766 if (error) { 1767 device_printf(dev, "couldn't allocate %s resources\n", 1768 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1769 "I/O"); 1770 mtx_destroy(&sc->msk_mtx); 1771 return (ENXIO); 1772 } 1773 } 1774 1775 /* Enable all clocks before accessing any registers. */ 1776 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1777 1778 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1779 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1780 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1781 /* Bail out if chip is not recognized. */ 1782 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1783 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1784 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1785 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1786 sc->msk_hw_id, sc->msk_hw_rev); 1787 mtx_destroy(&sc->msk_mtx); 1788 return (ENXIO); 1789 } 1790 1791 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1792 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1793 OID_AUTO, "process_limit", 1794 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1795 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1796 "max number of Rx events to process"); 1797 1798 sc->msk_process_limit = MSK_PROC_DEFAULT; 1799 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1800 "process_limit", &sc->msk_process_limit); 1801 if (error == 0) { 1802 if (sc->msk_process_limit < MSK_PROC_MIN || 1803 sc->msk_process_limit > MSK_PROC_MAX) { 1804 device_printf(dev, "process_limit value out of range; " 1805 "using default: %d\n", MSK_PROC_DEFAULT); 1806 sc->msk_process_limit = MSK_PROC_DEFAULT; 1807 } 1808 } 1809 1810 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1811 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1812 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1813 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1814 "Maximum number of time to delay interrupts"); 1815 resource_int_value(device_get_name(dev), device_get_unit(dev), 1816 "int_holdoff", &sc->msk_int_holdoff); 1817 1818 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1819 /* Check number of MACs. */ 1820 sc->msk_num_port = 1; 1821 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1822 CFG_DUAL_MAC_MSK) { 1823 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1824 sc->msk_num_port++; 1825 } 1826 1827 /* Check bus type. */ 1828 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1829 sc->msk_bustype = MSK_PEX_BUS; 1830 sc->msk_expcap = reg; 1831 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1832 sc->msk_bustype = MSK_PCIX_BUS; 1833 sc->msk_pcixcap = reg; 1834 } else 1835 sc->msk_bustype = MSK_PCI_BUS; 1836 1837 switch (sc->msk_hw_id) { 1838 case CHIP_ID_YUKON_EC: 1839 sc->msk_clock = 125; /* 125 MHz */ 1840 sc->msk_pflags |= MSK_FLAG_JUMBO; 1841 break; 1842 case CHIP_ID_YUKON_EC_U: 1843 sc->msk_clock = 125; /* 125 MHz */ 1844 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1845 break; 1846 case CHIP_ID_YUKON_EX: 1847 sc->msk_clock = 125; /* 125 MHz */ 1848 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1849 MSK_FLAG_AUTOTX_CSUM; 1850 /* 1851 * Yukon Extreme seems to have silicon bug for 1852 * automatic Tx checksum calculation capability. 1853 */ 1854 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1855 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1856 /* 1857 * Yukon Extreme A0 could not use store-and-forward 1858 * for jumbo frames, so disable Tx checksum 1859 * offloading for jumbo frames. 1860 */ 1861 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1862 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1863 break; 1864 case CHIP_ID_YUKON_FE: 1865 sc->msk_clock = 100; /* 100 MHz */ 1866 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1867 break; 1868 case CHIP_ID_YUKON_FE_P: 1869 sc->msk_clock = 50; /* 50 MHz */ 1870 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1871 MSK_FLAG_AUTOTX_CSUM; 1872 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1873 /* 1874 * XXX 1875 * FE+ A0 has status LE writeback bug so msk(4) 1876 * does not rely on status word of received frame 1877 * in msk_rxeof() which in turn disables all 1878 * hardware assistance bits reported by the status 1879 * word as well as validity of the received frame. 1880 * Just pass received frames to upper stack with 1881 * minimal test and let upper stack handle them. 1882 */ 1883 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1884 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1885 } 1886 break; 1887 case CHIP_ID_YUKON_XL: 1888 sc->msk_clock = 156; /* 156 MHz */ 1889 sc->msk_pflags |= MSK_FLAG_JUMBO; 1890 break; 1891 case CHIP_ID_YUKON_SUPR: 1892 sc->msk_clock = 125; /* 125 MHz */ 1893 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1894 MSK_FLAG_AUTOTX_CSUM; 1895 break; 1896 case CHIP_ID_YUKON_UL_2: 1897 sc->msk_clock = 125; /* 125 MHz */ 1898 sc->msk_pflags |= MSK_FLAG_JUMBO; 1899 break; 1900 case CHIP_ID_YUKON_OPT: 1901 sc->msk_clock = 125; /* 125 MHz */ 1902 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1903 break; 1904 default: 1905 sc->msk_clock = 156; /* 156 MHz */ 1906 break; 1907 } 1908 1909 /* Allocate IRQ resources. */ 1910 msic = pci_msi_count(dev); 1911 if (bootverbose) 1912 device_printf(dev, "MSI count : %d\n", msic); 1913 if (legacy_intr != 0) 1914 msi_disable = 1; 1915 if (msi_disable == 0 && msic > 0) { 1916 msir = 1; 1917 if (pci_alloc_msi(dev, &msir) == 0) { 1918 if (msir == 1) { 1919 sc->msk_pflags |= MSK_FLAG_MSI; 1920 sc->msk_irq_spec = msk_irq_spec_msi; 1921 } else 1922 pci_release_msi(dev); 1923 } 1924 } 1925 1926 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1927 if (error) { 1928 device_printf(dev, "couldn't allocate IRQ resources\n"); 1929 goto fail; 1930 } 1931 1932 if ((error = msk_status_dma_alloc(sc)) != 0) 1933 goto fail; 1934 1935 /* Set base interrupt mask. */ 1936 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1937 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1938 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1939 1940 /* Reset the adapter. */ 1941 mskc_reset(sc); 1942 1943 if ((error = mskc_setup_rambuffer(sc)) != 0) 1944 goto fail; 1945 1946 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1947 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1948 device_printf(dev, "failed to add child for PORT_A\n"); 1949 error = ENXIO; 1950 goto fail; 1951 } 1952 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1953 mmd->port = MSK_PORT_A; 1954 mmd->pmd = sc->msk_pmd; 1955 mmd->mii_flags |= MIIF_DOPAUSE; 1956 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1957 mmd->mii_flags |= MIIF_HAVEFIBER; 1958 if (sc->msk_pmd == 'P') 1959 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1960 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1961 1962 if (sc->msk_num_port > 1) { 1963 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1964 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1965 device_printf(dev, "failed to add child for PORT_B\n"); 1966 error = ENXIO; 1967 goto fail; 1968 } 1969 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1970 M_ZERO); 1971 mmd->port = MSK_PORT_B; 1972 mmd->pmd = sc->msk_pmd; 1973 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1974 mmd->mii_flags |= MIIF_HAVEFIBER; 1975 if (sc->msk_pmd == 'P') 1976 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1977 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1978 } 1979 1980 error = bus_generic_attach(dev); 1981 if (error) { 1982 device_printf(dev, "failed to attach port(s)\n"); 1983 goto fail; 1984 } 1985 1986 /* Hook interrupt last to avoid having to lock softc. */ 1987 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1988 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1989 if (error != 0) { 1990 device_printf(dev, "couldn't set up interrupt handler\n"); 1991 goto fail; 1992 } 1993fail: 1994 if (error != 0) 1995 mskc_detach(dev); 1996 1997 return (error); 1998} 1999 2000/* 2001 * Shutdown hardware and free up resources. This can be called any 2002 * time after the mutex has been initialized. It is called in both 2003 * the error case in attach and the normal detach case so it needs 2004 * to be careful about only freeing resources that have actually been 2005 * allocated. 2006 */ 2007static int 2008msk_detach(device_t dev) 2009{ 2010 struct msk_softc *sc; 2011 struct msk_if_softc *sc_if; 2012 if_t ifp; 2013 2014 sc_if = device_get_softc(dev); 2015 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2016 ("msk mutex not initialized in msk_detach")); 2017 MSK_IF_LOCK(sc_if); 2018 2019 ifp = sc_if->msk_ifp; 2020 if (device_is_attached(dev)) { 2021 /* XXX */ 2022 sc_if->msk_flags |= MSK_FLAG_DETACH; 2023 msk_stop(sc_if); 2024 /* Can't hold locks while calling detach. */ 2025 MSK_IF_UNLOCK(sc_if); 2026 callout_drain(&sc_if->msk_tick_ch); 2027 if (ifp) 2028 ether_ifdetach(ifp); 2029 MSK_IF_LOCK(sc_if); 2030 } 2031 2032 /* 2033 * We're generally called from mskc_detach() which is using 2034 * device_delete_child() to get to here. It's already trashed 2035 * miibus for us, so don't do it here or we'll panic. 2036 * 2037 * if (sc_if->msk_miibus != NULL) { 2038 * device_delete_child(dev, sc_if->msk_miibus); 2039 * sc_if->msk_miibus = NULL; 2040 * } 2041 */ 2042 2043 msk_rx_dma_jfree(sc_if); 2044 msk_txrx_dma_free(sc_if); 2045 bus_generic_detach(dev); 2046 2047 sc = sc_if->msk_softc; 2048 sc->msk_if[sc_if->msk_port] = NULL; 2049 MSK_IF_UNLOCK(sc_if); 2050 if (ifp) 2051 if_free(ifp); 2052 2053 return (0); 2054} 2055 2056static int 2057mskc_detach(device_t dev) 2058{ 2059 struct msk_softc *sc; 2060 2061 sc = device_get_softc(dev); 2062 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2063 2064 if (device_is_alive(dev)) { 2065 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2066 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2067 M_DEVBUF); 2068 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2069 } 2070 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2071 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2072 M_DEVBUF); 2073 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2074 } 2075 bus_generic_detach(dev); 2076 } 2077 2078 /* Disable all interrupts. */ 2079 CSR_WRITE_4(sc, B0_IMSK, 0); 2080 CSR_READ_4(sc, B0_IMSK); 2081 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2082 CSR_READ_4(sc, B0_HWE_IMSK); 2083 2084 /* LED Off. */ 2085 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2086 2087 /* Put hardware reset. */ 2088 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2089 2090 msk_status_dma_free(sc); 2091 2092 if (sc->msk_intrhand) { 2093 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2094 sc->msk_intrhand = NULL; 2095 } 2096 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2097 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2098 pci_release_msi(dev); 2099 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2100 mtx_destroy(&sc->msk_mtx); 2101 2102 return (0); 2103} 2104 2105static bus_dma_tag_t 2106mskc_get_dma_tag(device_t bus, device_t child __unused) 2107{ 2108 2109 return (bus_get_dma_tag(bus)); 2110} 2111 2112struct msk_dmamap_arg { 2113 bus_addr_t msk_busaddr; 2114}; 2115 2116static void 2117msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2118{ 2119 struct msk_dmamap_arg *ctx; 2120 2121 if (error != 0) 2122 return; 2123 ctx = arg; 2124 ctx->msk_busaddr = segs[0].ds_addr; 2125} 2126 2127/* Create status DMA region. */ 2128static int 2129msk_status_dma_alloc(struct msk_softc *sc) 2130{ 2131 struct msk_dmamap_arg ctx; 2132 bus_size_t stat_sz; 2133 int count, error; 2134 2135 /* 2136 * It seems controller requires number of status LE entries 2137 * is power of 2 and the maximum number of status LE entries 2138 * is 4096. For dual-port controllers, the number of status 2139 * LE entries should be large enough to hold both port's 2140 * status updates. 2141 */ 2142 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2143 count = imin(4096, roundup2(count, 1024)); 2144 sc->msk_stat_count = count; 2145 stat_sz = count * sizeof(struct msk_stat_desc); 2146 error = bus_dma_tag_create( 2147 bus_get_dma_tag(sc->msk_dev), /* parent */ 2148 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2149 BUS_SPACE_MAXADDR, /* lowaddr */ 2150 BUS_SPACE_MAXADDR, /* highaddr */ 2151 NULL, NULL, /* filter, filterarg */ 2152 stat_sz, /* maxsize */ 2153 1, /* nsegments */ 2154 stat_sz, /* maxsegsize */ 2155 0, /* flags */ 2156 NULL, NULL, /* lockfunc, lockarg */ 2157 &sc->msk_stat_tag); 2158 if (error != 0) { 2159 device_printf(sc->msk_dev, 2160 "failed to create status DMA tag\n"); 2161 return (error); 2162 } 2163 2164 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2165 error = bus_dmamem_alloc(sc->msk_stat_tag, 2166 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2167 BUS_DMA_ZERO, &sc->msk_stat_map); 2168 if (error != 0) { 2169 device_printf(sc->msk_dev, 2170 "failed to allocate DMA'able memory for status ring\n"); 2171 return (error); 2172 } 2173 2174 ctx.msk_busaddr = 0; 2175 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2176 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2177 if (error != 0) { 2178 device_printf(sc->msk_dev, 2179 "failed to load DMA'able memory for status ring\n"); 2180 return (error); 2181 } 2182 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2183 2184 return (0); 2185} 2186 2187static void 2188msk_status_dma_free(struct msk_softc *sc) 2189{ 2190 2191 /* Destroy status block. */ 2192 if (sc->msk_stat_tag) { 2193 if (sc->msk_stat_ring_paddr) { 2194 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2195 sc->msk_stat_ring_paddr = 0; 2196 } 2197 if (sc->msk_stat_ring) { 2198 bus_dmamem_free(sc->msk_stat_tag, 2199 sc->msk_stat_ring, sc->msk_stat_map); 2200 sc->msk_stat_ring = NULL; 2201 } 2202 bus_dma_tag_destroy(sc->msk_stat_tag); 2203 sc->msk_stat_tag = NULL; 2204 } 2205} 2206 2207static int 2208msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2209{ 2210 struct msk_dmamap_arg ctx; 2211 struct msk_txdesc *txd; 2212 struct msk_rxdesc *rxd; 2213 bus_size_t rxalign; 2214 int error, i; 2215 2216 /* Create parent DMA tag. */ 2217 error = bus_dma_tag_create( 2218 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2219 1, 0, /* alignment, boundary */ 2220 BUS_SPACE_MAXADDR, /* lowaddr */ 2221 BUS_SPACE_MAXADDR, /* highaddr */ 2222 NULL, NULL, /* filter, filterarg */ 2223 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2224 0, /* nsegments */ 2225 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2226 0, /* flags */ 2227 NULL, NULL, /* lockfunc, lockarg */ 2228 &sc_if->msk_cdata.msk_parent_tag); 2229 if (error != 0) { 2230 device_printf(sc_if->msk_if_dev, 2231 "failed to create parent DMA tag\n"); 2232 goto fail; 2233 } 2234 /* Create tag for Tx ring. */ 2235 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2236 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2237 BUS_SPACE_MAXADDR, /* lowaddr */ 2238 BUS_SPACE_MAXADDR, /* highaddr */ 2239 NULL, NULL, /* filter, filterarg */ 2240 MSK_TX_RING_SZ, /* maxsize */ 2241 1, /* nsegments */ 2242 MSK_TX_RING_SZ, /* maxsegsize */ 2243 0, /* flags */ 2244 NULL, NULL, /* lockfunc, lockarg */ 2245 &sc_if->msk_cdata.msk_tx_ring_tag); 2246 if (error != 0) { 2247 device_printf(sc_if->msk_if_dev, 2248 "failed to create Tx ring DMA tag\n"); 2249 goto fail; 2250 } 2251 2252 /* Create tag for Rx ring. */ 2253 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2254 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2255 BUS_SPACE_MAXADDR, /* lowaddr */ 2256 BUS_SPACE_MAXADDR, /* highaddr */ 2257 NULL, NULL, /* filter, filterarg */ 2258 MSK_RX_RING_SZ, /* maxsize */ 2259 1, /* nsegments */ 2260 MSK_RX_RING_SZ, /* maxsegsize */ 2261 0, /* flags */ 2262 NULL, NULL, /* lockfunc, lockarg */ 2263 &sc_if->msk_cdata.msk_rx_ring_tag); 2264 if (error != 0) { 2265 device_printf(sc_if->msk_if_dev, 2266 "failed to create Rx ring DMA tag\n"); 2267 goto fail; 2268 } 2269 2270 /* Create tag for Tx buffers. */ 2271 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2272 1, 0, /* alignment, boundary */ 2273 BUS_SPACE_MAXADDR, /* lowaddr */ 2274 BUS_SPACE_MAXADDR, /* highaddr */ 2275 NULL, NULL, /* filter, filterarg */ 2276 MSK_TSO_MAXSIZE, /* maxsize */ 2277 MSK_MAXTXSEGS, /* nsegments */ 2278 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2279 0, /* flags */ 2280 NULL, NULL, /* lockfunc, lockarg */ 2281 &sc_if->msk_cdata.msk_tx_tag); 2282 if (error != 0) { 2283 device_printf(sc_if->msk_if_dev, 2284 "failed to create Tx DMA tag\n"); 2285 goto fail; 2286 } 2287 2288 rxalign = 1; 2289 /* 2290 * Workaround hardware hang which seems to happen when Rx buffer 2291 * is not aligned on multiple of FIFO word(8 bytes). 2292 */ 2293 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2294 rxalign = MSK_RX_BUF_ALIGN; 2295 /* Create tag for Rx buffers. */ 2296 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2297 rxalign, 0, /* alignment, boundary */ 2298 BUS_SPACE_MAXADDR, /* lowaddr */ 2299 BUS_SPACE_MAXADDR, /* highaddr */ 2300 NULL, NULL, /* filter, filterarg */ 2301 MCLBYTES, /* maxsize */ 2302 1, /* nsegments */ 2303 MCLBYTES, /* maxsegsize */ 2304 0, /* flags */ 2305 NULL, NULL, /* lockfunc, lockarg */ 2306 &sc_if->msk_cdata.msk_rx_tag); 2307 if (error != 0) { 2308 device_printf(sc_if->msk_if_dev, 2309 "failed to create Rx DMA tag\n"); 2310 goto fail; 2311 } 2312 2313 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2314 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2315 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2316 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2317 if (error != 0) { 2318 device_printf(sc_if->msk_if_dev, 2319 "failed to allocate DMA'able memory for Tx ring\n"); 2320 goto fail; 2321 } 2322 2323 ctx.msk_busaddr = 0; 2324 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2325 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2326 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2327 if (error != 0) { 2328 device_printf(sc_if->msk_if_dev, 2329 "failed to load DMA'able memory for Tx ring\n"); 2330 goto fail; 2331 } 2332 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2333 2334 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2335 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2336 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2337 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2338 if (error != 0) { 2339 device_printf(sc_if->msk_if_dev, 2340 "failed to allocate DMA'able memory for Rx ring\n"); 2341 goto fail; 2342 } 2343 2344 ctx.msk_busaddr = 0; 2345 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2346 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2347 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2348 if (error != 0) { 2349 device_printf(sc_if->msk_if_dev, 2350 "failed to load DMA'able memory for Rx ring\n"); 2351 goto fail; 2352 } 2353 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2354 2355 /* Create DMA maps for Tx buffers. */ 2356 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2357 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2358 txd->tx_m = NULL; 2359 txd->tx_dmamap = NULL; 2360 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2361 &txd->tx_dmamap); 2362 if (error != 0) { 2363 device_printf(sc_if->msk_if_dev, 2364 "failed to create Tx dmamap\n"); 2365 goto fail; 2366 } 2367 } 2368 /* Create DMA maps for Rx buffers. */ 2369 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2370 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2371 device_printf(sc_if->msk_if_dev, 2372 "failed to create spare Rx dmamap\n"); 2373 goto fail; 2374 } 2375 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2376 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2377 rxd->rx_m = NULL; 2378 rxd->rx_dmamap = NULL; 2379 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2380 &rxd->rx_dmamap); 2381 if (error != 0) { 2382 device_printf(sc_if->msk_if_dev, 2383 "failed to create Rx dmamap\n"); 2384 goto fail; 2385 } 2386 } 2387 2388fail: 2389 return (error); 2390} 2391 2392static int 2393msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2394{ 2395 struct msk_dmamap_arg ctx; 2396 struct msk_rxdesc *jrxd; 2397 bus_size_t rxalign; 2398 int error, i; 2399 2400 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2401 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2402 device_printf(sc_if->msk_if_dev, 2403 "disabling jumbo frame support\n"); 2404 return (0); 2405 } 2406 /* Create tag for jumbo Rx ring. */ 2407 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2408 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2409 BUS_SPACE_MAXADDR, /* lowaddr */ 2410 BUS_SPACE_MAXADDR, /* highaddr */ 2411 NULL, NULL, /* filter, filterarg */ 2412 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2413 1, /* nsegments */ 2414 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2415 0, /* flags */ 2416 NULL, NULL, /* lockfunc, lockarg */ 2417 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2418 if (error != 0) { 2419 device_printf(sc_if->msk_if_dev, 2420 "failed to create jumbo Rx ring DMA tag\n"); 2421 goto jumbo_fail; 2422 } 2423 2424 rxalign = 1; 2425 /* 2426 * Workaround hardware hang which seems to happen when Rx buffer 2427 * is not aligned on multiple of FIFO word(8 bytes). 2428 */ 2429 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2430 rxalign = MSK_RX_BUF_ALIGN; 2431 /* Create tag for jumbo Rx buffers. */ 2432 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2433 rxalign, 0, /* alignment, boundary */ 2434 BUS_SPACE_MAXADDR, /* lowaddr */ 2435 BUS_SPACE_MAXADDR, /* highaddr */ 2436 NULL, NULL, /* filter, filterarg */ 2437 MJUM9BYTES, /* maxsize */ 2438 1, /* nsegments */ 2439 MJUM9BYTES, /* maxsegsize */ 2440 0, /* flags */ 2441 NULL, NULL, /* lockfunc, lockarg */ 2442 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2443 if (error != 0) { 2444 device_printf(sc_if->msk_if_dev, 2445 "failed to create jumbo Rx DMA tag\n"); 2446 goto jumbo_fail; 2447 } 2448 2449 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2450 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2451 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2452 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2453 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2454 if (error != 0) { 2455 device_printf(sc_if->msk_if_dev, 2456 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2457 goto jumbo_fail; 2458 } 2459 2460 ctx.msk_busaddr = 0; 2461 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2462 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2463 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2464 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2465 if (error != 0) { 2466 device_printf(sc_if->msk_if_dev, 2467 "failed to load DMA'able memory for jumbo Rx ring\n"); 2468 goto jumbo_fail; 2469 } 2470 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2471 2472 /* Create DMA maps for jumbo Rx buffers. */ 2473 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2474 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2475 device_printf(sc_if->msk_if_dev, 2476 "failed to create spare jumbo Rx dmamap\n"); 2477 goto jumbo_fail; 2478 } 2479 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2480 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2481 jrxd->rx_m = NULL; 2482 jrxd->rx_dmamap = NULL; 2483 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2484 &jrxd->rx_dmamap); 2485 if (error != 0) { 2486 device_printf(sc_if->msk_if_dev, 2487 "failed to create jumbo Rx dmamap\n"); 2488 goto jumbo_fail; 2489 } 2490 } 2491 2492 return (0); 2493 2494jumbo_fail: 2495 msk_rx_dma_jfree(sc_if); 2496 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2497 "due to resource shortage\n"); 2498 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2499 return (error); 2500} 2501 2502static void 2503msk_txrx_dma_free(struct msk_if_softc *sc_if) 2504{ 2505 struct msk_txdesc *txd; 2506 struct msk_rxdesc *rxd; 2507 int i; 2508 2509 /* Tx ring. */ 2510 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2511 if (sc_if->msk_rdata.msk_tx_ring_paddr) 2512 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2513 sc_if->msk_cdata.msk_tx_ring_map); 2514 if (sc_if->msk_rdata.msk_tx_ring) 2515 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2516 sc_if->msk_rdata.msk_tx_ring, 2517 sc_if->msk_cdata.msk_tx_ring_map); 2518 sc_if->msk_rdata.msk_tx_ring = NULL; 2519 sc_if->msk_rdata.msk_tx_ring_paddr = 0; 2520 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2521 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2522 } 2523 /* Rx ring. */ 2524 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2525 if (sc_if->msk_rdata.msk_rx_ring_paddr) 2526 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2527 sc_if->msk_cdata.msk_rx_ring_map); 2528 if (sc_if->msk_rdata.msk_rx_ring) 2529 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2530 sc_if->msk_rdata.msk_rx_ring, 2531 sc_if->msk_cdata.msk_rx_ring_map); 2532 sc_if->msk_rdata.msk_rx_ring = NULL; 2533 sc_if->msk_rdata.msk_rx_ring_paddr = 0; 2534 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2535 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2536 } 2537 /* Tx buffers. */ 2538 if (sc_if->msk_cdata.msk_tx_tag) { 2539 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2540 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2541 if (txd->tx_dmamap) { 2542 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2543 txd->tx_dmamap); 2544 txd->tx_dmamap = NULL; 2545 } 2546 } 2547 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2548 sc_if->msk_cdata.msk_tx_tag = NULL; 2549 } 2550 /* Rx buffers. */ 2551 if (sc_if->msk_cdata.msk_rx_tag) { 2552 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2553 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2554 if (rxd->rx_dmamap) { 2555 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2556 rxd->rx_dmamap); 2557 rxd->rx_dmamap = NULL; 2558 } 2559 } 2560 if (sc_if->msk_cdata.msk_rx_sparemap) { 2561 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2562 sc_if->msk_cdata.msk_rx_sparemap); 2563 sc_if->msk_cdata.msk_rx_sparemap = 0; 2564 } 2565 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2566 sc_if->msk_cdata.msk_rx_tag = NULL; 2567 } 2568 if (sc_if->msk_cdata.msk_parent_tag) { 2569 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2570 sc_if->msk_cdata.msk_parent_tag = NULL; 2571 } 2572} 2573 2574static void 2575msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2576{ 2577 struct msk_rxdesc *jrxd; 2578 int i; 2579 2580 /* Jumbo Rx ring. */ 2581 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2582 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr) 2583 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2584 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2585 if (sc_if->msk_rdata.msk_jumbo_rx_ring) 2586 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2587 sc_if->msk_rdata.msk_jumbo_rx_ring, 2588 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2589 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2590 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0; 2591 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2592 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2593 } 2594 /* Jumbo Rx buffers. */ 2595 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2596 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2597 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2598 if (jrxd->rx_dmamap) { 2599 bus_dmamap_destroy( 2600 sc_if->msk_cdata.msk_jumbo_rx_tag, 2601 jrxd->rx_dmamap); 2602 jrxd->rx_dmamap = NULL; 2603 } 2604 } 2605 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2606 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2607 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2608 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2609 } 2610 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2611 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2612 } 2613} 2614 2615static int 2616msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2617{ 2618 struct msk_txdesc *txd, *txd_last; 2619 struct msk_tx_desc *tx_le; 2620 struct mbuf *m; 2621 bus_dmamap_t map; 2622 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2623 uint32_t control, csum, prod, si; 2624 uint16_t offset, tcp_offset, tso_mtu; 2625 int error, i, nseg, tso; 2626 2627 MSK_IF_LOCK_ASSERT(sc_if); 2628 2629 tcp_offset = offset = 0; 2630 m = *m_head; 2631 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2632 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2633 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2634 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2635 /* 2636 * Since mbuf has no protocol specific structure information 2637 * in it we have to inspect protocol information here to 2638 * setup TSO and checksum offload. I don't know why Marvell 2639 * made a such decision in chip design because other GigE 2640 * hardwares normally takes care of all these chores in 2641 * hardware. However, TSO performance of Yukon II is very 2642 * good such that it's worth to implement it. 2643 */ 2644 struct ether_header *eh; 2645 struct ip *ip; 2646 struct tcphdr *tcp; 2647 2648 if (M_WRITABLE(m) == 0) { 2649 /* Get a writable copy. */ 2650 m = m_dup(*m_head, M_NOWAIT); 2651 m_freem(*m_head); 2652 if (m == NULL) { 2653 *m_head = NULL; 2654 return (ENOBUFS); 2655 } 2656 *m_head = m; 2657 } 2658 2659 offset = sizeof(struct ether_header); 2660 m = m_pullup(m, offset); 2661 if (m == NULL) { 2662 *m_head = NULL; 2663 return (ENOBUFS); 2664 } 2665 eh = mtod(m, struct ether_header *); 2666 /* Check if hardware VLAN insertion is off. */ 2667 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2668 offset = sizeof(struct ether_vlan_header); 2669 m = m_pullup(m, offset); 2670 if (m == NULL) { 2671 *m_head = NULL; 2672 return (ENOBUFS); 2673 } 2674 } 2675 m = m_pullup(m, offset + sizeof(struct ip)); 2676 if (m == NULL) { 2677 *m_head = NULL; 2678 return (ENOBUFS); 2679 } 2680 ip = (struct ip *)(mtod(m, char *) + offset); 2681 offset += (ip->ip_hl << 2); 2682 tcp_offset = offset; 2683 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2684 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2685 if (m == NULL) { 2686 *m_head = NULL; 2687 return (ENOBUFS); 2688 } 2689 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2690 offset += (tcp->th_off << 2); 2691 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2692 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2693 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2694 /* 2695 * It seems that Yukon II has Tx checksum offload bug 2696 * for small TCP packets that's less than 60 bytes in 2697 * size (e.g. TCP window probe packet, pure ACK packet). 2698 * Common work around like padding with zeros to make 2699 * the frame minimum ethernet frame size didn't work at 2700 * all. 2701 * Instead of disabling checksum offload completely we 2702 * resort to S/W checksum routine when we encounter 2703 * short TCP frames. 2704 * Short UDP packets appear to be handled correctly by 2705 * Yukon II. Also I assume this bug does not happen on 2706 * controllers that use newer descriptor format or 2707 * automatic Tx checksum calculation. 2708 */ 2709 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2710 if (m == NULL) { 2711 *m_head = NULL; 2712 return (ENOBUFS); 2713 } 2714 *(uint16_t *)(m->m_data + offset + 2715 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2716 m->m_pkthdr.len, offset); 2717 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2718 } 2719 *m_head = m; 2720 } 2721 2722 prod = sc_if->msk_cdata.msk_tx_prod; 2723 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2724 txd_last = txd; 2725 map = txd->tx_dmamap; 2726 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2727 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2728 if (error == EFBIG) { 2729 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2730 if (m == NULL) { 2731 m_freem(*m_head); 2732 *m_head = NULL; 2733 return (ENOBUFS); 2734 } 2735 *m_head = m; 2736 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2737 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2738 if (error != 0) { 2739 m_freem(*m_head); 2740 *m_head = NULL; 2741 return (error); 2742 } 2743 } else if (error != 0) 2744 return (error); 2745 if (nseg == 0) { 2746 m_freem(*m_head); 2747 *m_head = NULL; 2748 return (EIO); 2749 } 2750 2751 /* Check number of available descriptors. */ 2752 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2753 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2754 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2755 return (ENOBUFS); 2756 } 2757 2758 control = 0; 2759 tso = 0; 2760 tx_le = NULL; 2761 2762 /* Check TSO support. */ 2763 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2764 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2765 tso_mtu = m->m_pkthdr.tso_segsz; 2766 else 2767 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2768 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2769 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2770 tx_le->msk_addr = htole32(tso_mtu); 2771 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2772 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2773 else 2774 tx_le->msk_control = 2775 htole32(OP_LRGLEN | HW_OWNER); 2776 sc_if->msk_cdata.msk_tx_cnt++; 2777 MSK_INC(prod, MSK_TX_RING_CNT); 2778 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2779 } 2780 tso++; 2781 } 2782 /* Check if we have a VLAN tag to insert. */ 2783 if ((m->m_flags & M_VLANTAG) != 0) { 2784 if (tx_le == NULL) { 2785 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2786 tx_le->msk_addr = htole32(0); 2787 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2788 htons(m->m_pkthdr.ether_vtag)); 2789 sc_if->msk_cdata.msk_tx_cnt++; 2790 MSK_INC(prod, MSK_TX_RING_CNT); 2791 } else { 2792 tx_le->msk_control |= htole32(OP_VLAN | 2793 htons(m->m_pkthdr.ether_vtag)); 2794 } 2795 control |= INS_VLAN; 2796 } 2797 /* Check if we have to handle checksum offload. */ 2798 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2799 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2800 control |= CALSUM; 2801 else { 2802 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2803 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2804 control |= UDPTCP; 2805 /* Checksum write position. */ 2806 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2807 /* Checksum start position. */ 2808 csum |= (uint32_t)tcp_offset << 16; 2809 if (csum != sc_if->msk_cdata.msk_last_csum) { 2810 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2811 tx_le->msk_addr = htole32(csum); 2812 tx_le->msk_control = htole32(1 << 16 | 2813 (OP_TCPLISW | HW_OWNER)); 2814 sc_if->msk_cdata.msk_tx_cnt++; 2815 MSK_INC(prod, MSK_TX_RING_CNT); 2816 sc_if->msk_cdata.msk_last_csum = csum; 2817 } 2818 } 2819 } 2820 2821#ifdef MSK_64BIT_DMA 2822 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2823 sc_if->msk_cdata.msk_tx_high_addr) { 2824 sc_if->msk_cdata.msk_tx_high_addr = 2825 MSK_ADDR_HI(txsegs[0].ds_addr); 2826 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2827 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2828 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2829 sc_if->msk_cdata.msk_tx_cnt++; 2830 MSK_INC(prod, MSK_TX_RING_CNT); 2831 } 2832#endif 2833 si = prod; 2834 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2835 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2836 if (tso == 0) 2837 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2838 OP_PACKET); 2839 else 2840 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2841 OP_LARGESEND); 2842 sc_if->msk_cdata.msk_tx_cnt++; 2843 MSK_INC(prod, MSK_TX_RING_CNT); 2844 2845 for (i = 1; i < nseg; i++) { 2846 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2847#ifdef MSK_64BIT_DMA 2848 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2849 sc_if->msk_cdata.msk_tx_high_addr) { 2850 sc_if->msk_cdata.msk_tx_high_addr = 2851 MSK_ADDR_HI(txsegs[i].ds_addr); 2852 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2853 tx_le->msk_addr = 2854 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2855 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2856 sc_if->msk_cdata.msk_tx_cnt++; 2857 MSK_INC(prod, MSK_TX_RING_CNT); 2858 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2859 } 2860#endif 2861 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2862 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2863 OP_BUFFER | HW_OWNER); 2864 sc_if->msk_cdata.msk_tx_cnt++; 2865 MSK_INC(prod, MSK_TX_RING_CNT); 2866 } 2867 /* Update producer index. */ 2868 sc_if->msk_cdata.msk_tx_prod = prod; 2869 2870 /* Set EOP on the last descriptor. */ 2871 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2872 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2873 tx_le->msk_control |= htole32(EOP); 2874 2875 /* Turn the first descriptor ownership to hardware. */ 2876 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2877 tx_le->msk_control |= htole32(HW_OWNER); 2878 2879 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2880 map = txd_last->tx_dmamap; 2881 txd_last->tx_dmamap = txd->tx_dmamap; 2882 txd->tx_dmamap = map; 2883 txd->tx_m = m; 2884 2885 /* Sync descriptors. */ 2886 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2887 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2888 sc_if->msk_cdata.msk_tx_ring_map, 2889 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2890 2891 return (0); 2892} 2893 2894static void 2895msk_start(if_t ifp) 2896{ 2897 struct msk_if_softc *sc_if; 2898 2899 sc_if = if_getsoftc(ifp); 2900 MSK_IF_LOCK(sc_if); 2901 msk_start_locked(ifp); 2902 MSK_IF_UNLOCK(sc_if); 2903} 2904 2905static void 2906msk_start_locked(if_t ifp) 2907{ 2908 struct msk_if_softc *sc_if; 2909 struct mbuf *m_head; 2910 int enq; 2911 2912 sc_if = if_getsoftc(ifp); 2913 MSK_IF_LOCK_ASSERT(sc_if); 2914 2915 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2916 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2917 return; 2918 2919 for (enq = 0; !if_sendq_empty(ifp) && 2920 sc_if->msk_cdata.msk_tx_cnt < 2921 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2922 m_head = if_dequeue(ifp); 2923 if (m_head == NULL) 2924 break; 2925 /* 2926 * Pack the data into the transmit ring. If we 2927 * don't have room, set the OACTIVE flag and wait 2928 * for the NIC to drain the ring. 2929 */ 2930 if (msk_encap(sc_if, &m_head) != 0) { 2931 if (m_head == NULL) 2932 break; 2933 if_sendq_prepend(ifp, m_head); 2934 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2935 break; 2936 } 2937 2938 enq++; 2939 /* 2940 * If there's a BPF listener, bounce a copy of this frame 2941 * to him. 2942 */ 2943 ETHER_BPF_MTAP(ifp, m_head); 2944 } 2945 2946 if (enq > 0) { 2947 /* Transmit */ 2948 CSR_WRITE_2(sc_if->msk_softc, 2949 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2950 sc_if->msk_cdata.msk_tx_prod); 2951 2952 /* Set a timeout in case the chip goes out to lunch. */ 2953 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2954 } 2955} 2956 2957static void 2958msk_watchdog(struct msk_if_softc *sc_if) 2959{ 2960 if_t ifp; 2961 2962 MSK_IF_LOCK_ASSERT(sc_if); 2963 2964 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2965 return; 2966 ifp = sc_if->msk_ifp; 2967 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2968 if (bootverbose) 2969 if_printf(sc_if->msk_ifp, "watchdog timeout " 2970 "(missed link)\n"); 2971 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2972 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2973 msk_init_locked(sc_if); 2974 return; 2975 } 2976 2977 if_printf(ifp, "watchdog timeout\n"); 2978 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2979 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2980 msk_init_locked(sc_if); 2981 if (!if_sendq_empty(ifp)) 2982 msk_start_locked(ifp); 2983} 2984 2985static int 2986mskc_shutdown(device_t dev) 2987{ 2988 struct msk_softc *sc; 2989 int i; 2990 2991 sc = device_get_softc(dev); 2992 MSK_LOCK(sc); 2993 for (i = 0; i < sc->msk_num_port; i++) { 2994 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2995 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 2996 IFF_DRV_RUNNING) != 0)) 2997 msk_stop(sc->msk_if[i]); 2998 } 2999 MSK_UNLOCK(sc); 3000 3001 /* Put hardware reset. */ 3002 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3003 return (0); 3004} 3005 3006static int 3007mskc_suspend(device_t dev) 3008{ 3009 struct msk_softc *sc; 3010 int i; 3011 3012 sc = device_get_softc(dev); 3013 3014 MSK_LOCK(sc); 3015 3016 for (i = 0; i < sc->msk_num_port; i++) { 3017 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3018 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 3019 IFF_DRV_RUNNING) != 0)) 3020 msk_stop(sc->msk_if[i]); 3021 } 3022 3023 /* Disable all interrupts. */ 3024 CSR_WRITE_4(sc, B0_IMSK, 0); 3025 CSR_READ_4(sc, B0_IMSK); 3026 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3027 CSR_READ_4(sc, B0_HWE_IMSK); 3028 3029 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3030 3031 /* Put hardware reset. */ 3032 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3033 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3034 3035 MSK_UNLOCK(sc); 3036 3037 return (0); 3038} 3039 3040static int 3041mskc_resume(device_t dev) 3042{ 3043 struct msk_softc *sc; 3044 int i; 3045 3046 sc = device_get_softc(dev); 3047 3048 MSK_LOCK(sc); 3049 3050 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3051 mskc_reset(sc); 3052 for (i = 0; i < sc->msk_num_port; i++) { 3053 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3054 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) { 3055 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0, 3056 IFF_DRV_RUNNING); 3057 msk_init_locked(sc->msk_if[i]); 3058 } 3059 } 3060 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3061 3062 MSK_UNLOCK(sc); 3063 3064 return (0); 3065} 3066 3067#ifndef __NO_STRICT_ALIGNMENT 3068static __inline void 3069msk_fixup_rx(struct mbuf *m) 3070{ 3071 int i; 3072 uint16_t *src, *dst; 3073 3074 src = mtod(m, uint16_t *); 3075 dst = src - 3; 3076 3077 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3078 *dst++ = *src++; 3079 3080 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3081} 3082#endif 3083 3084static __inline void 3085msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3086{ 3087 struct ether_header *eh; 3088 struct ip *ip; 3089 struct udphdr *uh; 3090 int32_t hlen, len, pktlen, temp32; 3091 uint16_t csum, *opts; 3092 3093 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3094 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3095 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3096 if ((control & CSS_IPV4_CSUM_OK) != 0) 3097 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3098 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3099 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3100 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3101 CSUM_PSEUDO_HDR; 3102 m->m_pkthdr.csum_data = 0xffff; 3103 } 3104 } 3105 return; 3106 } 3107 /* 3108 * Marvell Yukon controllers that support OP_RXCHKS has known 3109 * to have various Rx checksum offloading bugs. These 3110 * controllers can be configured to compute simple checksum 3111 * at two different positions. So we can compute IP and TCP/UDP 3112 * checksum at the same time. We intentionally have controller 3113 * compute TCP/UDP checksum twice by specifying the same 3114 * checksum start position and compare the result. If the value 3115 * is different it would indicate the hardware logic was wrong. 3116 */ 3117 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3118 if (bootverbose) 3119 device_printf(sc_if->msk_if_dev, 3120 "Rx checksum value mismatch!\n"); 3121 return; 3122 } 3123 pktlen = m->m_pkthdr.len; 3124 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3125 return; 3126 eh = mtod(m, struct ether_header *); 3127 if (eh->ether_type != htons(ETHERTYPE_IP)) 3128 return; 3129 ip = (struct ip *)(eh + 1); 3130 if (ip->ip_v != IPVERSION) 3131 return; 3132 3133 hlen = ip->ip_hl << 2; 3134 pktlen -= sizeof(struct ether_header); 3135 if (hlen < sizeof(struct ip)) 3136 return; 3137 if (ntohs(ip->ip_len) < hlen) 3138 return; 3139 if (ntohs(ip->ip_len) != pktlen) 3140 return; 3141 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3142 return; /* can't handle fragmented packet. */ 3143 3144 switch (ip->ip_p) { 3145 case IPPROTO_TCP: 3146 if (pktlen < (hlen + sizeof(struct tcphdr))) 3147 return; 3148 break; 3149 case IPPROTO_UDP: 3150 if (pktlen < (hlen + sizeof(struct udphdr))) 3151 return; 3152 uh = (struct udphdr *)((caddr_t)ip + hlen); 3153 if (uh->uh_sum == 0) 3154 return; /* no checksum */ 3155 break; 3156 default: 3157 return; 3158 } 3159 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3160 /* Checksum fixup for IP options. */ 3161 len = hlen - sizeof(struct ip); 3162 if (len > 0) { 3163 opts = (uint16_t *)(ip + 1); 3164 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3165 temp32 = csum - *opts; 3166 temp32 = (temp32 >> 16) + (temp32 & 65535); 3167 csum = temp32 & 65535; 3168 } 3169 } 3170 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3171 m->m_pkthdr.csum_data = csum; 3172} 3173 3174static void 3175msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3176 int len) 3177{ 3178 struct mbuf *m; 3179 if_t ifp; 3180 struct msk_rxdesc *rxd; 3181 int cons, rxlen; 3182 3183 ifp = sc_if->msk_ifp; 3184 3185 MSK_IF_LOCK_ASSERT(sc_if); 3186 3187 cons = sc_if->msk_cdata.msk_rx_cons; 3188 do { 3189 rxlen = status >> 16; 3190 if ((status & GMR_FS_VLAN) != 0 && 3191 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3192 rxlen -= ETHER_VLAN_ENCAP_LEN; 3193 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3194 /* 3195 * For controllers that returns bogus status code 3196 * just do minimal check and let upper stack 3197 * handle this frame. 3198 */ 3199 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3200 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3201 msk_discard_rxbuf(sc_if, cons); 3202 break; 3203 } 3204 } else if (len > sc_if->msk_framesize || 3205 ((status & GMR_FS_ANY_ERR) != 0) || 3206 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3207 /* Don't count flow-control packet as errors. */ 3208 if ((status & GMR_FS_GOOD_FC) == 0) 3209 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3210 msk_discard_rxbuf(sc_if, cons); 3211 break; 3212 } 3213#ifdef MSK_64BIT_DMA 3214 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3215 MSK_RX_RING_CNT]; 3216#else 3217 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3218#endif 3219 m = rxd->rx_m; 3220 if (msk_newbuf(sc_if, cons) != 0) { 3221 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3222 /* Reuse old buffer. */ 3223 msk_discard_rxbuf(sc_if, cons); 3224 break; 3225 } 3226 m->m_pkthdr.rcvif = ifp; 3227 m->m_pkthdr.len = m->m_len = len; 3228#ifndef __NO_STRICT_ALIGNMENT 3229 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3230 msk_fixup_rx(m); 3231#endif 3232 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3233 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3234 msk_rxcsum(sc_if, control, m); 3235 /* Check for VLAN tagged packets. */ 3236 if ((status & GMR_FS_VLAN) != 0 && 3237 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3238 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3239 m->m_flags |= M_VLANTAG; 3240 } 3241 MSK_IF_UNLOCK(sc_if); 3242 if_input(ifp, m); 3243 MSK_IF_LOCK(sc_if); 3244 } while (0); 3245 3246 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3247 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3248} 3249 3250static void 3251msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3252 int len) 3253{ 3254 struct mbuf *m; 3255 if_t ifp; 3256 struct msk_rxdesc *jrxd; 3257 int cons, rxlen; 3258 3259 ifp = sc_if->msk_ifp; 3260 3261 MSK_IF_LOCK_ASSERT(sc_if); 3262 3263 cons = sc_if->msk_cdata.msk_rx_cons; 3264 do { 3265 rxlen = status >> 16; 3266 if ((status & GMR_FS_VLAN) != 0 && 3267 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3268 rxlen -= ETHER_VLAN_ENCAP_LEN; 3269 if (len > sc_if->msk_framesize || 3270 ((status & GMR_FS_ANY_ERR) != 0) || 3271 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3272 /* Don't count flow-control packet as errors. */ 3273 if ((status & GMR_FS_GOOD_FC) == 0) 3274 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3275 msk_discard_jumbo_rxbuf(sc_if, cons); 3276 break; 3277 } 3278#ifdef MSK_64BIT_DMA 3279 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3280 MSK_JUMBO_RX_RING_CNT]; 3281#else 3282 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3283#endif 3284 m = jrxd->rx_m; 3285 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3286 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3287 /* Reuse old buffer. */ 3288 msk_discard_jumbo_rxbuf(sc_if, cons); 3289 break; 3290 } 3291 m->m_pkthdr.rcvif = ifp; 3292 m->m_pkthdr.len = m->m_len = len; 3293#ifndef __NO_STRICT_ALIGNMENT 3294 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3295 msk_fixup_rx(m); 3296#endif 3297 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3298 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3299 msk_rxcsum(sc_if, control, m); 3300 /* Check for VLAN tagged packets. */ 3301 if ((status & GMR_FS_VLAN) != 0 && 3302 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3303 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3304 m->m_flags |= M_VLANTAG; 3305 } 3306 MSK_IF_UNLOCK(sc_if); 3307 if_input(ifp, m); 3308 MSK_IF_LOCK(sc_if); 3309 } while (0); 3310 3311 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3312 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3313} 3314 3315static void 3316msk_txeof(struct msk_if_softc *sc_if, int idx) 3317{ 3318 struct msk_txdesc *txd; 3319 struct msk_tx_desc *cur_tx; 3320 if_t ifp; 3321 uint32_t control; 3322 int cons, prog; 3323 3324 MSK_IF_LOCK_ASSERT(sc_if); 3325 3326 ifp = sc_if->msk_ifp; 3327 3328 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3329 sc_if->msk_cdata.msk_tx_ring_map, 3330 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3331 /* 3332 * Go through our tx ring and free mbufs for those 3333 * frames that have been sent. 3334 */ 3335 cons = sc_if->msk_cdata.msk_tx_cons; 3336 prog = 0; 3337 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3338 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3339 break; 3340 prog++; 3341 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3342 control = le32toh(cur_tx->msk_control); 3343 sc_if->msk_cdata.msk_tx_cnt--; 3344 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3345 if ((control & EOP) == 0) 3346 continue; 3347 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3348 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3349 BUS_DMASYNC_POSTWRITE); 3350 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3351 3352 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3353 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3354 __func__)); 3355 m_freem(txd->tx_m); 3356 txd->tx_m = NULL; 3357 } 3358 3359 if (prog > 0) { 3360 sc_if->msk_cdata.msk_tx_cons = cons; 3361 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3362 sc_if->msk_watchdog_timer = 0; 3363 /* No need to sync LEs as we didn't update LEs. */ 3364 } 3365} 3366 3367static void 3368msk_tick(void *xsc_if) 3369{ 3370 struct epoch_tracker et; 3371 struct msk_if_softc *sc_if; 3372 struct mii_data *mii; 3373 3374 sc_if = xsc_if; 3375 3376 MSK_IF_LOCK_ASSERT(sc_if); 3377 3378 mii = device_get_softc(sc_if->msk_miibus); 3379 3380 mii_tick(mii); 3381 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3382 msk_miibus_statchg(sc_if->msk_if_dev); 3383 NET_EPOCH_ENTER(et); 3384 msk_handle_events(sc_if->msk_softc); 3385 NET_EPOCH_EXIT(et); 3386 msk_watchdog(sc_if); 3387 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3388} 3389 3390static void 3391msk_intr_phy(struct msk_if_softc *sc_if) 3392{ 3393 uint16_t status; 3394 3395 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3396 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3397 /* Handle FIFO Underrun/Overflow? */ 3398 if ((status & PHY_M_IS_FIFO_ERROR)) 3399 device_printf(sc_if->msk_if_dev, 3400 "PHY FIFO underrun/overflow.\n"); 3401} 3402 3403static void 3404msk_intr_gmac(struct msk_if_softc *sc_if) 3405{ 3406 struct msk_softc *sc; 3407 uint8_t status; 3408 3409 sc = sc_if->msk_softc; 3410 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3411 3412 /* GMAC Rx FIFO overrun. */ 3413 if ((status & GM_IS_RX_FF_OR) != 0) 3414 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3415 GMF_CLI_RX_FO); 3416 /* GMAC Tx FIFO underrun. */ 3417 if ((status & GM_IS_TX_FF_UR) != 0) { 3418 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3419 GMF_CLI_TX_FU); 3420 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3421 /* 3422 * XXX 3423 * In case of Tx underrun, we may need to flush/reset 3424 * Tx MAC but that would also require resynchronization 3425 * with status LEs. Reinitializing status LEs would 3426 * affect other port in dual MAC configuration so it 3427 * should be avoided as possible as we can. 3428 * Due to lack of documentation it's all vague guess but 3429 * it needs more investigation. 3430 */ 3431 } 3432} 3433 3434static void 3435msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3436{ 3437 struct msk_softc *sc; 3438 3439 sc = sc_if->msk_softc; 3440 if ((status & Y2_IS_PAR_RD1) != 0) { 3441 device_printf(sc_if->msk_if_dev, 3442 "RAM buffer read parity error\n"); 3443 /* Clear IRQ. */ 3444 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3445 RI_CLR_RD_PERR); 3446 } 3447 if ((status & Y2_IS_PAR_WR1) != 0) { 3448 device_printf(sc_if->msk_if_dev, 3449 "RAM buffer write parity error\n"); 3450 /* Clear IRQ. */ 3451 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3452 RI_CLR_WR_PERR); 3453 } 3454 if ((status & Y2_IS_PAR_MAC1) != 0) { 3455 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3456 /* Clear IRQ. */ 3457 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3458 GMF_CLI_TX_PE); 3459 } 3460 if ((status & Y2_IS_PAR_RX1) != 0) { 3461 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3462 /* Clear IRQ. */ 3463 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3464 } 3465 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3466 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3467 /* Clear IRQ. */ 3468 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3469 } 3470} 3471 3472static void 3473msk_intr_hwerr(struct msk_softc *sc) 3474{ 3475 uint32_t status; 3476 uint32_t tlphead[4]; 3477 3478 status = CSR_READ_4(sc, B0_HWE_ISRC); 3479 /* Time Stamp timer overflow. */ 3480 if ((status & Y2_IS_TIST_OV) != 0) 3481 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3482 if ((status & Y2_IS_PCI_NEXP) != 0) { 3483 /* 3484 * PCI Express Error occurred which is not described in PEX 3485 * spec. 3486 * This error is also mapped either to Master Abort( 3487 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3488 * can only be cleared there. 3489 */ 3490 device_printf(sc->msk_dev, 3491 "PCI Express protocol violation error\n"); 3492 } 3493 3494 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3495 uint16_t v16; 3496 3497 if ((status & Y2_IS_MST_ERR) != 0) 3498 device_printf(sc->msk_dev, 3499 "unexpected IRQ Status error\n"); 3500 else 3501 device_printf(sc->msk_dev, 3502 "unexpected IRQ Master error\n"); 3503 /* Reset all bits in the PCI status register. */ 3504 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3505 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3506 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3507 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3508 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3509 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3510 } 3511 3512 /* Check for PCI Express Uncorrectable Error. */ 3513 if ((status & Y2_IS_PCI_EXP) != 0) { 3514 uint32_t v32; 3515 3516 /* 3517 * On PCI Express bus bridges are called root complexes (RC). 3518 * PCI Express errors are recognized by the root complex too, 3519 * which requests the system to handle the problem. After 3520 * error occurrence it may be that no access to the adapter 3521 * may be performed any longer. 3522 */ 3523 3524 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3525 if ((v32 & PEX_UNSUP_REQ) != 0) { 3526 /* Ignore unsupported request error. */ 3527 device_printf(sc->msk_dev, 3528 "Uncorrectable PCI Express error\n"); 3529 } 3530 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3531 int i; 3532 3533 /* Get TLP header form Log Registers. */ 3534 for (i = 0; i < 4; i++) 3535 tlphead[i] = CSR_PCI_READ_4(sc, 3536 PEX_HEADER_LOG + i * 4); 3537 /* Check for vendor defined broadcast message. */ 3538 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3539 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3540 CSR_WRITE_4(sc, B0_HWE_IMSK, 3541 sc->msk_intrhwemask); 3542 CSR_READ_4(sc, B0_HWE_IMSK); 3543 } 3544 } 3545 /* Clear the interrupt. */ 3546 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3547 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3548 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3549 } 3550 3551 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3552 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3553 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3554 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3555} 3556 3557static __inline void 3558msk_rxput(struct msk_if_softc *sc_if) 3559{ 3560 struct msk_softc *sc; 3561 3562 sc = sc_if->msk_softc; 3563 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3564 bus_dmamap_sync( 3565 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3566 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3568 else 3569 bus_dmamap_sync( 3570 sc_if->msk_cdata.msk_rx_ring_tag, 3571 sc_if->msk_cdata.msk_rx_ring_map, 3572 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3573 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3574 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3575} 3576 3577static int 3578msk_handle_events(struct msk_softc *sc) 3579{ 3580 struct msk_if_softc *sc_if; 3581 int rxput[2]; 3582 struct msk_stat_desc *sd; 3583 uint32_t control, status; 3584 int cons, len, port, rxprog; 3585 3586 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3587 return (0); 3588 3589 /* Sync status LEs. */ 3590 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3591 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3592 3593 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3594 rxprog = 0; 3595 cons = sc->msk_stat_cons; 3596 for (;;) { 3597 sd = &sc->msk_stat_ring[cons]; 3598 control = le32toh(sd->msk_control); 3599 if ((control & HW_OWNER) == 0) 3600 break; 3601 control &= ~HW_OWNER; 3602 sd->msk_control = htole32(control); 3603 status = le32toh(sd->msk_status); 3604 len = control & STLE_LEN_MASK; 3605 port = (control >> 16) & 0x01; 3606 sc_if = sc->msk_if[port]; 3607 if (sc_if == NULL) { 3608 device_printf(sc->msk_dev, "invalid port opcode " 3609 "0x%08x\n", control & STLE_OP_MASK); 3610 continue; 3611 } 3612 3613 switch (control & STLE_OP_MASK) { 3614 case OP_RXVLAN: 3615 sc_if->msk_vtag = ntohs(len); 3616 break; 3617 case OP_RXCHKSVLAN: 3618 sc_if->msk_vtag = ntohs(len); 3619 /* FALLTHROUGH */ 3620 case OP_RXCHKS: 3621 sc_if->msk_csum = status; 3622 break; 3623 case OP_RXSTAT: 3624 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING)) 3625 break; 3626 if (sc_if->msk_framesize > 3627 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3628 msk_jumbo_rxeof(sc_if, status, control, len); 3629 else 3630 msk_rxeof(sc_if, status, control, len); 3631 rxprog++; 3632 /* 3633 * Because there is no way to sync single Rx LE 3634 * put the DMA sync operation off until the end of 3635 * event processing. 3636 */ 3637 rxput[port]++; 3638 /* Update prefetch unit if we've passed water mark. */ 3639 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3640 msk_rxput(sc_if); 3641 rxput[port] = 0; 3642 } 3643 break; 3644 case OP_TXINDEXLE: 3645 if (sc->msk_if[MSK_PORT_A] != NULL) 3646 msk_txeof(sc->msk_if[MSK_PORT_A], 3647 status & STLE_TXA1_MSKL); 3648 if (sc->msk_if[MSK_PORT_B] != NULL) 3649 msk_txeof(sc->msk_if[MSK_PORT_B], 3650 ((status & STLE_TXA2_MSKL) >> 3651 STLE_TXA2_SHIFTL) | 3652 ((len & STLE_TXA2_MSKH) << 3653 STLE_TXA2_SHIFTH)); 3654 break; 3655 default: 3656 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3657 control & STLE_OP_MASK); 3658 break; 3659 } 3660 MSK_INC(cons, sc->msk_stat_count); 3661 if (rxprog > sc->msk_process_limit) 3662 break; 3663 } 3664 3665 sc->msk_stat_cons = cons; 3666 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3667 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3668 3669 if (rxput[MSK_PORT_A] > 0) 3670 msk_rxput(sc->msk_if[MSK_PORT_A]); 3671 if (rxput[MSK_PORT_B] > 0) 3672 msk_rxput(sc->msk_if[MSK_PORT_B]); 3673 3674 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3675} 3676 3677static void 3678msk_intr(void *xsc) 3679{ 3680 struct msk_softc *sc; 3681 struct msk_if_softc *sc_if0, *sc_if1; 3682 if_t ifp0, ifp1; 3683 uint32_t status; 3684 int domore; 3685 3686 sc = xsc; 3687 MSK_LOCK(sc); 3688 3689 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3690 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3691 if (status == 0 || status == 0xffffffff || 3692 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3693 (status & sc->msk_intrmask) == 0) { 3694 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3695 MSK_UNLOCK(sc); 3696 return; 3697 } 3698 3699 sc_if0 = sc->msk_if[MSK_PORT_A]; 3700 sc_if1 = sc->msk_if[MSK_PORT_B]; 3701 ifp0 = ifp1 = NULL; 3702 if (sc_if0 != NULL) 3703 ifp0 = sc_if0->msk_ifp; 3704 if (sc_if1 != NULL) 3705 ifp1 = sc_if1->msk_ifp; 3706 3707 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3708 msk_intr_phy(sc_if0); 3709 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3710 msk_intr_phy(sc_if1); 3711 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3712 msk_intr_gmac(sc_if0); 3713 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3714 msk_intr_gmac(sc_if1); 3715 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3716 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3717 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3718 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3719 CSR_READ_4(sc, B0_IMSK); 3720 } 3721 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3722 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3723 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3724 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3725 CSR_READ_4(sc, B0_IMSK); 3726 } 3727 if ((status & Y2_IS_HW_ERR) != 0) 3728 msk_intr_hwerr(sc); 3729 3730 domore = msk_handle_events(sc); 3731 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3732 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3733 3734 /* Reenable interrupts. */ 3735 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3736 3737 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 && 3738 !if_sendq_empty(ifp0)) 3739 msk_start_locked(ifp0); 3740 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 && 3741 !if_sendq_empty(ifp1)) 3742 msk_start_locked(ifp1); 3743 3744 MSK_UNLOCK(sc); 3745} 3746 3747static void 3748msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3749{ 3750 struct msk_softc *sc; 3751 if_t ifp; 3752 3753 ifp = sc_if->msk_ifp; 3754 sc = sc_if->msk_softc; 3755 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3756 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3757 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3758 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3759 TX_STFW_ENA); 3760 } else { 3761 if (if_getmtu(ifp) > ETHERMTU) { 3762 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3763 CSR_WRITE_4(sc, 3764 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3765 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3766 /* Disable Store & Forward mode for Tx. */ 3767 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3768 TX_STFW_DIS); 3769 } else { 3770 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3771 TX_STFW_ENA); 3772 } 3773 } 3774} 3775 3776static void 3777msk_init(void *xsc) 3778{ 3779 struct msk_if_softc *sc_if = xsc; 3780 3781 MSK_IF_LOCK(sc_if); 3782 msk_init_locked(sc_if); 3783 MSK_IF_UNLOCK(sc_if); 3784} 3785 3786static void 3787msk_init_locked(struct msk_if_softc *sc_if) 3788{ 3789 struct msk_softc *sc; 3790 if_t ifp; 3791 struct mii_data *mii; 3792 uint8_t *eaddr; 3793 uint16_t gmac; 3794 uint32_t reg; 3795 int error; 3796 3797 MSK_IF_LOCK_ASSERT(sc_if); 3798 3799 ifp = sc_if->msk_ifp; 3800 sc = sc_if->msk_softc; 3801 mii = device_get_softc(sc_if->msk_miibus); 3802 3803 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3804 return; 3805 3806 error = 0; 3807 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3808 msk_stop(sc_if); 3809 3810 if (if_getmtu(ifp) < ETHERMTU) 3811 sc_if->msk_framesize = ETHERMTU; 3812 else 3813 sc_if->msk_framesize = if_getmtu(ifp); 3814 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3815 if (if_getmtu(ifp) > ETHERMTU && 3816 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3817 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 3818 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 3819 } 3820 3821 /* GMAC Control reset. */ 3822 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3823 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3824 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3825 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3826 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3827 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3828 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3829 GMC_BYP_RETR_ON); 3830 3831 /* 3832 * Initialize GMAC first such that speed/duplex/flow-control 3833 * parameters are renegotiated when interface is brought up. 3834 */ 3835 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3836 3837 /* Dummy read the Interrupt Source Register. */ 3838 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3839 3840 /* Clear MIB stats. */ 3841 msk_stats_clear(sc_if); 3842 3843 /* Disable FCS. */ 3844 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3845 3846 /* Setup Transmit Control Register. */ 3847 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3848 3849 /* Setup Transmit Flow Control Register. */ 3850 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3851 3852 /* Setup Transmit Parameter Register. */ 3853 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3854 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3855 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3856 3857 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3858 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3859 3860 if (if_getmtu(ifp) > ETHERMTU) 3861 gmac |= GM_SMOD_JUMBO_ENA; 3862 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3863 3864 /* Set station address. */ 3865 eaddr = if_getlladdr(ifp); 3866 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3867 eaddr[0] | (eaddr[1] << 8)); 3868 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3869 eaddr[2] | (eaddr[3] << 8)); 3870 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3871 eaddr[4] | (eaddr[5] << 8)); 3872 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3873 eaddr[0] | (eaddr[1] << 8)); 3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3875 eaddr[2] | (eaddr[3] << 8)); 3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3877 eaddr[4] | (eaddr[5] << 8)); 3878 3879 /* Disable interrupts for counter overflows. */ 3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3881 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3882 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3883 3884 /* Configure Rx MAC FIFO. */ 3885 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3886 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3887 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3888 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3889 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3890 reg |= GMF_RX_OVER_ON; 3891 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3892 3893 /* Set receive filter. */ 3894 msk_rxfilter(sc_if); 3895 3896 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3897 /* Clear flush mask - HW bug. */ 3898 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3899 } else { 3900 /* Flush Rx MAC FIFO on any flow control or error. */ 3901 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3902 GMR_FS_ANY_ERR); 3903 } 3904 3905 /* 3906 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3907 * due to hardware hang on receipt of pause frames. 3908 */ 3909 reg = RX_GMF_FL_THR_DEF + 1; 3910 /* Another magic for Yukon FE+ - From Linux. */ 3911 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3912 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3913 reg = 0x178; 3914 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3915 3916 /* Configure Tx MAC FIFO. */ 3917 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3918 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3919 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3920 3921 /* Configure hardware VLAN tag insertion/stripping. */ 3922 msk_setvlan(sc_if, ifp); 3923 3924 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3925 /* Set Rx Pause threshold. */ 3926 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3927 MSK_ECU_LLPP); 3928 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3929 MSK_ECU_ULPP); 3930 /* Configure store-and-forward for Tx. */ 3931 msk_set_tx_stfwd(sc_if); 3932 } 3933 3934 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3935 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3936 /* Disable dynamic watermark - from Linux. */ 3937 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3938 reg &= ~0x03; 3939 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3940 } 3941 3942 /* 3943 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3944 * arbiter as we don't use Sync Tx queue. 3945 */ 3946 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3947 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3948 /* Enable the RAM Interface Arbiter. */ 3949 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3950 3951 /* Setup RAM buffer. */ 3952 msk_set_rambuffer(sc_if); 3953 3954 /* Disable Tx sync Queue. */ 3955 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3956 3957 /* Setup Tx Queue Bus Memory Interface. */ 3958 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3959 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3960 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3961 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3962 switch (sc->msk_hw_id) { 3963 case CHIP_ID_YUKON_EC_U: 3964 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3965 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3966 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3967 MSK_ECU_TXFF_LEV); 3968 } 3969 break; 3970 case CHIP_ID_YUKON_EX: 3971 /* 3972 * Yukon Extreme seems to have silicon bug for 3973 * automatic Tx checksum calculation capability. 3974 */ 3975 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3976 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3977 F_TX_CHK_AUTO_OFF); 3978 break; 3979 } 3980 3981 /* Setup Rx Queue Bus Memory Interface. */ 3982 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3983 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3984 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3985 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3986 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3987 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3988 /* MAC Rx RAM Read is controlled by hardware. */ 3989 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3990 } 3991 3992 msk_set_prefetch(sc, sc_if->msk_txq, 3993 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3994 msk_init_tx_ring(sc_if); 3995 3996 /* Disable Rx checksum offload and RSS hash. */ 3997 reg = BMU_DIS_RX_RSS_HASH; 3998 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3999 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 4000 reg |= BMU_ENA_RX_CHKSUM; 4001 else 4002 reg |= BMU_DIS_RX_CHKSUM; 4003 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4004 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4005 msk_set_prefetch(sc, sc_if->msk_rxq, 4006 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4007 MSK_JUMBO_RX_RING_CNT - 1); 4008 error = msk_init_jumbo_rx_ring(sc_if); 4009 } else { 4010 msk_set_prefetch(sc, sc_if->msk_rxq, 4011 sc_if->msk_rdata.msk_rx_ring_paddr, 4012 MSK_RX_RING_CNT - 1); 4013 error = msk_init_rx_ring(sc_if); 4014 } 4015 if (error != 0) { 4016 device_printf(sc_if->msk_if_dev, 4017 "initialization failed: no memory for Rx buffers\n"); 4018 msk_stop(sc_if); 4019 return; 4020 } 4021 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4022 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4023 /* Disable flushing of non-ASF packets. */ 4024 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4025 GMF_RX_MACSEC_FLUSH_OFF); 4026 } 4027 4028 /* Configure interrupt handling. */ 4029 if (sc_if->msk_port == MSK_PORT_A) { 4030 sc->msk_intrmask |= Y2_IS_PORT_A; 4031 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4032 } else { 4033 sc->msk_intrmask |= Y2_IS_PORT_B; 4034 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4035 } 4036 /* Configure IRQ moderation mask. */ 4037 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4038 if (sc->msk_int_holdoff > 0) { 4039 /* Configure initial IRQ moderation timer value. */ 4040 CSR_WRITE_4(sc, B2_IRQM_INI, 4041 MSK_USECS(sc, sc->msk_int_holdoff)); 4042 CSR_WRITE_4(sc, B2_IRQM_VAL, 4043 MSK_USECS(sc, sc->msk_int_holdoff)); 4044 /* Start IRQ moderation. */ 4045 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4046 } 4047 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4048 CSR_READ_4(sc, B0_HWE_IMSK); 4049 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4050 CSR_READ_4(sc, B0_IMSK); 4051 4052 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4053 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4054 4055 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4056 mii_mediachg(mii); 4057 4058 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4059} 4060 4061static void 4062msk_set_rambuffer(struct msk_if_softc *sc_if) 4063{ 4064 struct msk_softc *sc; 4065 int ltpp, utpp; 4066 4067 sc = sc_if->msk_softc; 4068 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4069 return; 4070 4071 /* Setup Rx Queue. */ 4072 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4074 sc->msk_rxqstart[sc_if->msk_port] / 8); 4075 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4076 sc->msk_rxqend[sc_if->msk_port] / 8); 4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4078 sc->msk_rxqstart[sc_if->msk_port] / 8); 4079 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4080 sc->msk_rxqstart[sc_if->msk_port] / 8); 4081 4082 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4083 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4084 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4085 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4086 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4087 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4088 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4089 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4090 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4091 4092 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4093 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4094 4095 /* Setup Tx Queue. */ 4096 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4097 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4098 sc->msk_txqstart[sc_if->msk_port] / 8); 4099 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4100 sc->msk_txqend[sc_if->msk_port] / 8); 4101 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4102 sc->msk_txqstart[sc_if->msk_port] / 8); 4103 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4104 sc->msk_txqstart[sc_if->msk_port] / 8); 4105 /* Enable Store & Forward for Tx side. */ 4106 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4107 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4108 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4109} 4110 4111static void 4112msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4113 uint32_t count) 4114{ 4115 4116 /* Reset the prefetch unit. */ 4117 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4118 PREF_UNIT_RST_SET); 4119 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4120 PREF_UNIT_RST_CLR); 4121 /* Set LE base address. */ 4122 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4123 MSK_ADDR_LO(addr)); 4124 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4125 MSK_ADDR_HI(addr)); 4126 /* Set the list last index. */ 4127 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4128 count); 4129 /* Turn on prefetch unit. */ 4130 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4131 PREF_UNIT_OP_ON); 4132 /* Dummy read to ensure write. */ 4133 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4134} 4135 4136static void 4137msk_stop(struct msk_if_softc *sc_if) 4138{ 4139 struct msk_softc *sc; 4140 struct msk_txdesc *txd; 4141 struct msk_rxdesc *rxd; 4142 struct msk_rxdesc *jrxd; 4143 if_t ifp; 4144 uint32_t val; 4145 int i; 4146 4147 MSK_IF_LOCK_ASSERT(sc_if); 4148 sc = sc_if->msk_softc; 4149 ifp = sc_if->msk_ifp; 4150 4151 callout_stop(&sc_if->msk_tick_ch); 4152 sc_if->msk_watchdog_timer = 0; 4153 4154 /* Disable interrupts. */ 4155 if (sc_if->msk_port == MSK_PORT_A) { 4156 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4157 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4158 } else { 4159 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4160 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4161 } 4162 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4163 CSR_READ_4(sc, B0_HWE_IMSK); 4164 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4165 CSR_READ_4(sc, B0_IMSK); 4166 4167 /* Disable Tx/Rx MAC. */ 4168 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4169 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4170 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4171 /* Read again to ensure writing. */ 4172 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4173 /* Update stats and clear counters. */ 4174 msk_stats_update(sc_if); 4175 4176 /* Stop Tx BMU. */ 4177 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4178 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4179 for (i = 0; i < MSK_TIMEOUT; i++) { 4180 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4181 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4182 BMU_STOP); 4183 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4184 } else 4185 break; 4186 DELAY(1); 4187 } 4188 if (i == MSK_TIMEOUT) 4189 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4190 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4191 RB_RST_SET | RB_DIS_OP_MD); 4192 4193 /* Disable all GMAC interrupt. */ 4194 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4195 /* Disable PHY interrupt. */ 4196 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4197 4198 /* Disable the RAM Interface Arbiter. */ 4199 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4200 4201 /* Reset the PCI FIFO of the async Tx queue */ 4202 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4203 BMU_RST_SET | BMU_FIFO_RST); 4204 4205 /* Reset the Tx prefetch units. */ 4206 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4207 PREF_UNIT_RST_SET); 4208 4209 /* Reset the RAM Buffer async Tx queue. */ 4210 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4211 4212 /* Reset Tx MAC FIFO. */ 4213 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4214 /* Set Pause Off. */ 4215 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4216 4217 /* 4218 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4219 * reach the end of packet and since we can't make sure that we have 4220 * incoming data, we must reset the BMU while it is not during a DMA 4221 * transfer. Since it is possible that the Rx path is still active, 4222 * the Rx RAM buffer will be stopped first, so any possible incoming 4223 * data will not trigger a DMA. After the RAM buffer is stopped, the 4224 * BMU is polled until any DMA in progress is ended and only then it 4225 * will be reset. 4226 */ 4227 4228 /* Disable the RAM Buffer receive queue. */ 4229 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4230 for (i = 0; i < MSK_TIMEOUT; i++) { 4231 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4232 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4233 break; 4234 DELAY(1); 4235 } 4236 if (i == MSK_TIMEOUT) 4237 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4238 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4239 BMU_RST_SET | BMU_FIFO_RST); 4240 /* Reset the Rx prefetch unit. */ 4241 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4242 PREF_UNIT_RST_SET); 4243 /* Reset the RAM Buffer receive queue. */ 4244 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4245 /* Reset Rx MAC FIFO. */ 4246 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4247 4248 /* Free Rx and Tx mbufs still in the queues. */ 4249 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4250 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4251 if (rxd->rx_m != NULL) { 4252 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4253 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4254 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4255 rxd->rx_dmamap); 4256 m_freem(rxd->rx_m); 4257 rxd->rx_m = NULL; 4258 } 4259 } 4260 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4261 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4262 if (jrxd->rx_m != NULL) { 4263 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4264 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4265 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4266 jrxd->rx_dmamap); 4267 m_freem(jrxd->rx_m); 4268 jrxd->rx_m = NULL; 4269 } 4270 } 4271 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4272 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4273 if (txd->tx_m != NULL) { 4274 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4275 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4276 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4277 txd->tx_dmamap); 4278 m_freem(txd->tx_m); 4279 txd->tx_m = NULL; 4280 } 4281 } 4282 4283 /* 4284 * Mark the interface down. 4285 */ 4286 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4287 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4288} 4289 4290/* 4291 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4292 * counter clears high 16 bits of the counter such that accessing 4293 * lower 16 bits should be the last operation. 4294 */ 4295#define MSK_READ_MIB32(x, y) \ 4296 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4297 (uint32_t)GMAC_READ_2(sc, x, y)) 4298#define MSK_READ_MIB64(x, y) \ 4299 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4300 (uint64_t)MSK_READ_MIB32(x, y)) 4301 4302static void 4303msk_stats_clear(struct msk_if_softc *sc_if) 4304{ 4305 struct msk_softc *sc; 4306 uint16_t gmac; 4307 int i; 4308 4309 MSK_IF_LOCK_ASSERT(sc_if); 4310 4311 sc = sc_if->msk_softc; 4312 /* Set MIB Clear Counter Mode. */ 4313 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4314 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4315 /* Read all MIB Counters with Clear Mode set. */ 4316 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4317 (void)MSK_READ_MIB32(sc_if->msk_port, i); 4318 /* Clear MIB Clear Counter Mode. */ 4319 gmac &= ~GM_PAR_MIB_CLR; 4320 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4321} 4322 4323static void 4324msk_stats_update(struct msk_if_softc *sc_if) 4325{ 4326 struct msk_softc *sc; 4327 if_t ifp; 4328 struct msk_hw_stats *stats; 4329 uint16_t gmac; 4330 4331 MSK_IF_LOCK_ASSERT(sc_if); 4332 4333 ifp = sc_if->msk_ifp; 4334 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 4335 return; 4336 sc = sc_if->msk_softc; 4337 stats = &sc_if->msk_stats; 4338 /* Set MIB Clear Counter Mode. */ 4339 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4340 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4341 4342 /* Rx stats. */ 4343 stats->rx_ucast_frames += 4344 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4345 stats->rx_bcast_frames += 4346 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4347 stats->rx_pause_frames += 4348 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4349 stats->rx_mcast_frames += 4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4351 stats->rx_crc_errs += 4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4353 stats->rx_good_octets += 4354 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4355 stats->rx_bad_octets += 4356 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4357 stats->rx_runts += 4358 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4359 stats->rx_runt_errs += 4360 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4361 stats->rx_pkts_64 += 4362 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4363 stats->rx_pkts_65_127 += 4364 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4365 stats->rx_pkts_128_255 += 4366 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4367 stats->rx_pkts_256_511 += 4368 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4369 stats->rx_pkts_512_1023 += 4370 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4371 stats->rx_pkts_1024_1518 += 4372 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4373 stats->rx_pkts_1519_max += 4374 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4375 stats->rx_pkts_too_long += 4376 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4377 stats->rx_pkts_jabbers += 4378 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4379 stats->rx_fifo_oflows += 4380 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4381 4382 /* Tx stats. */ 4383 stats->tx_ucast_frames += 4384 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4385 stats->tx_bcast_frames += 4386 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4387 stats->tx_pause_frames += 4388 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4389 stats->tx_mcast_frames += 4390 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4391 stats->tx_octets += 4392 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4393 stats->tx_pkts_64 += 4394 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4395 stats->tx_pkts_65_127 += 4396 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4397 stats->tx_pkts_128_255 += 4398 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4399 stats->tx_pkts_256_511 += 4400 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4401 stats->tx_pkts_512_1023 += 4402 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4403 stats->tx_pkts_1024_1518 += 4404 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4405 stats->tx_pkts_1519_max += 4406 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4407 stats->tx_colls += 4408 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4409 stats->tx_late_colls += 4410 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4411 stats->tx_excess_colls += 4412 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4413 stats->tx_multi_colls += 4414 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4415 stats->tx_single_colls += 4416 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4417 stats->tx_underflows += 4418 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4419 /* Clear MIB Clear Counter Mode. */ 4420 gmac &= ~GM_PAR_MIB_CLR; 4421 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4422} 4423 4424static int 4425msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4426{ 4427 struct msk_softc *sc; 4428 struct msk_if_softc *sc_if; 4429 uint32_t result, *stat; 4430 int off; 4431 4432 sc_if = (struct msk_if_softc *)arg1; 4433 sc = sc_if->msk_softc; 4434 off = arg2; 4435 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4436 4437 MSK_IF_LOCK(sc_if); 4438 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4439 result += *stat; 4440 MSK_IF_UNLOCK(sc_if); 4441 4442 return (sysctl_handle_int(oidp, &result, 0, req)); 4443} 4444 4445static int 4446msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4447{ 4448 struct msk_softc *sc; 4449 struct msk_if_softc *sc_if; 4450 uint64_t result, *stat; 4451 int off; 4452 4453 sc_if = (struct msk_if_softc *)arg1; 4454 sc = sc_if->msk_softc; 4455 off = arg2; 4456 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4457 4458 MSK_IF_LOCK(sc_if); 4459 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4460 result += *stat; 4461 MSK_IF_UNLOCK(sc_if); 4462 4463 return (sysctl_handle_64(oidp, &result, 0, req)); 4464} 4465 4466#undef MSK_READ_MIB32 4467#undef MSK_READ_MIB64 4468 4469#define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4470 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4471 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4472 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4473 "IU", d) 4474#define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4475 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4476 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4477 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4478 "QU", d) 4479 4480static void 4481msk_sysctl_node(struct msk_if_softc *sc_if) 4482{ 4483 struct sysctl_ctx_list *ctx; 4484 struct sysctl_oid_list *child, *schild; 4485 struct sysctl_oid *tree; 4486 4487 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4488 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4489 4490 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4491 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics"); 4492 schild = SYSCTL_CHILDREN(tree); 4493 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 4494 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics"); 4495 child = SYSCTL_CHILDREN(tree); 4496 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4497 child, rx_ucast_frames, "Good unicast frames"); 4498 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4499 child, rx_bcast_frames, "Good broadcast frames"); 4500 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4501 child, rx_pause_frames, "Pause frames"); 4502 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4503 child, rx_mcast_frames, "Multicast frames"); 4504 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4505 child, rx_crc_errs, "CRC errors"); 4506 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4507 child, rx_good_octets, "Good octets"); 4508 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4509 child, rx_bad_octets, "Bad octets"); 4510 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4511 child, rx_pkts_64, "64 bytes frames"); 4512 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4513 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4514 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4515 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4516 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4517 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4519 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4521 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4523 child, rx_pkts_1519_max, "1519 to max frames"); 4524 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4525 child, rx_pkts_too_long, "frames too long"); 4526 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4527 child, rx_pkts_jabbers, "Jabber errors"); 4528 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4529 child, rx_fifo_oflows, "FIFO overflows"); 4530 4531 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 4532 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics"); 4533 child = SYSCTL_CHILDREN(tree); 4534 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4535 child, tx_ucast_frames, "Unicast frames"); 4536 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4537 child, tx_bcast_frames, "Broadcast frames"); 4538 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4539 child, tx_pause_frames, "Pause frames"); 4540 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4541 child, tx_mcast_frames, "Multicast frames"); 4542 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4543 child, tx_octets, "Octets"); 4544 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4545 child, tx_pkts_64, "64 bytes frames"); 4546 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4547 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4548 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4549 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4550 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4551 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4552 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4553 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4554 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4555 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4556 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4557 child, tx_pkts_1519_max, "1519 to max frames"); 4558 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4559 child, tx_colls, "Collisions"); 4560 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4561 child, tx_late_colls, "Late collisions"); 4562 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4563 child, tx_excess_colls, "Excessive collisions"); 4564 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4565 child, tx_multi_colls, "Multiple collisions"); 4566 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4567 child, tx_single_colls, "Single collisions"); 4568 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4569 child, tx_underflows, "FIFO underflows"); 4570} 4571 4572#undef MSK_SYSCTL_STAT32 4573#undef MSK_SYSCTL_STAT64 4574 4575static int 4576sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4577{ 4578 int error, value; 4579 4580 if (!arg1) 4581 return (EINVAL); 4582 value = *(int *)arg1; 4583 error = sysctl_handle_int(oidp, &value, 0, req); 4584 if (error || !req->newptr) 4585 return (error); 4586 if (value < low || value > high) 4587 return (EINVAL); 4588 *(int *)arg1 = value; 4589 4590 return (0); 4591} 4592 4593static int 4594sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4595{ 4596 4597 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4598 MSK_PROC_MAX)); 4599} 4600