1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 */ 31 32/* 33 * Copyright (c) 2006-2015 LSI Corporation. 34 * Copyright (c) 2013-2015 Avago Technologies 35 * 36 * 37 * Name: mpi2.h 38 * Title: MPI Message independent structures and definitions 39 * including System Interface Register Set and 40 * scatter/gather formats. 41 * Creation Date: June 21, 2006 42 * 43 * mpi2.h Version: 02.00.18 44 * 45 * Version History 46 * --------------- 47 * 48 * Date Version Description 49 * -------- -------- ------------------------------------------------------ 50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 51 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 52 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 53 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 54 * Moved ReplyPostHostIndex register to offset 0x6C of the 55 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 56 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 57 * Added union of request descriptors. 58 * Added union of reply descriptors. 59 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 60 * Added define for MPI2_VERSION_02_00. 61 * Fixed the size of the FunctionDependent5 field in the 62 * MPI2_DEFAULT_REPLY structure. 63 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 64 * Removed the MPI-defined Fault Codes and extended the 65 * product specific codes up to 0xEFFF. 66 * Added a sixth key value for the WriteSequence register 67 * and changed the flush value to 0x0. 68 * Added message function codes for Diagnostic Buffer Post 69 * and Diagnsotic Release. 70 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 71 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 72 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 73 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 74 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 75 * Added #defines for marking a reply descriptor as unused. 76 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 77 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 78 * Moved LUN field defines from mpi2_init.h. 79 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 80 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 81 * In all request and reply descriptors, replaced VF_ID 82 * field with MSIxIndex field. 83 * Removed DevHandle field from 84 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 85 * bytes reserved. 86 * Added RAID Accelerator functionality. 87 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 88 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 89 * Added MSI-x index mask and shift for Reply Post Host 90 * Index register. 91 * Added function code for Host Based Discovery Action. 92 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 93 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 94 * Added defines for product-specific range of message 95 * function codes, 0xF0 to 0xFF. 96 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 97 * Added alternative defines for the SGE Direction bit. 98 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 99 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 100 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 101 * -------------------------------------------------------------------------- 102 */ 103 104#ifndef MPI2_H 105#define MPI2_H 106 107/***************************************************************************** 108* 109* MPI Version Definitions 110* 111*****************************************************************************/ 112 113#define MPI2_VERSION_MAJOR (0x02) 114#define MPI2_VERSION_MINOR (0x00) 115#define MPI2_VERSION_MAJOR_MASK (0xFF00) 116#define MPI2_VERSION_MAJOR_SHIFT (8) 117#define MPI2_VERSION_MINOR_MASK (0x00FF) 118#define MPI2_VERSION_MINOR_SHIFT (0) 119#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 120 MPI2_VERSION_MINOR) 121 122#define MPI2_VERSION_02_00 (0x0200) 123 124/* versioning for this MPI header set */ 125#define MPI2_HEADER_VERSION_UNIT (0x12) 126#define MPI2_HEADER_VERSION_DEV (0x00) 127#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 128#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 129#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 130#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 131#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 132 133/***************************************************************************** 134* 135* IOC State Definitions 136* 137*****************************************************************************/ 138 139#define MPI2_IOC_STATE_RESET (0x00000000) 140#define MPI2_IOC_STATE_READY (0x10000000) 141#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 142#define MPI2_IOC_STATE_FAULT (0x40000000) 143 144#define MPI2_IOC_STATE_MASK (0xF0000000) 145#define MPI2_IOC_STATE_SHIFT (28) 146 147/* Fault state range for prodcut specific codes */ 148#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 149#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 150 151/***************************************************************************** 152* 153* System Interface Register Definitions 154* 155*****************************************************************************/ 156 157typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 158{ 159 U32 Doorbell; /* 0x00 */ 160 U32 WriteSequence; /* 0x04 */ 161 U32 HostDiagnostic; /* 0x08 */ 162 U32 Reserved1; /* 0x0C */ 163 U32 DiagRWData; /* 0x10 */ 164 U32 DiagRWAddressLow; /* 0x14 */ 165 U32 DiagRWAddressHigh; /* 0x18 */ 166 U32 Reserved2[5]; /* 0x1C */ 167 U32 HostInterruptStatus; /* 0x30 */ 168 U32 HostInterruptMask; /* 0x34 */ 169 U32 DCRData; /* 0x38 */ 170 U32 DCRAddress; /* 0x3C */ 171 U32 Reserved3[2]; /* 0x40 */ 172 U32 ReplyFreeHostIndex; /* 0x48 */ 173 U32 Reserved4[8]; /* 0x4C */ 174 U32 ReplyPostHostIndex; /* 0x6C */ 175 U32 Reserved5; /* 0x70 */ 176 U32 HCBSize; /* 0x74 */ 177 U32 HCBAddressLow; /* 0x78 */ 178 U32 HCBAddressHigh; /* 0x7C */ 179 U32 Reserved6[16]; /* 0x80 */ 180 U32 RequestDescriptorPostLow; /* 0xC0 */ 181 U32 RequestDescriptorPostHigh; /* 0xC4 */ 182 U32 Reserved7[14]; /* 0xC8 */ 183} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 184 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 185 186/* 187 * Defines for working with the Doorbell register. 188 */ 189#define MPI2_DOORBELL_OFFSET (0x00000000) 190 191/* IOC --> System values */ 192#define MPI2_DOORBELL_USED (0x08000000) 193#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 194#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 195#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 196#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 197 198/* System --> IOC values */ 199#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 200#define MPI2_DOORBELL_FUNCTION_SHIFT (24) 201#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 202#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 203 204/* 205 * Defines for the WriteSequence register 206 */ 207#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 208#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 209#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 210#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 211#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 212#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 213#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 214#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 215#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 216 217/* 218 * Defines for the HostDiagnostic register 219 */ 220#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 221 222#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 223#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 224#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 225 226#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 227#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 228#define MPI2_DIAG_HCB_MODE (0x00000100) 229#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 230#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 231#define MPI2_DIAG_RESET_HISTORY (0x00000020) 232#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 233#define MPI2_DIAG_RESET_ADAPTER (0x00000004) 234#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 235 236/* 237 * Offsets for DiagRWData and address 238 */ 239#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 240#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 241#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 242 243/* 244 * Defines for the HostInterruptStatus register 245 */ 246#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 247#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 248#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 249#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 250#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 251#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 252#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 253 254/* 255 * Defines for the HostInterruptMask register 256 */ 257#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 258#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 259#define MPI2_HIM_REPLY_INT_MASK (0x00000008) 260#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 261#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 262#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 263 264/* 265 * Offsets for DCRData and address 266 */ 267#define MPI2_DCR_DATA_OFFSET (0x00000038) 268#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 269 270/* 271 * Offset for the Reply Free Queue 272 */ 273#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 274 275/* 276 * Defines for the Reply Descriptor Post Queue 277 */ 278#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 279#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 280#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 281#define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 282 283/* 284 * Defines for the HCBSize and address 285 */ 286#define MPI2_HCB_SIZE_OFFSET (0x00000074) 287#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 288#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 289 290#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 291#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 292 293/* 294 * Offsets for the Request Queue 295 */ 296#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 297#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 298 299/***************************************************************************** 300* 301* Message Descriptors 302* 303*****************************************************************************/ 304 305/* Request Descriptors */ 306 307/* Default Request Descriptor */ 308typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 309{ 310 U8 RequestFlags; /* 0x00 */ 311 U8 MSIxIndex; /* 0x01 */ 312 U16 SMID; /* 0x02 */ 313 U16 LMID; /* 0x04 */ 314 U16 DescriptorTypeDependent; /* 0x06 */ 315} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 316 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 317 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 318 319/* defines for the RequestFlags field */ 320#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 321#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 322#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 323#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 324#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 325#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 326 327#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 328 329/* High Priority Request Descriptor */ 330typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 331{ 332 U8 RequestFlags; /* 0x00 */ 333 U8 MSIxIndex; /* 0x01 */ 334 U16 SMID; /* 0x02 */ 335 U16 LMID; /* 0x04 */ 336 U16 Reserved1; /* 0x06 */ 337} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 338 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 339 Mpi2HighPriorityRequestDescriptor_t, 340 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 341 342/* SCSI IO Request Descriptor */ 343typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 344{ 345 U8 RequestFlags; /* 0x00 */ 346 U8 MSIxIndex; /* 0x01 */ 347 U16 SMID; /* 0x02 */ 348 U16 LMID; /* 0x04 */ 349 U16 DevHandle; /* 0x06 */ 350} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 351 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 352 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 353 354/* SCSI Target Request Descriptor */ 355typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 356{ 357 U8 RequestFlags; /* 0x00 */ 358 U8 MSIxIndex; /* 0x01 */ 359 U16 SMID; /* 0x02 */ 360 U16 LMID; /* 0x04 */ 361 U16 IoIndex; /* 0x06 */ 362} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 363 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 364 Mpi2SCSITargetRequestDescriptor_t, 365 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 366 367/* RAID Accelerator Request Descriptor */ 368typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 369{ 370 U8 RequestFlags; /* 0x00 */ 371 U8 MSIxIndex; /* 0x01 */ 372 U16 SMID; /* 0x02 */ 373 U16 LMID; /* 0x04 */ 374 U16 Reserved; /* 0x06 */ 375} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 376 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 377 Mpi2RAIDAcceleratorRequestDescriptor_t, 378 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 379 380/* union of Request Descriptors */ 381typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 382{ 383 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 384 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 385 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 386 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 387 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 388 U64 Words; 389} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 390 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 391 392/* Reply Descriptors */ 393 394/* Default Reply Descriptor */ 395typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 396{ 397 U8 ReplyFlags; /* 0x00 */ 398 U8 MSIxIndex; /* 0x01 */ 399 U16 DescriptorTypeDependent1; /* 0x02 */ 400 U32 DescriptorTypeDependent2; /* 0x04 */ 401} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 402 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 403 404/* defines for the ReplyFlags field */ 405#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 406#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 407#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 408#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 409#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 410#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 411#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 412 413/* values for marking a reply descriptor as unused */ 414#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 415#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 416 417/* Address Reply Descriptor */ 418typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 419{ 420 U8 ReplyFlags; /* 0x00 */ 421 U8 MSIxIndex; /* 0x01 */ 422 U16 SMID; /* 0x02 */ 423 U32 ReplyFrameAddress; /* 0x04 */ 424} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 425 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 426 427#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 428 429/* SCSI IO Success Reply Descriptor */ 430typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 431{ 432 U8 ReplyFlags; /* 0x00 */ 433 U8 MSIxIndex; /* 0x01 */ 434 U16 SMID; /* 0x02 */ 435 U16 TaskTag; /* 0x04 */ 436 U16 Reserved1; /* 0x06 */ 437} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 438 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 439 Mpi2SCSIIOSuccessReplyDescriptor_t, 440 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 441 442/* TargetAssist Success Reply Descriptor */ 443typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 444{ 445 U8 ReplyFlags; /* 0x00 */ 446 U8 MSIxIndex; /* 0x01 */ 447 U16 SMID; /* 0x02 */ 448 U8 SequenceNumber; /* 0x04 */ 449 U8 Reserved1; /* 0x05 */ 450 U16 IoIndex; /* 0x06 */ 451} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 452 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 453 Mpi2TargetAssistSuccessReplyDescriptor_t, 454 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 455 456/* Target Command Buffer Reply Descriptor */ 457typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 458{ 459 U8 ReplyFlags; /* 0x00 */ 460 U8 MSIxIndex; /* 0x01 */ 461 U8 VP_ID; /* 0x02 */ 462 U8 Flags; /* 0x03 */ 463 U16 InitiatorDevHandle; /* 0x04 */ 464 U16 IoIndex; /* 0x06 */ 465} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 466 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 467 Mpi2TargetCommandBufferReplyDescriptor_t, 468 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 469 470/* defines for Flags field */ 471#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 472 473/* RAID Accelerator Success Reply Descriptor */ 474typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 475{ 476 U8 ReplyFlags; /* 0x00 */ 477 U8 MSIxIndex; /* 0x01 */ 478 U16 SMID; /* 0x02 */ 479 U32 Reserved; /* 0x04 */ 480} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 481 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 482 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 483 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 484 485/* union of Reply Descriptors */ 486typedef union _MPI2_REPLY_DESCRIPTORS_UNION 487{ 488 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 489 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 490 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 491 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 492 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 493 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 494 U64 Words; 495} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 496 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 497 498/***************************************************************************** 499* 500* Message Functions 501* 502*****************************************************************************/ 503 504#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 505#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 506#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 507#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 508#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 509#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 510#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 511#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 512#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 513#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 514#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 515#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 516#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 517#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 518#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 519#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 520#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 521#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 522#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 523#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 524#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 525#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 526#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 527#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 528#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 529#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 530#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 531#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 532#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 533#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 534 535/* Doorbell functions */ 536#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 537#define MPI2_FUNCTION_HANDSHAKE (0x42) 538 539/***************************************************************************** 540* 541* IOC Status Values 542* 543*****************************************************************************/ 544 545/* mask for IOCStatus status value */ 546#define MPI2_IOCSTATUS_MASK (0x7FFF) 547 548/**************************************************************************** 549* Common IOCStatus values for all replies 550****************************************************************************/ 551 552#define MPI2_IOCSTATUS_SUCCESS (0x0000) 553#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 554#define MPI2_IOCSTATUS_BUSY (0x0002) 555#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 556#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 557#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 558#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 559#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 560#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 561#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 562 563/**************************************************************************** 564* Config IOCStatus values 565****************************************************************************/ 566 567#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 568#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 569#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 570#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 571#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 572#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 573 574/**************************************************************************** 575* SCSI IO Reply 576****************************************************************************/ 577 578#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 579#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 580#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 581#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 582#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 583#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 584#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 585#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 586#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 587#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 588#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 589#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 590 591/**************************************************************************** 592* For use by SCSI Initiator and SCSI Target end-to-end data protection 593****************************************************************************/ 594 595#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 596#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 597#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 598 599/**************************************************************************** 600* SCSI Target values 601****************************************************************************/ 602 603#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 604#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 605#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 606#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 607#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 608#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 609#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 610#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 611#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 612#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 613 614/**************************************************************************** 615* Serial Attached SCSI values 616****************************************************************************/ 617 618#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 619#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 620 621/**************************************************************************** 622* Diagnostic Buffer Post / Diagnostic Release values 623****************************************************************************/ 624 625#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 626 627/**************************************************************************** 628* RAID Accelerator values 629****************************************************************************/ 630 631#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 632 633/**************************************************************************** 634* IOCStatus flag to indicate that log info is available 635****************************************************************************/ 636 637#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 638 639/**************************************************************************** 640* IOCLogInfo Types 641****************************************************************************/ 642 643#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 644#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 645#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 646#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 647#define MPI2_IOCLOGINFO_TYPE_FC (0x2) 648#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 649#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 650#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 651 652/***************************************************************************** 653* 654* Standard Message Structures 655* 656*****************************************************************************/ 657 658/**************************************************************************** 659* Request Message Header for all request messages 660****************************************************************************/ 661 662typedef struct _MPI2_REQUEST_HEADER 663{ 664 U16 FunctionDependent1; /* 0x00 */ 665 U8 ChainOffset; /* 0x02 */ 666 U8 Function; /* 0x03 */ 667 U16 FunctionDependent2; /* 0x04 */ 668 U8 FunctionDependent3; /* 0x06 */ 669 U8 MsgFlags; /* 0x07 */ 670 U8 VP_ID; /* 0x08 */ 671 U8 VF_ID; /* 0x09 */ 672 U16 Reserved1; /* 0x0A */ 673} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 674 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 675 676/**************************************************************************** 677* Default Reply 678****************************************************************************/ 679 680typedef struct _MPI2_DEFAULT_REPLY 681{ 682 U16 FunctionDependent1; /* 0x00 */ 683 U8 MsgLength; /* 0x02 */ 684 U8 Function; /* 0x03 */ 685 U16 FunctionDependent2; /* 0x04 */ 686 U8 FunctionDependent3; /* 0x06 */ 687 U8 MsgFlags; /* 0x07 */ 688 U8 VP_ID; /* 0x08 */ 689 U8 VF_ID; /* 0x09 */ 690 U16 Reserved1; /* 0x0A */ 691 U16 FunctionDependent5; /* 0x0C */ 692 U16 IOCStatus; /* 0x0E */ 693 U32 IOCLogInfo; /* 0x10 */ 694} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 695 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 696 697/* common version structure/union used in messages and configuration pages */ 698 699typedef struct _MPI2_VERSION_STRUCT 700{ 701 U8 Dev; /* 0x00 */ 702 U8 Unit; /* 0x01 */ 703 U8 Minor; /* 0x02 */ 704 U8 Major; /* 0x03 */ 705} MPI2_VERSION_STRUCT; 706 707typedef union _MPI2_VERSION_UNION 708{ 709 MPI2_VERSION_STRUCT Struct; 710 U32 Word; 711} MPI2_VERSION_UNION; 712 713/* LUN field defines, common to many structures */ 714#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 715#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 716#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 717#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 718#define MPI2_LUN_LEVEL_1_WORD (0xFF00) 719#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 720 721/***************************************************************************** 722* 723* Fusion-MPT MPI Scatter Gather Elements 724* 725*****************************************************************************/ 726 727/**************************************************************************** 728* MPI Simple Element structures 729****************************************************************************/ 730 731typedef struct _MPI2_SGE_SIMPLE32 732{ 733 U32 FlagsLength; 734 U32 Address; 735} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 736 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 737 738typedef struct _MPI2_SGE_SIMPLE64 739{ 740 U32 FlagsLength; 741 U64 Address; 742} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 743 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 744 745typedef struct _MPI2_SGE_SIMPLE_UNION 746{ 747 U32 FlagsLength; 748 union 749 { 750 U32 Address32; 751 U64 Address64; 752 } u; 753} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 754 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 755 756/**************************************************************************** 757* MPI Chain Element structures 758****************************************************************************/ 759 760typedef struct _MPI2_SGE_CHAIN32 761{ 762 U16 Length; 763 U8 NextChainOffset; 764 U8 Flags; 765 U32 Address; 766} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 767 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 768 769typedef struct _MPI2_SGE_CHAIN64 770{ 771 U16 Length; 772 U8 NextChainOffset; 773 U8 Flags; 774 U64 Address; 775} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 776 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 777 778typedef struct _MPI2_SGE_CHAIN_UNION 779{ 780 U16 Length; 781 U8 NextChainOffset; 782 U8 Flags; 783 union 784 { 785 U32 Address32; 786 U64 Address64; 787 } u; 788} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 789 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 790 791/**************************************************************************** 792* MPI Transaction Context Element structures 793****************************************************************************/ 794 795typedef struct _MPI2_SGE_TRANSACTION32 796{ 797 U8 Reserved; 798 U8 ContextSize; 799 U8 DetailsLength; 800 U8 Flags; 801 U32 TransactionContext[1]; 802 U32 TransactionDetails[1]; 803} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 804 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 805 806typedef struct _MPI2_SGE_TRANSACTION64 807{ 808 U8 Reserved; 809 U8 ContextSize; 810 U8 DetailsLength; 811 U8 Flags; 812 U32 TransactionContext[2]; 813 U32 TransactionDetails[1]; 814} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 815 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 816 817typedef struct _MPI2_SGE_TRANSACTION96 818{ 819 U8 Reserved; 820 U8 ContextSize; 821 U8 DetailsLength; 822 U8 Flags; 823 U32 TransactionContext[3]; 824 U32 TransactionDetails[1]; 825} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 826 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 827 828typedef struct _MPI2_SGE_TRANSACTION128 829{ 830 U8 Reserved; 831 U8 ContextSize; 832 U8 DetailsLength; 833 U8 Flags; 834 U32 TransactionContext[4]; 835 U32 TransactionDetails[1]; 836} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 837 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 838 839typedef struct _MPI2_SGE_TRANSACTION_UNION 840{ 841 U8 Reserved; 842 U8 ContextSize; 843 U8 DetailsLength; 844 U8 Flags; 845 union 846 { 847 U32 TransactionContext32[1]; 848 U32 TransactionContext64[2]; 849 U32 TransactionContext96[3]; 850 U32 TransactionContext128[4]; 851 } u; 852 U32 TransactionDetails[1]; 853} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 854 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 855 856/**************************************************************************** 857* MPI SGE union for IO SGL's 858****************************************************************************/ 859 860typedef struct _MPI2_MPI_SGE_IO_UNION 861{ 862 union 863 { 864 MPI2_SGE_SIMPLE_UNION Simple; 865 MPI2_SGE_CHAIN_UNION Chain; 866 } u; 867} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 868 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 869 870/**************************************************************************** 871* MPI SGE union for SGL's with Simple and Transaction elements 872****************************************************************************/ 873 874typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 875{ 876 union 877 { 878 MPI2_SGE_SIMPLE_UNION Simple; 879 MPI2_SGE_TRANSACTION_UNION Transaction; 880 } u; 881} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 882 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 883 884/**************************************************************************** 885* All MPI SGE types union 886****************************************************************************/ 887 888typedef struct _MPI2_MPI_SGE_UNION 889{ 890 union 891 { 892 MPI2_SGE_SIMPLE_UNION Simple; 893 MPI2_SGE_CHAIN_UNION Chain; 894 MPI2_SGE_TRANSACTION_UNION Transaction; 895 } u; 896} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 897 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 898 899/**************************************************************************** 900* MPI SGE field definition and masks 901****************************************************************************/ 902 903/* Flags field bit definitions */ 904 905#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 906#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 907#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 908#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 909#define MPI2_SGE_FLAGS_DIRECTION (0x04) 910#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 911#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 912 913#define MPI2_SGE_FLAGS_SHIFT (24) 914 915#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 916#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 917 918/* Element Type */ 919 920#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 921#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 922#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 923#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 924 925/* Address location */ 926 927#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 928 929/* Direction */ 930 931#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 932#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 933 934#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 935#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 936 937/* Address Size */ 938 939#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 940#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 941 942/* Context Size */ 943 944#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 945#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 946#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 947#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 948 949#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 950#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 951 952/**************************************************************************** 953* MPI SGE operation Macros 954****************************************************************************/ 955 956/* SIMPLE FlagsLength manipulations... */ 957#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 958#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 959#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 960#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 961 962#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 963 964#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 965#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 966#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 967 968/* CAUTION - The following are READ-MODIFY-WRITE! */ 969#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 970#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 971 972#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 973 974/***************************************************************************** 975* 976* Fusion-MPT IEEE Scatter Gather Elements 977* 978*****************************************************************************/ 979 980/**************************************************************************** 981* IEEE Simple Element structures 982****************************************************************************/ 983 984typedef struct _MPI2_IEEE_SGE_SIMPLE32 985{ 986 U32 Address; 987 U32 FlagsLength; 988} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 989 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 990 991typedef struct _MPI2_IEEE_SGE_SIMPLE64 992{ 993 U64 Address; 994 U32 Length; 995 U16 Reserved1; 996 U8 Reserved2; 997 U8 Flags; 998} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 999 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1000 1001typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1002{ 1003 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1004 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1005} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1006 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1007 1008/**************************************************************************** 1009* IEEE Chain Element structures 1010****************************************************************************/ 1011 1012typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1013 1014typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1015 1016typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1017{ 1018 MPI2_IEEE_SGE_CHAIN32 Chain32; 1019 MPI2_IEEE_SGE_CHAIN64 Chain64; 1020} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1021 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1022 1023/**************************************************************************** 1024* All IEEE SGE types union 1025****************************************************************************/ 1026 1027typedef struct _MPI2_IEEE_SGE_UNION 1028{ 1029 union 1030 { 1031 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1032 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1033 } u; 1034} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1035 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1036 1037/**************************************************************************** 1038* IEEE SGE field definitions and masks 1039****************************************************************************/ 1040 1041/* Flags field bit definitions */ 1042 1043#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1044 1045#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1046 1047#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1048 1049/* Element Type */ 1050 1051#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1052#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1053 1054/* Data Location Address Space */ 1055 1056#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1057#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */ 1058#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */ 1059#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1060#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */ 1061#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */ 1062 1063/**************************************************************************** 1064* IEEE SGE operation Macros 1065****************************************************************************/ 1066 1067/* SIMPLE FlagsLength manipulations... */ 1068#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1069#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1070#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1071 1072#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1073 1074#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1075#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1076#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1077 1078/* CAUTION - The following are READ-MODIFY-WRITE! */ 1079#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1080#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1081 1082/***************************************************************************** 1083* 1084* Fusion-MPT MPI/IEEE Scatter Gather Unions 1085* 1086*****************************************************************************/ 1087 1088typedef union _MPI2_SIMPLE_SGE_UNION 1089{ 1090 MPI2_SGE_SIMPLE_UNION MpiSimple; 1091 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1092} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1093 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1094 1095typedef union _MPI2_SGE_IO_UNION 1096{ 1097 MPI2_SGE_SIMPLE_UNION MpiSimple; 1098 MPI2_SGE_CHAIN_UNION MpiChain; 1099 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1100 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1101} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1102 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1103 1104/**************************************************************************** 1105* 1106* Values for SGLFlags field, used in many request messages with an SGL 1107* 1108****************************************************************************/ 1109 1110/* values for MPI SGL Data Location Address Space subfield */ 1111#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1112#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1113#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1114#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1115#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1116/* values for SGL Type subfield */ 1117#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1118#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1119#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1120#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1121 1122#endif 1123