162587Sitojun/*- 278064Sume * Copyright 2000-2020 Broadcom Inc. All rights reserved. 362587Sitojun * 4139826Simp * Redistribution and use in source and binary forms, with or without 562587Sitojun * modification, are permitted provided that the following conditions 662587Sitojun * are met: 7120941Sume * 1. Redistributions of source code must retain the above copyright 862587Sitojun * notice, this list of conditions and the following disclaimer. 962587Sitojun * 2. Redistributions in binary form must reproduce the above copyright 1062587Sitojun * notice, this list of conditions and the following disclaimer in the 1162587Sitojun * documentation and/or other materials provided with the distribution. 1262587Sitojun * 3. Neither the name of the author nor the names of any co-contributors 1362587Sitojun * may be used to endorse or promote products derived from this software 1462587Sitojun * without specific prior written permission. 1562587Sitojun * 1662587Sitojun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1762587Sitojun * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1862587Sitojun * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19120941Sume * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2062587Sitojun * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2162587Sitojun * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2262587Sitojun * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2362587Sitojun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2462587Sitojun * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2562587Sitojun * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2662587Sitojun * SUCH DAMAGE. 2762587Sitojun * 2862587Sitojun * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 2962587Sitojun */ 3062587Sitojun 3162587Sitojun/* 3262587Sitojun * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3362587Sitojun * 3462587Sitojun * 3562587Sitojun * Name: mpi2.h 3662587Sitojun * Title: MPI Message independent structures and definitions 3762587Sitojun * including System Interface Register Set and 3878064Sume * scatter/gather formats. 39148385Sume * Creation Date: June 21, 2006 4062587Sitojun * 4162587Sitojun * mpi2.h Version: 02.00.52 4262587Sitojun * 4362587Sitojun * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 4462587Sitojun * prefix are for use only on MPI v2.5 products, and must not be used 4562587Sitojun * with MPI v2.0 products. Unless otherwise noted, names beginning with 4662587Sitojun * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 4762587Sitojun * 4862587Sitojun * Version History 49148385Sume * --------------- 50148385Sume * 51148385Sume * Date Version Description 52148385Sume * -------- -------- ------------------------------------------------------ 53148385Sume * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 54148385Sume * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 55121343Sume * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 56138184Sgnn * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 57138184Sgnn * Moved ReplyPostHostIndex register to offset 0x6C of the 58121343Sume * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 59121343Sume * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 60121343Sume * Added union of request descriptors. 61121343Sume * Added union of reply descriptors. 62121343Sume * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 63121343Sume * Added define for MPI2_VERSION_02_00. 64121343Sume * Fixed the size of the FunctionDependent5 field in the 65121161Sume * MPI2_DEFAULT_REPLY structure. 66121161Sume * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 67121161Sume * Removed the MPI-defined Fault Codes and extended the 6862587Sitojun * product specific codes up to 0xEFFF. 6962587Sitojun * Added a sixth key value for the WriteSequence register 70121161Sume * and changed the flush value to 0x0. 71121161Sume * Added message function codes for Diagnostic Buffer Post 72121161Sume * and Diagnsotic Release. 73121343Sume * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 74121161Sume * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 75121161Sume * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 76121161Sume * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 77121161Sume * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 7862587Sitojun * Added #defines for marking a reply descriptor as unused. 7962587Sitojun * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 8062587Sitojun * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 81121161Sume * Moved LUN field defines from mpi2_init.h. 8262587Sitojun * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 83121161Sume * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 84121161Sume * In all request and reply descriptors, replaced VF_ID 8562587Sitojun * field with MSIxIndex field. 8662587Sitojun * Removed DevHandle field from 8762587Sitojun * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 8862587Sitojun * bytes reserved. 8962587Sitojun * Added RAID Accelerator functionality. 90121315Sume * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 91121161Sume * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 9262587Sitojun * Added MSI-x index mask and shift for Reply Post Host 9362587Sitojun * Index register. 94121161Sume * Added function code for Host Based Discovery Action. 95121161Sume * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 9662587Sitojun * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 9762587Sitojun * Added defines for product-specific range of message 98121161Sume * function codes, 0xF0 to 0xFF. 9962587Sitojun * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 10062587Sitojun * Added alternative defines for the SGE Direction bit. 101121161Sume * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 102121161Sume * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 103121161Sume * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 104121161Sume * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 105121161Sume * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 106121161Sume * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 107121161Sume * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 108121161Sume * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 10962587Sitojun * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 11062587Sitojun * Incorporating additions for MPI v2.5. 11162587Sitojun * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 112121161Sume * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 11362587Sitojun * Added Hard Reset delay timings. 114138184Sgnn * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 11562587Sitojun * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 116138184Sgnn * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 11762587Sitojun * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 118138184Sgnn * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 119138184Sgnn * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 120138184Sgnn * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 121138184Sgnn * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 122138184Sgnn * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 123120856Sume * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 124138184Sgnn * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 12562587Sitojun * 11-18-14 02.00.36 Updated copyright information. 12662587Sitojun * Bumped MPI2_HEADER_VERSION_UNIT. 12762587Sitojun * 03-16-15 02.00.37 Updated for MPI v2.6. 12862587Sitojun * Bumped MPI2_HEADER_VERSION_UNIT. 12962587Sitojun * Added Scratchpad registers and 13062587Sitojun * AtomicRequestDescriptorPost register to 13162587Sitojun * MPI2_SYSTEM_INTERFACE_REGS. 13262587Sitojun * Added MPI2_DIAG_SBR_RELOAD. 133120941Sume * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. 13462587Sitojun * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 13562587Sitojun * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT 136121343Sume * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 13762587Sitojun * Added V7 HostDiagnostic register defines 138121161Sume * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 139121161Sume * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 140121315Sume * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 141121315Sume * to be unique within first 32 characters. 142121315Sume * Removed AHCI support. 143121315Sume * Removed SOP support. 144121315Sume * Bumped MPI2_HEADER_VERSION_UNIT. 145121315Sume * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 146138184Sgnn * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 147138184Sgnn * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 148121315Sume * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. 149121315Sume * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 150121315Sume * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. 15162587Sitojun * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. 152121161Sume * 07-22-18 02.00.51 Added SECURE_BOOT define. 15362587Sitojun * Bumped MPI2_HEADER_VERSION_UNIT 15462587Sitojun * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT. 15562587Sitojun * -------------------------------------------------------------------------- 15662587Sitojun */ 15762587Sitojun 15862587Sitojun#ifndef MPI2_H 159138184Sgnn#define MPI2_H 160138184Sgnn 161120856Sume/***************************************************************************** 16262587Sitojun* 16362587Sitojun* MPI Version Definitions 16462587Sitojun* 16562587Sitojun*****************************************************************************/ 16662587Sitojun 16762587Sitojun#define MPI2_VERSION_MAJOR_MASK (0xFF00) 16862587Sitojun#define MPI2_VERSION_MAJOR_SHIFT (8) 169121161Sume#define MPI2_VERSION_MINOR_MASK (0x00FF) 17062587Sitojun#define MPI2_VERSION_MINOR_SHIFT (0) 17162587Sitojun 172121343Sume/* major version for all MPI v2.x */ 173138184Sgnn#define MPI2_VERSION_MAJOR (0x02) 17462587Sitojun 175120856Sume/* minor version for MPI v2.0 compatible products */ 17662587Sitojun#define MPI2_VERSION_MINOR (0x00) 17762587Sitojun#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 17862587Sitojun MPI2_VERSION_MINOR) 17962587Sitojun#define MPI2_VERSION_02_00 (0x0200) 18062587Sitojun 181121161Sume/* minor version for MPI v2.5 compatible products */ 18262587Sitojun#define MPI25_VERSION_MINOR (0x05) 183138184Sgnn#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 184138184Sgnn MPI25_VERSION_MINOR) 185121161Sume#define MPI2_VERSION_02_05 (0x0205) 186121161Sume 187138184Sgnn/* minor version for MPI v2.6 compatible products */ 188138184Sgnn#define MPI26_VERSION_MINOR (0x06) 189120856Sume#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 190138184Sgnn MPI26_VERSION_MINOR) 19162587Sitojun#define MPI2_VERSION_02_06 (0x0206) 192121343Sume 193121161Sume/* Unit and Dev versioning for this MPI header set */ 194121343Sume#define MPI2_HEADER_VERSION_UNIT (0x34) 19562587Sitojun#define MPI2_HEADER_VERSION_DEV (0x00) 196138184Sgnn#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 197120856Sume#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 19862587Sitojun#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 19962587Sitojun#define MPI2_HEADER_VERSION_DEV_SHIFT (0) 20062587Sitojun#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 20162587Sitojun 20262587Sitojun/***************************************************************************** 20362587Sitojun* 20462587Sitojun* IOC State Definitions 20562587Sitojun* 206120941Sume*****************************************************************************/ 20762587Sitojun 20862587Sitojun#define MPI2_IOC_STATE_RESET (0x00000000) 20962587Sitojun#define MPI2_IOC_STATE_READY (0x10000000) 210121315Sume#define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 211121315Sume#define MPI2_IOC_STATE_FAULT (0x40000000) 21262587Sitojun 21362587Sitojun#define MPI2_IOC_STATE_MASK (0xF0000000) 21462587Sitojun#define MPI2_IOC_STATE_SHIFT (28) 21562587Sitojun 21662587Sitojun/* Fault state range for prodcut specific codes */ 21762587Sitojun#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 21862587Sitojun#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 21962587Sitojun 22062587Sitojun/***************************************************************************** 22162587Sitojun* 22262587Sitojun* System Interface Register Definitions 22362587Sitojun* 22462587Sitojun*****************************************************************************/ 22562587Sitojun 22662587Sitojuntypedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 227121315Sume{ 228121315Sume U32 Doorbell; /* 0x00 */ 22962587Sitojun U32 WriteSequence; /* 0x04 */ 23062587Sitojun U32 HostDiagnostic; /* 0x08 */ 23162587Sitojun U32 Reserved1; /* 0x0C */ 23262587Sitojun U32 DiagRWData; /* 0x10 */ 23362587Sitojun U32 DiagRWAddressLow; /* 0x14 */ 23462587Sitojun U32 DiagRWAddressHigh; /* 0x18 */ 235121315Sume U32 Reserved2[5]; /* 0x1C */ 236121315Sume U32 HostInterruptStatus; /* 0x30 */ 23762587Sitojun U32 HostInterruptMask; /* 0x34 */ 23862587Sitojun U32 DCRData; /* 0x38 */ 23962587Sitojun U32 DCRAddress; /* 0x3C */ 24062587Sitojun U32 Reserved3[2]; /* 0x40 */ 24162587Sitojun U32 ReplyFreeHostIndex; /* 0x48 */ 24262587Sitojun U32 Reserved4[8]; /* 0x4C */ 24362587Sitojun U32 ReplyPostHostIndex; /* 0x6C */ 24462587Sitojun U32 Reserved5; /* 0x70 */ 24562587Sitojun U32 HCBSize; /* 0x74 */ 24662587Sitojun U32 HCBAddressLow; /* 0x78 */ 24762587Sitojun U32 HCBAddressHigh; /* 0x7C */ 24862587Sitojun U32 Reserved6[12]; /* 0x80 */ 24962587Sitojun U32 Scratchpad[4]; /* 0xB0 */ 250121315Sume U32 RequestDescriptorPostLow; /* 0xC0 */ 251121315Sume U32 RequestDescriptorPostHigh; /* 0xC4 */ 252121315Sume U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ 253121315Sume U32 Reserved7[13]; /* 0xCC */ 25493128Sume} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 255121315Sume Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 25662587Sitojun 257121315Sume/* 258121315Sume * Defines for working with the Doorbell register. 25962587Sitojun */ 26062587Sitojun#define MPI2_DOORBELL_OFFSET (0x00000000) 26162587Sitojun 26262587Sitojun/* IOC --> System values */ 26362587Sitojun#define MPI2_DOORBELL_USED (0x08000000) 26462587Sitojun#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 26562587Sitojun#define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 26662587Sitojun#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 26762587Sitojun#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 26862587Sitojun 269138184Sgnn/* System --> IOC values */ 270121161Sume#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 27162587Sitojun#define MPI2_DOORBELL_FUNCTION_SHIFT (24) 27262587Sitojun#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 27362587Sitojun#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 274121343Sume 27562587Sitojun/* 276121315Sume * Defines for the WriteSequence register 27762587Sitojun */ 278121161Sume#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 279121161Sume#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 280120941Sume#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 281121315Sume#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 282121161Sume#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 28362587Sitojun#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 284121343Sume#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 28562587Sitojun#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 28662587Sitojun#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 28762587Sitojun 28862587Sitojun/* 289121161Sume * Defines for the HostDiagnostic register 29062587Sitojun */ 291121343Sume#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 292121343Sume 293121161Sume#define MPI26_DIAG_SECURE_BOOT (0x80000000) 294121343Sume 29562587Sitojun#define MPI2_DIAG_SBR_RELOAD (0x00002000) 296120856Sume 29762587Sitojun#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 29862587Sitojun#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 29962587Sitojun#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 30062587Sitojun 30162587Sitojun/* Defines for V7A/V7R HostDiagnostic Register */ 30262587Sitojun#define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 303121343Sume#define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 304121343Sume#define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 305121161Sume#define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 306121161Sume 307121161Sume#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 308121161Sume#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 309121161Sume#define MPI2_DIAG_HCB_MODE (0x00000100) 310121161Sume#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 311121161Sume#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 312121343Sume#define MPI2_DIAG_RESET_HISTORY (0x00000020) 313121343Sume#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 314121343Sume#define MPI2_DIAG_RESET_ADAPTER (0x00000004) 315121343Sume#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 316121343Sume 317121343Sume/* 318121343Sume * Offsets for DiagRWData and address 319121343Sume */ 32062587Sitojun#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 321148385Sume#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 322148385Sume#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 323148385Sume 324148385Sume/* 325148385Sume * Defines for the HostInterruptStatus register 326148385Sume */ 327148385Sume#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 328148385Sume#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 329148385Sume#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 330148385Sume#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 331148385Sume#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 332148385Sume#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 333148385Sume#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 334148385Sume 335148385Sume/* 336148385Sume * Defines for the HostInterruptMask register 337148385Sume */ 338148385Sume#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 339148385Sume#define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 340148385Sume#define MPI2_HIM_REPLY_INT_MASK (0x00000008) 341148385Sume#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 342148385Sume#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 343148385Sume#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 344148385Sume 345148385Sume/* 346148385Sume * Offsets for DCRData and address 347148385Sume */ 348148385Sume#define MPI2_DCR_DATA_OFFSET (0x00000038) 349148385Sume#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 350148385Sume 351148385Sume/* 352148385Sume * Offset for the Reply Free Queue 353148385Sume */ 354148385Sume#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 355148385Sume 356148385Sume/* 357148385Sume * Defines for the Reply Descriptor Post Queue 358148385Sume */ 359148385Sume#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 360148385Sume#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 361148385Sume#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 362148385Sume#define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 363148385Sume#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 364148385Sume 365148385Sume/* 366148385Sume * Defines for the HCBSize and address 367148385Sume */ 368148385Sume#define MPI2_HCB_SIZE_OFFSET (0x00000074) 369148385Sume#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 370148385Sume#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 371148385Sume 372148385Sume#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 373148385Sume#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 374148385Sume 375148385Sume/* 376148385Sume * Offsets for the Scratchpad registers 377148385Sume */ 378148385Sume#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 379148385Sume#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 380148385Sume#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 381148385Sume#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 382148385Sume 383148385Sume/* 384148385Sume * Offsets for the Request Descriptor Post Queue 385148385Sume */ 386148385Sume#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 387148385Sume#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 388148385Sume#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 389148385Sume 390148385Sume/* Hard Reset delay timings */ 391148385Sume#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 392148385Sume#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 393148385Sume#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 394148385Sume 395148385Sume/***************************************************************************** 396148385Sume* 397148385Sume* Message Descriptors 398148385Sume* 399148385Sume*****************************************************************************/ 400148385Sume 401148385Sume/* Request Descriptors */ 402148385Sume 403148385Sume/* Default Request Descriptor */ 404148385Sumetypedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 405148385Sume{ 406148385Sume U8 RequestFlags; /* 0x00 */ 407148385Sume U8 MSIxIndex; /* 0x01 */ 408148385Sume U16 SMID; /* 0x02 */ 409148385Sume U16 LMID; /* 0x04 */ 410148385Sume U16 DescriptorTypeDependent; /* 0x06 */ 411148385Sume} MPI2_DEFAULT_REQUEST_DESCRIPTOR, 412148385Sume MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 413148396Sume Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 414148385Sume 415148396Sume/* defines for the RequestFlags field */ 416148396Sume#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 417148396Sume#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ 418148396Sume#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 419148385Sume#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 420148385Sume#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 421148385Sume#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 422148385Sume#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 423148385Sume#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 424148385Sume#define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 425148385Sume 426148385Sume#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 427148385Sume 428148385Sume/* High Priority Request Descriptor */ 429148385Sumetypedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 430148385Sume{ 431148399Sume U8 RequestFlags; /* 0x00 */ 432148396Sume U8 MSIxIndex; /* 0x01 */ 433148385Sume U16 SMID; /* 0x02 */ 434148399Sume U16 LMID; /* 0x04 */ 435148385Sume U16 Reserved1; /* 0x06 */ 436148385Sume} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 437148396Sume MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 438148385Sume Mpi2HighPriorityRequestDescriptor_t, 439148385Sume MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 440148385Sume 441148385Sume/* SCSI IO Request Descriptor */ 442148385Sumetypedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 443148385Sume{ 444148396Sume U8 RequestFlags; /* 0x00 */ 445148385Sume U8 MSIxIndex; /* 0x01 */ 446148385Sume U16 SMID; /* 0x02 */ 447148385Sume U16 LMID; /* 0x04 */ 448148385Sume U16 DevHandle; /* 0x06 */ 449148385Sume} MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 450148385Sume MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 451148385Sume Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 452148385Sume 453148385Sume/* SCSI Target Request Descriptor */ 454148385Sumetypedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 455148385Sume{ 456148385Sume U8 RequestFlags; /* 0x00 */ 457148385Sume U8 MSIxIndex; /* 0x01 */ 458148385Sume U16 SMID; /* 0x02 */ 459148385Sume U16 LMID; /* 0x04 */ 460148385Sume U16 IoIndex; /* 0x06 */ 461148385Sume} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 462148385Sume MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 463148385Sume Mpi2SCSITargetRequestDescriptor_t, 464148385Sume MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 465148385Sume 466148396Sume/* RAID Accelerator Request Descriptor */ 467148396Sumetypedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 468148385Sume{ 469148385Sume U8 RequestFlags; /* 0x00 */ 470148385Sume U8 MSIxIndex; /* 0x01 */ 471148385Sume U16 SMID; /* 0x02 */ 472148385Sume U16 LMID; /* 0x04 */ 473148385Sume U16 Reserved; /* 0x06 */ 474148385Sume} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 475148385Sume MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 476148385Sume Mpi2RAIDAcceleratorRequestDescriptor_t, 477148385Sume MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 478148385Sume 479148385Sume/* Fast Path SCSI IO Request Descriptor */ 480148385Sumetypedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 481148385Sume MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 482148385Sume MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 483148385Sume Mpi25FastPathSCSIIORequestDescriptor_t, 484148385Sume MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; 485148385Sume 486148385Sume/* PCIe Encapsulated Request Descriptor */ 487148385Sumetypedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 488148385Sume MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 489148385Sume MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 490148385Sume Mpi26PCIeEncapsulatedRequestDescriptor_t, 491148385Sume MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; 492148385Sume 493148385Sume/* union of Request Descriptors */ 494148385Sumetypedef union _MPI2_REQUEST_DESCRIPTOR_UNION 495148385Sume{ 496 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 497 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 498 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 499 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 500 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 501 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 502 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 503 U64 Words; 504} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 505 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 506 507/* Atomic Request Descriptors */ 508 509/* 510 * All Atomic Request Descriptors have the same format, so the following 511 * structure is used for all Atomic Request Descriptors: 512 * Atomic Default Request Descriptor 513 * Atomic High Priority Request Descriptor 514 * Atomic SCSI IO Request Descriptor 515 * Atomic SCSI Target Request Descriptor 516 * Atomic RAID Accelerator Request Descriptor 517 * Atomic Fast Path SCSI IO Request Descriptor 518 * Atomic PCIe Encapsulated Request Descriptor 519 */ 520 521/* Atomic Request Descriptor */ 522typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR 523{ 524 U8 RequestFlags; /* 0x00 */ 525 U8 MSIxIndex; /* 0x01 */ 526 U16 SMID; /* 0x02 */ 527} MPI26_ATOMIC_REQUEST_DESCRIPTOR, 528 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 529 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; 530 531/* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ 532 533/* Reply Descriptors */ 534 535/* Default Reply Descriptor */ 536typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 537{ 538 U8 ReplyFlags; /* 0x00 */ 539 U8 MSIxIndex; /* 0x01 */ 540 U16 DescriptorTypeDependent1; /* 0x02 */ 541 U32 DescriptorTypeDependent2; /* 0x04 */ 542} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 543 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 544 545/* defines for the ReplyFlags field */ 546#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 547#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 548#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 549#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 550#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 551#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 552#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 553#define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 554#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 555 556/* values for marking a reply descriptor as unused */ 557#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 558#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 559 560/* Address Reply Descriptor */ 561typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 562{ 563 U8 ReplyFlags; /* 0x00 */ 564 U8 MSIxIndex; /* 0x01 */ 565 U16 SMID; /* 0x02 */ 566 U32 ReplyFrameAddress; /* 0x04 */ 567} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 568 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 569 570#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 571 572/* SCSI IO Success Reply Descriptor */ 573typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 574{ 575 U8 ReplyFlags; /* 0x00 */ 576 U8 MSIxIndex; /* 0x01 */ 577 U16 SMID; /* 0x02 */ 578 U16 TaskTag; /* 0x04 */ 579 U16 Reserved1; /* 0x06 */ 580} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 581 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 582 Mpi2SCSIIOSuccessReplyDescriptor_t, 583 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 584 585/* TargetAssist Success Reply Descriptor */ 586typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 587{ 588 U8 ReplyFlags; /* 0x00 */ 589 U8 MSIxIndex; /* 0x01 */ 590 U16 SMID; /* 0x02 */ 591 U8 SequenceNumber; /* 0x04 */ 592 U8 Reserved1; /* 0x05 */ 593 U16 IoIndex; /* 0x06 */ 594} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 595 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 596 Mpi2TargetAssistSuccessReplyDescriptor_t, 597 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 598 599/* Target Command Buffer Reply Descriptor */ 600typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 601{ 602 U8 ReplyFlags; /* 0x00 */ 603 U8 MSIxIndex; /* 0x01 */ 604 U8 VP_ID; /* 0x02 */ 605 U8 Flags; /* 0x03 */ 606 U16 InitiatorDevHandle; /* 0x04 */ 607 U16 IoIndex; /* 0x06 */ 608} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 609 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 610 Mpi2TargetCommandBufferReplyDescriptor_t, 611 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 612 613/* defines for Flags field */ 614#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 615 616/* RAID Accelerator Success Reply Descriptor */ 617typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 618{ 619 U8 ReplyFlags; /* 0x00 */ 620 U8 MSIxIndex; /* 0x01 */ 621 U16 SMID; /* 0x02 */ 622 U32 Reserved; /* 0x04 */ 623} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 624 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 625 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 626 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 627 628/* Fast Path SCSI IO Success Reply Descriptor */ 629typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 630 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 631 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 632 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 633 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 634 635/* PCIe Encapsulated Success Reply Descriptor */ 636typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 637 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 638 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 639 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 640 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 641 642/* union of Reply Descriptors */ 643typedef union _MPI2_REPLY_DESCRIPTORS_UNION 644{ 645 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 646 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 647 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 648 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 649 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 650 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 651 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 652 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; 653 U64 Words; 654} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 655 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 656 657/***************************************************************************** 658* 659* Message Functions 660* 661*****************************************************************************/ 662 663#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 664#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 665#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 666#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 667#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 668#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 669#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 670#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 671#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 672#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 673#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 674#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 675#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 676#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 677#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 678#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 679#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 680#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 681#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 682#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ 683#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ 684#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 685#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 686#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 687#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 688#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 689#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 690#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 691#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 692#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ 693#define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ 694#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 695#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 696 697/* Doorbell functions */ 698#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 699#define MPI2_FUNCTION_HANDSHAKE (0x42) 700 701/***************************************************************************** 702* 703* IOC Status Values 704* 705*****************************************************************************/ 706 707/* mask for IOCStatus status value */ 708#define MPI2_IOCSTATUS_MASK (0x7FFF) 709 710/**************************************************************************** 711* Common IOCStatus values for all replies 712****************************************************************************/ 713 714#define MPI2_IOCSTATUS_SUCCESS (0x0000) 715#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 716#define MPI2_IOCSTATUS_BUSY (0x0002) 717#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 718#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 719#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 720#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 721#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 722#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 723#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 724#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ 725 726/**************************************************************************** 727* Config IOCStatus values 728****************************************************************************/ 729 730#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 731#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 732#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 733#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 734#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 735#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 736 737/**************************************************************************** 738* SCSI IO Reply 739****************************************************************************/ 740 741#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 742#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 743#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 744#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 745#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 746#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 747#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 748#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 749#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 750#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 751#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 752#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 753 754/**************************************************************************** 755* For use by SCSI Initiator and SCSI Target end-to-end data protection 756****************************************************************************/ 757 758#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 759#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 760#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 761 762/**************************************************************************** 763* SCSI Target values 764****************************************************************************/ 765 766#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 767#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 768#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 769#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 770#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 771#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 772#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 773#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 774#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 775#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 776 777/**************************************************************************** 778* Serial Attached SCSI values 779****************************************************************************/ 780 781#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 782#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 783 784/**************************************************************************** 785* Diagnostic Buffer Post / Diagnostic Release values 786****************************************************************************/ 787 788#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 789 790/**************************************************************************** 791* RAID Accelerator values 792****************************************************************************/ 793 794#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 795 796/**************************************************************************** 797* IOCStatus flag to indicate that log info is available 798****************************************************************************/ 799 800#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 801 802/**************************************************************************** 803* IOCLogInfo Types 804****************************************************************************/ 805 806#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 807#define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 808#define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 809#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 810#define MPI2_IOCLOGINFO_TYPE_FC (0x2) 811#define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 812#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 813#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 814 815/***************************************************************************** 816* 817* Standard Message Structures 818* 819*****************************************************************************/ 820 821/**************************************************************************** 822* Request Message Header for all request messages 823****************************************************************************/ 824 825typedef struct _MPI2_REQUEST_HEADER 826{ 827 U16 FunctionDependent1; /* 0x00 */ 828 U8 ChainOffset; /* 0x02 */ 829 U8 Function; /* 0x03 */ 830 U16 FunctionDependent2; /* 0x04 */ 831 U8 FunctionDependent3; /* 0x06 */ 832 U8 MsgFlags; /* 0x07 */ 833 U8 VP_ID; /* 0x08 */ 834 U8 VF_ID; /* 0x09 */ 835 U16 Reserved1; /* 0x0A */ 836} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 837 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 838 839/**************************************************************************** 840* Default Reply 841****************************************************************************/ 842 843typedef struct _MPI2_DEFAULT_REPLY 844{ 845 U16 FunctionDependent1; /* 0x00 */ 846 U8 MsgLength; /* 0x02 */ 847 U8 Function; /* 0x03 */ 848 U16 FunctionDependent2; /* 0x04 */ 849 U8 FunctionDependent3; /* 0x06 */ 850 U8 MsgFlags; /* 0x07 */ 851 U8 VP_ID; /* 0x08 */ 852 U8 VF_ID; /* 0x09 */ 853 U16 Reserved1; /* 0x0A */ 854 U16 FunctionDependent5; /* 0x0C */ 855 U16 IOCStatus; /* 0x0E */ 856 U32 IOCLogInfo; /* 0x10 */ 857} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 858 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 859 860/* common version structure/union used in messages and configuration pages */ 861 862typedef struct _MPI2_VERSION_STRUCT 863{ 864 U8 Dev; /* 0x00 */ 865 U8 Unit; /* 0x01 */ 866 U8 Minor; /* 0x02 */ 867 U8 Major; /* 0x03 */ 868} MPI2_VERSION_STRUCT; 869 870typedef union _MPI2_VERSION_UNION 871{ 872 MPI2_VERSION_STRUCT Struct; 873 U32 Word; 874} MPI2_VERSION_UNION; 875 876/* LUN field defines, common to many structures */ 877#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 878#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 879#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 880#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 881#define MPI2_LUN_LEVEL_1_WORD (0xFF00) 882#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 883 884/***************************************************************************** 885* 886* Fusion-MPT MPI Scatter Gather Elements 887* 888*****************************************************************************/ 889 890/**************************************************************************** 891* MPI Simple Element structures 892****************************************************************************/ 893 894typedef struct _MPI2_SGE_SIMPLE32 895{ 896 U32 FlagsLength; 897 U32 Address; 898} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 899 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 900 901typedef struct _MPI2_SGE_SIMPLE64 902{ 903 U32 FlagsLength; 904 U64 Address; 905} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 906 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 907 908typedef struct _MPI2_SGE_SIMPLE_UNION 909{ 910 U32 FlagsLength; 911 union 912 { 913 U32 Address32; 914 U64 Address64; 915 } u; 916} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 917 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 918 919/**************************************************************************** 920* MPI Chain Element structures - for MPI v2.0 products only 921****************************************************************************/ 922 923typedef struct _MPI2_SGE_CHAIN32 924{ 925 U16 Length; 926 U8 NextChainOffset; 927 U8 Flags; 928 U32 Address; 929} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 930 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 931 932typedef struct _MPI2_SGE_CHAIN64 933{ 934 U16 Length; 935 U8 NextChainOffset; 936 U8 Flags; 937 U64 Address; 938} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 939 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 940 941typedef struct _MPI2_SGE_CHAIN_UNION 942{ 943 U16 Length; 944 U8 NextChainOffset; 945 U8 Flags; 946 union 947 { 948 U32 Address32; 949 U64 Address64; 950 } u; 951} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 952 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 953 954/**************************************************************************** 955* MPI Transaction Context Element structures - for MPI v2.0 products only 956****************************************************************************/ 957 958typedef struct _MPI2_SGE_TRANSACTION32 959{ 960 U8 Reserved; 961 U8 ContextSize; 962 U8 DetailsLength; 963 U8 Flags; 964 U32 TransactionContext[1]; 965 U32 TransactionDetails[1]; 966} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 967 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 968 969typedef struct _MPI2_SGE_TRANSACTION64 970{ 971 U8 Reserved; 972 U8 ContextSize; 973 U8 DetailsLength; 974 U8 Flags; 975 U32 TransactionContext[2]; 976 U32 TransactionDetails[1]; 977} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 978 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 979 980typedef struct _MPI2_SGE_TRANSACTION96 981{ 982 U8 Reserved; 983 U8 ContextSize; 984 U8 DetailsLength; 985 U8 Flags; 986 U32 TransactionContext[3]; 987 U32 TransactionDetails[1]; 988} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 989 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 990 991typedef struct _MPI2_SGE_TRANSACTION128 992{ 993 U8 Reserved; 994 U8 ContextSize; 995 U8 DetailsLength; 996 U8 Flags; 997 U32 TransactionContext[4]; 998 U32 TransactionDetails[1]; 999} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 1000 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 1001 1002typedef struct _MPI2_SGE_TRANSACTION_UNION 1003{ 1004 U8 Reserved; 1005 U8 ContextSize; 1006 U8 DetailsLength; 1007 U8 Flags; 1008 union 1009 { 1010 U32 TransactionContext32[1]; 1011 U32 TransactionContext64[2]; 1012 U32 TransactionContext96[3]; 1013 U32 TransactionContext128[4]; 1014 } u; 1015 U32 TransactionDetails[1]; 1016} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 1017 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 1018 1019/**************************************************************************** 1020* MPI SGE union for IO SGL's - for MPI v2.0 products only 1021****************************************************************************/ 1022 1023typedef struct _MPI2_MPI_SGE_IO_UNION 1024{ 1025 union 1026 { 1027 MPI2_SGE_SIMPLE_UNION Simple; 1028 MPI2_SGE_CHAIN_UNION Chain; 1029 } u; 1030} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 1031 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 1032 1033/**************************************************************************** 1034* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1035****************************************************************************/ 1036 1037typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 1038{ 1039 union 1040 { 1041 MPI2_SGE_SIMPLE_UNION Simple; 1042 MPI2_SGE_TRANSACTION_UNION Transaction; 1043 } u; 1044} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1045 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 1046 1047/**************************************************************************** 1048* All MPI SGE types union 1049****************************************************************************/ 1050 1051typedef struct _MPI2_MPI_SGE_UNION 1052{ 1053 union 1054 { 1055 MPI2_SGE_SIMPLE_UNION Simple; 1056 MPI2_SGE_CHAIN_UNION Chain; 1057 MPI2_SGE_TRANSACTION_UNION Transaction; 1058 } u; 1059} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 1060 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 1061 1062/**************************************************************************** 1063* MPI SGE field definition and masks 1064****************************************************************************/ 1065 1066/* Flags field bit definitions */ 1067 1068#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1069#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1070#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1071#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1072#define MPI2_SGE_FLAGS_DIRECTION (0x04) 1073#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1074#define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1075 1076#define MPI2_SGE_FLAGS_SHIFT (24) 1077 1078#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1079#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1080 1081/* Element Type */ 1082 1083#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */ 1084#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1085#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */ 1086#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1087 1088/* Address location */ 1089 1090#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1091 1092/* Direction */ 1093 1094#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1095#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1096 1097#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1098#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1099 1100/* Address Size */ 1101 1102#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1103#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1104 1105/* Context Size */ 1106 1107#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1108#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1109#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1110#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1111 1112#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1113#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1114 1115/**************************************************************************** 1116* MPI SGE operation Macros 1117****************************************************************************/ 1118 1119/* SIMPLE FlagsLength manipulations... */ 1120#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1121#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 1122#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1123#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1124 1125#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 1126 1127#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1128#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1129#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1130 1131/* CAUTION - The following are READ-MODIFY-WRITE! */ 1132#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1133#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1134 1135#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1136 1137/***************************************************************************** 1138* 1139* Fusion-MPT IEEE Scatter Gather Elements 1140* 1141*****************************************************************************/ 1142 1143/**************************************************************************** 1144* IEEE Simple Element structures 1145****************************************************************************/ 1146 1147/* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1148typedef struct _MPI2_IEEE_SGE_SIMPLE32 1149{ 1150 U32 Address; 1151 U32 FlagsLength; 1152} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1153 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1154 1155typedef struct _MPI2_IEEE_SGE_SIMPLE64 1156{ 1157 U64 Address; 1158 U32 Length; 1159 U16 Reserved1; 1160 U8 Reserved2; 1161 U8 Flags; 1162} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1163 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1164 1165typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1166{ 1167 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1168 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1169} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1170 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1171 1172/**************************************************************************** 1173* IEEE Chain Element structures 1174****************************************************************************/ 1175 1176/* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1177typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1178 1179/* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1180typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1181 1182typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1183{ 1184 MPI2_IEEE_SGE_CHAIN32 Chain32; 1185 MPI2_IEEE_SGE_CHAIN64 Chain64; 1186} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1187 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1188 1189/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1190typedef struct _MPI25_IEEE_SGE_CHAIN64 1191{ 1192 U64 Address; 1193 U32 Length; 1194 U16 Reserved1; 1195 U8 NextChainOffset; 1196 U8 Flags; 1197} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 1198 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 1199 1200/**************************************************************************** 1201* All IEEE SGE types union 1202****************************************************************************/ 1203 1204/* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1205typedef struct _MPI2_IEEE_SGE_UNION 1206{ 1207 union 1208 { 1209 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1210 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1211 } u; 1212} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1213 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1214 1215/**************************************************************************** 1216* IEEE SGE union for IO SGL's 1217****************************************************************************/ 1218 1219typedef union _MPI25_SGE_IO_UNION 1220{ 1221 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1222 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1223} MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION, 1224 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t; 1225 1226/**************************************************************************** 1227* IEEE SGE field definitions and masks 1228****************************************************************************/ 1229 1230/* Flags field bit definitions */ 1231 1232#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1233#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1234 1235#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1236 1237#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1238 1239/* Element Type */ 1240 1241#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1242#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1243 1244/* Next Segment Format */ 1245 1246#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1247#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1248#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1249#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1250 1251/* Data Location Address Space */ 1252 1253#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1254#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ 1255#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ 1256#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1257#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ 1258#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ 1259#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1260 1261#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ 1262 1263/**************************************************************************** 1264* IEEE SGE operation Macros 1265****************************************************************************/ 1266 1267/* SIMPLE FlagsLength manipulations... */ 1268#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1269#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1270#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1271 1272#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1273 1274#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1275#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1276#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1277 1278/* CAUTION - The following are READ-MODIFY-WRITE! */ 1279#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1280#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1281 1282/***************************************************************************** 1283* 1284* Fusion-MPT MPI/IEEE Scatter Gather Unions 1285* 1286*****************************************************************************/ 1287 1288typedef union _MPI2_SIMPLE_SGE_UNION 1289{ 1290 MPI2_SGE_SIMPLE_UNION MpiSimple; 1291 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1292} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1293 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1294 1295typedef union _MPI2_SGE_IO_UNION 1296{ 1297 MPI2_SGE_SIMPLE_UNION MpiSimple; 1298 MPI2_SGE_CHAIN_UNION MpiChain; 1299 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1300 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1301} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1302 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1303 1304/**************************************************************************** 1305* 1306* Values for SGLFlags field, used in many request messages with an SGL 1307* 1308****************************************************************************/ 1309 1310/* values for MPI SGL Data Location Address Space subfield */ 1311#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1312#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1313#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1314#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ 1315#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ 1316#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ 1317/* values for SGL Type subfield */ 1318#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1319#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1320#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ 1321#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1322 1323#endif 1324