1/*
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020-2024, Broadcom Inc. All rights reserved.
5 * Support: <fbsd-storage-driver.pdl@broadcom.com>
6 *
7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com>
8 *	    Chandrakanth Patil <chandrakanth.patil@broadcom.com>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * 1. Redistributions of source code must retain the above copyright notice,
15 *    this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright notice,
17 *    this list of conditions and the following disclaimer in the documentation and/or other
18 *    materials provided with the distribution.
19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors
20 *    may be used to endorse or promote products derived from this software without
21 *    specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are
36 * those of the authors and should not be interpreted as representing
37 * official policies,either expressed or implied, of the FreeBSD Project.
38 *
39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131
40 *
41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD
42 */
43
44#include "mpi3mr.h"
45
46#ifndef _MPI3MR_APP_H_
47#define	_MPI3MR_APP_H_
48
49#define MPI3MR_IOCTL_ADPTYPE_AVGFAMILY  1
50#define MPI3MR_IOCTL_VERSION		0x06
51
52#define MPI3MRDRVCMD    _IOWR('B', 1, struct mpi3mr_ioctl_drvcmd)
53#define MPI3MRMPTCMD    _IOWR('B', 2, struct mpi3mr_ioctl_mptcmd)
54
55#define MPI3MR_IOCTL_DEFAULT_TIMEOUT	(10)
56#define PEND_IOCTLS_COMP_WAIT_TIME	(10)
57
58#define MPI3MR_IOCTL_LOGDATA_MAX_ENTRIES	400
59#define MPI3MR_IOCTL_LOGDATA_ENTRY_HEADER_SZ	0x5
60
61#define GET_IOC_STATUS(ioc_status)	\
62	ioc_status & MPI3_IOCSTATUS_STATUS_MASK
63
64/* Encapsulated NVMe command definitions */
65#define	MPI3MR_NVME_PRP_SIZE		8
66#define	MPI3MR_NVME_CMD_PRP1_OFFSET	24
67#define	MPI3MR_NVME_CMD_PRP2_OFFSET	32
68#define	MPI3MR_NVME_CMD_SGL_OFFSET	24
69#define MPI3MR_NVME_DATA_FORMAT_PRP	0
70#define MPI3MR_NVME_DATA_FORMAT_SGL1	1
71#define MPI3MR_NVME_DATA_FORMAT_SGL2	2
72
73#define MPI3MR_NVMESGL_DATA_SEGMENT	0x00
74#define MPI3MR_NVMESGL_LAST_SEGMENT	0x03
75
76int mpi3mr_app_attach(struct mpi3mr_softc *);
77void mpi3mr_app_detach(struct mpi3mr_softc *);
78
79enum mpi3mr_ioctl_adp_state {
80	MPI3MR_IOCTL_ADP_STATE_UNKNOWN		= 0,
81	MPI3MR_IOCTL_ADP_STATE_OPERATIONAL	= 1,
82	MPI3MR_IOCTL_ADP_STATE_FAULT		= 2,
83	MPI3MR_IOCTL_ADP_STATE_IN_RESET		= 3,
84	MPI3MR_IOCTL_ADP_STATE_UNRECOVERABLE	= 4,
85};
86
87enum mpi3mr_ioctl_data_dir {
88	MPI3MR_APP_DDN,
89	MPI3MR_APP_DDI,
90	MPI3MR_APP_DDO,
91};
92
93enum mpi3mr_ioctl_drvcmds_opcode {
94	MPI3MR_DRVRIOCTL_OPCODE_UNKNOWN		= 0,
95	MPI3MR_DRVRIOCTL_OPCODE_ADPINFO		= 1,
96	MPI3MR_DRVRIOCTL_OPCODE_ADPRESET	= 2,
97	MPI3MR_DRVRIOCTL_OPCODE_TGTDEVINFO	= 3,
98	MPI3MR_DRVRIOCTL_OPCODE_ALLTGTDEVINFO	= 4,
99	MPI3MR_DRVRIOCTL_OPCODE_GETCHGCNT	= 5,
100	MPI3MR_DRVRIOCTL_OPCODE_LOGDATAENABLE	= 6,
101	MPI3MR_DRVRIOCTL_OPCODE_PELENABLE	= 7,
102	MPI3MR_DRVRIOCTL_OPCODE_GETLOGDATA	= 8,
103	MPI3MR_DRVRIOCTL_OPCODE_GETPCIINFO	= 100,
104};
105
106enum mpi3mr_ioctl_mpibuffer_type {
107	MPI3MR_IOCTL_BUFTYPE_UNKNOWN,
108	MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_CMD,
109	MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_RESP,
110	MPI3MR_IOCTL_BUFTYPE_DATA_IN,
111	MPI3MR_IOCTL_BUFTYPE_DATA_OUT,
112	MPI3MR_IOCTL_BUFTYPE_MPI_REPLY,
113	MPI3MR_IOCTL_BUFTYPE_ERR_RESPONSE,
114};
115
116enum mpi3mr_ioctl_mpireply_type {
117	MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_UNKNOWN,
118	MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_STATUS,
119	MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_ADDRESS,
120};
121
122enum  mpi3mr_ioctl_reset_type {
123	MPI3MR_IOCTL_ADPRESET_UNKNOWN,
124	MPI3MR_IOCTL_ADPRESET_SOFT,
125	MPI3MR_IOCTL_ADPRESET_DIAG_FAULT,
126};
127
128struct mpi3mr_ioctl_drvcmd {
129        U8 mrioc_id;
130        U8 opcode;
131        U16 rsvd1;
132        U32 rsvd2;
133        void *data_in_buf;
134        void *data_out_buf;
135        U32 data_in_size;
136        U32 data_out_size;
137};
138
139struct mpi3mr_ioctl_adpinfo {
140	U32 adp_type;
141	U32 rsvd1;
142	U32 pci_dev_id;
143	U32 pci_dev_hw_rev;
144	U32 pci_subsys_dev_id;
145	U32 pci_subsys_ven_id;
146	U32 pci_dev:5;
147	U32 pci_func:3;
148	U32 pci_bus:8;
149	U32 rsvd2:16;
150	U32 pci_seg_id;
151	U32 ioctl_ver;
152	U8 adp_state;
153	U8 rsvd3;
154	U16 rsvd4;
155	U32 rsvd5[2];
156	Mpi3DriverInfoLayout_t driver_info;
157};
158
159struct mpi3mr_ioctl_pciinfo {
160	U32	config_space[64];
161};
162
163struct mpi3mr_ioctl_tgtinfo {
164        U32 target_id;
165        U8 bus_id;
166        U8 rsvd1;
167        U16 rsvd2;
168        U16 dev_handle;
169        U16 persistent_id;
170        U32 seq_num;
171};
172
173struct mpi3mr_device_map_info {
174	U16 handle;
175	U16 per_id;
176	U32 target_id;
177	U8 bus_id;
178	U8 rsvd1;
179	U16 rsvd2;
180};
181
182struct mpi3mr_ioctl_all_tgtinfo {
183	U16 num_devices;
184	U16 rsvd1;
185        U32 rsvd2;
186	struct mpi3mr_device_map_info dmi[1];
187};
188
189struct mpi3mr_ioctl_chgcnt {
190	U16 change_count;
191	U16 rsvd;
192};
193
194struct mpi3mr_ioctl_adpreset {
195	U8 reset_type;
196	U8 rsvd1;
197	U16 rsvd2;
198};
199
200struct mpi3mr_ioctl_mptcmd {
201        U8 mrioc_id;
202        U8 rsvd1;
203        U16 timeout;
204        U16 rsvd2;
205        U16 mpi_msg_size;
206        void *mpi_msg_buf;
207        void *buf_entry_list;
208        U32 buf_entry_list_size;
209};
210
211struct mpi3mr_buf_entry {
212	U8 buf_type;
213	U8 rsvd1;
214	U16 rsvd2;
215	U32 buf_len;
216	void *buffer;
217};
218
219struct mpi3mr_ioctl_buf_entry_list {
220	U8 num_of_buf_entries;
221	U8 rsvd1;
222	U16 rsvd2;
223	U32 rsvd3;
224	struct mpi3mr_buf_entry buf_entry[1];
225};
226
227struct mpi3mr_ioctl_mpt_dma_buffer {
228	void *user_buf;
229	void *kern_buf;
230	U32 user_buf_len;
231	U32 kern_buf_len;
232	bus_addr_t kern_buf_dma;
233	bus_dma_tag_t kern_buf_dmatag;
234	bus_dmamap_t kern_buf_dmamap;
235	U8 data_dir;
236	U16 num_dma_desc;
237	struct dma_memory_desc *dma_desc;
238};
239
240struct mpi3mr_ioctl_mpirepbuf {
241	U8 mpirep_type;
242	U8 rsvd1;
243	U16 rsvd2;
244	U8 repbuf[1];
245};
246
247struct mpi3mr_nvme_pt_sge {
248	U64 base_addr;
249	U32 length;
250	U16 rsvd;
251	U8 rsvd1;
252	U8 sub_type:4;
253	U8 type:4;
254};
255
256struct mpi3mr_log_data_entry {
257	U8 valid_entry;
258	U8 rsvd1;
259	U16 rsvd2;
260	U8 data[1];
261};
262
263struct mpi3mr_ioctl_logdata_enable {
264	U16 max_entries;
265	U16 rsvd;
266};
267
268struct mpi3mr_ioctl_pel_enable {
269	U16 pel_locale;
270	U8 pel_class;
271	U8 rsvd;
272};
273
274int
275mpi3mr_pel_abort(struct mpi3mr_softc *sc);
276void
277mpi3mr_pel_getseq_complete(struct mpi3mr_softc *sc,
278			   struct mpi3mr_drvr_cmd *drvr_cmd);
279void
280mpi3mr_issue_pel_wait(struct mpi3mr_softc *sc,
281		     struct mpi3mr_drvr_cmd *drvr_cmd);
282void
283mpi3mr_pel_wait_complete(struct mpi3mr_softc *sc,
284			 struct mpi3mr_drvr_cmd *drvr_cmd);
285void
286mpi3mr_send_pel_getseq(struct mpi3mr_softc *sc,
287		       struct mpi3mr_drvr_cmd *drvr_cmd);
288void
289mpi3mr_app_send_aen(struct mpi3mr_softc *sc);
290
291#endif /* !_MPI3MR_API_H_ */
292