1/*- 2 * Copyright (c) 2013-2021, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include "opt_rss.h" 27#include "opt_ratelimit.h" 28 29#include <linux/module.h> 30#include <rdma/ib_umem.h> 31#include <rdma/ib_cache.h> 32#include <rdma/ib_user_verbs.h> 33#include <rdma/uverbs_ioctl.h> 34#include <dev/mlx5/mlx5_ib/mlx5_ib.h> 35 36/* not supported currently */ 37static int wq_signature; 38 39enum { 40 MLX5_IB_ACK_REQ_FREQ = 8, 41}; 42 43enum { 44 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, 45 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 46 MLX5_IB_LINK_TYPE_IB = 0, 47 MLX5_IB_LINK_TYPE_ETH = 1 48}; 49 50enum { 51 MLX5_IB_SQ_STRIDE = 6, 52}; 53 54static const u32 mlx5_ib_opcode[] = { 55 [IB_WR_SEND] = MLX5_OPCODE_SEND, 56 [IB_WR_LSO] = MLX5_OPCODE_LSO, 57 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, 58 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, 59 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, 60 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, 61 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, 62 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, 63 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, 64 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, 65 [IB_WR_REG_MR] = MLX5_OPCODE_UMR, 66 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, 67 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, 68 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, 69}; 70 71struct mlx5_wqe_eth_pad { 72 u8 rsvd0[16]; 73}; 74 75enum raw_qp_set_mask_map { 76 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 77}; 78 79struct mlx5_modify_raw_qp_param { 80 u16 operation; 81 82 u32 set_mask; /* raw_qp_set_mask_map */ 83 u8 rq_q_ctr_id; 84}; 85 86static void get_cqs(enum ib_qp_type qp_type, 87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); 89 90static int is_qp0(enum ib_qp_type qp_type) 91{ 92 return qp_type == IB_QPT_SMI; 93} 94 95static int is_sqp(enum ib_qp_type qp_type) 96{ 97 return is_qp0(qp_type) || is_qp1(qp_type); 98} 99 100static void *get_wqe(struct mlx5_ib_qp *qp, int offset) 101{ 102 return mlx5_buf_offset(&qp->buf, offset); 103} 104 105static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n) 106{ 107 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 108} 109 110void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n) 111{ 112 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE)); 113} 114 115/** 116 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space. 117 * 118 * @qp: QP to copy from. 119 * @send: copy from the send queue when non-zero, use the receive queue 120 * otherwise. 121 * @wqe_index: index to start copying from. For send work queues, the 122 * wqe_index is in units of MLX5_SEND_WQE_BB. 123 * For receive work queue, it is the number of work queue 124 * element in the queue. 125 * @buffer: destination buffer. 126 * @length: maximum number of bytes to copy. 127 * 128 * Copies at least a single WQE, but may copy more data. 129 * 130 * Return: the number of bytes copied, or an error code. 131 */ 132int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index, 133 void *buffer, u32 length, 134 struct mlx5_ib_qp_base *base) 135{ 136 struct ib_device *ibdev = qp->ibqp.device; 137 struct mlx5_ib_dev *dev = to_mdev(ibdev); 138 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq; 139 size_t offset; 140 size_t wq_end; 141 struct ib_umem *umem = base->ubuffer.umem; 142 u32 first_copy_length; 143 int wqe_length; 144 int ret; 145 146 if (wq->wqe_cnt == 0) { 147 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n", 148 qp->ibqp.qp_type); 149 return -EINVAL; 150 } 151 152 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift); 153 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift); 154 155 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg)) 156 return -EINVAL; 157 158 if (offset > umem->length || 159 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length)) 160 return -EINVAL; 161 162 first_copy_length = min_t(u32, offset + length, wq_end) - offset; 163 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length); 164 if (ret) 165 return ret; 166 167 if (send) { 168 struct mlx5_wqe_ctrl_seg *ctrl = buffer; 169 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; 170 171 wqe_length = ds * MLX5_WQE_DS_UNITS; 172 } else { 173 wqe_length = 1 << wq->wqe_shift; 174 } 175 176 if (wqe_length <= first_copy_length) 177 return first_copy_length; 178 179 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset, 180 wqe_length - first_copy_length); 181 if (ret) 182 return ret; 183 184 return wqe_length; 185} 186 187static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) 188{ 189 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 190 struct ib_event event; 191 192 if (type == MLX5_EVENT_TYPE_PATH_MIG) { 193 /* This event is only valid for trans_qps */ 194 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; 195 } 196 197 if (ibqp->event_handler) { 198 event.device = ibqp->device; 199 event.element.qp = ibqp; 200 switch (type) { 201 case MLX5_EVENT_TYPE_PATH_MIG: 202 event.event = IB_EVENT_PATH_MIG; 203 break; 204 case MLX5_EVENT_TYPE_COMM_EST: 205 event.event = IB_EVENT_COMM_EST; 206 break; 207 case MLX5_EVENT_TYPE_SQ_DRAINED: 208 event.event = IB_EVENT_SQ_DRAINED; 209 break; 210 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 211 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 212 break; 213 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 214 event.event = IB_EVENT_QP_FATAL; 215 break; 216 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 217 event.event = IB_EVENT_PATH_MIG_ERR; 218 break; 219 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 220 event.event = IB_EVENT_QP_REQ_ERR; 221 break; 222 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 223 event.event = IB_EVENT_QP_ACCESS_ERR; 224 break; 225 default: 226 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); 227 return; 228 } 229 230 ibqp->event_handler(&event, ibqp->qp_context); 231 } 232} 233 234static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, 235 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) 236{ 237 int wqe_size; 238 int wq_size; 239 240 /* Sanity check RQ size before proceeding */ 241 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) 242 return -EINVAL; 243 244 if (!has_rq) { 245 qp->rq.max_gs = 0; 246 qp->rq.wqe_cnt = 0; 247 qp->rq.wqe_shift = 0; 248 cap->max_recv_wr = 0; 249 cap->max_recv_sge = 0; 250 } else { 251 if (ucmd) { 252 qp->rq.wqe_cnt = ucmd->rq_wqe_count; 253 qp->rq.wqe_shift = ucmd->rq_wqe_shift; 254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 255 qp->rq.max_post = qp->rq.wqe_cnt; 256 } else { 257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; 258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); 259 wqe_size = roundup_pow_of_two(wqe_size); 260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; 261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); 262 qp->rq.wqe_cnt = wq_size / wqe_size; 263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { 264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", 265 wqe_size, 266 MLX5_CAP_GEN(dev->mdev, 267 max_wqe_sz_rq)); 268 return -EINVAL; 269 } 270 qp->rq.wqe_shift = ilog2(wqe_size); 271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; 272 qp->rq.max_post = qp->rq.wqe_cnt; 273 } 274 } 275 276 return 0; 277} 278 279static int sq_overhead(struct ib_qp_init_attr *attr) 280{ 281 int size = 0; 282 283 switch (attr->qp_type) { 284 case IB_QPT_XRC_INI: 285 size += sizeof(struct mlx5_wqe_xrc_seg); 286 /* fall through */ 287 case IB_QPT_RC: 288 size += sizeof(struct mlx5_wqe_ctrl_seg) + 289 max(sizeof(struct mlx5_wqe_atomic_seg) + 290 sizeof(struct mlx5_wqe_raddr_seg), 291 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 292 sizeof(struct mlx5_mkey_seg)); 293 break; 294 295 case IB_QPT_XRC_TGT: 296 return 0; 297 298 case IB_QPT_UC: 299 size += sizeof(struct mlx5_wqe_ctrl_seg) + 300 max(sizeof(struct mlx5_wqe_raddr_seg), 301 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 302 sizeof(struct mlx5_mkey_seg)); 303 break; 304 305 case IB_QPT_UD: 306 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 307 size += sizeof(struct mlx5_wqe_eth_pad) + 308 sizeof(struct mlx5_wqe_eth_seg); 309 /* fall through */ 310 case IB_QPT_SMI: 311 case MLX5_IB_QPT_HW_GSI: 312 size += sizeof(struct mlx5_wqe_ctrl_seg) + 313 sizeof(struct mlx5_wqe_datagram_seg); 314 break; 315 316 case MLX5_IB_QPT_REG_UMR: 317 size += sizeof(struct mlx5_wqe_ctrl_seg) + 318 sizeof(struct mlx5_wqe_umr_ctrl_seg) + 319 sizeof(struct mlx5_mkey_seg); 320 break; 321 322 default: 323 return -EINVAL; 324 } 325 326 return size; 327} 328 329static int calc_send_wqe(struct ib_qp_init_attr *attr) 330{ 331 int inl_size = 0; 332 int size; 333 334 size = sq_overhead(attr); 335 if (size < 0) 336 return size; 337 338 if (attr->cap.max_inline_data) { 339 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + 340 attr->cap.max_inline_data; 341 } 342 343 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); 344 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && 345 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) 346 return MLX5_SIG_WQE_SIZE; 347 else 348 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 349} 350 351static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) 352{ 353 int max_sge; 354 355 if (attr->qp_type == IB_QPT_RC) 356 max_sge = (min_t(int, wqe_size, 512) - 357 sizeof(struct mlx5_wqe_ctrl_seg) - 358 sizeof(struct mlx5_wqe_raddr_seg)) / 359 sizeof(struct mlx5_wqe_data_seg); 360 else if (attr->qp_type == IB_QPT_XRC_INI) 361 max_sge = (min_t(int, wqe_size, 512) - 362 sizeof(struct mlx5_wqe_ctrl_seg) - 363 sizeof(struct mlx5_wqe_xrc_seg) - 364 sizeof(struct mlx5_wqe_raddr_seg)) / 365 sizeof(struct mlx5_wqe_data_seg); 366 else 367 max_sge = (wqe_size - sq_overhead(attr)) / 368 sizeof(struct mlx5_wqe_data_seg); 369 370 return min_t(int, max_sge, wqe_size - sq_overhead(attr) / 371 sizeof(struct mlx5_wqe_data_seg)); 372} 373 374static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 375 struct mlx5_ib_qp *qp) 376{ 377 int wqe_size; 378 int wq_size; 379 380 if (!attr->cap.max_send_wr) 381 return 0; 382 383 wqe_size = calc_send_wqe(attr); 384 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); 385 if (wqe_size < 0) 386 return wqe_size; 387 388 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 389 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", 390 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 391 return -EINVAL; 392 } 393 394 qp->max_inline_data = wqe_size - sq_overhead(attr) - 395 sizeof(struct mlx5_wqe_inline_seg); 396 attr->cap.max_inline_data = qp->max_inline_data; 397 398 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) 399 qp->signature_en = true; 400 401 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 402 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 403 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 404 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 405 qp->sq.wqe_cnt, 406 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 407 return -ENOMEM; 408 } 409 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 410 qp->sq.max_gs = get_send_sge(attr, wqe_size); 411 if (qp->sq.max_gs < attr->cap.max_send_sge) 412 return -ENOMEM; 413 414 attr->cap.max_send_sge = qp->sq.max_gs; 415 qp->sq.max_post = wq_size / wqe_size; 416 attr->cap.max_send_wr = qp->sq.max_post; 417 418 return wq_size; 419} 420 421static int set_user_buf_size(struct mlx5_ib_dev *dev, 422 struct mlx5_ib_qp *qp, 423 struct mlx5_ib_create_qp *ucmd, 424 struct mlx5_ib_qp_base *base, 425 struct ib_qp_init_attr *attr) 426{ 427 int desc_sz = 1 << qp->sq.wqe_shift; 428 429 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { 430 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", 431 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); 432 return -EINVAL; 433 } 434 435 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) { 436 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n", 437 ucmd->sq_wqe_count, ucmd->sq_wqe_count); 438 return -EINVAL; 439 } 440 441 qp->sq.wqe_cnt = ucmd->sq_wqe_count; 442 443 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 444 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", 445 qp->sq.wqe_cnt, 446 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 447 return -EINVAL; 448 } 449 450 if (attr->qp_type == IB_QPT_RAW_PACKET) { 451 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; 452 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; 453 } else { 454 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 455 (qp->sq.wqe_cnt << 6); 456 } 457 458 return 0; 459} 460 461static int qp_has_rq(struct ib_qp_init_attr *attr) 462{ 463 if (attr->qp_type == IB_QPT_XRC_INI || 464 attr->qp_type == IB_QPT_XRC_TGT || attr->srq || 465 attr->qp_type == MLX5_IB_QPT_REG_UMR || 466 !attr->cap.max_recv_wr) 467 return 0; 468 469 return 1; 470} 471 472enum { 473 /* this is the first blue flame register in the array of bfregs assigned 474 * to a processes. Since we do not use it for blue flame but rather 475 * regular 64 bit doorbells, we do not need a lock for maintaiing 476 * "odd/even" order 477 */ 478 NUM_NON_BLUE_FLAME_BFREGS = 1, 479}; 480 481static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) 482{ 483 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; 484} 485 486static int num_med_bfreg(struct mlx5_ib_dev *dev, 487 struct mlx5_bfreg_info *bfregi) 488{ 489 int n; 490 491 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - 492 NUM_NON_BLUE_FLAME_BFREGS; 493 494 return n >= 0 ? n : 0; 495} 496 497static int first_med_bfreg(struct mlx5_ib_dev *dev, 498 struct mlx5_bfreg_info *bfregi) 499{ 500 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; 501} 502 503static int first_hi_bfreg(struct mlx5_ib_dev *dev, 504 struct mlx5_bfreg_info *bfregi) 505{ 506 int med; 507 508 med = num_med_bfreg(dev, bfregi); 509 return ++med; 510} 511 512static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, 513 struct mlx5_bfreg_info *bfregi) 514{ 515 int i; 516 517 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { 518 if (!bfregi->count[i]) { 519 bfregi->count[i]++; 520 return i; 521 } 522 } 523 524 return -ENOMEM; 525} 526 527static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, 528 struct mlx5_bfreg_info *bfregi) 529{ 530 int minidx = first_med_bfreg(dev, bfregi); 531 int i; 532 533 if (minidx < 0) 534 return minidx; 535 536 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { 537 if (bfregi->count[i] < bfregi->count[minidx]) 538 minidx = i; 539 if (!bfregi->count[minidx]) 540 break; 541 } 542 543 bfregi->count[minidx]++; 544 return minidx; 545} 546 547static int alloc_bfreg(struct mlx5_ib_dev *dev, 548 struct mlx5_bfreg_info *bfregi) 549{ 550 int bfregn = -ENOMEM; 551 552 if (bfregi->lib_uar_dyn) 553 return -EINVAL; 554 555 mutex_lock(&bfregi->lock); 556 if (bfregi->ver >= 2) { 557 bfregn = alloc_high_class_bfreg(dev, bfregi); 558 if (bfregn < 0) 559 bfregn = alloc_med_class_bfreg(dev, bfregi); 560 } 561 562 if (bfregn < 0) { 563 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); 564 bfregn = 0; 565 bfregi->count[bfregn]++; 566 } 567 mutex_unlock(&bfregi->lock); 568 569 return bfregn; 570} 571 572void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) 573{ 574 mutex_lock(&bfregi->lock); 575 bfregi->count[bfregn]--; 576 mutex_unlock(&bfregi->lock); 577} 578 579static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) 580{ 581 switch (state) { 582 case IB_QPS_RESET: return MLX5_QP_STATE_RST; 583 case IB_QPS_INIT: return MLX5_QP_STATE_INIT; 584 case IB_QPS_RTR: return MLX5_QP_STATE_RTR; 585 case IB_QPS_RTS: return MLX5_QP_STATE_RTS; 586 case IB_QPS_SQD: return MLX5_QP_STATE_SQD; 587 case IB_QPS_SQE: return MLX5_QP_STATE_SQER; 588 case IB_QPS_ERR: return MLX5_QP_STATE_ERR; 589 default: return -1; 590 } 591} 592 593static int to_mlx5_st(enum ib_qp_type type) 594{ 595 switch (type) { 596 case IB_QPT_RC: return MLX5_QP_ST_RC; 597 case IB_QPT_UC: return MLX5_QP_ST_UC; 598 case IB_QPT_UD: return MLX5_QP_ST_UD; 599 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; 600 case IB_QPT_XRC_INI: 601 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; 602 case IB_QPT_SMI: return MLX5_QP_ST_QP0; 603 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; 604 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; 605 case IB_QPT_RAW_PACKET: 606 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; 607 case IB_QPT_MAX: 608 default: return -EINVAL; 609 } 610} 611 612static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, 613 struct mlx5_ib_cq *recv_cq); 614static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, 615 struct mlx5_ib_cq *recv_cq); 616 617int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 618 struct mlx5_bfreg_info *bfregi, u32 bfregn, 619 bool dyn_bfreg) 620{ 621 unsigned int bfregs_per_sys_page; 622 u32 index_of_sys_page; 623 u32 offset; 624 625 if (bfregi->lib_uar_dyn) 626 return -EINVAL; 627 628 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * 629 MLX5_NON_FP_BFREGS_PER_UAR; 630 index_of_sys_page = bfregn / bfregs_per_sys_page; 631 632 if (dyn_bfreg) { 633 index_of_sys_page += bfregi->num_static_sys_pages; 634 635 if (index_of_sys_page >= bfregi->num_sys_pages) 636 return -EINVAL; 637 638 if (bfregn > bfregi->num_dyn_bfregs || 639 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { 640 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); 641 return -EINVAL; 642 } 643 } 644 645 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; 646 return bfregi->sys_pages[index_of_sys_page] + offset; 647} 648 649static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, 650 struct ib_pd *pd, 651 unsigned long addr, size_t size, 652 struct ib_umem **umem, 653 int *npages, int *page_shift, int *ncont, 654 u32 *offset) 655{ 656 int err; 657 658 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0); 659 if (IS_ERR(*umem)) { 660 mlx5_ib_dbg(dev, "umem_get failed\n"); 661 return PTR_ERR(*umem); 662 } 663 664 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); 665 666 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 667 if (err) { 668 mlx5_ib_warn(dev, "bad offset\n"); 669 goto err_umem; 670 } 671 672 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", 673 addr, size, *npages, *page_shift, *ncont, *offset); 674 675 return 0; 676 677err_umem: 678 ib_umem_release(*umem); 679 *umem = NULL; 680 681 return err; 682} 683 684static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq, 685 struct ib_udata *udata) 686{ 687 struct mlx5_ib_ucontext *context = 688 rdma_udata_to_drv_context( 689 udata, 690 struct mlx5_ib_ucontext, 691 ibucontext); 692 693 mlx5_ib_db_unmap_user(context, &rwq->db); 694 if (rwq->umem) 695 ib_umem_release(rwq->umem); 696} 697 698static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, 699 struct mlx5_ib_rwq *rwq, 700 struct mlx5_ib_create_wq *ucmd) 701{ 702 struct mlx5_ib_ucontext *context; 703 int page_shift = 0; 704 int npages; 705 u32 offset = 0; 706 int ncont = 0; 707 int err; 708 709 if (!ucmd->buf_addr) 710 return -EINVAL; 711 712 context = to_mucontext(pd->uobject->context); 713 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr, 714 rwq->buf_size, 0, 0); 715 if (IS_ERR(rwq->umem)) { 716 mlx5_ib_dbg(dev, "umem_get failed\n"); 717 err = PTR_ERR(rwq->umem); 718 return err; 719 } 720 721 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, 722 &ncont, NULL); 723 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 724 &rwq->rq_page_offset); 725 if (err) { 726 mlx5_ib_warn(dev, "bad offset\n"); 727 goto err_umem; 728 } 729 730 rwq->rq_num_pas = ncont; 731 rwq->page_shift = page_shift; 732 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; 733 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); 734 735 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", 736 (unsigned long long)ucmd->buf_addr, rwq->buf_size, 737 npages, page_shift, ncont, offset); 738 739 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db); 740 if (err) { 741 mlx5_ib_dbg(dev, "map failed\n"); 742 goto err_umem; 743 } 744 745 rwq->create_type = MLX5_WQ_USER; 746 return 0; 747 748err_umem: 749 ib_umem_release(rwq->umem); 750 return err; 751} 752 753static int adjust_bfregn(struct mlx5_ib_dev *dev, 754 struct mlx5_bfreg_info *bfregi, int bfregn) 755{ 756 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + 757 bfregn % MLX5_NON_FP_BFREGS_PER_UAR; 758} 759 760static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, 761 struct mlx5_ib_qp *qp, struct ib_udata *udata, 762 struct ib_qp_init_attr *attr, 763 u32 **in, 764 struct mlx5_ib_create_qp_resp *resp, int *inlen, 765 struct mlx5_ib_qp_base *base) 766{ 767 struct mlx5_ib_ucontext *context; 768 struct mlx5_ib_create_qp ucmd; 769 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; 770 int page_shift = 0; 771 int uar_index = 0; 772 int npages; 773 u32 offset = 0; 774 int bfregn; 775 int ncont = 0; 776 __be64 *pas; 777 void *qpc; 778 int err; 779 u16 uid; 780 u32 uar_flags; 781 782 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); 783 if (err) { 784 mlx5_ib_dbg(dev, "copy failed\n"); 785 return err; 786 } 787 788 context = to_mucontext(pd->uobject->context); 789 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX | 790 MLX5_QP_FLAG_BFREG_INDEX); 791 switch (uar_flags) { 792 case MLX5_QP_FLAG_UAR_PAGE_INDEX: 793 uar_index = ucmd.bfreg_index; 794 bfregn = MLX5_IB_INVALID_BFREG; 795 break; 796 case MLX5_QP_FLAG_BFREG_INDEX: 797 uar_index = bfregn_to_uar_index(dev, &context->bfregi, 798 ucmd.bfreg_index, true); 799 if (uar_index < 0) 800 return uar_index; 801 bfregn = MLX5_IB_INVALID_BFREG; 802 break; 803 case 0: 804 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 805 return -EINVAL; 806 bfregn = alloc_bfreg(dev, &context->bfregi); 807 if (bfregn < 0) 808 return bfregn; 809 break; 810 default: 811 return -EINVAL; 812 } 813 814 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); 815 if (bfregn != MLX5_IB_INVALID_BFREG) 816 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, 817 false); 818 819 qp->rq.offset = 0; 820 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 821 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 822 823 err = set_user_buf_size(dev, qp, &ucmd, base, attr); 824 if (err) 825 goto err_bfreg; 826 827 if (ucmd.buf_addr && ubuffer->buf_size) { 828 ubuffer->buf_addr = ucmd.buf_addr; 829 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, 830 ubuffer->buf_size, 831 &ubuffer->umem, &npages, &page_shift, 832 &ncont, &offset); 833 if (err) 834 goto err_bfreg; 835 } else { 836 ubuffer->umem = NULL; 837 } 838 839 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 840 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; 841 *in = mlx5_vzalloc(*inlen); 842 if (!*in) { 843 err = -ENOMEM; 844 goto err_umem; 845 } 846 847 uid = (attr->qp_type != IB_QPT_XRC_TGT && 848 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; 849 MLX5_SET(create_qp_in, *in, uid, uid); 850 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); 851 if (ubuffer->umem) 852 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); 853 854 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 855 856 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 857 MLX5_SET(qpc, qpc, page_offset, offset); 858 859 MLX5_SET(qpc, qpc, uar_page, uar_index); 860 if (bfregn != MLX5_IB_INVALID_BFREG) 861 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); 862 else 863 resp->bfreg_index = MLX5_IB_INVALID_BFREG; 864 qp->bfregn = bfregn; 865 866 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db); 867 if (err) { 868 mlx5_ib_dbg(dev, "map failed\n"); 869 goto err_free; 870 } 871 872 err = ib_copy_to_udata(udata, resp, sizeof(*resp)); 873 if (err) { 874 mlx5_ib_dbg(dev, "copy failed\n"); 875 goto err_unmap; 876 } 877 qp->create_type = MLX5_QP_USER; 878 879 return 0; 880 881err_unmap: 882 mlx5_ib_db_unmap_user(context, &qp->db); 883 884err_free: 885 kvfree(*in); 886 887err_umem: 888 if (ubuffer->umem) 889 ib_umem_release(ubuffer->umem); 890 891err_bfreg: 892 if (bfregn != MLX5_IB_INVALID_BFREG) 893 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); 894 return err; 895} 896 897static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp, 898 struct mlx5_ib_qp_base *base, 899 struct ib_udata *udata) 900{ 901 struct mlx5_ib_ucontext *context = 902 rdma_udata_to_drv_context( 903 udata, 904 struct mlx5_ib_ucontext, 905 ibucontext); 906 907 mlx5_ib_db_unmap_user(context, &qp->db); 908 if (base->ubuffer.umem) 909 ib_umem_release(base->ubuffer.umem); 910 911 /* 912 * Free only the BFREGs which are handled by the kernel. 913 * BFREGs of UARs allocated dynamically are handled by user. 914 */ 915 if (qp->bfregn != MLX5_IB_INVALID_BFREG) 916 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); 917} 918 919static int create_kernel_qp(struct mlx5_ib_dev *dev, 920 struct ib_qp_init_attr *init_attr, 921 struct mlx5_ib_qp *qp, 922 u32 **in, int *inlen, 923 struct mlx5_ib_qp_base *base) 924{ 925 int uar_index; 926 void *qpc; 927 int err; 928 929 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | 930 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | 931 IB_QP_CREATE_IPOIB_UD_LSO | 932 MLX5_IB_QP_CREATE_SQPN_QP1 | 933 MLX5_IB_QP_CREATE_WC_TEST)) 934 return -EINVAL; 935 936 spin_lock_init(&qp->bf.lock32); 937 938 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) 939 qp->bf.bfreg = &dev->fp_bfreg; 940 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST) 941 qp->bf.bfreg = &dev->wc_bfreg; 942 else 943 qp->bf.bfreg = &dev->bfreg; 944 945 /* We need to divide by two since each register is comprised of 946 * two buffers of identical size, namely odd and even 947 */ 948 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; 949 uar_index = qp->bf.bfreg->index; 950 951 err = calc_sq_size(dev, init_attr, qp); 952 if (err < 0) { 953 mlx5_ib_dbg(dev, "err %d\n", err); 954 return err; 955 } 956 957 qp->rq.offset = 0; 958 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 959 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); 960 961 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, 962 2 * PAGE_SIZE, &qp->buf); 963 if (err) { 964 mlx5_ib_dbg(dev, "err %d\n", err); 965 return err; 966 } 967 968 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt); 969 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + 970 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; 971 *in = mlx5_vzalloc(*inlen); 972 if (!*in) { 973 err = -ENOMEM; 974 goto err_buf; 975 } 976 977 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); 978 MLX5_SET(qpc, qpc, uar_page, uar_index); 979 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 980 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); 981 982 /* Set "fast registration enabled" for all kernel QPs */ 983 MLX5_SET(qpc, qpc, fre, 1); 984 MLX5_SET(qpc, qpc, rlky, 1); 985 986 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) { 987 MLX5_SET(qpc, qpc, deth_sqpn, 1); 988 qp->flags |= MLX5_IB_QP_SQPN_QP1; 989 } 990 991 mlx5_fill_page_array(&qp->buf, 992 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas)); 993 994 err = mlx5_db_alloc(dev->mdev, &qp->db); 995 if (err) { 996 mlx5_ib_dbg(dev, "err %d\n", err); 997 goto err_free; 998 } 999 1000 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL); 1001 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL); 1002 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL); 1003 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL); 1004 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL); 1005 1006 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || 1007 !qp->sq.w_list || !qp->sq.wqe_head) { 1008 err = -ENOMEM; 1009 goto err_wrid; 1010 } 1011 qp->create_type = MLX5_QP_KERNEL; 1012 1013 return 0; 1014 1015err_wrid: 1016 kfree(qp->sq.wqe_head); 1017 kfree(qp->sq.w_list); 1018 kfree(qp->sq.wrid); 1019 kfree(qp->sq.wr_data); 1020 kfree(qp->rq.wrid); 1021 mlx5_db_free(dev->mdev, &qp->db); 1022 1023err_free: 1024 kvfree(*in); 1025 1026err_buf: 1027 mlx5_buf_free(dev->mdev, &qp->buf); 1028 return err; 1029} 1030 1031static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1032{ 1033 kfree(qp->sq.wqe_head); 1034 kfree(qp->sq.w_list); 1035 kfree(qp->sq.wrid); 1036 kfree(qp->sq.wr_data); 1037 kfree(qp->rq.wrid); 1038 mlx5_db_free(dev->mdev, &qp->db); 1039 mlx5_buf_free(dev->mdev, &qp->buf); 1040} 1041 1042static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) 1043{ 1044 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || 1045 (attr->qp_type == IB_QPT_XRC_INI)) 1046 return MLX5_SRQ_RQ; 1047 else if (!qp->has_rq) 1048 return MLX5_ZERO_LEN_RQ; 1049 else 1050 return MLX5_NON_ZERO_RQ; 1051} 1052 1053static int is_connected(enum ib_qp_type qp_type) 1054{ 1055 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC) 1056 return 1; 1057 1058 return 0; 1059} 1060 1061static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1062 struct mlx5_ib_sq *sq, u32 tdn, 1063 struct ib_pd *pd) 1064{ 1065 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1066 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 1067 1068 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); 1069 MLX5_SET(tisc, tisc, transport_domain, tdn); 1070 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); 1071} 1072 1073static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, 1074 struct mlx5_ib_sq *sq, struct ib_pd *pd) 1075{ 1076 mlx5_core_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); 1077} 1078 1079static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1080 struct mlx5_ib_sq *sq, void *qpin, 1081 struct ib_pd *pd) 1082{ 1083 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; 1084 __be64 *pas; 1085 void *in; 1086 void *sqc; 1087 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1088 void *wq; 1089 int inlen; 1090 int err; 1091 int page_shift = 0; 1092 int npages; 1093 int ncont = 0; 1094 u32 offset = 0; 1095 u8 ts_format; 1096 1097 ts_format = mlx5_get_sq_default_ts(dev->mdev); 1098 1099 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size, 1100 &sq->ubuffer.umem, &npages, &page_shift, 1101 &ncont, &offset); 1102 if (err) 1103 return err; 1104 1105 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; 1106 in = mlx5_vzalloc(inlen); 1107 if (!in) { 1108 err = -ENOMEM; 1109 goto err_umem; 1110 } 1111 1112 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); 1113 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1114 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1115 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1116 MLX5_SET(sqc, sqc, ts_format, ts_format); 1117 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1118 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); 1119 MLX5_SET(sqc, sqc, tis_lst_sz, 1); 1120 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); 1121 1122 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1123 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1124 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1125 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); 1126 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1127 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 1128 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); 1129 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); 1130 MLX5_SET(wq, wq, page_offset, offset); 1131 1132 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1133 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); 1134 1135 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); 1136 1137 kvfree(in); 1138 1139 if (err) 1140 goto err_umem; 1141 1142 return 0; 1143 1144err_umem: 1145 ib_umem_release(sq->ubuffer.umem); 1146 sq->ubuffer.umem = NULL; 1147 1148 return err; 1149} 1150 1151static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, 1152 struct mlx5_ib_sq *sq) 1153{ 1154 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); 1155 ib_umem_release(sq->ubuffer.umem); 1156} 1157 1158static int get_rq_pas_size(void *qpc) 1159{ 1160 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; 1161 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); 1162 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); 1163 u32 page_offset = MLX5_GET(qpc, qpc, page_offset); 1164 u32 po_quanta = 1 << (log_page_size - 6); 1165 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); 1166 u32 page_size = 1 << log_page_size; 1167 u32 rq_sz_po = rq_sz + (page_offset * po_quanta); 1168 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; 1169 1170 return rq_num_pas * sizeof(u64); 1171} 1172 1173static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1174 struct mlx5_ib_rq *rq, void *qpin, 1175 struct ib_pd *pd) 1176{ 1177 struct mlx5_ib_qp *mqp = rq->base.container_mibqp; 1178 __be64 *pas; 1179 __be64 *qp_pas; 1180 void *in; 1181 void *rqc; 1182 void *wq; 1183 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); 1184 int inlen; 1185 int err; 1186 u32 rq_pas_size = get_rq_pas_size(qpc); 1187 u8 ts_format; 1188 1189 ts_format = mlx5_get_rq_default_ts(dev->mdev); 1190 1191 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; 1192 in = mlx5_vzalloc(inlen); 1193 if (!in) 1194 return -ENOMEM; 1195 1196 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 1197 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 1198 MLX5_SET(rqc, rqc, vlan_strip_disable, 1); 1199 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 1200 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 1201 MLX5_SET(rqc, rqc, ts_format, ts_format); 1202 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 1203 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); 1204 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); 1205 1206 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) 1207 MLX5_SET(rqc, rqc, scatter_fcs, 1); 1208 1209 wq = MLX5_ADDR_OF(rqc, rqc, wq); 1210 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1211 MLX5_SET(wq, wq, end_padding_mode, 1212 MLX5_GET(qpc, qpc, end_padding_mode)); 1213 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); 1214 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); 1215 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); 1216 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); 1217 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); 1218 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); 1219 1220 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 1221 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); 1222 memcpy(pas, qp_pas, rq_pas_size); 1223 1224 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); 1225 1226 kvfree(in); 1227 1228 return err; 1229} 1230 1231static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, 1232 struct mlx5_ib_rq *rq) 1233{ 1234 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); 1235} 1236 1237static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1238 struct mlx5_ib_rq *rq, u32 tdn, 1239 struct ib_pd *pd) 1240{ 1241 u32 *in; 1242 void *tirc; 1243 int inlen; 1244 int err; 1245 1246 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1247 in = mlx5_vzalloc(inlen); 1248 if (!in) 1249 return -ENOMEM; 1250 1251 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1252 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1253 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); 1254 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); 1255 MLX5_SET(tirc, tirc, transport_domain, tdn); 1256 1257 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); 1258 1259 kvfree(in); 1260 1261 return err; 1262} 1263 1264static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, 1265 struct mlx5_ib_rq *rq, 1266 struct ib_pd *pd) 1267{ 1268 mlx5_core_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); 1269} 1270 1271static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1272 u32 *in, 1273 struct ib_pd *pd) 1274{ 1275 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1276 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1277 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1278 struct ib_uobject *uobj = pd->uobject; 1279 struct ib_ucontext *ucontext = uobj->context; 1280 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1281 int err; 1282 u32 tdn = mucontext->tdn; 1283 1284 if (qp->sq.wqe_cnt) { 1285 err = create_raw_packet_qp_tis(dev, sq, tdn, pd); 1286 if (err) 1287 return err; 1288 1289 err = create_raw_packet_qp_sq(dev, sq, in, pd); 1290 if (err) 1291 goto err_destroy_tis; 1292 1293 sq->base.container_mibqp = qp; 1294 } 1295 1296 if (qp->rq.wqe_cnt) { 1297 rq->base.container_mibqp = qp; 1298 1299 err = create_raw_packet_qp_rq(dev, rq, in, pd); 1300 if (err) 1301 goto err_destroy_sq; 1302 1303 1304 err = create_raw_packet_qp_tir(dev, rq, tdn, pd); 1305 if (err) 1306 goto err_destroy_rq; 1307 } 1308 1309 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : 1310 rq->base.mqp.qpn; 1311 1312 return 0; 1313 1314err_destroy_rq: 1315 destroy_raw_packet_qp_rq(dev, rq); 1316err_destroy_sq: 1317 if (!qp->sq.wqe_cnt) 1318 return err; 1319 destroy_raw_packet_qp_sq(dev, sq); 1320err_destroy_tis: 1321 destroy_raw_packet_qp_tis(dev, sq, pd); 1322 1323 return err; 1324} 1325 1326static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, 1327 struct mlx5_ib_qp *qp) 1328{ 1329 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 1330 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1331 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1332 1333 if (qp->rq.wqe_cnt) { 1334 destroy_raw_packet_qp_tir(dev, rq, qp->ibqp.pd); 1335 destroy_raw_packet_qp_rq(dev, rq); 1336 } 1337 1338 if (qp->sq.wqe_cnt) { 1339 destroy_raw_packet_qp_sq(dev, sq); 1340 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); 1341 } 1342} 1343 1344static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, 1345 struct mlx5_ib_raw_packet_qp *raw_packet_qp) 1346{ 1347 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 1348 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 1349 1350 sq->sq = &qp->sq; 1351 rq->rq = &qp->rq; 1352 sq->doorbell = &qp->db; 1353 rq->doorbell = &qp->db; 1354} 1355 1356static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) 1357{ 1358 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn, 1359 to_mpd(qp->ibqp.pd)->uid); 1360} 1361 1362static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1363 struct ib_pd *pd, 1364 struct ib_qp_init_attr *init_attr, 1365 struct ib_udata *udata) 1366{ 1367 struct ib_uobject *uobj = pd->uobject; 1368 struct ib_ucontext *ucontext = uobj->context; 1369 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext); 1370 struct mlx5_ib_create_qp_resp resp = {}; 1371 int inlen; 1372 int err; 1373 u32 *in; 1374 void *tirc; 1375 void *hfso; 1376 u32 selected_fields = 0; 1377 size_t min_resp_len; 1378 u32 tdn = mucontext->tdn; 1379 struct mlx5_ib_create_qp_rss ucmd = {}; 1380 size_t required_cmd_sz; 1381 1382 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1383 return -EOPNOTSUPP; 1384 1385 if (init_attr->create_flags || init_attr->send_cq) 1386 return -EINVAL; 1387 1388 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); 1389 if (udata->outlen < min_resp_len) 1390 return -EINVAL; 1391 1392 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1); 1393 if (udata->inlen < required_cmd_sz) { 1394 mlx5_ib_dbg(dev, "invalid inlen\n"); 1395 return -EINVAL; 1396 } 1397 1398 if (udata->inlen > sizeof(ucmd) && 1399 !ib_is_udata_cleared(udata, sizeof(ucmd), 1400 udata->inlen - sizeof(ucmd))) { 1401 mlx5_ib_dbg(dev, "inlen is not supported\n"); 1402 return -EOPNOTSUPP; 1403 } 1404 1405 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 1406 mlx5_ib_dbg(dev, "copy failed\n"); 1407 return -EFAULT; 1408 } 1409 1410 if (ucmd.comp_mask) { 1411 mlx5_ib_dbg(dev, "invalid comp mask\n"); 1412 return -EOPNOTSUPP; 1413 } 1414 1415 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) { 1416 mlx5_ib_dbg(dev, "invalid reserved\n"); 1417 return -EOPNOTSUPP; 1418 } 1419 1420 err = ib_copy_to_udata(udata, &resp, min_resp_len); 1421 if (err) { 1422 mlx5_ib_dbg(dev, "copy failed\n"); 1423 return -EINVAL; 1424 } 1425 1426 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 1427 in = mlx5_vzalloc(inlen); 1428 if (!in) 1429 return -ENOMEM; 1430 1431 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); 1432 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context); 1433 MLX5_SET(tirc, tirc, disp_type, 1434 MLX5_TIRC_DISP_TYPE_INDIRECT); 1435 MLX5_SET(tirc, tirc, indirect_table, 1436 init_attr->rwq_ind_tbl->ind_tbl_num); 1437 MLX5_SET(tirc, tirc, transport_domain, tdn); 1438 1439 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 1440 switch (ucmd.rx_hash_function) { 1441 case MLX5_RX_HASH_FUNC_TOEPLITZ: 1442 { 1443 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); 1444 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); 1445 1446 if (len != ucmd.rx_key_len) { 1447 err = -EINVAL; 1448 goto err; 1449 } 1450 1451 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FUNC_TOEPLITZ); 1452 memcpy(rss_key, ucmd.rx_hash_key, len); 1453 break; 1454 } 1455 default: 1456 err = -EOPNOTSUPP; 1457 goto err; 1458 } 1459 1460 if (!ucmd.rx_hash_fields_mask) { 1461 /* special case when this TIR serves as steering entry without hashing */ 1462 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) 1463 goto create_tir; 1464 err = -EINVAL; 1465 goto err; 1466 } 1467 1468 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1469 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && 1470 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1471 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { 1472 err = -EINVAL; 1473 goto err; 1474 } 1475 1476 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ 1477 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1478 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) 1479 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1480 MLX5_L3_PROT_TYPE_IPV4); 1481 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || 1482 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1483 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 1484 MLX5_L3_PROT_TYPE_IPV6); 1485 1486 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1487 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) && 1488 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1489 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) { 1490 err = -EINVAL; 1491 goto err; 1492 } 1493 1494 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ 1495 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1496 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) 1497 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1498 MLX5_L4_PROT_TYPE_TCP); 1499 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || 1500 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1501 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 1502 MLX5_L4_PROT_TYPE_UDP); 1503 1504 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || 1505 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) 1506 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; 1507 1508 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || 1509 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) 1510 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; 1511 1512 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || 1513 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) 1514 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; 1515 1516 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || 1517 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) 1518 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; 1519 1520 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); 1521 1522create_tir: 1523 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); 1524 1525 if (err) 1526 goto err; 1527 1528 kvfree(in); 1529 /* qpn is reserved for that QP */ 1530 qp->trans_qp.base.mqp.qpn = 0; 1531 qp->flags |= MLX5_IB_QP_RSS; 1532 return 0; 1533 1534err: 1535 kvfree(in); 1536 return err; 1537} 1538 1539static int atomic_size_to_mode(int size_mask) 1540{ 1541 /* driver does not support atomic_size > 256B 1542 * and does not know how to translate bigger sizes 1543 */ 1544 int supported_size_mask = size_mask & 0x1ff; 1545 int log_max_size; 1546 1547 if (!supported_size_mask) 1548 return -EOPNOTSUPP; 1549 1550 log_max_size = __fls(supported_size_mask); 1551 1552 if (log_max_size > 3) 1553 return log_max_size; 1554 1555 return MLX5_ATOMIC_MODE_8B; 1556} 1557 1558static int get_atomic_mode(struct mlx5_ib_dev *dev, 1559 enum ib_qp_type qp_type) 1560{ 1561 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 1562 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); 1563 int atomic_mode = -EOPNOTSUPP; 1564 int atomic_size_mask; 1565 1566 if (!atomic) 1567 return -EOPNOTSUPP; 1568 1569 if (qp_type == MLX5_IB_QPT_DCT) 1570 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); 1571 else 1572 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 1573 1574 if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) || 1575 (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD)) 1576 atomic_mode = atomic_size_to_mode(atomic_size_mask); 1577 1578 if (atomic_mode <= 0 && 1579 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && 1580 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) 1581 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; 1582 1583 return atomic_mode; 1584} 1585 1586static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, 1587 struct ib_qp_init_attr *init_attr, 1588 struct ib_udata *udata, struct mlx5_ib_qp *qp) 1589{ 1590 struct mlx5_ib_resources *devr = &dev->devr; 1591 int inlen = MLX5_ST_SZ_BYTES(create_qp_in); 1592 struct mlx5_core_dev *mdev = dev->mdev; 1593 struct mlx5_ib_create_qp_resp resp; 1594 struct mlx5_ib_cq *send_cq; 1595 struct mlx5_ib_cq *recv_cq; 1596 unsigned long flags; 1597 u32 uidx = MLX5_IB_DEFAULT_UIDX; 1598 struct mlx5_ib_create_qp ucmd; 1599 struct mlx5_ib_qp_base *base; 1600 void *qpc; 1601 u32 *in; 1602 int err; 1603 1604 base = init_attr->qp_type == IB_QPT_RAW_PACKET ? 1605 &qp->raw_packet_qp.rq.base : 1606 &qp->trans_qp.base; 1607 1608 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1609 mlx5_ib_odp_create_qp(qp); 1610 1611 mutex_init(&qp->mutex); 1612 spin_lock_init(&qp->sq.lock); 1613 spin_lock_init(&qp->rq.lock); 1614 1615 if (init_attr->rwq_ind_tbl) { 1616 if (!udata) 1617 return -ENOSYS; 1618 1619 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); 1620 return err; 1621 } 1622 1623 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { 1624 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { 1625 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); 1626 return -EINVAL; 1627 } else { 1628 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1629 } 1630 } 1631 1632 if (init_attr->create_flags & 1633 (IB_QP_CREATE_CROSS_CHANNEL | 1634 IB_QP_CREATE_MANAGED_SEND | 1635 IB_QP_CREATE_MANAGED_RECV)) { 1636 if (!MLX5_CAP_GEN(mdev, cd)) { 1637 mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); 1638 return -EINVAL; 1639 } 1640 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) 1641 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; 1642 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) 1643 qp->flags |= MLX5_IB_QP_MANAGED_SEND; 1644 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) 1645 qp->flags |= MLX5_IB_QP_MANAGED_RECV; 1646 } 1647 1648 if (init_attr->qp_type == IB_QPT_UD && 1649 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) 1650 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 1651 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); 1652 return -EOPNOTSUPP; 1653 } 1654 1655 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { 1656 if (init_attr->qp_type != IB_QPT_RAW_PACKET) { 1657 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); 1658 return -EOPNOTSUPP; 1659 } 1660 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || 1661 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { 1662 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); 1663 return -EOPNOTSUPP; 1664 } 1665 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; 1666 } 1667 1668 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 1669 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; 1670 1671 if (pd && pd->uobject) { 1672 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { 1673 mlx5_ib_dbg(dev, "copy failed\n"); 1674 return -EFAULT; 1675 } 1676 1677 err = get_qp_user_index(to_mucontext(pd->uobject->context), 1678 &ucmd, udata->inlen, &uidx); 1679 if (err) 1680 return err; 1681 1682 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); 1683 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); 1684 } else { 1685 qp->wq_sig = !!wq_signature; 1686 } 1687 1688 qp->has_rq = qp_has_rq(init_attr); 1689 err = set_rq_size(dev, &init_attr->cap, qp->has_rq, 1690 qp, (pd && pd->uobject) ? &ucmd : NULL); 1691 if (err) { 1692 mlx5_ib_dbg(dev, "err %d\n", err); 1693 return err; 1694 } 1695 1696 if (pd) { 1697 if (pd->uobject) { 1698 __u32 max_wqes = 1699 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1700 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); 1701 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || 1702 ucmd.rq_wqe_count != qp->rq.wqe_cnt) { 1703 mlx5_ib_dbg(dev, "invalid rq params\n"); 1704 return -EINVAL; 1705 } 1706 if (ucmd.sq_wqe_count > max_wqes) { 1707 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", 1708 ucmd.sq_wqe_count, max_wqes); 1709 return -EINVAL; 1710 } 1711 if (init_attr->create_flags & 1712 MLX5_IB_QP_CREATE_SQPN_QP1) { 1713 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); 1714 return -EINVAL; 1715 } 1716 err = create_user_qp(dev, pd, qp, udata, init_attr, &in, 1717 &resp, &inlen, base); 1718 if (err) 1719 mlx5_ib_dbg(dev, "err %d\n", err); 1720 } else { 1721 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, 1722 base); 1723 if (err) 1724 mlx5_ib_dbg(dev, "err %d\n", err); 1725 } 1726 1727 if (err) 1728 return err; 1729 } else { 1730 in = mlx5_vzalloc(inlen); 1731 if (!in) 1732 return -ENOMEM; 1733 1734 qp->create_type = MLX5_QP_EMPTY; 1735 } 1736 1737 if (is_sqp(init_attr->qp_type)) 1738 qp->port = init_attr->port_num; 1739 1740 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1741 1742 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type)); 1743 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1744 1745 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) 1746 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); 1747 else 1748 MLX5_SET(qpc, qpc, latency_sensitive, 1); 1749 1750 1751 if (qp->wq_sig) 1752 MLX5_SET(qpc, qpc, wq_signature, 1); 1753 1754 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 1755 MLX5_SET(qpc, qpc, block_lb_mc, 1); 1756 1757 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 1758 MLX5_SET(qpc, qpc, cd_master, 1); 1759 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 1760 MLX5_SET(qpc, qpc, cd_slave_send, 1); 1761 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 1762 MLX5_SET(qpc, qpc, cd_slave_receive, 1); 1763 1764 if (qp->scat_cqe && is_connected(init_attr->qp_type)) { 1765 int rcqe_sz; 1766 int scqe_sz; 1767 1768 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq); 1769 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq); 1770 1771 if (rcqe_sz == 128) 1772 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); 1773 else 1774 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); 1775 1776 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) { 1777 if (scqe_sz == 128) 1778 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); 1779 else 1780 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); 1781 } 1782 } 1783 1784 if (qp->rq.wqe_cnt) { 1785 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); 1786 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); 1787 } 1788 1789 if (init_attr->qp_type != IB_QPT_RAW_PACKET) 1790 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev)); 1791 1792 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); 1793 1794 if (qp->sq.wqe_cnt) 1795 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); 1796 else 1797 MLX5_SET(qpc, qpc, no_sq, 1); 1798 1799 /* Set default resources */ 1800 switch (init_attr->qp_type) { 1801 case IB_QPT_XRC_TGT: 1802 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1803 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); 1804 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1805 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); 1806 break; 1807 case IB_QPT_XRC_INI: 1808 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); 1809 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1810 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn); 1811 break; 1812 default: 1813 if (init_attr->srq) { 1814 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); 1815 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn); 1816 } else { 1817 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); 1818 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn); 1819 } 1820 } 1821 1822 if (init_attr->send_cq) 1823 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); 1824 1825 if (init_attr->recv_cq) 1826 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); 1827 1828 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); 1829 1830 /* 0xffffff means we ask to work with cqe version 0 */ 1831 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) 1832 MLX5_SET(qpc, qpc, user_index, uidx); 1833 1834 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ 1835 if (init_attr->qp_type == IB_QPT_UD && 1836 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { 1837 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); 1838 qp->flags |= MLX5_IB_QP_LSO; 1839 } 1840 1841 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 1842 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; 1843 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); 1844 err = create_raw_packet_qp(dev, qp, in, pd); 1845 } else { 1846 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); 1847 } 1848 1849 if (err) { 1850 mlx5_ib_dbg(dev, "create qp failed\n"); 1851 goto err_create; 1852 } 1853 1854 kvfree(in); 1855 1856 base->container_mibqp = qp; 1857 base->mqp.event = mlx5_ib_qp_event; 1858 1859 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, 1860 &send_cq, &recv_cq); 1861 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1862 mlx5_ib_lock_cqs(send_cq, recv_cq); 1863 /* Maintain device to QPs access, needed for further handling via reset 1864 * flow 1865 */ 1866 list_add_tail(&qp->qps_list, &dev->qp_list); 1867 /* Maintain CQ to QPs access, needed for further handling via reset flow 1868 */ 1869 if (send_cq) 1870 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); 1871 if (recv_cq) 1872 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); 1873 mlx5_ib_unlock_cqs(send_cq, recv_cq); 1874 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1875 1876 return 0; 1877 1878err_create: 1879 if (qp->create_type == MLX5_QP_USER) 1880 destroy_qp_user(dev, pd, qp, base, udata); 1881 else if (qp->create_type == MLX5_QP_KERNEL) 1882 destroy_qp_kernel(dev, qp); 1883 1884 kvfree(in); 1885 return err; 1886} 1887 1888static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1889 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 1890{ 1891 if (send_cq) { 1892 if (recv_cq) { 1893 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1894 spin_lock(&send_cq->lock); 1895 spin_lock_nested(&recv_cq->lock, 1896 SINGLE_DEPTH_NESTING); 1897 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1898 spin_lock(&send_cq->lock); 1899 __acquire(&recv_cq->lock); 1900 } else { 1901 spin_lock(&recv_cq->lock); 1902 spin_lock_nested(&send_cq->lock, 1903 SINGLE_DEPTH_NESTING); 1904 } 1905 } else { 1906 spin_lock(&send_cq->lock); 1907 __acquire(&recv_cq->lock); 1908 } 1909 } else if (recv_cq) { 1910 spin_lock(&recv_cq->lock); 1911 __acquire(&send_cq->lock); 1912 } else { 1913 __acquire(&send_cq->lock); 1914 __acquire(&recv_cq->lock); 1915 } 1916} 1917 1918static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) 1919 __releases(&send_cq->lock) __releases(&recv_cq->lock) 1920{ 1921 if (send_cq) { 1922 if (recv_cq) { 1923 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 1924 spin_unlock(&recv_cq->lock); 1925 spin_unlock(&send_cq->lock); 1926 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { 1927 __release(&recv_cq->lock); 1928 spin_unlock(&send_cq->lock); 1929 } else { 1930 spin_unlock(&send_cq->lock); 1931 spin_unlock(&recv_cq->lock); 1932 } 1933 } else { 1934 __release(&recv_cq->lock); 1935 spin_unlock(&send_cq->lock); 1936 } 1937 } else if (recv_cq) { 1938 __release(&send_cq->lock); 1939 spin_unlock(&recv_cq->lock); 1940 } else { 1941 __release(&recv_cq->lock); 1942 __release(&send_cq->lock); 1943 } 1944} 1945 1946static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) 1947{ 1948 return to_mpd(qp->ibqp.pd); 1949} 1950 1951static void get_cqs(enum ib_qp_type qp_type, 1952 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, 1953 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) 1954{ 1955 switch (qp_type) { 1956 case IB_QPT_XRC_TGT: 1957 *send_cq = NULL; 1958 *recv_cq = NULL; 1959 break; 1960 case MLX5_IB_QPT_REG_UMR: 1961 case IB_QPT_XRC_INI: 1962 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1963 *recv_cq = NULL; 1964 break; 1965 1966 case IB_QPT_SMI: 1967 case MLX5_IB_QPT_HW_GSI: 1968 case IB_QPT_RC: 1969 case IB_QPT_UC: 1970 case IB_QPT_UD: 1971 case IB_QPT_RAW_IPV6: 1972 case IB_QPT_RAW_ETHERTYPE: 1973 case IB_QPT_RAW_PACKET: 1974 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; 1975 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; 1976 break; 1977 1978 case IB_QPT_MAX: 1979 default: 1980 *send_cq = NULL; 1981 *recv_cq = NULL; 1982 break; 1983 } 1984} 1985 1986static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1987 const struct mlx5_modify_raw_qp_param *raw_qp_param, 1988 u8 lag_tx_affinity); 1989 1990static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 1991 struct ib_udata *udata) 1992{ 1993 struct mlx5_ib_cq *send_cq, *recv_cq; 1994 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 1995 unsigned long flags; 1996 int err; 1997 1998 if (qp->ibqp.rwq_ind_tbl) { 1999 destroy_rss_raw_qp_tir(dev, qp); 2000 return; 2001 } 2002 2003 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ? 2004 &qp->raw_packet_qp.rq.base : 2005 &qp->trans_qp.base; 2006 2007 if (qp->state != IB_QPS_RESET) { 2008 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) { 2009 mlx5_ib_qp_disable_pagefaults(qp); 2010 err = mlx5_core_qp_modify(dev->mdev, 2011 MLX5_CMD_OP_2RST_QP, 0, 2012 NULL, &base->mqp); 2013 } else { 2014 struct mlx5_modify_raw_qp_param raw_qp_param = { 2015 .operation = MLX5_CMD_OP_2RST_QP 2016 }; 2017 2018 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2019 } 2020 if (err) 2021 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", 2022 base->mqp.qpn); 2023 } 2024 2025 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2026 &send_cq, &recv_cq); 2027 2028 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 2029 mlx5_ib_lock_cqs(send_cq, recv_cq); 2030 /* del from lists under both locks above to protect reset flow paths */ 2031 list_del(&qp->qps_list); 2032 if (send_cq) 2033 list_del(&qp->cq_send_list); 2034 2035 if (recv_cq) 2036 list_del(&qp->cq_recv_list); 2037 2038 if (qp->create_type == MLX5_QP_KERNEL) { 2039 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2040 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); 2041 if (send_cq != recv_cq) 2042 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, 2043 NULL); 2044 } 2045 mlx5_ib_unlock_cqs(send_cq, recv_cq); 2046 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 2047 2048 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2049 destroy_raw_packet_qp(dev, qp); 2050 } else { 2051 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); 2052 if (err) 2053 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", 2054 base->mqp.qpn); 2055 } 2056 2057 if (qp->create_type == MLX5_QP_KERNEL) 2058 destroy_qp_kernel(dev, qp); 2059 else if (qp->create_type == MLX5_QP_USER) 2060 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata); 2061} 2062 2063static const char *ib_qp_type_str(enum ib_qp_type type) 2064{ 2065 switch (type) { 2066 case IB_QPT_SMI: 2067 return "IB_QPT_SMI"; 2068 case IB_QPT_GSI: 2069 return "IB_QPT_GSI"; 2070 case IB_QPT_RC: 2071 return "IB_QPT_RC"; 2072 case IB_QPT_UC: 2073 return "IB_QPT_UC"; 2074 case IB_QPT_UD: 2075 return "IB_QPT_UD"; 2076 case IB_QPT_RAW_IPV6: 2077 return "IB_QPT_RAW_IPV6"; 2078 case IB_QPT_RAW_ETHERTYPE: 2079 return "IB_QPT_RAW_ETHERTYPE"; 2080 case IB_QPT_XRC_INI: 2081 return "IB_QPT_XRC_INI"; 2082 case IB_QPT_XRC_TGT: 2083 return "IB_QPT_XRC_TGT"; 2084 case IB_QPT_RAW_PACKET: 2085 return "IB_QPT_RAW_PACKET"; 2086 case MLX5_IB_QPT_REG_UMR: 2087 return "MLX5_IB_QPT_REG_UMR"; 2088 case IB_QPT_MAX: 2089 default: 2090 return "Invalid QP type"; 2091 } 2092} 2093 2094struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 2095 struct ib_qp_init_attr *init_attr, 2096 struct ib_udata *udata) 2097{ 2098 struct mlx5_ib_dev *dev; 2099 struct mlx5_ib_qp *qp; 2100 u16 xrcdn = 0; 2101 int err; 2102 2103 if (pd) { 2104 dev = to_mdev(pd->device); 2105 2106 if (init_attr->qp_type == IB_QPT_RAW_PACKET) { 2107 if (!pd->uobject) { 2108 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); 2109 return ERR_PTR(-EINVAL); 2110 } else if (!to_mucontext(pd->uobject->context)->cqe_version) { 2111 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); 2112 return ERR_PTR(-EINVAL); 2113 } 2114 } 2115 } else { 2116 /* being cautious here */ 2117 if (init_attr->qp_type != IB_QPT_XRC_TGT && 2118 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { 2119 pr_warn("%s: no PD for transport %s\n", __func__, 2120 ib_qp_type_str(init_attr->qp_type)); 2121 return ERR_PTR(-EINVAL); 2122 } 2123 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); 2124 } 2125 2126 switch (init_attr->qp_type) { 2127 case IB_QPT_XRC_TGT: 2128 case IB_QPT_XRC_INI: 2129 if (!MLX5_CAP_GEN(dev->mdev, xrc)) { 2130 mlx5_ib_dbg(dev, "XRC not supported\n"); 2131 return ERR_PTR(-ENOSYS); 2132 } 2133 init_attr->recv_cq = NULL; 2134 if (init_attr->qp_type == IB_QPT_XRC_TGT) { 2135 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 2136 init_attr->send_cq = NULL; 2137 } 2138 2139 /* fall through */ 2140 case IB_QPT_RAW_PACKET: 2141 case IB_QPT_RC: 2142 case IB_QPT_UC: 2143 case IB_QPT_UD: 2144 case IB_QPT_SMI: 2145 case MLX5_IB_QPT_HW_GSI: 2146 case MLX5_IB_QPT_REG_UMR: 2147 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 2148 if (!qp) 2149 return ERR_PTR(-ENOMEM); 2150 2151 err = create_qp_common(dev, pd, init_attr, udata, qp); 2152 if (err) { 2153 mlx5_ib_dbg(dev, "create_qp_common failed\n"); 2154 kfree(qp); 2155 return ERR_PTR(err); 2156 } 2157 2158 if (is_qp0(init_attr->qp_type)) 2159 qp->ibqp.qp_num = 0; 2160 else if (is_qp1(init_attr->qp_type)) 2161 qp->ibqp.qp_num = 1; 2162 else 2163 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; 2164 2165 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", 2166 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, 2167 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, 2168 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); 2169 2170 qp->trans_qp.xrcdn = xrcdn; 2171 2172 break; 2173 2174 case IB_QPT_GSI: 2175 return mlx5_ib_gsi_create_qp(pd, init_attr); 2176 2177 case IB_QPT_RAW_IPV6: 2178 case IB_QPT_RAW_ETHERTYPE: 2179 case IB_QPT_MAX: 2180 default: 2181 mlx5_ib_dbg(dev, "unsupported qp type %d\n", 2182 init_attr->qp_type); 2183 /* Don't support raw QPs */ 2184 return ERR_PTR(-EINVAL); 2185 } 2186 2187 return &qp->ibqp; 2188} 2189 2190int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 2191{ 2192 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2193 struct mlx5_ib_qp *mqp = to_mqp(qp); 2194 2195 if (unlikely(qp->qp_type == IB_QPT_GSI)) 2196 return mlx5_ib_gsi_destroy_qp(qp); 2197 2198 destroy_qp_common(dev, mqp, udata); 2199 2200 kfree(mqp); 2201 2202 return 0; 2203} 2204 2205static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, 2206 const struct ib_qp_attr *attr, 2207 int attr_mask, __be32 *hw_access_flags_be) 2208{ 2209 u8 dest_rd_atomic; 2210 u32 access_flags, hw_access_flags = 0; 2211 2212 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); 2213 2214 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2215 dest_rd_atomic = attr->max_dest_rd_atomic; 2216 else 2217 dest_rd_atomic = qp->trans_qp.resp_depth; 2218 2219 if (attr_mask & IB_QP_ACCESS_FLAGS) 2220 access_flags = attr->qp_access_flags; 2221 else 2222 access_flags = qp->trans_qp.atomic_rd_en; 2223 2224 if (!dest_rd_atomic) 2225 access_flags &= IB_ACCESS_REMOTE_WRITE; 2226 2227 if (access_flags & IB_ACCESS_REMOTE_READ) 2228 hw_access_flags |= MLX5_QP_BIT_RRE; 2229 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { 2230 int atomic_mode; 2231 2232 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); 2233 if (atomic_mode < 0) 2234 return -EOPNOTSUPP; 2235 2236 hw_access_flags |= MLX5_QP_BIT_RAE; 2237 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF; 2238 } 2239 2240 if (access_flags & IB_ACCESS_REMOTE_WRITE) 2241 hw_access_flags |= MLX5_QP_BIT_RWE; 2242 2243 *hw_access_flags_be = cpu_to_be32(hw_access_flags); 2244 2245 return 0; 2246} 2247 2248enum { 2249 MLX5_PATH_FLAG_FL = 1 << 0, 2250 MLX5_PATH_FLAG_FREE_AR = 1 << 1, 2251 MLX5_PATH_FLAG_COUNTER = 1 << 2, 2252}; 2253 2254static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) 2255{ 2256 if (rate == IB_RATE_PORT_CURRENT) { 2257 return 0; 2258 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) { 2259 return -EINVAL; 2260 } else { 2261 while (rate != IB_RATE_2_5_GBPS && 2262 !(1 << (rate + MLX5_STAT_RATE_OFFSET) & 2263 MLX5_CAP_GEN(dev->mdev, stat_rate_support))) 2264 --rate; 2265 } 2266 2267 return rate + MLX5_STAT_RATE_OFFSET; 2268} 2269 2270static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, 2271 struct mlx5_ib_sq *sq, u8 sl, 2272 struct ib_pd *pd) 2273{ 2274 void *in; 2275 void *tisc; 2276 int inlen; 2277 int err; 2278 2279 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2280 in = mlx5_vzalloc(inlen); 2281 if (!in) 2282 return -ENOMEM; 2283 2284 MLX5_SET(modify_tis_in, in, bitmask.prio, 1); 2285 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2286 2287 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2288 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); 2289 2290 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2291 2292 kvfree(in); 2293 2294 return err; 2295} 2296 2297static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, 2298 struct mlx5_ib_sq *sq, u8 tx_affinity, 2299 struct ib_pd *pd) 2300{ 2301 void *in; 2302 void *tisc; 2303 int inlen; 2304 int err; 2305 2306 inlen = MLX5_ST_SZ_BYTES(modify_tis_in); 2307 in = mlx5_vzalloc(inlen); 2308 if (!in) 2309 return -ENOMEM; 2310 2311 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); 2312 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); 2313 2314 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); 2315 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); 2316 2317 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); 2318 2319 kvfree(in); 2320 2321 return err; 2322} 2323 2324static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2325 const struct ib_ah_attr *ah, 2326 struct mlx5_qp_path *path, u8 port, int attr_mask, 2327 u32 path_flags, const struct ib_qp_attr *attr, 2328 bool alt) 2329{ 2330 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port); 2331 int err; 2332 enum ib_gid_type gid_type; 2333 2334 if (attr_mask & IB_QP_PKEY_INDEX) 2335 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : 2336 attr->pkey_index); 2337 2338 if (ah->ah_flags & IB_AH_GRH) { 2339 if (ah->grh.sgid_index >= 2340 dev->mdev->port_caps[port - 1].gid_table_len) { 2341 pr_err("sgid_index (%u) too large. max is %d\n", 2342 ah->grh.sgid_index, 2343 dev->mdev->port_caps[port - 1].gid_table_len); 2344 return -EINVAL; 2345 } 2346 } 2347 2348 if (ll == IB_LINK_LAYER_ETHERNET) { 2349 if (!(ah->ah_flags & IB_AH_GRH)) 2350 return -EINVAL; 2351 err = mlx5_get_roce_gid_type(dev, port, ah->grh.sgid_index, 2352 &gid_type); 2353 if (err) 2354 return err; 2355 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac)); 2356 path->udp_sport = mlx5_get_roce_udp_sport(dev, port, 2357 ah->grh.sgid_index); 2358 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4; 2359 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) 2360 path->ecn_dscp = (ah->grh.traffic_class >> 2) & 0x3f; 2361 } else { 2362 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; 2363 path->fl_free_ar |= 2364 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; 2365 path->rlid = cpu_to_be16(ah->dlid); 2366 path->grh_mlid = ah->src_path_bits & 0x7f; 2367 if (ah->ah_flags & IB_AH_GRH) 2368 path->grh_mlid |= 1 << 7; 2369 path->dci_cfi_prio_sl = ah->sl & 0xf; 2370 } 2371 2372 if (ah->ah_flags & IB_AH_GRH) { 2373 path->mgid_index = ah->grh.sgid_index; 2374 path->hop_limit = ah->grh.hop_limit; 2375 path->tclass_flowlabel = 2376 cpu_to_be32((ah->grh.traffic_class << 20) | 2377 (ah->grh.flow_label)); 2378 memcpy(path->rgid, ah->grh.dgid.raw, 16); 2379 } 2380 2381 err = ib_rate_to_mlx5(dev, ah->static_rate); 2382 if (err < 0) 2383 return err; 2384 path->static_rate = err; 2385 path->port = port; 2386 2387 if (attr_mask & IB_QP_TIMEOUT) 2388 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; 2389 2390 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) 2391 return modify_raw_packet_eth_prio(dev->mdev, 2392 &qp->raw_packet_qp.sq, 2393 ah->sl & 0xf, qp->ibqp.pd); 2394 2395 return 0; 2396} 2397 2398static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { 2399 [MLX5_QP_STATE_INIT] = { 2400 [MLX5_QP_STATE_INIT] = { 2401 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2402 MLX5_QP_OPTPAR_RAE | 2403 MLX5_QP_OPTPAR_RWE | 2404 MLX5_QP_OPTPAR_PKEY_INDEX | 2405 MLX5_QP_OPTPAR_PRI_PORT, 2406 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2407 MLX5_QP_OPTPAR_PKEY_INDEX | 2408 MLX5_QP_OPTPAR_PRI_PORT, 2409 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2410 MLX5_QP_OPTPAR_Q_KEY | 2411 MLX5_QP_OPTPAR_PRI_PORT, 2412 }, 2413 [MLX5_QP_STATE_RTR] = { 2414 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2415 MLX5_QP_OPTPAR_RRE | 2416 MLX5_QP_OPTPAR_RAE | 2417 MLX5_QP_OPTPAR_RWE | 2418 MLX5_QP_OPTPAR_PKEY_INDEX, 2419 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2420 MLX5_QP_OPTPAR_RWE | 2421 MLX5_QP_OPTPAR_PKEY_INDEX, 2422 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | 2423 MLX5_QP_OPTPAR_Q_KEY, 2424 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | 2425 MLX5_QP_OPTPAR_Q_KEY, 2426 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2427 MLX5_QP_OPTPAR_RRE | 2428 MLX5_QP_OPTPAR_RAE | 2429 MLX5_QP_OPTPAR_RWE | 2430 MLX5_QP_OPTPAR_PKEY_INDEX, 2431 }, 2432 }, 2433 [MLX5_QP_STATE_RTR] = { 2434 [MLX5_QP_STATE_RTS] = { 2435 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2436 MLX5_QP_OPTPAR_RRE | 2437 MLX5_QP_OPTPAR_RAE | 2438 MLX5_QP_OPTPAR_RWE | 2439 MLX5_QP_OPTPAR_PM_STATE | 2440 MLX5_QP_OPTPAR_RNR_TIMEOUT, 2441 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | 2442 MLX5_QP_OPTPAR_RWE | 2443 MLX5_QP_OPTPAR_PM_STATE, 2444 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2445 }, 2446 }, 2447 [MLX5_QP_STATE_RTS] = { 2448 [MLX5_QP_STATE_RTS] = { 2449 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | 2450 MLX5_QP_OPTPAR_RAE | 2451 MLX5_QP_OPTPAR_RWE | 2452 MLX5_QP_OPTPAR_RNR_TIMEOUT | 2453 MLX5_QP_OPTPAR_PM_STATE | 2454 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2455 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | 2456 MLX5_QP_OPTPAR_PM_STATE | 2457 MLX5_QP_OPTPAR_ALT_ADDR_PATH, 2458 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | 2459 MLX5_QP_OPTPAR_SRQN | 2460 MLX5_QP_OPTPAR_CQN_RCV, 2461 }, 2462 }, 2463 [MLX5_QP_STATE_SQER] = { 2464 [MLX5_QP_STATE_RTS] = { 2465 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, 2466 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, 2467 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, 2468 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | 2469 MLX5_QP_OPTPAR_RWE | 2470 MLX5_QP_OPTPAR_RAE | 2471 MLX5_QP_OPTPAR_RRE, 2472 }, 2473 }, 2474}; 2475 2476static int ib_nr_to_mlx5_nr(int ib_mask) 2477{ 2478 switch (ib_mask) { 2479 case IB_QP_STATE: 2480 return 0; 2481 case IB_QP_CUR_STATE: 2482 return 0; 2483 case IB_QP_EN_SQD_ASYNC_NOTIFY: 2484 return 0; 2485 case IB_QP_ACCESS_FLAGS: 2486 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | 2487 MLX5_QP_OPTPAR_RAE; 2488 case IB_QP_PKEY_INDEX: 2489 return MLX5_QP_OPTPAR_PKEY_INDEX; 2490 case IB_QP_PORT: 2491 return MLX5_QP_OPTPAR_PRI_PORT; 2492 case IB_QP_QKEY: 2493 return MLX5_QP_OPTPAR_Q_KEY; 2494 case IB_QP_AV: 2495 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | 2496 MLX5_QP_OPTPAR_PRI_PORT; 2497 case IB_QP_PATH_MTU: 2498 return 0; 2499 case IB_QP_TIMEOUT: 2500 return MLX5_QP_OPTPAR_ACK_TIMEOUT; 2501 case IB_QP_RETRY_CNT: 2502 return MLX5_QP_OPTPAR_RETRY_COUNT; 2503 case IB_QP_RNR_RETRY: 2504 return MLX5_QP_OPTPAR_RNR_RETRY; 2505 case IB_QP_RQ_PSN: 2506 return 0; 2507 case IB_QP_MAX_QP_RD_ATOMIC: 2508 return MLX5_QP_OPTPAR_SRA_MAX; 2509 case IB_QP_ALT_PATH: 2510 return MLX5_QP_OPTPAR_ALT_ADDR_PATH; 2511 case IB_QP_MIN_RNR_TIMER: 2512 return MLX5_QP_OPTPAR_RNR_TIMEOUT; 2513 case IB_QP_SQ_PSN: 2514 return 0; 2515 case IB_QP_MAX_DEST_RD_ATOMIC: 2516 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | 2517 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; 2518 case IB_QP_PATH_MIG_STATE: 2519 return MLX5_QP_OPTPAR_PM_STATE; 2520 case IB_QP_CAP: 2521 return 0; 2522 case IB_QP_DEST_QPN: 2523 return 0; 2524 } 2525 return 0; 2526} 2527 2528static int ib_mask_to_mlx5_opt(int ib_mask) 2529{ 2530 int result = 0; 2531 int i; 2532 2533 for (i = 0; i < 8 * sizeof(int); i++) { 2534 if ((1 << i) & ib_mask) 2535 result |= ib_nr_to_mlx5_nr(1 << i); 2536 } 2537 2538 return result; 2539} 2540 2541static int modify_raw_packet_qp_rq( 2542 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, 2543 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) 2544{ 2545 void *in; 2546 void *rqc; 2547 int inlen; 2548 int err; 2549 2550 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 2551 in = mlx5_vzalloc(inlen); 2552 if (!in) 2553 return -ENOMEM; 2554 2555 MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn); 2556 MLX5_SET(modify_rq_in, in, rq_state, rq->state); 2557 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); 2558 2559 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 2560 MLX5_SET(rqc, rqc, state, new_state); 2561 2562 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { 2563 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) { 2564 MLX5_SET64(modify_rq_in, in, modify_bitmask, 2565 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID); 2566 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); 2567 } else 2568 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n", 2569 dev->ib_dev.name); 2570 } 2571 2572 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 2573 if (err) 2574 goto out; 2575 2576 rq->state = new_state; 2577 2578out: 2579 kvfree(in); 2580 return err; 2581} 2582 2583static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2584 struct mlx5_ib_sq *sq, int new_state, 2585 struct ib_pd *pd) 2586{ 2587 void *in; 2588 void *sqc; 2589 int inlen; 2590 int err; 2591 2592 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 2593 in = mlx5_vzalloc(inlen); 2594 if (!in) 2595 return -ENOMEM; 2596 2597 MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn); 2598 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); 2599 MLX5_SET(modify_sq_in, in, sq_state, sq->state); 2600 2601 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2602 MLX5_SET(sqc, sqc, state, new_state); 2603 2604 err = mlx5_core_modify_sq(dev, in, inlen); 2605 if (err) 2606 goto out; 2607 2608 sq->state = new_state; 2609 2610out: 2611 kvfree(in); 2612 return err; 2613} 2614 2615static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 2616 const struct mlx5_modify_raw_qp_param *raw_qp_param, 2617 u8 tx_affinity) 2618{ 2619 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2620 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2621 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2622 int modify_rq = !!qp->rq.wqe_cnt; 2623 int modify_sq = !!qp->sq.wqe_cnt; 2624 int rq_state; 2625 int sq_state; 2626 int err; 2627 2628 switch (raw_qp_param->operation) { 2629 case MLX5_CMD_OP_RST2INIT_QP: 2630 rq_state = MLX5_RQC_STATE_RDY; 2631 sq_state = MLX5_SQC_STATE_RDY; 2632 break; 2633 case MLX5_CMD_OP_2ERR_QP: 2634 rq_state = MLX5_RQC_STATE_ERR; 2635 sq_state = MLX5_SQC_STATE_ERR; 2636 break; 2637 case MLX5_CMD_OP_2RST_QP: 2638 rq_state = MLX5_RQC_STATE_RST; 2639 sq_state = MLX5_SQC_STATE_RST; 2640 break; 2641 case MLX5_CMD_OP_RTR2RTS_QP: 2642 case MLX5_CMD_OP_RTS2RTS_QP: 2643 return raw_qp_param->set_mask ? -EINVAL : 0; 2644 case MLX5_CMD_OP_INIT2INIT_QP: 2645 case MLX5_CMD_OP_INIT2RTR_QP: 2646 if (raw_qp_param->set_mask) 2647 return -EINVAL; 2648 else 2649 return 0; 2650 default: 2651 WARN_ON(1); 2652 return -EINVAL; 2653 } 2654 2655 if (modify_rq) { 2656 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, 2657 qp->ibqp.pd); 2658 if (err) 2659 return err; 2660 } 2661 2662 if (modify_sq) { 2663 if (tx_affinity) { 2664 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2665 tx_affinity, 2666 qp->ibqp.pd); 2667 if (err) 2668 return err; 2669 } 2670 2671 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, qp->ibqp.pd); 2672 } 2673 2674 return 0; 2675} 2676 2677static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, 2678 const struct ib_qp_attr *attr, int attr_mask, 2679 enum ib_qp_state cur_state, enum ib_qp_state new_state) 2680{ 2681 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { 2682 [MLX5_QP_STATE_RST] = { 2683 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2684 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2685 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, 2686 }, 2687 [MLX5_QP_STATE_INIT] = { 2688 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2689 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2690 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, 2691 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, 2692 }, 2693 [MLX5_QP_STATE_RTR] = { 2694 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2695 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2696 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, 2697 }, 2698 [MLX5_QP_STATE_RTS] = { 2699 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2700 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2701 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, 2702 }, 2703 [MLX5_QP_STATE_SQD] = { 2704 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2705 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2706 }, 2707 [MLX5_QP_STATE_SQER] = { 2708 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2709 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2710 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, 2711 }, 2712 [MLX5_QP_STATE_ERR] = { 2713 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, 2714 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, 2715 } 2716 }; 2717 2718 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2719 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2720 struct mlx5_ib_qp_base *base = &qp->trans_qp.base; 2721 struct mlx5_ib_cq *send_cq, *recv_cq; 2722 struct mlx5_qp_context *context; 2723 struct mlx5_ib_pd *pd; 2724 struct mlx5_ib_port *mibport = NULL; 2725 enum mlx5_qp_state mlx5_cur, mlx5_new; 2726 enum mlx5_qp_optpar optpar; 2727 int mlx5_st; 2728 int err; 2729 u16 op; 2730 2731 context = kzalloc(sizeof(*context), GFP_KERNEL); 2732 if (!context) 2733 return -ENOMEM; 2734 2735 err = to_mlx5_st(ibqp->qp_type); 2736 if (err < 0) { 2737 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type); 2738 goto out; 2739 } 2740 2741 context->flags = cpu_to_be32(err << 16); 2742 2743 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { 2744 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2745 } else { 2746 switch (attr->path_mig_state) { 2747 case IB_MIG_MIGRATED: 2748 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); 2749 break; 2750 case IB_MIG_REARM: 2751 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); 2752 break; 2753 case IB_MIG_ARMED: 2754 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); 2755 break; 2756 } 2757 } 2758 2759 if (is_sqp(ibqp->qp_type)) { 2760 context->mtu_msgmax = (IB_MTU_256 << 5) | 8; 2761 } else if (ibqp->qp_type == IB_QPT_UD || 2762 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { 2763 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 2764 } else if (attr_mask & IB_QP_PATH_MTU) { 2765 if (attr->path_mtu < IB_MTU_256 || 2766 attr->path_mtu > IB_MTU_4096) { 2767 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); 2768 err = -EINVAL; 2769 goto out; 2770 } 2771 context->mtu_msgmax = (attr->path_mtu << 5) | 2772 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); 2773 } 2774 2775 if (attr_mask & IB_QP_DEST_QPN) 2776 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); 2777 2778 if (attr_mask & IB_QP_PKEY_INDEX) 2779 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); 2780 2781 /* todo implement counter_index functionality */ 2782 2783 if (is_sqp(ibqp->qp_type)) 2784 context->pri_path.port = qp->port; 2785 2786 if (attr_mask & IB_QP_PORT) 2787 context->pri_path.port = attr->port_num; 2788 2789 if (attr_mask & IB_QP_AV) { 2790 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, 2791 attr_mask & IB_QP_PORT ? attr->port_num : qp->port, 2792 attr_mask, 0, attr, false); 2793 if (err) 2794 goto out; 2795 } 2796 2797 if (attr_mask & IB_QP_TIMEOUT) 2798 context->pri_path.ackto_lt |= attr->timeout << 3; 2799 2800 if (attr_mask & IB_QP_ALT_PATH) { 2801 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, 2802 &context->alt_path, 2803 attr->alt_port_num, 2804 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, 2805 0, attr, true); 2806 if (err) 2807 goto out; 2808 } 2809 2810 pd = get_pd(qp); 2811 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, 2812 &send_cq, &recv_cq); 2813 2814 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); 2815 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; 2816 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; 2817 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); 2818 2819 if (attr_mask & IB_QP_RNR_RETRY) 2820 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 2821 2822 if (attr_mask & IB_QP_RETRY_CNT) 2823 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 2824 2825 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 2826 if (attr->max_rd_atomic) 2827 context->params1 |= 2828 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 2829 } 2830 2831 if (attr_mask & IB_QP_SQ_PSN) 2832 context->next_send_psn = cpu_to_be32(attr->sq_psn); 2833 2834 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 2835 if (attr->max_dest_rd_atomic) 2836 context->params2 |= 2837 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 2838 } 2839 2840 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 2841 __be32 access_flags; 2842 2843 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); 2844 if (err) 2845 goto out; 2846 2847 context->params2 |= access_flags; 2848 } 2849 2850 if (attr_mask & IB_QP_MIN_RNR_TIMER) 2851 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 2852 2853 if (attr_mask & IB_QP_RQ_PSN) 2854 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 2855 2856 if (attr_mask & IB_QP_QKEY) 2857 context->qkey = cpu_to_be32(attr->qkey); 2858 2859 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2860 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2861 2862 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2863 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2864 qp->port) - 1; 2865 mibport = &dev->port[port_num]; 2866 context->qp_counter_set_usr_page |= 2867 cpu_to_be32((u32)(mibport->q_cnt_id) << 24); 2868 } 2869 2870 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2871 context->sq_crq_size |= cpu_to_be16(1 << 4); 2872 2873 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 2874 context->deth_sqpn = cpu_to_be32(1); 2875 2876 mlx5_cur = to_mlx5_state(cur_state); 2877 mlx5_new = to_mlx5_state(new_state); 2878 mlx5_st = to_mlx5_st(ibqp->qp_type); 2879 if (mlx5_st < 0) 2880 goto out; 2881 2882 /* If moving to a reset or error state, we must disable page faults on 2883 * this QP and flush all current page faults. Otherwise a stale page 2884 * fault may attempt to work on this QP after it is reset and moved 2885 * again to RTS, and may cause the driver and the device to get out of 2886 * sync. */ 2887 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2888 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) && 2889 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2890 mlx5_ib_qp_disable_pagefaults(qp); 2891 2892 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || 2893 !optab[mlx5_cur][mlx5_new]) 2894 goto out; 2895 2896 op = optab[mlx5_cur][mlx5_new]; 2897 optpar = ib_mask_to_mlx5_opt(attr_mask); 2898 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; 2899 2900 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 2901 struct mlx5_modify_raw_qp_param raw_qp_param = {}; 2902 2903 raw_qp_param.operation = op; 2904 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2905 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2906 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2907 } 2908 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); 2909 } else { 2910 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2911 &base->mqp); 2912 } 2913 2914 if (err) 2915 goto out; 2916 2917 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT && 2918 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET)) 2919 mlx5_ib_qp_enable_pagefaults(qp); 2920 2921 qp->state = new_state; 2922 2923 if (attr_mask & IB_QP_ACCESS_FLAGS) 2924 qp->trans_qp.atomic_rd_en = attr->qp_access_flags; 2925 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2926 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; 2927 if (attr_mask & IB_QP_PORT) 2928 qp->port = attr->port_num; 2929 if (attr_mask & IB_QP_ALT_PATH) 2930 qp->trans_qp.alt_port = attr->alt_port_num; 2931 2932 /* 2933 * If we moved a kernel QP to RESET, clean up all old CQ 2934 * entries and reinitialize the QP. 2935 */ 2936 if (new_state == IB_QPS_RESET && !ibqp->uobject) { 2937 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, 2938 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2939 if (send_cq != recv_cq) 2940 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); 2941 2942 qp->rq.head = 0; 2943 qp->rq.tail = 0; 2944 qp->sq.head = 0; 2945 qp->sq.tail = 0; 2946 qp->sq.cur_post = 0; 2947 qp->sq.last_poll = 0; 2948 qp->db.db[MLX5_RCV_DBR] = 0; 2949 qp->db.db[MLX5_SND_DBR] = 0; 2950 } 2951 2952out: 2953 kfree(context); 2954 return err; 2955} 2956 2957int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2958 int attr_mask, struct ib_udata *udata) 2959{ 2960 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2961 struct mlx5_ib_qp *qp = to_mqp(ibqp); 2962 enum ib_qp_type qp_type; 2963 enum ib_qp_state cur_state, new_state; 2964 int err = -EINVAL; 2965 int port; 2966 2967 if (ibqp->rwq_ind_tbl) 2968 return -ENOSYS; 2969 2970 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 2971 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); 2972 2973 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? 2974 IB_QPT_GSI : ibqp->qp_type; 2975 2976 mutex_lock(&qp->mutex); 2977 2978 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2979 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2980 2981 if (qp_type != MLX5_IB_QPT_REG_UMR && 2982 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask)) { 2983 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", 2984 cur_state, new_state, ibqp->qp_type, attr_mask); 2985 goto out; 2986 } 2987 2988 if ((attr_mask & IB_QP_PORT) && 2989 (attr->port_num == 0 || 2990 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) { 2991 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", 2992 attr->port_num, dev->num_ports); 2993 goto out; 2994 } 2995 2996 if (attr_mask & IB_QP_PKEY_INDEX) { 2997 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2998 if (attr->pkey_index >= 2999 dev->mdev->port_caps[port - 1].pkey_table_len) { 3000 mlx5_ib_dbg(dev, "invalid pkey index %d\n", 3001 attr->pkey_index); 3002 goto out; 3003 } 3004 } 3005 3006 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 3007 attr->max_rd_atomic > 3008 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { 3009 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", 3010 attr->max_rd_atomic); 3011 goto out; 3012 } 3013 3014 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 3015 attr->max_dest_rd_atomic > 3016 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { 3017 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", 3018 attr->max_dest_rd_atomic); 3019 goto out; 3020 } 3021 3022 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 3023 err = 0; 3024 goto out; 3025 } 3026 3027 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state); 3028 3029out: 3030 mutex_unlock(&qp->mutex); 3031 return err; 3032} 3033 3034static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 3035{ 3036 struct mlx5_ib_cq *cq; 3037 unsigned cur; 3038 3039 cur = wq->head - wq->tail; 3040 if (likely(cur + nreq < wq->max_post)) 3041 return 0; 3042 3043 cq = to_mcq(ib_cq); 3044 spin_lock(&cq->lock); 3045 cur = wq->head - wq->tail; 3046 spin_unlock(&cq->lock); 3047 3048 return cur + nreq >= wq->max_post; 3049} 3050 3051static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, 3052 u64 remote_addr, u32 rkey) 3053{ 3054 rseg->raddr = cpu_to_be64(remote_addr); 3055 rseg->rkey = cpu_to_be32(rkey); 3056 rseg->reserved = 0; 3057} 3058 3059static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg, 3060 const struct ib_send_wr *wr, void *qend, 3061 struct mlx5_ib_qp *qp, int *size) 3062{ 3063 void *seg = eseg; 3064 3065 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); 3066 3067 if (wr->send_flags & IB_SEND_IP_CSUM) 3068 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | 3069 MLX5_ETH_WQE_L4_CSUM; 3070 3071 seg += sizeof(struct mlx5_wqe_eth_seg); 3072 *size += sizeof(struct mlx5_wqe_eth_seg) / 16; 3073 3074 if (wr->opcode == IB_WR_LSO) { 3075 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); 3076 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start); 3077 u64 left, leftlen, copysz; 3078 void *pdata = ud_wr->header; 3079 3080 left = ud_wr->hlen; 3081 eseg->mss = cpu_to_be16(ud_wr->mss); 3082 eseg->inline_hdr_sz = cpu_to_be16(left); 3083 3084 /* 3085 * check if there is space till the end of queue, if yes, 3086 * copy all in one shot, otherwise copy till the end of queue, 3087 * rollback and than the copy the left 3088 */ 3089 leftlen = qend - (void *)eseg->inline_hdr_start; 3090 copysz = min_t(u64, leftlen, left); 3091 3092 memcpy(seg - size_of_inl_hdr_start, pdata, copysz); 3093 3094 if (likely(copysz > size_of_inl_hdr_start)) { 3095 seg += ALIGN(copysz - size_of_inl_hdr_start, 16); 3096 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16; 3097 } 3098 3099 if (unlikely(copysz < left)) { /* the last wqe in the queue */ 3100 seg = mlx5_get_send_wqe(qp, 0); 3101 left -= copysz; 3102 pdata += copysz; 3103 memcpy(seg, pdata, left); 3104 seg += ALIGN(left, 16); 3105 *size += ALIGN(left, 16) / 16; 3106 } 3107 } 3108 3109 return seg; 3110} 3111 3112static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, 3113 const struct ib_send_wr *wr) 3114{ 3115 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); 3116 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); 3117 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); 3118} 3119 3120static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) 3121{ 3122 dseg->byte_count = cpu_to_be32(sg->length); 3123 dseg->lkey = cpu_to_be32(sg->lkey); 3124 dseg->addr = cpu_to_be64(sg->addr); 3125} 3126 3127static __be16 get_klm_octo(int npages) 3128{ 3129 return cpu_to_be16(ALIGN(npages, 8) / 2); 3130} 3131 3132static __be64 frwr_mkey_mask(void) 3133{ 3134 u64 result; 3135 3136 result = MLX5_MKEY_MASK_LEN | 3137 MLX5_MKEY_MASK_PAGE_SIZE | 3138 MLX5_MKEY_MASK_START_ADDR | 3139 MLX5_MKEY_MASK_EN_RINVAL | 3140 MLX5_MKEY_MASK_KEY | 3141 MLX5_MKEY_MASK_LR | 3142 MLX5_MKEY_MASK_LW | 3143 MLX5_MKEY_MASK_RR | 3144 MLX5_MKEY_MASK_RW | 3145 MLX5_MKEY_MASK_A | 3146 MLX5_MKEY_MASK_SMALL_FENCE | 3147 MLX5_MKEY_MASK_FREE; 3148 3149 return cpu_to_be64(result); 3150} 3151 3152static __be64 sig_mkey_mask(void) 3153{ 3154 u64 result; 3155 3156 result = MLX5_MKEY_MASK_LEN | 3157 MLX5_MKEY_MASK_PAGE_SIZE | 3158 MLX5_MKEY_MASK_START_ADDR | 3159 MLX5_MKEY_MASK_EN_SIGERR | 3160 MLX5_MKEY_MASK_EN_RINVAL | 3161 MLX5_MKEY_MASK_KEY | 3162 MLX5_MKEY_MASK_LR | 3163 MLX5_MKEY_MASK_LW | 3164 MLX5_MKEY_MASK_RR | 3165 MLX5_MKEY_MASK_RW | 3166 MLX5_MKEY_MASK_SMALL_FENCE | 3167 MLX5_MKEY_MASK_FREE | 3168 MLX5_MKEY_MASK_BSF_EN; 3169 3170 return cpu_to_be64(result); 3171} 3172 3173static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, 3174 struct mlx5_ib_mr *mr) 3175{ 3176 int ndescs = mr->ndescs; 3177 3178 memset(umr, 0, sizeof(*umr)); 3179 3180 if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3181 /* KLMs take twice the size of MTTs */ 3182 ndescs *= 2; 3183 3184 umr->flags = MLX5_UMR_CHECK_NOT_FREE; 3185 umr->klm_octowords = get_klm_octo(ndescs); 3186 umr->mkey_mask = frwr_mkey_mask(); 3187} 3188 3189static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) 3190{ 3191 memset(umr, 0, sizeof(*umr)); 3192 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3193 umr->flags = 1 << 7; 3194} 3195 3196static __be64 get_umr_reg_mr_mask(void) 3197{ 3198 u64 result; 3199 3200 result = MLX5_MKEY_MASK_LEN | 3201 MLX5_MKEY_MASK_PAGE_SIZE | 3202 MLX5_MKEY_MASK_START_ADDR | 3203 MLX5_MKEY_MASK_PD | 3204 MLX5_MKEY_MASK_LR | 3205 MLX5_MKEY_MASK_LW | 3206 MLX5_MKEY_MASK_KEY | 3207 MLX5_MKEY_MASK_RR | 3208 MLX5_MKEY_MASK_RW | 3209 MLX5_MKEY_MASK_A | 3210 MLX5_MKEY_MASK_FREE; 3211 3212 return cpu_to_be64(result); 3213} 3214 3215static __be64 get_umr_unreg_mr_mask(void) 3216{ 3217 u64 result; 3218 3219 result = MLX5_MKEY_MASK_FREE; 3220 3221 return cpu_to_be64(result); 3222} 3223 3224static __be64 get_umr_update_mtt_mask(void) 3225{ 3226 u64 result; 3227 3228 result = MLX5_MKEY_MASK_FREE; 3229 3230 return cpu_to_be64(result); 3231} 3232 3233static __be64 get_umr_update_translation_mask(void) 3234{ 3235 u64 result; 3236 3237 result = MLX5_MKEY_MASK_LEN | 3238 MLX5_MKEY_MASK_PAGE_SIZE | 3239 MLX5_MKEY_MASK_START_ADDR | 3240 MLX5_MKEY_MASK_KEY | 3241 MLX5_MKEY_MASK_FREE; 3242 3243 return cpu_to_be64(result); 3244} 3245 3246static __be64 get_umr_update_access_mask(void) 3247{ 3248 u64 result; 3249 3250 result = MLX5_MKEY_MASK_LW | 3251 MLX5_MKEY_MASK_RR | 3252 MLX5_MKEY_MASK_RW | 3253 MLX5_MKEY_MASK_A | 3254 MLX5_MKEY_MASK_KEY | 3255 MLX5_MKEY_MASK_FREE; 3256 3257 return cpu_to_be64(result); 3258} 3259 3260static __be64 get_umr_update_pd_mask(void) 3261{ 3262 u64 result; 3263 3264 result = MLX5_MKEY_MASK_PD | 3265 MLX5_MKEY_MASK_KEY | 3266 MLX5_MKEY_MASK_FREE; 3267 3268 return cpu_to_be64(result); 3269} 3270 3271static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3272 const struct ib_send_wr *wr) 3273{ 3274 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3275 3276 memset(umr, 0, sizeof(*umr)); 3277 3278 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) 3279 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ 3280 else 3281 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ 3282 3283 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) { 3284 umr->klm_octowords = get_klm_octo(umrwr->npages); 3285 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) { 3286 umr->mkey_mask = get_umr_update_mtt_mask(); 3287 umr->bsf_octowords = get_klm_octo(umrwr->target.offset); 3288 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; 3289 } 3290 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) 3291 umr->mkey_mask |= get_umr_update_translation_mask(); 3292 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS) 3293 umr->mkey_mask |= get_umr_update_access_mask(); 3294 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3295 umr->mkey_mask |= get_umr_update_pd_mask(); 3296 if (!umr->mkey_mask) 3297 umr->mkey_mask = get_umr_reg_mr_mask(); 3298 } else { 3299 umr->mkey_mask = get_umr_unreg_mr_mask(); 3300 } 3301 3302 if (!wr->num_sge) 3303 umr->flags |= MLX5_UMR_INLINE; 3304} 3305 3306static u8 get_umr_flags(int acc) 3307{ 3308 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | 3309 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | 3310 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | 3311 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | 3312 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; 3313} 3314 3315static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, 3316 struct mlx5_ib_mr *mr, 3317 u32 key, int access) 3318{ 3319 int ndescs = ALIGN(mr->ndescs, 8) >> 1; 3320 3321 memset(seg, 0, sizeof(*seg)); 3322 3323 if (mr->access_mode == MLX5_ACCESS_MODE_MTT) 3324 seg->log2_page_size = ilog2(mr->ibmr.page_size); 3325 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM) 3326 /* KLMs take twice the size of MTTs */ 3327 ndescs *= 2; 3328 3329 seg->flags = get_umr_flags(access) | mr->access_mode; 3330 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); 3331 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); 3332 seg->start_addr = cpu_to_be64(mr->ibmr.iova); 3333 seg->len = cpu_to_be64(mr->ibmr.length); 3334 seg->xlt_oct_size = cpu_to_be32(ndescs); 3335} 3336 3337static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) 3338{ 3339 memset(seg, 0, sizeof(*seg)); 3340 seg->status = MLX5_MKEY_STATUS_FREE; 3341} 3342 3343static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, const struct ib_send_wr *wr) 3344{ 3345 const struct mlx5_umr_wr *umrwr = umr_wr(wr); 3346 3347 memset(seg, 0, sizeof(*seg)); 3348 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) { 3349 seg->status = MLX5_MKEY_STATUS_FREE; 3350 return; 3351 } 3352 3353 seg->flags = convert_access(umrwr->access_flags); 3354 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) { 3355 if (umrwr->pd) 3356 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); 3357 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr); 3358 } 3359 seg->len = cpu_to_be64(umrwr->length); 3360 seg->log2_page_size = umrwr->page_shift; 3361 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | 3362 mlx5_mkey_variant(umrwr->mkey)); 3363} 3364 3365static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, 3366 struct mlx5_ib_mr *mr, 3367 struct mlx5_ib_pd *pd) 3368{ 3369 int bcount = mr->desc_size * mr->ndescs; 3370 3371 dseg->addr = cpu_to_be64(mr->desc_map); 3372 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); 3373 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); 3374} 3375 3376static __be32 send_ieth(const struct ib_send_wr *wr) 3377{ 3378 switch (wr->opcode) { 3379 case IB_WR_SEND_WITH_IMM: 3380 case IB_WR_RDMA_WRITE_WITH_IMM: 3381 return wr->ex.imm_data; 3382 3383 case IB_WR_SEND_WITH_INV: 3384 return cpu_to_be32(wr->ex.invalidate_rkey); 3385 3386 default: 3387 return 0; 3388 } 3389} 3390 3391static u8 calc_sig(void *wqe, int size) 3392{ 3393 u8 *p = wqe; 3394 u8 res = 0; 3395 int i; 3396 3397 for (i = 0; i < size; i++) 3398 res ^= p[i]; 3399 3400 return ~res; 3401} 3402 3403static u8 wq_sig(void *wqe) 3404{ 3405 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); 3406} 3407 3408static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, 3409 void *wqe, int *sz) 3410{ 3411 struct mlx5_wqe_inline_seg *seg; 3412 void *qend = qp->sq.qend; 3413 void *addr; 3414 int inl = 0; 3415 int copy; 3416 int len; 3417 int i; 3418 3419 seg = wqe; 3420 wqe += sizeof(*seg); 3421 for (i = 0; i < wr->num_sge; i++) { 3422 addr = (void *)(unsigned long)(wr->sg_list[i].addr); 3423 len = wr->sg_list[i].length; 3424 inl += len; 3425 3426 if (unlikely(inl > qp->max_inline_data)) 3427 return -ENOMEM; 3428 3429 if (unlikely(wqe + len > qend)) { 3430 copy = qend - wqe; 3431 memcpy(wqe, addr, copy); 3432 addr += copy; 3433 len -= copy; 3434 wqe = mlx5_get_send_wqe(qp, 0); 3435 } 3436 memcpy(wqe, addr, len); 3437 wqe += len; 3438 } 3439 3440 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); 3441 3442 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16; 3443 3444 return 0; 3445} 3446 3447static u16 prot_field_size(enum ib_signature_type type) 3448{ 3449 switch (type) { 3450 case IB_SIG_TYPE_T10_DIF: 3451 return MLX5_DIF_SIZE; 3452 default: 3453 return 0; 3454 } 3455} 3456 3457static u8 bs_selector(int block_size) 3458{ 3459 switch (block_size) { 3460 case 512: return 0x1; 3461 case 520: return 0x2; 3462 case 4096: return 0x3; 3463 case 4160: return 0x4; 3464 case 1073741824: return 0x5; 3465 default: return 0; 3466 } 3467} 3468 3469static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, 3470 struct mlx5_bsf_inl *inl) 3471{ 3472 /* Valid inline section and allow BSF refresh */ 3473 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | 3474 MLX5_BSF_REFRESH_DIF); 3475 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); 3476 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); 3477 /* repeating block */ 3478 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; 3479 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? 3480 MLX5_DIF_CRC : MLX5_DIF_IPCS; 3481 3482 if (domain->sig.dif.ref_remap) 3483 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; 3484 3485 if (domain->sig.dif.app_escape) { 3486 if (domain->sig.dif.ref_escape) 3487 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; 3488 else 3489 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; 3490 } 3491 3492 inl->dif_app_bitmask_check = 3493 cpu_to_be16(domain->sig.dif.apptag_check_mask); 3494} 3495 3496static int mlx5_set_bsf(struct ib_mr *sig_mr, 3497 struct ib_sig_attrs *sig_attrs, 3498 struct mlx5_bsf *bsf, u32 data_size) 3499{ 3500 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; 3501 struct mlx5_bsf_basic *basic = &bsf->basic; 3502 struct ib_sig_domain *mem = &sig_attrs->mem; 3503 struct ib_sig_domain *wire = &sig_attrs->wire; 3504 3505 memset(bsf, 0, sizeof(*bsf)); 3506 3507 /* Basic + Extended + Inline */ 3508 basic->bsf_size_sbs = 1 << 7; 3509 /* Input domain check byte mask */ 3510 basic->check_byte_mask = sig_attrs->check_mask; 3511 basic->raw_data_size = cpu_to_be32(data_size); 3512 3513 /* Memory domain */ 3514 switch (sig_attrs->mem.sig_type) { 3515 case IB_SIG_TYPE_NONE: 3516 break; 3517 case IB_SIG_TYPE_T10_DIF: 3518 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); 3519 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); 3520 mlx5_fill_inl_bsf(mem, &bsf->m_inl); 3521 break; 3522 default: 3523 return -EINVAL; 3524 } 3525 3526 /* Wire domain */ 3527 switch (sig_attrs->wire.sig_type) { 3528 case IB_SIG_TYPE_NONE: 3529 break; 3530 case IB_SIG_TYPE_T10_DIF: 3531 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && 3532 mem->sig_type == wire->sig_type) { 3533 /* Same block structure */ 3534 basic->bsf_size_sbs |= 1 << 4; 3535 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) 3536 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; 3537 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) 3538 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; 3539 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) 3540 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; 3541 } else 3542 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); 3543 3544 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); 3545 mlx5_fill_inl_bsf(wire, &bsf->w_inl); 3546 break; 3547 default: 3548 return -EINVAL; 3549 } 3550 3551 return 0; 3552} 3553 3554static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, 3555 struct mlx5_ib_qp *qp, void **seg, int *size) 3556{ 3557 struct ib_sig_attrs *sig_attrs = wr->sig_attrs; 3558 struct ib_mr *sig_mr = wr->sig_mr; 3559 struct mlx5_bsf *bsf; 3560 u32 data_len = wr->wr.sg_list->length; 3561 u32 data_key = wr->wr.sg_list->lkey; 3562 u64 data_va = wr->wr.sg_list->addr; 3563 int ret; 3564 int wqe_size; 3565 3566 if (!wr->prot || 3567 (data_key == wr->prot->lkey && 3568 data_va == wr->prot->addr && 3569 data_len == wr->prot->length)) { 3570 /** 3571 * Source domain doesn't contain signature information 3572 * or data and protection are interleaved in memory. 3573 * So need construct: 3574 * ------------------ 3575 * | data_klm | 3576 * ------------------ 3577 * | BSF | 3578 * ------------------ 3579 **/ 3580 struct mlx5_klm *data_klm = *seg; 3581 3582 data_klm->bcount = cpu_to_be32(data_len); 3583 data_klm->key = cpu_to_be32(data_key); 3584 data_klm->va = cpu_to_be64(data_va); 3585 wqe_size = ALIGN(sizeof(*data_klm), 64); 3586 } else { 3587 /** 3588 * Source domain contains signature information 3589 * So need construct a strided block format: 3590 * --------------------------- 3591 * | stride_block_ctrl | 3592 * --------------------------- 3593 * | data_klm | 3594 * --------------------------- 3595 * | prot_klm | 3596 * --------------------------- 3597 * | BSF | 3598 * --------------------------- 3599 **/ 3600 struct mlx5_stride_block_ctrl_seg *sblock_ctrl; 3601 struct mlx5_stride_block_entry *data_sentry; 3602 struct mlx5_stride_block_entry *prot_sentry; 3603 u32 prot_key = wr->prot->lkey; 3604 u64 prot_va = wr->prot->addr; 3605 u16 block_size = sig_attrs->mem.sig.dif.pi_interval; 3606 int prot_size; 3607 3608 sblock_ctrl = *seg; 3609 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); 3610 prot_sentry = (void *)data_sentry + sizeof(*data_sentry); 3611 3612 prot_size = prot_field_size(sig_attrs->mem.sig_type); 3613 if (!prot_size) { 3614 pr_err("Bad block size given: %u\n", block_size); 3615 return -EINVAL; 3616 } 3617 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + 3618 prot_size); 3619 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); 3620 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); 3621 sblock_ctrl->num_entries = cpu_to_be16(2); 3622 3623 data_sentry->bcount = cpu_to_be16(block_size); 3624 data_sentry->key = cpu_to_be32(data_key); 3625 data_sentry->va = cpu_to_be64(data_va); 3626 data_sentry->stride = cpu_to_be16(block_size); 3627 3628 prot_sentry->bcount = cpu_to_be16(prot_size); 3629 prot_sentry->key = cpu_to_be32(prot_key); 3630 prot_sentry->va = cpu_to_be64(prot_va); 3631 prot_sentry->stride = cpu_to_be16(prot_size); 3632 3633 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + 3634 sizeof(*prot_sentry), 64); 3635 } 3636 3637 *seg += wqe_size; 3638 *size += wqe_size / 16; 3639 if (unlikely((*seg == qp->sq.qend))) 3640 *seg = mlx5_get_send_wqe(qp, 0); 3641 3642 bsf = *seg; 3643 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); 3644 if (ret) 3645 return -EINVAL; 3646 3647 *seg += sizeof(*bsf); 3648 *size += sizeof(*bsf) / 16; 3649 if (unlikely((*seg == qp->sq.qend))) 3650 *seg = mlx5_get_send_wqe(qp, 0); 3651 3652 return 0; 3653} 3654 3655static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, 3656 const struct ib_sig_handover_wr *wr, u32 nelements, 3657 u32 length, u32 pdn) 3658{ 3659 struct ib_mr *sig_mr = wr->sig_mr; 3660 u32 sig_key = sig_mr->rkey; 3661 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; 3662 3663 memset(seg, 0, sizeof(*seg)); 3664 3665 seg->flags = get_umr_flags(wr->access_flags) | 3666 MLX5_ACCESS_MODE_KLM; 3667 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); 3668 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | 3669 MLX5_MKEY_BSF_EN | pdn); 3670 seg->len = cpu_to_be64(length); 3671 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements))); 3672 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); 3673} 3674 3675static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3676 u32 nelements) 3677{ 3678 memset(umr, 0, sizeof(*umr)); 3679 3680 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; 3681 umr->klm_octowords = get_klm_octo(nelements); 3682 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); 3683 umr->mkey_mask = sig_mkey_mask(); 3684} 3685 3686 3687static int set_sig_umr_wr(const struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp, 3688 void **seg, int *size) 3689{ 3690 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); 3691 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); 3692 u32 pdn = get_pd(qp)->pdn; 3693 u32 klm_oct_size; 3694 int region_len, ret; 3695 3696 if (unlikely(wr->wr.num_sge != 1) || 3697 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || 3698 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || 3699 unlikely(!sig_mr->sig->sig_status_checked)) 3700 return -EINVAL; 3701 3702 /* length of the protected region, data + protection */ 3703 region_len = wr->wr.sg_list->length; 3704 if (wr->prot && 3705 (wr->prot->lkey != wr->wr.sg_list->lkey || 3706 wr->prot->addr != wr->wr.sg_list->addr || 3707 wr->prot->length != wr->wr.sg_list->length)) 3708 region_len += wr->prot->length; 3709 3710 /** 3711 * KLM octoword size - if protection was provided 3712 * then we use strided block format (3 octowords), 3713 * else we use single KLM (1 octoword) 3714 **/ 3715 klm_oct_size = wr->prot ? 3 : 1; 3716 3717 set_sig_umr_segment(*seg, klm_oct_size); 3718 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3719 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3720 if (unlikely((*seg == qp->sq.qend))) 3721 *seg = mlx5_get_send_wqe(qp, 0); 3722 3723 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn); 3724 *seg += sizeof(struct mlx5_mkey_seg); 3725 *size += sizeof(struct mlx5_mkey_seg) / 16; 3726 if (unlikely((*seg == qp->sq.qend))) 3727 *seg = mlx5_get_send_wqe(qp, 0); 3728 3729 ret = set_sig_data_segment(wr, qp, seg, size); 3730 if (ret) 3731 return ret; 3732 3733 sig_mr->sig->sig_status_checked = false; 3734 return 0; 3735} 3736 3737static int set_psv_wr(struct ib_sig_domain *domain, 3738 u32 psv_idx, void **seg, int *size) 3739{ 3740 struct mlx5_seg_set_psv *psv_seg = *seg; 3741 3742 memset(psv_seg, 0, sizeof(*psv_seg)); 3743 psv_seg->psv_num = cpu_to_be32(psv_idx); 3744 switch (domain->sig_type) { 3745 case IB_SIG_TYPE_NONE: 3746 break; 3747 case IB_SIG_TYPE_T10_DIF: 3748 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | 3749 domain->sig.dif.app_tag); 3750 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); 3751 break; 3752 default: 3753 pr_err("Bad signature type given.\n"); 3754 return 1; 3755 } 3756 3757 *seg += sizeof(*psv_seg); 3758 *size += sizeof(*psv_seg) / 16; 3759 3760 return 0; 3761} 3762 3763static int set_reg_wr(struct mlx5_ib_qp *qp, 3764 const struct ib_reg_wr *wr, 3765 void **seg, int *size) 3766{ 3767 struct mlx5_ib_mr *mr = to_mmr(wr->mr); 3768 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); 3769 3770 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { 3771 mlx5_ib_warn(to_mdev(qp->ibqp.device), 3772 "Invalid IB_SEND_INLINE send flag\n"); 3773 return -EINVAL; 3774 } 3775 3776 set_reg_umr_seg(*seg, mr); 3777 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3778 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3779 if (unlikely((*seg == qp->sq.qend))) 3780 *seg = mlx5_get_send_wqe(qp, 0); 3781 3782 set_reg_mkey_seg(*seg, mr, wr->key, wr->access); 3783 *seg += sizeof(struct mlx5_mkey_seg); 3784 *size += sizeof(struct mlx5_mkey_seg) / 16; 3785 if (unlikely((*seg == qp->sq.qend))) 3786 *seg = mlx5_get_send_wqe(qp, 0); 3787 3788 set_reg_data_seg(*seg, mr, pd); 3789 *seg += sizeof(struct mlx5_wqe_data_seg); 3790 *size += (sizeof(struct mlx5_wqe_data_seg) / 16); 3791 3792 return 0; 3793} 3794 3795static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size) 3796{ 3797 set_linv_umr_seg(*seg); 3798 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 3799 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 3800 if (unlikely((*seg == qp->sq.qend))) 3801 *seg = mlx5_get_send_wqe(qp, 0); 3802 set_linv_mkey_seg(*seg); 3803 *seg += sizeof(struct mlx5_mkey_seg); 3804 *size += sizeof(struct mlx5_mkey_seg) / 16; 3805 if (unlikely((*seg == qp->sq.qend))) 3806 *seg = mlx5_get_send_wqe(qp, 0); 3807} 3808 3809static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16) 3810{ 3811 __be32 *p = NULL; 3812 int tidx = idx; 3813 int i, j; 3814 3815 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx)); 3816 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { 3817 if ((i & 0xf) == 0) { 3818 void *buf = mlx5_get_send_wqe(qp, tidx); 3819 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); 3820 p = buf; 3821 j = 0; 3822 } 3823 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), 3824 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), 3825 be32_to_cpu(p[j + 3])); 3826 } 3827} 3828 3829static u8 get_fence(u8 fence, const struct ib_send_wr *wr) 3830{ 3831 if (unlikely(wr->opcode == IB_WR_LOCAL_INV && 3832 wr->send_flags & IB_SEND_FENCE)) 3833 return MLX5_FENCE_MODE_STRONG_ORDERING; 3834 3835 if (unlikely(fence)) { 3836 if (wr->send_flags & IB_SEND_FENCE) 3837 return MLX5_FENCE_MODE_SMALL_AND_FENCE; 3838 else 3839 return fence; 3840 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) { 3841 return MLX5_FENCE_MODE_FENCE; 3842 } 3843 3844 return 0; 3845} 3846 3847static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, 3848 struct mlx5_wqe_ctrl_seg **ctrl, 3849 const struct ib_send_wr *wr, unsigned *idx, 3850 int *size, int nreq, int send_flags) 3851{ 3852 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) 3853 return -ENOMEM; 3854 3855 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); 3856 *seg = mlx5_get_send_wqe(qp, *idx); 3857 *ctrl = *seg; 3858 *(uint32_t *)(*seg + 8) = 0; 3859 (*ctrl)->imm = send_ieth(wr); 3860 (*ctrl)->fm_ce_se = qp->sq_signal_bits | 3861 (send_flags & IB_SEND_SIGNALED ? 3862 MLX5_WQE_CTRL_CQ_UPDATE : 0) | 3863 (send_flags & IB_SEND_SOLICITED ? 3864 MLX5_WQE_CTRL_SOLICITED : 0); 3865 3866 *seg += sizeof(**ctrl); 3867 *size = sizeof(**ctrl) / 16; 3868 3869 return 0; 3870} 3871 3872static void finish_wqe(struct mlx5_ib_qp *qp, 3873 struct mlx5_wqe_ctrl_seg *ctrl, 3874 u8 size, unsigned idx, u64 wr_id, 3875 int nreq, u8 fence, u8 next_fence, 3876 u32 mlx5_opcode) 3877{ 3878 u8 opmod = 0; 3879 3880 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | 3881 mlx5_opcode | ((u32)opmod << 24)); 3882 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); 3883 ctrl->fm_ce_se |= fence; 3884 qp->fm_cache = next_fence; 3885 if (unlikely(qp->wq_sig)) 3886 ctrl->signature = wq_sig(ctrl); 3887 3888 qp->sq.wrid[idx] = wr_id; 3889 qp->sq.w_list[idx].opcode = mlx5_opcode; 3890 qp->sq.wqe_head[idx] = qp->sq.head + nreq; 3891 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); 3892 qp->sq.w_list[idx].next = qp->sq.cur_post; 3893} 3894 3895 3896int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 3897 const struct ib_send_wr **bad_wr) 3898{ 3899 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ 3900 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 3901 struct mlx5_core_dev *mdev = dev->mdev; 3902 struct mlx5_ib_qp *qp; 3903 struct mlx5_ib_mr *mr; 3904 struct mlx5_wqe_data_seg *dpseg; 3905 struct mlx5_wqe_xrc_seg *xrc; 3906 struct mlx5_bf *bf; 3907 int uninitialized_var(size); 3908 void *qend; 3909 unsigned long flags; 3910 unsigned idx; 3911 int err = 0; 3912 int num_sge; 3913 void *seg; 3914 int nreq; 3915 int i; 3916 u8 next_fence = 0; 3917 u8 fence; 3918 3919 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 3920 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); 3921 3922 qp = to_mqp(ibqp); 3923 bf = &qp->bf; 3924 qend = qp->sq.qend; 3925 3926 spin_lock_irqsave(&qp->sq.lock, flags); 3927 3928 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 3929 err = -EIO; 3930 *bad_wr = wr; 3931 nreq = 0; 3932 goto out; 3933 } 3934 3935 for (nreq = 0; wr; nreq++, wr = wr->next) { 3936 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { 3937 mlx5_ib_warn(dev, "\n"); 3938 err = -EINVAL; 3939 *bad_wr = wr; 3940 goto out; 3941 } 3942 3943 fence = qp->fm_cache; 3944 num_sge = wr->num_sge; 3945 if (unlikely(num_sge > qp->sq.max_gs)) { 3946 mlx5_ib_warn(dev, "\n"); 3947 err = -EINVAL; 3948 *bad_wr = wr; 3949 goto out; 3950 } 3951 3952 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq, wr->send_flags); 3953 if (err) { 3954 mlx5_ib_warn(dev, "\n"); 3955 err = -ENOMEM; 3956 *bad_wr = wr; 3957 goto out; 3958 } 3959 3960 switch (ibqp->qp_type) { 3961 case IB_QPT_XRC_INI: 3962 xrc = seg; 3963 seg += sizeof(*xrc); 3964 size += sizeof(*xrc) / 16; 3965 /* fall through */ 3966 case IB_QPT_RC: 3967 switch (wr->opcode) { 3968 case IB_WR_RDMA_READ: 3969 case IB_WR_RDMA_WRITE: 3970 case IB_WR_RDMA_WRITE_WITH_IMM: 3971 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 3972 rdma_wr(wr)->rkey); 3973 seg += sizeof(struct mlx5_wqe_raddr_seg); 3974 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 3975 break; 3976 3977 case IB_WR_ATOMIC_CMP_AND_SWP: 3978 case IB_WR_ATOMIC_FETCH_AND_ADD: 3979 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3980 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); 3981 err = -ENOSYS; 3982 *bad_wr = wr; 3983 goto out; 3984 3985 case IB_WR_LOCAL_INV: 3986 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3987 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; 3988 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); 3989 set_linv_wr(qp, &seg, &size); 3990 num_sge = 0; 3991 break; 3992 3993 case IB_WR_REG_MR: 3994 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 3995 qp->sq.wr_data[idx] = IB_WR_REG_MR; 3996 ctrl->imm = cpu_to_be32(reg_wr(wr)->key); 3997 err = set_reg_wr(qp, reg_wr(wr), &seg, &size); 3998 if (err) { 3999 *bad_wr = wr; 4000 goto out; 4001 } 4002 num_sge = 0; 4003 break; 4004 4005 case IB_WR_REG_SIG_MR: 4006 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; 4007 mr = to_mmr(sig_handover_wr(wr)->sig_mr); 4008 4009 ctrl->imm = cpu_to_be32(mr->ibmr.rkey); 4010 err = set_sig_umr_wr(wr, qp, &seg, &size); 4011 if (err) { 4012 mlx5_ib_warn(dev, "\n"); 4013 *bad_wr = wr; 4014 goto out; 4015 } 4016 4017 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4018 nreq, get_fence(fence, wr), 4019 next_fence, MLX5_OPCODE_UMR); 4020 /* 4021 * SET_PSV WQEs are not signaled and solicited 4022 * on error 4023 */ 4024 err = begin_wqe(qp, &seg, &ctrl, wr, 4025 &idx, &size, nreq, IB_SEND_SOLICITED); 4026 if (err) { 4027 mlx5_ib_warn(dev, "\n"); 4028 err = -ENOMEM; 4029 *bad_wr = wr; 4030 goto out; 4031 } 4032 4033 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, 4034 mr->sig->psv_memory.psv_idx, &seg, 4035 &size); 4036 if (err) { 4037 mlx5_ib_warn(dev, "\n"); 4038 *bad_wr = wr; 4039 goto out; 4040 } 4041 4042 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4043 nreq, get_fence(fence, wr), 4044 next_fence, MLX5_OPCODE_SET_PSV); 4045 err = begin_wqe(qp, &seg, &ctrl, wr, 4046 &idx, &size, nreq, wr->send_flags); 4047 if (err) { 4048 mlx5_ib_warn(dev, "\n"); 4049 err = -ENOMEM; 4050 *bad_wr = wr; 4051 goto out; 4052 } 4053 4054 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; 4055 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, 4056 mr->sig->psv_wire.psv_idx, &seg, 4057 &size); 4058 if (err) { 4059 mlx5_ib_warn(dev, "\n"); 4060 *bad_wr = wr; 4061 goto out; 4062 } 4063 4064 finish_wqe(qp, ctrl, size, idx, wr->wr_id, 4065 nreq, get_fence(fence, wr), 4066 next_fence, MLX5_OPCODE_SET_PSV); 4067 num_sge = 0; 4068 goto skip_psv; 4069 4070 default: 4071 break; 4072 } 4073 break; 4074 4075 case IB_QPT_UC: 4076 switch (wr->opcode) { 4077 case IB_WR_RDMA_WRITE: 4078 case IB_WR_RDMA_WRITE_WITH_IMM: 4079 set_raddr_seg(seg, rdma_wr(wr)->remote_addr, 4080 rdma_wr(wr)->rkey); 4081 seg += sizeof(struct mlx5_wqe_raddr_seg); 4082 size += sizeof(struct mlx5_wqe_raddr_seg) / 16; 4083 break; 4084 4085 default: 4086 break; 4087 } 4088 break; 4089 4090 case IB_QPT_SMI: 4091 case MLX5_IB_QPT_HW_GSI: 4092 set_datagram_seg(seg, wr); 4093 seg += sizeof(struct mlx5_wqe_datagram_seg); 4094 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4095 if (unlikely((seg == qend))) 4096 seg = mlx5_get_send_wqe(qp, 0); 4097 break; 4098 case IB_QPT_UD: 4099 set_datagram_seg(seg, wr); 4100 seg += sizeof(struct mlx5_wqe_datagram_seg); 4101 size += sizeof(struct mlx5_wqe_datagram_seg) / 16; 4102 4103 if (unlikely((seg == qend))) 4104 seg = mlx5_get_send_wqe(qp, 0); 4105 4106 /* handle qp that supports ud offload */ 4107 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { 4108 struct mlx5_wqe_eth_pad *pad; 4109 4110 pad = seg; 4111 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); 4112 seg += sizeof(struct mlx5_wqe_eth_pad); 4113 size += sizeof(struct mlx5_wqe_eth_pad) / 16; 4114 4115 seg = set_eth_seg(seg, wr, qend, qp, &size); 4116 4117 if (unlikely((seg == qend))) 4118 seg = mlx5_get_send_wqe(qp, 0); 4119 } 4120 break; 4121 case MLX5_IB_QPT_REG_UMR: 4122 if (wr->opcode != MLX5_IB_WR_UMR) { 4123 err = -EINVAL; 4124 mlx5_ib_warn(dev, "bad opcode\n"); 4125 goto out; 4126 } 4127 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4128 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4129 set_reg_umr_segment(seg, wr); 4130 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4131 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4132 if (unlikely((seg == qend))) 4133 seg = mlx5_get_send_wqe(qp, 0); 4134 set_reg_mkey_segment(seg, wr); 4135 seg += sizeof(struct mlx5_mkey_seg); 4136 size += sizeof(struct mlx5_mkey_seg) / 16; 4137 if (unlikely((seg == qend))) 4138 seg = mlx5_get_send_wqe(qp, 0); 4139 break; 4140 4141 default: 4142 break; 4143 } 4144 4145 if (wr->send_flags & IB_SEND_INLINE && num_sge) { 4146 int uninitialized_var(sz); 4147 4148 err = set_data_inl_seg(qp, wr, seg, &sz); 4149 if (unlikely(err)) { 4150 mlx5_ib_warn(dev, "\n"); 4151 *bad_wr = wr; 4152 goto out; 4153 } 4154 size += sz; 4155 } else { 4156 dpseg = seg; 4157 for (i = 0; i < num_sge; i++) { 4158 if (unlikely(dpseg == qend)) { 4159 seg = mlx5_get_send_wqe(qp, 0); 4160 dpseg = seg; 4161 } 4162 if (likely(wr->sg_list[i].length)) { 4163 set_data_ptr_seg(dpseg, wr->sg_list + i); 4164 size += sizeof(struct mlx5_wqe_data_seg) / 16; 4165 dpseg++; 4166 } 4167 } 4168 } 4169 4170 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, 4171 get_fence(fence, wr), next_fence, 4172 mlx5_ib_opcode[wr->opcode]); 4173skip_psv: 4174 if (0) 4175 dump_wqe(qp, idx, size); 4176 } 4177 4178out: 4179 if (likely(nreq)) { 4180 qp->sq.head += nreq; 4181 4182 /* Make sure that descriptors are written before 4183 * updating doorbell record and ringing the doorbell 4184 */ 4185 wmb(); 4186 4187 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); 4188 4189 /* Make sure doorbell record is visible to the HCA before 4190 * we hit doorbell */ 4191 wmb(); 4192 4193 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, 4194 MLX5_GET_DOORBELL_LOCK(&bf->lock32)); 4195 /* Make sure doorbells don't leak out of SQ spinlock 4196 * and reach the HCA out of order. 4197 */ 4198 bf->offset ^= bf->buf_size; 4199 } 4200 4201 spin_unlock_irqrestore(&qp->sq.lock, flags); 4202 4203 return err; 4204} 4205 4206static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) 4207{ 4208 sig->signature = calc_sig(sig, size); 4209} 4210 4211int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 4212 const struct ib_recv_wr **bad_wr) 4213{ 4214 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4215 struct mlx5_wqe_data_seg *scat; 4216 struct mlx5_rwqe_sig *sig; 4217 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4218 struct mlx5_core_dev *mdev = dev->mdev; 4219 unsigned long flags; 4220 int err = 0; 4221 int nreq; 4222 int ind; 4223 int i; 4224 4225 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4226 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); 4227 4228 spin_lock_irqsave(&qp->rq.lock, flags); 4229 4230 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 4231 err = -EIO; 4232 *bad_wr = wr; 4233 nreq = 0; 4234 goto out; 4235 } 4236 4237 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 4238 4239 for (nreq = 0; wr; nreq++, wr = wr->next) { 4240 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 4241 err = -ENOMEM; 4242 *bad_wr = wr; 4243 goto out; 4244 } 4245 4246 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 4247 err = -EINVAL; 4248 *bad_wr = wr; 4249 goto out; 4250 } 4251 4252 scat = get_recv_wqe(qp, ind); 4253 if (qp->wq_sig) 4254 scat++; 4255 4256 for (i = 0; i < wr->num_sge; i++) 4257 set_data_ptr_seg(scat + i, wr->sg_list + i); 4258 4259 if (i < qp->rq.max_gs) { 4260 scat[i].byte_count = 0; 4261 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 4262 scat[i].addr = 0; 4263 } 4264 4265 if (qp->wq_sig) { 4266 sig = (struct mlx5_rwqe_sig *)scat; 4267 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); 4268 } 4269 4270 qp->rq.wrid[ind] = wr->wr_id; 4271 4272 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 4273 } 4274 4275out: 4276 if (likely(nreq)) { 4277 qp->rq.head += nreq; 4278 4279 /* Make sure that descriptors are written before 4280 * doorbell record. 4281 */ 4282 wmb(); 4283 4284 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 4285 } 4286 4287 spin_unlock_irqrestore(&qp->rq.lock, flags); 4288 4289 return err; 4290} 4291 4292static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) 4293{ 4294 switch (mlx5_state) { 4295 case MLX5_QP_STATE_RST: return IB_QPS_RESET; 4296 case MLX5_QP_STATE_INIT: return IB_QPS_INIT; 4297 case MLX5_QP_STATE_RTR: return IB_QPS_RTR; 4298 case MLX5_QP_STATE_RTS: return IB_QPS_RTS; 4299 case MLX5_QP_STATE_SQ_DRAINING: 4300 case MLX5_QP_STATE_SQD: return IB_QPS_SQD; 4301 case MLX5_QP_STATE_SQER: return IB_QPS_SQE; 4302 case MLX5_QP_STATE_ERR: return IB_QPS_ERR; 4303 default: return -1; 4304 } 4305} 4306 4307static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) 4308{ 4309 switch (mlx5_mig_state) { 4310 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; 4311 case MLX5_QP_PM_REARM: return IB_MIG_REARM; 4312 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 4313 default: return -1; 4314 } 4315} 4316 4317static int to_ib_qp_access_flags(int mlx5_flags) 4318{ 4319 int ib_flags = 0; 4320 4321 if (mlx5_flags & MLX5_QP_BIT_RRE) 4322 ib_flags |= IB_ACCESS_REMOTE_READ; 4323 if (mlx5_flags & MLX5_QP_BIT_RWE) 4324 ib_flags |= IB_ACCESS_REMOTE_WRITE; 4325 if (mlx5_flags & MLX5_QP_BIT_RAE) 4326 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 4327 4328 return ib_flags; 4329} 4330 4331static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr, 4332 struct mlx5_qp_path *path) 4333{ 4334 struct mlx5_core_dev *dev = ibdev->mdev; 4335 4336 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr)); 4337 ib_ah_attr->port_num = path->port; 4338 4339 if (ib_ah_attr->port_num == 0 || 4340 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports)) 4341 return; 4342 4343 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf; 4344 4345 ib_ah_attr->dlid = be16_to_cpu(path->rlid); 4346 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f; 4347 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0; 4348 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0; 4349 if (ib_ah_attr->ah_flags) { 4350 ib_ah_attr->grh.sgid_index = path->mgid_index; 4351 ib_ah_attr->grh.hop_limit = path->hop_limit; 4352 ib_ah_attr->grh.traffic_class = 4353 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff; 4354 ib_ah_attr->grh.flow_label = 4355 be32_to_cpu(path->tclass_flowlabel) & 0xfffff; 4356 memcpy(ib_ah_attr->grh.dgid.raw, 4357 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw)); 4358 } 4359} 4360 4361static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, 4362 struct mlx5_ib_sq *sq, 4363 u8 *sq_state) 4364{ 4365 void *out; 4366 void *sqc; 4367 int inlen; 4368 int err; 4369 4370 inlen = MLX5_ST_SZ_BYTES(query_sq_out); 4371 out = mlx5_vzalloc(inlen); 4372 if (!out) 4373 return -ENOMEM; 4374 4375 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out); 4376 if (err) 4377 goto out; 4378 4379 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context); 4380 *sq_state = MLX5_GET(sqc, sqc, state); 4381 sq->state = *sq_state; 4382 4383out: 4384 kvfree(out); 4385 return err; 4386} 4387 4388static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, 4389 struct mlx5_ib_rq *rq, 4390 u8 *rq_state) 4391{ 4392 void *out; 4393 void *rqc; 4394 int inlen; 4395 int err; 4396 4397 inlen = MLX5_ST_SZ_BYTES(query_rq_out); 4398 out = mlx5_vzalloc(inlen); 4399 if (!out) 4400 return -ENOMEM; 4401 4402 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); 4403 if (err) 4404 goto out; 4405 4406 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); 4407 *rq_state = MLX5_GET(rqc, rqc, state); 4408 rq->state = *rq_state; 4409 4410out: 4411 kvfree(out); 4412 return err; 4413} 4414 4415static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, 4416 struct mlx5_ib_qp *qp, u8 *qp_state) 4417{ 4418 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { 4419 [MLX5_RQC_STATE_RST] = { 4420 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4421 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4422 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, 4423 [MLX5_SQ_STATE_NA] = IB_QPS_RESET, 4424 }, 4425 [MLX5_RQC_STATE_RDY] = { 4426 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4427 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4428 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, 4429 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, 4430 }, 4431 [MLX5_RQC_STATE_ERR] = { 4432 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, 4433 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, 4434 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, 4435 [MLX5_SQ_STATE_NA] = IB_QPS_ERR, 4436 }, 4437 [MLX5_RQ_STATE_NA] = { 4438 [MLX5_SQC_STATE_RST] = IB_QPS_RESET, 4439 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, 4440 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, 4441 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, 4442 }, 4443 }; 4444 4445 *qp_state = sqrq_trans[rq_state][sq_state]; 4446 4447 if (*qp_state == MLX5_QP_STATE_BAD) { 4448 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", 4449 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, 4450 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); 4451 return -EINVAL; 4452 } 4453 4454 if (*qp_state == MLX5_QP_STATE) 4455 *qp_state = qp->state; 4456 4457 return 0; 4458} 4459 4460static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, 4461 struct mlx5_ib_qp *qp, 4462 u8 *raw_packet_qp_state) 4463{ 4464 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 4465 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 4466 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 4467 int err; 4468 u8 sq_state = MLX5_SQ_STATE_NA; 4469 u8 rq_state = MLX5_RQ_STATE_NA; 4470 4471 if (qp->sq.wqe_cnt) { 4472 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); 4473 if (err) 4474 return err; 4475 } 4476 4477 if (qp->rq.wqe_cnt) { 4478 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); 4479 if (err) 4480 return err; 4481 } 4482 4483 return sqrq_state_to_qp_state(sq_state, rq_state, qp, 4484 raw_packet_qp_state); 4485} 4486 4487static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, 4488 struct ib_qp_attr *qp_attr) 4489{ 4490 int outlen = MLX5_ST_SZ_BYTES(query_qp_out); 4491 struct mlx5_qp_context *context; 4492 int mlx5_state; 4493 u32 *outb; 4494 int err = 0; 4495 4496 outb = kzalloc(outlen, GFP_KERNEL); 4497 if (!outb) 4498 return -ENOMEM; 4499 4500 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, 4501 outlen); 4502 if (err) 4503 goto out; 4504 4505 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ 4506 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); 4507 4508 mlx5_state = be32_to_cpu(context->flags) >> 28; 4509 4510 qp->state = to_ib_qp_state(mlx5_state); 4511 qp_attr->path_mtu = context->mtu_msgmax >> 5; 4512 qp_attr->path_mig_state = 4513 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); 4514 qp_attr->qkey = be32_to_cpu(context->qkey); 4515 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; 4516 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; 4517 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; 4518 qp_attr->qp_access_flags = 4519 to_ib_qp_access_flags(be32_to_cpu(context->params2)); 4520 4521 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 4522 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); 4523 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); 4524 qp_attr->alt_pkey_index = 4525 be16_to_cpu(context->alt_path.pkey_index); 4526 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num; 4527 } 4528 4529 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); 4530 qp_attr->port_num = context->pri_path.port; 4531 4532 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 4533 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; 4534 4535 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); 4536 4537 qp_attr->max_dest_rd_atomic = 4538 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); 4539 qp_attr->min_rnr_timer = 4540 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; 4541 qp_attr->timeout = context->pri_path.ackto_lt >> 3; 4542 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; 4543 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; 4544 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; 4545 4546out: 4547 kfree(outb); 4548 return err; 4549} 4550 4551int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 4552 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 4553{ 4554 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 4555 struct mlx5_ib_qp *qp = to_mqp(ibqp); 4556 int err = 0; 4557 u8 raw_packet_qp_state; 4558 4559 if (ibqp->rwq_ind_tbl) 4560 return -ENOSYS; 4561 4562 if (unlikely(ibqp->qp_type == IB_QPT_GSI)) 4563 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, 4564 qp_init_attr); 4565 4566#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 4567 /* 4568 * Wait for any outstanding page faults, in case the user frees memory 4569 * based upon this query's result. 4570 */ 4571 flush_workqueue(mlx5_ib_page_fault_wq); 4572#endif 4573 4574 mutex_lock(&qp->mutex); 4575 4576 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 4577 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); 4578 if (err) 4579 goto out; 4580 qp->state = raw_packet_qp_state; 4581 qp_attr->port_num = 1; 4582 } else { 4583 err = query_qp_attr(dev, qp, qp_attr); 4584 if (err) 4585 goto out; 4586 } 4587 4588 qp_attr->qp_state = qp->state; 4589 qp_attr->cur_qp_state = qp_attr->qp_state; 4590 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 4591 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 4592 4593 if (!ibqp->uobject) { 4594 qp_attr->cap.max_send_wr = qp->sq.max_post; 4595 qp_attr->cap.max_send_sge = qp->sq.max_gs; 4596 qp_init_attr->qp_context = ibqp->qp_context; 4597 } else { 4598 qp_attr->cap.max_send_wr = 0; 4599 qp_attr->cap.max_send_sge = 0; 4600 } 4601 4602 qp_init_attr->qp_type = ibqp->qp_type; 4603 qp_init_attr->recv_cq = ibqp->recv_cq; 4604 qp_init_attr->send_cq = ibqp->send_cq; 4605 qp_init_attr->srq = ibqp->srq; 4606 qp_attr->cap.max_inline_data = qp->max_inline_data; 4607 4608 qp_init_attr->cap = qp_attr->cap; 4609 4610 qp_init_attr->create_flags = 0; 4611 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) 4612 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 4613 4614 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) 4615 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; 4616 if (qp->flags & MLX5_IB_QP_MANAGED_SEND) 4617 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; 4618 if (qp->flags & MLX5_IB_QP_MANAGED_RECV) 4619 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; 4620 if (qp->flags & MLX5_IB_QP_SQPN_QP1) 4621 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1; 4622 4623 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? 4624 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 4625 4626out: 4627 mutex_unlock(&qp->mutex); 4628 return err; 4629} 4630 4631struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, 4632 struct ib_udata *udata) 4633{ 4634 struct mlx5_ib_dev *dev = to_mdev(ibdev); 4635 struct mlx5_ib_xrcd *xrcd; 4636 int err; 4637 4638 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 4639 return ERR_PTR(-ENOSYS); 4640 4641 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); 4642 if (!xrcd) 4643 return ERR_PTR(-ENOMEM); 4644 4645 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn); 4646 if (err) { 4647 kfree(xrcd); 4648 return ERR_PTR(-ENOMEM); 4649 } 4650 4651 return &xrcd->ibxrcd; 4652} 4653 4654int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata) 4655{ 4656 struct mlx5_ib_dev *dev = to_mdev(xrcd->device); 4657 u32 xrcdn = to_mxrcd(xrcd)->xrcdn; 4658 int err; 4659 4660 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn); 4661 if (err) 4662 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); 4663 4664 kfree(xrcd); 4665 return 0; 4666} 4667 4668static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) 4669{ 4670 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); 4671 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); 4672 struct ib_event event; 4673 4674 if (rwq->ibwq.event_handler) { 4675 event.device = rwq->ibwq.device; 4676 event.element.wq = &rwq->ibwq; 4677 switch (type) { 4678 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 4679 event.event = IB_EVENT_WQ_FATAL; 4680 break; 4681 default: 4682 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); 4683 return; 4684 } 4685 4686 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); 4687 } 4688} 4689 4690static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, 4691 struct ib_wq_init_attr *init_attr) 4692{ 4693 struct mlx5_ib_dev *dev; 4694 __be64 *rq_pas0; 4695 void *in; 4696 void *rqc; 4697 void *wq; 4698 int inlen; 4699 int err; 4700 4701 dev = to_mdev(pd->device); 4702 4703 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; 4704 in = mlx5_vzalloc(inlen); 4705 if (!in) 4706 return -ENOMEM; 4707 4708 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); 4709 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 4710 MLX5_SET(rqc, rqc, mem_rq_type, 4711 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE); 4712 MLX5_SET(rqc, rqc, user_index, rwq->user_index); 4713 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); 4714 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 4715 MLX5_SET(rqc, rqc, flush_in_error_en, 1); 4716 wq = MLX5_ADDR_OF(rqc, rqc, wq); 4717 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 4718 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 4719 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); 4720 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); 4721 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); 4722 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); 4723 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); 4724 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); 4725 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); 4726 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); 4727 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); 4728 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); 4729 kvfree(in); 4730 return err; 4731} 4732 4733static int set_user_rq_size(struct mlx5_ib_dev *dev, 4734 struct ib_wq_init_attr *wq_init_attr, 4735 struct mlx5_ib_create_wq *ucmd, 4736 struct mlx5_ib_rwq *rwq) 4737{ 4738 /* Sanity check RQ size before proceeding */ 4739 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) 4740 return -EINVAL; 4741 4742 if (!ucmd->rq_wqe_count) 4743 return -EINVAL; 4744 4745 rwq->wqe_count = ucmd->rq_wqe_count; 4746 rwq->wqe_shift = ucmd->rq_wqe_shift; 4747 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift); 4748 rwq->log_rq_stride = rwq->wqe_shift; 4749 rwq->log_rq_size = ilog2(rwq->wqe_count); 4750 return 0; 4751} 4752 4753static int prepare_user_rq(struct ib_pd *pd, 4754 struct ib_wq_init_attr *init_attr, 4755 struct ib_udata *udata, 4756 struct mlx5_ib_rwq *rwq) 4757{ 4758 struct mlx5_ib_dev *dev = to_mdev(pd->device); 4759 struct mlx5_ib_create_wq ucmd = {}; 4760 int err; 4761 size_t required_cmd_sz; 4762 4763 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4764 if (udata->inlen < required_cmd_sz) { 4765 mlx5_ib_dbg(dev, "invalid inlen\n"); 4766 return -EINVAL; 4767 } 4768 4769 if (udata->inlen > sizeof(ucmd) && 4770 !ib_is_udata_cleared(udata, sizeof(ucmd), 4771 udata->inlen - sizeof(ucmd))) { 4772 mlx5_ib_dbg(dev, "inlen is not supported\n"); 4773 return -EOPNOTSUPP; 4774 } 4775 4776 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { 4777 mlx5_ib_dbg(dev, "copy failed\n"); 4778 return -EFAULT; 4779 } 4780 4781 if (ucmd.comp_mask) { 4782 mlx5_ib_dbg(dev, "invalid comp mask\n"); 4783 return -EOPNOTSUPP; 4784 } 4785 4786 if (ucmd.reserved) { 4787 mlx5_ib_dbg(dev, "invalid reserved\n"); 4788 return -EOPNOTSUPP; 4789 } 4790 4791 err = set_user_rq_size(dev, init_attr, &ucmd, rwq); 4792 if (err) { 4793 mlx5_ib_dbg(dev, "err %d\n", err); 4794 return err; 4795 } 4796 4797 err = create_user_rq(dev, pd, rwq, &ucmd); 4798 if (err) { 4799 mlx5_ib_dbg(dev, "err %d\n", err); 4800 if (err) 4801 return err; 4802 } 4803 4804 rwq->user_index = ucmd.user_index; 4805 return 0; 4806} 4807 4808struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 4809 struct ib_wq_init_attr *init_attr, 4810 struct ib_udata *udata) 4811{ 4812 struct mlx5_ib_dev *dev; 4813 struct mlx5_ib_rwq *rwq; 4814 struct mlx5_ib_create_wq_resp resp = {}; 4815 size_t min_resp_len; 4816 int err; 4817 4818 if (!udata) 4819 return ERR_PTR(-ENOSYS); 4820 4821 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4822 if (udata->outlen && udata->outlen < min_resp_len) 4823 return ERR_PTR(-EINVAL); 4824 4825 dev = to_mdev(pd->device); 4826 switch (init_attr->wq_type) { 4827 case IB_WQT_RQ: 4828 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); 4829 if (!rwq) 4830 return ERR_PTR(-ENOMEM); 4831 err = prepare_user_rq(pd, init_attr, udata, rwq); 4832 if (err) 4833 goto err; 4834 err = create_rq(rwq, pd, init_attr); 4835 if (err) 4836 goto err_user_rq; 4837 break; 4838 default: 4839 mlx5_ib_dbg(dev, "unsupported wq type %d\n", 4840 init_attr->wq_type); 4841 return ERR_PTR(-EINVAL); 4842 } 4843 4844 rwq->ibwq.wq_num = rwq->core_qp.qpn; 4845 rwq->ibwq.state = IB_WQS_RESET; 4846 if (udata->outlen) { 4847 resp.response_length = offsetof(typeof(resp), response_length) + 4848 sizeof(resp.response_length); 4849 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4850 if (err) 4851 goto err_copy; 4852 } 4853 4854 rwq->core_qp.event = mlx5_ib_wq_event; 4855 rwq->ibwq.event_handler = init_attr->event_handler; 4856 return &rwq->ibwq; 4857 4858err_copy: 4859 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4860err_user_rq: 4861 destroy_user_rq(pd, rwq, udata); 4862err: 4863 kfree(rwq); 4864 return ERR_PTR(err); 4865} 4866 4867void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata) 4868{ 4869 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4870 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4871 4872 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); 4873 destroy_user_rq(wq->pd, rwq, udata); 4874 kfree(rwq); 4875} 4876 4877struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 4878 struct ib_rwq_ind_table_init_attr *init_attr, 4879 struct ib_udata *udata) 4880{ 4881 struct mlx5_ib_dev *dev = to_mdev(device); 4882 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; 4883 int sz = 1 << init_attr->log_ind_tbl_size; 4884 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; 4885 size_t min_resp_len; 4886 int inlen; 4887 int err; 4888 int i; 4889 u32 *in; 4890 void *rqtc; 4891 4892 if (udata->inlen > 0 && 4893 !ib_is_udata_cleared(udata, 0, 4894 udata->inlen)) 4895 return ERR_PTR(-EOPNOTSUPP); 4896 4897 if (init_attr->log_ind_tbl_size > 4898 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { 4899 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", 4900 init_attr->log_ind_tbl_size, 4901 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); 4902 return ERR_PTR(-EINVAL); 4903 } 4904 4905 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); 4906 if (udata->outlen && udata->outlen < min_resp_len) 4907 return ERR_PTR(-EINVAL); 4908 4909 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); 4910 if (!rwq_ind_tbl) 4911 return ERR_PTR(-ENOMEM); 4912 4913 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 4914 in = mlx5_vzalloc(inlen); 4915 if (!in) { 4916 err = -ENOMEM; 4917 goto err; 4918 } 4919 4920 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 4921 4922 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 4923 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 4924 4925 for (i = 0; i < sz; i++) 4926 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); 4927 4928 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; 4929 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); 4930 4931 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); 4932 kvfree(in); 4933 4934 if (err) 4935 goto err; 4936 4937 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; 4938 if (udata->outlen) { 4939 resp.response_length = offsetof(typeof(resp), response_length) + 4940 sizeof(resp.response_length); 4941 err = ib_copy_to_udata(udata, &resp, resp.response_length); 4942 if (err) 4943 goto err_copy; 4944 } 4945 4946 return &rwq_ind_tbl->ib_rwq_ind_tbl; 4947 4948err_copy: 4949 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4950err: 4951 kfree(rwq_ind_tbl); 4952 return ERR_PTR(err); 4953} 4954 4955int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 4956{ 4957 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); 4958 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); 4959 4960 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); 4961 4962 kfree(rwq_ind_tbl); 4963 return 0; 4964} 4965 4966int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 4967 u32 wq_attr_mask, struct ib_udata *udata) 4968{ 4969 struct mlx5_ib_dev *dev = to_mdev(wq->device); 4970 struct mlx5_ib_rwq *rwq = to_mrwq(wq); 4971 struct mlx5_ib_modify_wq ucmd = {}; 4972 size_t required_cmd_sz; 4973 int curr_wq_state; 4974 int wq_state; 4975 int inlen; 4976 int err; 4977 void *rqc; 4978 void *in; 4979 4980 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); 4981 if (udata->inlen < required_cmd_sz) 4982 return -EINVAL; 4983 4984 if (udata->inlen > sizeof(ucmd) && 4985 !ib_is_udata_cleared(udata, sizeof(ucmd), 4986 udata->inlen - sizeof(ucmd))) 4987 return -EOPNOTSUPP; 4988 4989 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) 4990 return -EFAULT; 4991 4992 if (ucmd.comp_mask || ucmd.reserved) 4993 return -EOPNOTSUPP; 4994 4995 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 4996 in = mlx5_vzalloc(inlen); 4997 if (!in) 4998 return -ENOMEM; 4999 5000 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 5001 5002 MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn); 5003 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? 5004 wq_attr->curr_wq_state : wq->state; 5005 wq_state = (wq_attr_mask & IB_WQ_STATE) ? 5006 wq_attr->wq_state : curr_wq_state; 5007 if (curr_wq_state == IB_WQS_ERR) 5008 curr_wq_state = MLX5_RQC_STATE_ERR; 5009 if (wq_state == IB_WQS_ERR) 5010 wq_state = MLX5_RQC_STATE_ERR; 5011 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); 5012 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); 5013 MLX5_SET(rqc, rqc, state, wq_state); 5014 5015 err = mlx5_core_modify_rq(dev->mdev, in, inlen); 5016 kvfree(in); 5017 if (!err) 5018 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; 5019 5020 return err; 5021} 5022