1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2017 Cavium, Inc.. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Cavium, Inc. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include "lio_bsd.h" 35#include "lio_common.h" 36#include "lio_droq.h" 37#include "lio_iq.h" 38#include "lio_response_manager.h" 39#include "lio_device.h" 40#include "lio_main.h" 41#include "lio_network.h" 42#include "cn23xx_pf_device.h" 43#include "lio_rxtx.h" 44 45struct lio_iq_post_status { 46 int status; 47 int index; 48}; 49 50static void lio_check_db_timeout(void *arg, int pending); 51static void __lio_check_db_timeout(struct octeon_device *oct, 52 uint64_t iq_no); 53 54/* Return 0 on success, 1 on failure */ 55int 56lio_init_instr_queue(struct octeon_device *oct, union octeon_txpciq txpciq, 57 uint32_t num_descs) 58{ 59 struct lio_instr_queue *iq; 60 struct lio_iq_config *conf = NULL; 61 struct lio_tq *db_tq; 62 struct lio_request_list *request_buf; 63 bus_size_t max_size; 64 uint32_t iq_no = (uint32_t)txpciq.s.q_no; 65 uint32_t q_size; 66 int error, i; 67 68 if (LIO_CN23XX_PF(oct)) 69 conf = &(LIO_GET_IQ_CFG(LIO_CHIP_CONF(oct, cn23xx_pf))); 70 if (conf == NULL) { 71 lio_dev_err(oct, "Unsupported Chip %x\n", oct->chip_id); 72 return (1); 73 } 74 75 q_size = (uint32_t)conf->instr_type * num_descs; 76 iq = oct->instr_queue[iq_no]; 77 iq->oct_dev = oct; 78 79 max_size = LIO_CN23XX_PKI_MAX_FRAME_SIZE * num_descs; 80 81 error = bus_dma_tag_create(bus_get_dma_tag(oct->device), /* parent */ 82 1, 0, /* alignment, bounds */ 83 BUS_SPACE_MAXADDR, /* lowaddr */ 84 BUS_SPACE_MAXADDR, /* highaddr */ 85 NULL, NULL, /* filter, filterarg */ 86 max_size, /* maxsize */ 87 LIO_MAX_SG, /* nsegments */ 88 PAGE_SIZE, /* maxsegsize */ 89 0, /* flags */ 90 NULL, /* lockfunc */ 91 NULL, /* lockfuncarg */ 92 &iq->txtag); 93 if (error) { 94 lio_dev_err(oct, "Cannot allocate memory for instr queue %d\n", 95 iq_no); 96 return (1); 97 } 98 99 iq->base_addr = lio_dma_alloc(q_size, (vm_paddr_t *)&iq->base_addr_dma); 100 if (!iq->base_addr) { 101 lio_dev_err(oct, "Cannot allocate memory for instr queue %d\n", 102 iq_no); 103 return (1); 104 } 105 106 iq->max_count = num_descs; 107 108 /* 109 * Initialize a list to holds requests that have been posted to 110 * Octeon but has yet to be fetched by octeon 111 */ 112 iq->request_list = malloc(sizeof(*iq->request_list) * num_descs, 113 M_DEVBUF, M_NOWAIT | M_ZERO); 114 if (iq->request_list == NULL) { 115 lio_dev_err(oct, "Alloc failed for IQ[%d] nr free list\n", 116 iq_no); 117 return (1); 118 } 119 120 lio_dev_dbg(oct, "IQ[%d]: base: %p basedma: %llx count: %d\n", 121 iq_no, iq->base_addr, LIO_CAST64(iq->base_addr_dma), 122 iq->max_count); 123 124 /* Create the descriptor buffer dma maps */ 125 request_buf = iq->request_list; 126 for (i = 0; i < num_descs; i++, request_buf++) { 127 error = bus_dmamap_create(iq->txtag, 0, &request_buf->map); 128 if (error) { 129 lio_dev_err(oct, "Unable to create TX DMA map\n"); 130 return (1); 131 } 132 } 133 134 iq->txpciq.txpciq64 = txpciq.txpciq64; 135 iq->fill_cnt = 0; 136 iq->host_write_index = 0; 137 iq->octeon_read_index = 0; 138 iq->flush_index = 0; 139 iq->last_db_time = 0; 140 iq->db_timeout = (uint32_t)conf->db_timeout; 141 atomic_store_rel_int(&iq->instr_pending, 0); 142 143 /* Initialize the lock for this instruction queue */ 144 mtx_init(&iq->lock, "Tx_lock", NULL, MTX_DEF); 145 mtx_init(&iq->post_lock, "iq_post_lock", NULL, MTX_DEF); 146 mtx_init(&iq->enq_lock, "enq_lock", NULL, MTX_DEF); 147 148 mtx_init(&iq->iq_flush_running_lock, "iq_flush_running_lock", NULL, 149 MTX_DEF); 150 151 oct->io_qmask.iq |= BIT_ULL(iq_no); 152 153 /* Set the 32B/64B mode for each input queue */ 154 oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no); 155 iq->iqcmd_64B = (conf->instr_type == 64); 156 157 oct->fn_list.setup_iq_regs(oct, iq_no); 158 159 db_tq = &oct->check_db_tq[iq_no]; 160 db_tq->tq = taskqueue_create("lio_check_db_timeout", M_WAITOK, 161 taskqueue_thread_enqueue, &db_tq->tq); 162 if (db_tq->tq == NULL) { 163 lio_dev_err(oct, "check db wq create failed for iq %d\n", 164 iq_no); 165 return (1); 166 } 167 168 TIMEOUT_TASK_INIT(db_tq->tq, &db_tq->work, 0, lio_check_db_timeout, 169 (void *)db_tq); 170 db_tq->ctxul = iq_no; 171 db_tq->ctxptr = oct; 172 173 taskqueue_start_threads(&db_tq->tq, 1, PI_NET, 174 "lio%d_check_db_timeout:%d", 175 oct->octeon_id, iq_no); 176 taskqueue_enqueue_timeout(db_tq->tq, &db_tq->work, 1); 177 178 /* Allocate a buf ring */ 179 oct->instr_queue[iq_no]->br = 180 buf_ring_alloc(LIO_BR_SIZE, M_DEVBUF, M_WAITOK, 181 &oct->instr_queue[iq_no]->enq_lock); 182 if (oct->instr_queue[iq_no]->br == NULL) { 183 lio_dev_err(oct, "Critical Failure setting up buf ring\n"); 184 return (1); 185 } 186 187 return (0); 188} 189 190int 191lio_delete_instr_queue(struct octeon_device *oct, uint32_t iq_no) 192{ 193 struct lio_instr_queue *iq = oct->instr_queue[iq_no]; 194 struct lio_request_list *request_buf; 195 struct lio_mbuf_free_info *finfo; 196 uint64_t desc_size = 0, q_size; 197 int i; 198 199 lio_dev_dbg(oct, "%s[%d]\n", __func__, iq_no); 200 201 if (oct->check_db_tq[iq_no].tq != NULL) { 202 while (taskqueue_cancel_timeout(oct->check_db_tq[iq_no].tq, 203 &oct->check_db_tq[iq_no].work, 204 NULL)) 205 taskqueue_drain_timeout(oct->check_db_tq[iq_no].tq, 206 &oct->check_db_tq[iq_no].work); 207 taskqueue_free(oct->check_db_tq[iq_no].tq); 208 oct->check_db_tq[iq_no].tq = NULL; 209 } 210 211 if (LIO_CN23XX_PF(oct)) 212 desc_size = 213 LIO_GET_IQ_INSTR_TYPE_CFG(LIO_CHIP_CONF(oct, cn23xx_pf)); 214 215 request_buf = iq->request_list; 216 for (i = 0; i < iq->max_count; i++, request_buf++) { 217 if ((request_buf->reqtype == LIO_REQTYPE_NORESP_NET) || 218 (request_buf->reqtype == LIO_REQTYPE_NORESP_NET_SG)) { 219 if (request_buf->buf != NULL) { 220 finfo = request_buf->buf; 221 bus_dmamap_sync(iq->txtag, request_buf->map, 222 BUS_DMASYNC_POSTWRITE); 223 bus_dmamap_unload(iq->txtag, 224 request_buf->map); 225 m_freem(finfo->mb); 226 request_buf->buf = NULL; 227 if (request_buf->map != NULL) { 228 bus_dmamap_destroy(iq->txtag, 229 request_buf->map); 230 request_buf->map = NULL; 231 } 232 } else if (request_buf->map != NULL) { 233 bus_dmamap_unload(iq->txtag, request_buf->map); 234 bus_dmamap_destroy(iq->txtag, request_buf->map); 235 request_buf->map = NULL; 236 } 237 } 238 } 239 240 if (iq->br != NULL) { 241 buf_ring_free(iq->br, M_DEVBUF); 242 iq->br = NULL; 243 } 244 245 if (iq->request_list != NULL) { 246 free(iq->request_list, M_DEVBUF); 247 iq->request_list = NULL; 248 } 249 250 if (iq->txtag != NULL) { 251 bus_dma_tag_destroy(iq->txtag); 252 iq->txtag = NULL; 253 } 254 255 if (iq->base_addr) { 256 q_size = iq->max_count * desc_size; 257 lio_dma_free((uint32_t)q_size, iq->base_addr); 258 259 oct->io_qmask.iq &= ~(1ULL << iq_no); 260 bzero(oct->instr_queue[iq_no], sizeof(struct lio_instr_queue)); 261 oct->num_iqs--; 262 263 return (0); 264 } 265 266 return (1); 267} 268 269/* Return 0 on success, 1 on failure */ 270int 271lio_setup_iq(struct octeon_device *oct, int ifidx, int q_index, 272 union octeon_txpciq txpciq, uint32_t num_descs) 273{ 274 uint32_t iq_no = (uint32_t)txpciq.s.q_no; 275 276 if (oct->instr_queue[iq_no]->oct_dev != NULL) { 277 lio_dev_dbg(oct, "IQ is in use. Cannot create the IQ: %d again\n", 278 iq_no); 279 oct->instr_queue[iq_no]->txpciq.txpciq64 = txpciq.txpciq64; 280 return (0); 281 } 282 283 oct->instr_queue[iq_no]->q_index = q_index; 284 oct->instr_queue[iq_no]->ifidx = ifidx; 285 286 if (lio_init_instr_queue(oct, txpciq, num_descs)) { 287 lio_delete_instr_queue(oct, iq_no); 288 return (1); 289 } 290 291 oct->num_iqs++; 292 if (oct->fn_list.enable_io_queues(oct)) 293 return (1); 294 295 return (0); 296} 297 298int 299lio_wait_for_instr_fetch(struct octeon_device *oct) 300{ 301 int i, retry = 1000, pending, instr_cnt = 0; 302 303 do { 304 instr_cnt = 0; 305 306 for (i = 0; i < LIO_MAX_INSTR_QUEUES(oct); i++) { 307 if (!(oct->io_qmask.iq & BIT_ULL(i))) 308 continue; 309 pending = atomic_load_acq_int( 310 &oct->instr_queue[i]->instr_pending); 311 if (pending) 312 __lio_check_db_timeout(oct, i); 313 instr_cnt += pending; 314 } 315 316 if (instr_cnt == 0) 317 break; 318 319 lio_sleep_timeout(1); 320 321 } while (retry-- && instr_cnt); 322 323 return (instr_cnt); 324} 325 326static inline void 327lio_ring_doorbell(struct octeon_device *oct, struct lio_instr_queue *iq) 328{ 329 330 if (atomic_load_acq_int(&oct->status) == LIO_DEV_RUNNING) { 331 lio_write_csr32(oct, iq->doorbell_reg, iq->fill_cnt); 332 /* make sure doorbell write goes through */ 333 __compiler_membar(); 334 iq->fill_cnt = 0; 335 iq->last_db_time = ticks; 336 return; 337 } 338} 339 340static inline void 341__lio_copy_cmd_into_iq(struct lio_instr_queue *iq, uint8_t *cmd) 342{ 343 uint8_t *iqptr, cmdsize; 344 345 cmdsize = ((iq->iqcmd_64B) ? 64 : 32); 346 iqptr = iq->base_addr + (cmdsize * iq->host_write_index); 347 348 memcpy(iqptr, cmd, cmdsize); 349} 350 351static inline struct lio_iq_post_status 352__lio_post_command2(struct lio_instr_queue *iq, uint8_t *cmd) 353{ 354 struct lio_iq_post_status st; 355 356 st.status = LIO_IQ_SEND_OK; 357 358 /* 359 * This ensures that the read index does not wrap around to the same 360 * position if queue gets full before Octeon could fetch any instr. 361 */ 362 if (atomic_load_acq_int(&iq->instr_pending) >= 363 (int32_t)(iq->max_count - 1)) { 364 st.status = LIO_IQ_SEND_FAILED; 365 st.index = -1; 366 return (st); 367 } 368 369 if (atomic_load_acq_int(&iq->instr_pending) >= 370 (int32_t)(iq->max_count - 2)) 371 st.status = LIO_IQ_SEND_STOP; 372 373 __lio_copy_cmd_into_iq(iq, cmd); 374 375 /* "index" is returned, host_write_index is modified. */ 376 st.index = iq->host_write_index; 377 iq->host_write_index = lio_incr_index(iq->host_write_index, 1, 378 iq->max_count); 379 iq->fill_cnt++; 380 381 /* 382 * Flush the command into memory. We need to be sure the data is in 383 * memory before indicating that the instruction is pending. 384 */ 385 wmb(); 386 387 atomic_add_int(&iq->instr_pending, 1); 388 389 return (st); 390} 391 392static inline void 393__lio_add_to_request_list(struct lio_instr_queue *iq, int idx, void *buf, 394 int reqtype) 395{ 396 397 iq->request_list[idx].buf = buf; 398 iq->request_list[idx].reqtype = reqtype; 399} 400 401/* Can only run in process context */ 402int 403lio_process_iq_request_list(struct octeon_device *oct, 404 struct lio_instr_queue *iq, uint32_t budget) 405{ 406 struct lio_soft_command *sc; 407 struct octeon_instr_irh *irh = NULL; 408 void *buf; 409 uint32_t inst_count = 0; 410 uint32_t old = iq->flush_index; 411 int reqtype; 412 413 while (old != iq->octeon_read_index) { 414 reqtype = iq->request_list[old].reqtype; 415 buf = iq->request_list[old].buf; 416 417 if (reqtype == LIO_REQTYPE_NONE) 418 goto skip_this; 419 420 switch (reqtype) { 421 case LIO_REQTYPE_NORESP_NET: 422 lio_free_mbuf(iq, buf); 423 break; 424 case LIO_REQTYPE_NORESP_NET_SG: 425 lio_free_sgmbuf(iq, buf); 426 break; 427 case LIO_REQTYPE_RESP_NET: 428 case LIO_REQTYPE_SOFT_COMMAND: 429 sc = buf; 430 if (LIO_CN23XX_PF(oct)) 431 irh = (struct octeon_instr_irh *) 432 &sc->cmd.cmd3.irh; 433 if (irh->rflag) { 434 /* 435 * We're expecting a response from Octeon. 436 * It's up to lio_process_ordered_list() to 437 * process sc. Add sc to the ordered soft 438 * command response list because we expect 439 * a response from Octeon. 440 */ 441 mtx_lock(&oct->response_list 442 [LIO_ORDERED_SC_LIST].lock); 443 atomic_add_int(&oct->response_list 444 [LIO_ORDERED_SC_LIST]. 445 pending_req_count, 1); 446 STAILQ_INSERT_TAIL(&oct->response_list 447 [LIO_ORDERED_SC_LIST]. 448 head, &sc->node, entries); 449 mtx_unlock(&oct->response_list 450 [LIO_ORDERED_SC_LIST].lock); 451 } else { 452 if (sc->callback != NULL) { 453 /* This callback must not sleep */ 454 sc->callback(oct, LIO_REQUEST_DONE, 455 sc->callback_arg); 456 } 457 } 458 459 break; 460 default: 461 lio_dev_err(oct, "%s Unknown reqtype: %d buf: %p at idx %d\n", 462 __func__, reqtype, buf, old); 463 } 464 465 iq->request_list[old].buf = NULL; 466 iq->request_list[old].reqtype = 0; 467 468skip_this: 469 inst_count++; 470 old = lio_incr_index(old, 1, iq->max_count); 471 472 if ((budget) && (inst_count >= budget)) 473 break; 474 } 475 476 iq->flush_index = old; 477 478 return (inst_count); 479} 480 481/* Can only be called from process context */ 482int 483lio_flush_iq(struct octeon_device *oct, struct lio_instr_queue *iq, 484 uint32_t budget) 485{ 486 uint32_t inst_processed = 0; 487 uint32_t tot_inst_processed = 0; 488 int tx_done = 1; 489 490 if (!mtx_trylock(&iq->iq_flush_running_lock)) 491 return (tx_done); 492 493 mtx_lock(&iq->lock); 494 495 iq->octeon_read_index = oct->fn_list.update_iq_read_idx(iq); 496 497 do { 498 /* Process any outstanding IQ packets. */ 499 if (iq->flush_index == iq->octeon_read_index) 500 break; 501 502 if (budget) 503 inst_processed = 504 lio_process_iq_request_list(oct, iq, 505 budget - 506 tot_inst_processed); 507 else 508 inst_processed = 509 lio_process_iq_request_list(oct, iq, 0); 510 511 if (inst_processed) { 512 atomic_subtract_int(&iq->instr_pending, inst_processed); 513 iq->stats.instr_processed += inst_processed; 514 } 515 tot_inst_processed += inst_processed; 516 inst_processed = 0; 517 518 } while (tot_inst_processed < budget); 519 520 if (budget && (tot_inst_processed >= budget)) 521 tx_done = 0; 522 523 iq->last_db_time = ticks; 524 525 mtx_unlock(&iq->lock); 526 527 mtx_unlock(&iq->iq_flush_running_lock); 528 529 return (tx_done); 530} 531 532/* 533 * Process instruction queue after timeout. 534 * This routine gets called from a taskqueue or when removing the module. 535 */ 536static void 537__lio_check_db_timeout(struct octeon_device *oct, uint64_t iq_no) 538{ 539 struct lio_instr_queue *iq; 540 uint64_t next_time; 541 542 if (oct == NULL) 543 return; 544 545 iq = oct->instr_queue[iq_no]; 546 if (iq == NULL) 547 return; 548 549 if (atomic_load_acq_int(&iq->instr_pending)) { 550 /* If ticks - last_db_time < db_timeout do nothing */ 551 next_time = iq->last_db_time + lio_ms_to_ticks(iq->db_timeout); 552 if (!lio_check_timeout(ticks, next_time)) 553 return; 554 555 iq->last_db_time = ticks; 556 557 /* Flush the instruction queue */ 558 lio_flush_iq(oct, iq, 0); 559 560 lio_enable_irq(NULL, iq); 561 } 562 563 if (oct->props.ifp != NULL && iq->br != NULL) { 564 if (mtx_trylock(&iq->enq_lock)) { 565 if (!drbr_empty(oct->props.ifp, iq->br)) 566 lio_mq_start_locked(oct->props.ifp, iq); 567 568 mtx_unlock(&iq->enq_lock); 569 } 570 } 571} 572 573/* 574 * Called by the Poll thread at regular intervals to check the instruction 575 * queue for commands to be posted and for commands that were fetched by Octeon. 576 */ 577static void 578lio_check_db_timeout(void *arg, int pending) 579{ 580 struct lio_tq *db_tq = (struct lio_tq *)arg; 581 struct octeon_device *oct = db_tq->ctxptr; 582 uint64_t iq_no = db_tq->ctxul; 583 uint32_t delay = 10; 584 585 __lio_check_db_timeout(oct, iq_no); 586 taskqueue_enqueue_timeout(db_tq->tq, &db_tq->work, 587 lio_ms_to_ticks(delay)); 588} 589 590int 591lio_send_command(struct octeon_device *oct, uint32_t iq_no, 592 uint32_t force_db, void *cmd, void *buf, 593 uint32_t datasize, uint32_t reqtype) 594{ 595 struct lio_iq_post_status st; 596 struct lio_instr_queue *iq = oct->instr_queue[iq_no]; 597 598 /* 599 * Get the lock and prevent other tasks and tx interrupt handler 600 * from running. 601 */ 602 mtx_lock(&iq->post_lock); 603 604 st = __lio_post_command2(iq, cmd); 605 606 if (st.status != LIO_IQ_SEND_FAILED) { 607 __lio_add_to_request_list(iq, st.index, buf, reqtype); 608 LIO_INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize); 609 LIO_INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1); 610 611 if (force_db || (st.status == LIO_IQ_SEND_STOP)) 612 lio_ring_doorbell(oct, iq); 613 } else { 614 LIO_INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1); 615 } 616 617 mtx_unlock(&iq->post_lock); 618 619 /* 620 * This is only done here to expedite packets being flushed for 621 * cases where there are no IQ completion interrupts. 622 */ 623 624 return (st.status); 625} 626 627void 628lio_prepare_soft_command(struct octeon_device *oct, struct lio_soft_command *sc, 629 uint8_t opcode, uint8_t subcode, uint32_t irh_ossp, 630 uint64_t ossp0, uint64_t ossp1) 631{ 632 struct octeon_instr_ih3 *ih3; 633 struct octeon_instr_pki_ih3 *pki_ih3; 634 struct octeon_instr_irh *irh; 635 struct octeon_instr_rdp *rdp; 636 637 KASSERT(opcode <= 15, ("%s, %d, opcode > 15", __func__, __LINE__)); 638 KASSERT(subcode <= 127, ("%s, %d, opcode > 127", __func__, __LINE__)); 639 640 if (LIO_CN23XX_PF(oct)) { 641 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3; 642 643 ih3->pkind = oct->instr_queue[sc->iq_no]->txpciq.s.pkind; 644 645 pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3; 646 647 pki_ih3->w = 1; 648 pki_ih3->raw = 1; 649 pki_ih3->utag = 1; 650 pki_ih3->uqpg = oct->instr_queue[sc->iq_no]->txpciq.s.use_qpg; 651 pki_ih3->utt = 1; 652 pki_ih3->tag = LIO_CONTROL; 653 pki_ih3->tagtype = LIO_ATOMIC_TAG; 654 pki_ih3->qpg = oct->instr_queue[sc->iq_no]->txpciq.s.qpg; 655 pki_ih3->pm = 0x7; 656 pki_ih3->sl = 8; 657 658 if (sc->datasize) 659 ih3->dlengsz = sc->datasize; 660 661 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh; 662 irh->opcode = opcode; 663 irh->subcode = subcode; 664 665 /* opcode/subcode specific parameters (ossp) */ 666 irh->ossp = irh_ossp; 667 sc->cmd.cmd3.ossp[0] = ossp0; 668 sc->cmd.cmd3.ossp[1] = ossp1; 669 670 if (sc->rdatasize) { 671 rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp; 672 rdp->pcie_port = oct->pcie_port; 673 rdp->rlen = sc->rdatasize; 674 675 irh->rflag = 1; 676 /* PKI IH3 */ 677 /* pki_ih3 irh+ossp[0]+ossp[1]+rdp+rptr = 48 bytes */ 678 ih3->fsz = LIO_SOFTCMDRESP_IH3; 679 } else { 680 irh->rflag = 0; 681 /* PKI IH3 */ 682 /* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */ 683 ih3->fsz = LIO_PCICMD_O3; 684 } 685 } 686} 687 688int 689lio_send_soft_command(struct octeon_device *oct, struct lio_soft_command *sc) 690{ 691 struct octeon_instr_ih3 *ih3; 692 struct octeon_instr_irh *irh; 693 uint32_t len = 0; 694 695 if (LIO_CN23XX_PF(oct)) { 696 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3; 697 if (ih3->dlengsz) { 698 KASSERT(sc->dmadptr, ("%s, %d, sc->dmadptr is NULL", 699 __func__, __LINE__)); 700 sc->cmd.cmd3.dptr = sc->dmadptr; 701 } 702 703 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh; 704 if (irh->rflag) { 705 KASSERT(sc->dmarptr, ("%s, %d, sc->dmarptr is NULL", 706 __func__, __LINE__)); 707 KASSERT(sc->status_word, ("%s, %d, sc->status_word is NULL", 708 __func__, __LINE__)); 709 *sc->status_word = COMPLETION_WORD_INIT; 710 sc->cmd.cmd3.rptr = sc->dmarptr; 711 } 712 len = (uint32_t)ih3->dlengsz; 713 } 714 if (sc->wait_time) 715 sc->timeout = ticks + lio_ms_to_ticks(sc->wait_time); 716 717 return (lio_send_command(oct, sc->iq_no, 1, &sc->cmd, sc, 718 len, LIO_REQTYPE_SOFT_COMMAND)); 719} 720 721int 722lio_setup_sc_buffer_pool(struct octeon_device *oct) 723{ 724 struct lio_soft_command *sc; 725 uint64_t dma_addr; 726 int i; 727 728 STAILQ_INIT(&oct->sc_buf_pool.head); 729 mtx_init(&oct->sc_buf_pool.lock, "sc_pool_lock", NULL, MTX_DEF); 730 atomic_store_rel_int(&oct->sc_buf_pool.alloc_buf_count, 0); 731 732 for (i = 0; i < LIO_MAX_SOFT_COMMAND_BUFFERS; i++) { 733 sc = (struct lio_soft_command *) 734 lio_dma_alloc(LIO_SOFT_COMMAND_BUFFER_SIZE, (vm_paddr_t *)&dma_addr); 735 if (sc == NULL) { 736 lio_free_sc_buffer_pool(oct); 737 return (1); 738 } 739 740 sc->dma_addr = dma_addr; 741 sc->size = LIO_SOFT_COMMAND_BUFFER_SIZE; 742 743 STAILQ_INSERT_TAIL(&oct->sc_buf_pool.head, &sc->node, entries); 744 } 745 746 return (0); 747} 748 749int 750lio_free_sc_buffer_pool(struct octeon_device *oct) 751{ 752 struct lio_stailq_node *tmp, *tmp2; 753 struct lio_soft_command *sc; 754 755 mtx_lock(&oct->sc_buf_pool.lock); 756 757 STAILQ_FOREACH_SAFE(tmp, &oct->sc_buf_pool.head, entries, tmp2) { 758 sc = LIO_STAILQ_FIRST_ENTRY(&oct->sc_buf_pool.head, 759 struct lio_soft_command, node); 760 761 STAILQ_REMOVE_HEAD(&oct->sc_buf_pool.head, entries); 762 763 lio_dma_free(sc->size, sc); 764 } 765 766 STAILQ_INIT(&oct->sc_buf_pool.head); 767 768 mtx_unlock(&oct->sc_buf_pool.lock); 769 770 return (0); 771} 772 773struct lio_soft_command * 774lio_alloc_soft_command(struct octeon_device *oct, uint32_t datasize, 775 uint32_t rdatasize, uint32_t ctxsize) 776{ 777 struct lio_soft_command *sc = NULL; 778 struct lio_stailq_node *tmp; 779 uint64_t dma_addr; 780 uint32_t size; 781 uint32_t offset = sizeof(struct lio_soft_command); 782 783 KASSERT((offset + datasize + rdatasize + ctxsize) <= 784 LIO_SOFT_COMMAND_BUFFER_SIZE, 785 ("%s, %d, offset + datasize + rdatasize + ctxsize > LIO_SOFT_COMMAND_BUFFER_SIZE", 786 __func__, __LINE__)); 787 788 mtx_lock(&oct->sc_buf_pool.lock); 789 790 if (STAILQ_EMPTY(&oct->sc_buf_pool.head)) { 791 mtx_unlock(&oct->sc_buf_pool.lock); 792 return (NULL); 793 } 794 tmp = STAILQ_LAST(&oct->sc_buf_pool.head, lio_stailq_node, entries); 795 796 STAILQ_REMOVE(&oct->sc_buf_pool.head, tmp, lio_stailq_node, entries); 797 798 atomic_add_int(&oct->sc_buf_pool.alloc_buf_count, 1); 799 800 mtx_unlock(&oct->sc_buf_pool.lock); 801 802 sc = (struct lio_soft_command *)tmp; 803 804 dma_addr = sc->dma_addr; 805 size = sc->size; 806 807 bzero(sc, sc->size); 808 809 sc->dma_addr = dma_addr; 810 sc->size = size; 811 812 if (ctxsize) { 813 sc->ctxptr = (uint8_t *)sc + offset; 814 sc->ctxsize = ctxsize; 815 } 816 817 /* Start data at 128 byte boundary */ 818 offset = (offset + ctxsize + 127) & 0xffffff80; 819 820 if (datasize) { 821 sc->virtdptr = (uint8_t *)sc + offset; 822 sc->dmadptr = dma_addr + offset; 823 sc->datasize = datasize; 824 } 825 /* Start rdata at 128 byte boundary */ 826 offset = (offset + datasize + 127) & 0xffffff80; 827 828 if (rdatasize) { 829 KASSERT(rdatasize >= 16, ("%s, %d, rdatasize < 16", __func__, 830 __LINE__)); 831 sc->virtrptr = (uint8_t *)sc + offset; 832 sc->dmarptr = dma_addr + offset; 833 sc->rdatasize = rdatasize; 834 sc->status_word = (uint64_t *)((uint8_t *)(sc->virtrptr) + 835 rdatasize - 8); 836 } 837 return (sc); 838} 839 840void 841lio_free_soft_command(struct octeon_device *oct, 842 struct lio_soft_command *sc) 843{ 844 845 mtx_lock(&oct->sc_buf_pool.lock); 846 847 STAILQ_INSERT_TAIL(&oct->sc_buf_pool.head, &sc->node, entries); 848 849 atomic_subtract_int(&oct->sc_buf_pool.alloc_buf_count, 1); 850 851 mtx_unlock(&oct->sc_buf_pool.lock); 852} 853