1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 1997-2009 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31/* 32 * Machine Independent (well, as best as possible) register 33 * definitions for Qlogic ISP SCSI adapters. 34 */ 35#ifndef _ISPREG_H 36#define _ISPREG_H 37 38/* 39 * Hardware definitions for the Qlogic ISP registers. 40 */ 41 42/* 43 * This defines types of access to various registers. 44 * 45 * R: Read Only 46 * W: Write Only 47 * RW: Read/Write 48 * 49 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only 50 * if RISC processor in ISP is paused. 51 */ 52 53/* 54 * NB: The *_BLOCK definitions have no specific hardware meaning. 55 * They serve simply to note to the MD layer which block of 56 * registers offsets are being accessed. 57 */ 58#define _NREG_BLKS 2 59#define _BLK_REG_SHFT 7 60#define _BLK_REG_MASK (1 << _BLK_REG_SHFT) 61#define BIU_BLOCK (0 << _BLK_REG_SHFT) 62#define MBOX_BLOCK (1 << _BLK_REG_SHFT) 63 64#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */ 65#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */ 66#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */ 67#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */ 68#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */ 69#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */ 70#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 71#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */ 72#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 73#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */ 74#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */ 75#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */ 76#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */ 77#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */ 78#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */ 79#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */ 80 81/* 82 * 2400 Interface Offsets and Register Definitions 83 * 84 * The 2400 looks quite different in terms of registers from other QLogic cards. 85 * It is getting to be a genuine pain and challenge to keep the same model 86 * for all. 87 */ 88#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) /* Flash Access Address */ 89#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) /* Flash Data */ 90#define BIU2400_CSR (BIU_BLOCK+0x08) /* ISP Control/Status */ 91#define BIU2400_ICR (BIU_BLOCK+0x0C) /* ISP to PCI Interrupt Control */ 92#define BIU2400_ISR (BIU_BLOCK+0x10) /* ISP to PCI Interrupt Status */ 93 94#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */ 95#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */ 96#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */ 97#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */ 98 99#define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */ 100#define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */ 101 102#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */ 103#define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */ 104 105#define BIU2400_R2HSTS (BIU_BLOCK+0x44) /* RISC to Host Status */ 106 107#define BIU2400_HCCR (BIU_BLOCK+0x48) /* Host Command and Control Status */ 108#define BIU2400_GPIOD (BIU_BLOCK+0x4C) /* General Purpose I/O Data */ 109#define BIU2400_GPIOE (BIU_BLOCK+0x50) /* General Purpose I/O Enable */ 110#define BIU2400_IOBBA (BIU_BLOCK+0x54) /* I/O Bus Base Address */ 111#define BIU2400_HSEMA (BIU_BLOCK+0x58) /* Host-to-Host Semaphore */ 112 113/* BIU2400_FLASH_ADDR definitions */ 114#define BIU2400_FLASH_DFLAG (1 << 30) 115 116/* BIU2400_CSR definitions */ 117#define BIU2400_NVERR (1 << 18) 118#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */ 119#define BIU2400_DMA_STOP (1 << 16) 120#define BIU2400_FUNCTION (1 << 15) /* RO */ 121#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */ 122#define BIU2400_CSR_64BIT (1 << 2) /* RO */ 123#define BIU2400_FLASH_ENABLE (1 << 1) 124#define BIU2400_SOFT_RESET (1 << 0) 125 126/* BIU2400_ICR definitions */ 127#define BIU2400_ICR_ENA_RISC_INT 0x8 128#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT) 129 130/* BIU2400_ISR definitions */ 131#define BIU2400_ISR_RISC_INT 0x8 132 133/* BIU2400_HCCR definitions */ 134#define HCCR_2400_CMD_NOP 0x00000000 135#define HCCR_2400_CMD_RESET 0x10000000 136#define HCCR_2400_CMD_CLEAR_RESET 0x20000000 137#define HCCR_2400_CMD_PAUSE 0x30000000 138#define HCCR_2400_CMD_RELEASE 0x40000000 139#define HCCR_2400_CMD_SET_HOST_INT 0x50000000 140#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 141#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 142 143#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 144#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 145#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 146 147 148/* 149 * Mailbox Block Register Offsets 150 */ 151#define INMAILBOX0 (MBOX_BLOCK+0x0) 152#define INMAILBOX1 (MBOX_BLOCK+0x2) 153#define INMAILBOX2 (MBOX_BLOCK+0x4) 154#define INMAILBOX3 (MBOX_BLOCK+0x6) 155#define INMAILBOX4 (MBOX_BLOCK+0x8) 156#define INMAILBOX5 (MBOX_BLOCK+0xA) 157#define INMAILBOX6 (MBOX_BLOCK+0xC) 158#define INMAILBOX7 (MBOX_BLOCK+0xE) 159 160#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 161#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 162#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 163#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 164#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 165#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 166#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 167#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 168 169#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 170#define ISP_NMBOX(isp) 32 171#define MAX_MAILBOX 32 172 173/* if timeout == 0, then default timeout is picked */ 174#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 175typedef struct { 176 uint16_t param[MAX_MAILBOX]; 177 uint32_t ibits; /* bits to add for register copyin */ 178 uint32_t obits; /* bits to add for register copyout */ 179 uint32_t ibitm; /* bits to mask for register copyin */ 180 uint32_t obitm; /* bits to mask for register copyout */ 181 uint32_t logval; /* Bitmask of status codes to log */ 182 uint32_t timeout; 183 uint32_t lineno; 184 const char *func; 185} mbreg_t; 186#define MBSINIT(mbxp, code, loglev, timo) \ 187 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \ 188 (mbxp)->ibitm = ~0; \ 189 (mbxp)->obitm = ~0; \ 190 (mbxp)->param[0] = code; \ 191 (mbxp)->lineno = __LINE__; \ 192 (mbxp)->func = __func__; \ 193 (mbxp)->logval = loglev; \ 194 (mbxp)->timeout = timo 195 196/* 197 * Defines for Interrupts 198 */ 199#define ISP_INTS_ENABLED(isp) \ 200 (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) 201 202#define ISP_ENABLE_INTS(isp) \ 203 ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK) 204 205#define ISP_DISABLE_INTS(isp) \ 206 ISP_WRITE(isp, BIU2400_ICR, 0) 207 208/* 209 * NVRAM Definitions (PCI cards only) 210 */ 211 212/* 213 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 214 */ 215#define ISP2400_NVRAM_PORT_ADDR(c) (0x100 * (c) + 0x80) 216#define ISP2400_NVRAM_SIZE 512 217 218#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 219#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 220#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 221 222#define ISP2400_NVRAM_PORT_NAME(c) (\ 223 (((uint64_t)(c)[20]) << 56) | \ 224 (((uint64_t)(c)[21]) << 48) | \ 225 (((uint64_t)(c)[22]) << 40) | \ 226 (((uint64_t)(c)[23]) << 32) | \ 227 (((uint64_t)(c)[24]) << 24) | \ 228 (((uint64_t)(c)[25]) << 16) | \ 229 (((uint64_t)(c)[26]) << 8) | \ 230 (((uint64_t)(c)[27]) << 0)) 231 232#define ISP2400_NVRAM_NODE_NAME(c) (\ 233 (((uint64_t)(c)[28]) << 56) | \ 234 (((uint64_t)(c)[29]) << 48) | \ 235 (((uint64_t)(c)[30]) << 40) | \ 236 (((uint64_t)(c)[31]) << 32) | \ 237 (((uint64_t)(c)[32]) << 24) | \ 238 (((uint64_t)(c)[33]) << 16) | \ 239 (((uint64_t)(c)[34]) << 8) | \ 240 (((uint64_t)(c)[35]) << 0)) 241 242#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 243#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 244#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 245#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 246 247#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 248 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 249#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 250 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 251#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 252 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 253 254/* 255 * Qlogic FLT 256 */ 257#define ISP24XX_BASE_ADDR 0x7ff00000 258#define ISP24XX_FLT_ADDR 0x11400 259 260#define ISP25XX_BASE_ADDR ISP24XX_BASE_ADDR 261#define ISP25XX_FLT_ADDR 0x50400 262 263#define ISP27XX_BASE_ADDR 0x7f800000 264#define ISP27XX_FLT_ADDR (0x3F1000 / 4) 265 266#define ISP28XX_BASE_ADDR 0x7f7d0000 267#define ISP28XX_FLT_ADDR (0x11000 / 4) 268 269#define FLT_HEADER_SIZE 8 270#define FLT_REGION_SIZE 16 271#define FLT_MAX_REGIONS 0xFF 272#define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS) 273 274#define ISP2XXX_FLT_VERSION(c) ((c)[0] | ((c)[1] << 8)) 275#define ISP2XXX_FLT_LENGTH(c) ((c)[2] | ((c)[3] << 8)) 276#define ISP2XXX_FLT_CSUM(c) ((c)[4] | ((c)[5] << 8)) 277#define ISP2XXX_FLT_REG_CODE(c, o) \ 278 ((c)[0 + FLT_REGION_SIZE * o] | ((c)[1 + FLT_REGION_SIZE * o] << 8)) 279#define ISP2XXX_FLT_REG_ATTR(c, o) ((c)[2 + FLT_REGION_SIZE * o]) 280#define ISP2XXX_FLT_REG_RES(c, o) ((c)[3 + FLT_REGION_SIZE * o]) 281#define ISP2XXX_FLT_REG_SIZE(c, o) (\ 282 ((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) | \ 283 ((uint32_t)(c)[5 + FLT_REGION_SIZE * o] << 8) | \ 284 ((uint32_t)(c)[6 + FLT_REGION_SIZE * o] << 16) | \ 285 ((uint32_t)(c)[7 + FLT_REGION_SIZE * o] << 24)) 286#define ISP2XXX_FLT_REG_START(c, o) (\ 287 ((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) | \ 288 ((uint32_t)(c)[9 + FLT_REGION_SIZE * o] << 8) | \ 289 ((uint32_t)(c)[10 + FLT_REGION_SIZE * o] << 16) | \ 290 ((uint32_t)(c)[11 + FLT_REGION_SIZE * o] << 24)) 291#define ISP2XXX_FLT_REG_END(c, o) (\ 292 ((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) | \ 293 ((uint32_t)(c)[13 + FLT_REGION_SIZE * o] << 8) | \ 294 ((uint32_t)(c)[14 + FLT_REGION_SIZE * o] << 16) | \ 295 ((uint32_t)(c)[15 + FLT_REGION_SIZE * o] << 24)) 296 297struct flt_region { 298 uint16_t code; 299 uint8_t attribute; 300 uint8_t reserved; 301 uint32_t size; 302 uint32_t start; 303 uint32_t end; 304}; 305 306#define FLT_REG_FW 0x01 307#define FLT_REG_BOOT_CODE 0x07 308#define FLT_REG_VPD_0 0x14 309#define FLT_REG_NVRAM_0 0x15 310#define FLT_REG_VPD_1 0x16 311#define FLT_REG_NVRAM_1 0x17 312#define FLT_REG_VPD_2 0xd4 313#define FLT_REG_NVRAM_2 0xd5 314#define FLT_REG_VPD_3 0xd6 315#define FLT_REG_NVRAM_3 0xd7 316#define FLT_REG_FDT 0x1a 317#define FLT_REG_FLT 0x1c 318#define FLT_REG_NPIV_CONF_0 0x29 319#define FLT_REG_NPIV_CONF_1 0x2a 320#define FLT_REG_GOLD_FW 0x2f 321#define FLT_REG_FCP_PRIO_0 0x87 322#define FLT_REG_FCP_PRIO_1 0x88 323 324/* 27xx */ 325#define FLT_REG_IMG_PRI_27XX 0x95 326#define FLT_REG_IMG_SEC_27XX 0x96 327#define FLT_REG_FW_SEC_27XX 0x02 328#define FLT_REG_BOOTLOAD_SEC_27XX 0x9 329#define FLT_REG_VPD_SEC_27XX_0 0x50 330#define FLT_REG_VPD_SEC_27XX_1 0x52 331#define FLT_REG_VPD_SEC_27XX_2 0xd8 332#define FLT_REG_VPD_SEC_27XX_3 0xda 333 334/* 28xx */ 335#define FLT_REG_AUX_IMG_PRI_28XX 0x125 336#define FLT_REG_AUX_IMG_SEC_28XX 0x126 337#define FLT_REG_NVRAM_SEC_28XX_0 0x10d 338#define FLT_REG_NVRAM_SEC_28XX_1 0x10f 339#define FLT_REG_NVRAM_SEC_28XX_2 0x111 340#define FLT_REG_NVRAM_SEC_28XX_3 0x113 341#define FLT_REG_VPD_SEC_28XX_0 0x10c 342#define FLT_REG_VPD_SEC_28XX_1 0x10e 343#define FLT_REG_VPD_SEC_28XX_2 0x110 344#define FLT_REG_VPD_SEC_28XX_3 0x112 345 346#define ISP27XX_IMG_STATUS_VER_MAJOR 0x01 347#define ISP27XX_IMG_STATUS_VER_MINOR 0x00 348#define ISP27XX_IMG_STATUS_SIGN 0xfacefade 349#define ISP28XX_IMG_STATUS_SIGN 0xfacefadf 350#define ISP28XX_AUX_IMG_STATUS_SIGN 0xfacefaed 351#define ISP27XX_DEFAULT_IMAGE 0 352#define ISP27XX_PRIMARY_IMAGE 1 353#define ISP27XX_SECONDARY_IMAGE 2 354 355#define ISP_RISC_CODE_SEGMENTS 2 356 357#endif /* _ISPREG_H */ 358