150488Speter/*- 232672Sache * Copyright (C) 2012 Intel Corporation 332672Sache * All rights reserved. 432672Sache * 532672Sache * Redistribution and use in source and binary forms, with or without 632672Sache * modification, are permitted provided that the following conditions 732672Sache * are met: 832672Sache * 1. Redistributions of source code must retain the above copyright 932672Sache * notice, this list of conditions and the following disclaimer. 1032672Sache * 2. Redistributions in binary form must reproduce the above copyright 1132672Sache * notice, this list of conditions and the following disclaimer in the 1232672Sache * documentation and/or other materials provided with the distribution. 1332672Sache * 1432672Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1532672Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1632672Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1732672Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1832672Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1932672Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2032672Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2132672Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2232672Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2332672Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2432672Sache * SUCH DAMAGE. 2532672Sache */ 2632672Sache#ifndef __IOAT_TEST_H__ 2732672Sache#define __IOAT_TEST_H__ 2832672Sache 2932672Sacheenum ioat_res { 3032672Sache IOAT_TEST_OK = 0, 3132672Sache IOAT_TEST_NO_DMA_ENGINE, 32105017Skris IOAT_TEST_NO_MEMORY, 3332672Sache IOAT_TEST_MISCOMPARE, 3432672Sache IOAT_TEST_INVALID_INPUT, 3532672Sache IOAT_NUM_RES 36105017Skris}; 37105017Skris 3832672Sacheenum ioat_test_kind { 3932672Sache IOAT_TEST_FILL = 0, 4032672Sache IOAT_TEST_DMA, 4132672Sache IOAT_TEST_RAW_DMA, 4232672Sache IOAT_TEST_DMA_8K, 4332672Sache IOAT_TEST_MEMCPY, 4432672Sache IOAT_TEST_DMA_8K_PB, 4532672Sache IOAT_TEST_DMA_CRC, 4632672Sache IOAT_TEST_DMA_CRC_COPY, 4732672Sache IOAT_NUM_TESTKINDS 4832672Sache}; 4932672Sache 5032672Sachestruct test_transaction; 5132672Sache 5232672Sachestruct ioat_test { 5332672Sache volatile uint32_t status[IOAT_NUM_RES]; 5432672Sache uint32_t channel_index; 5532672Sache 5632672Sache enum ioat_test_kind testkind; 5732672Sache 5832672Sache /* HW max of 1MB */ 5932672Sache uint32_t buffer_size; 6032672Sache uint32_t chain_depth; 6132672Sache uint32_t transactions; 6232672Sache 6332672Sache /* 6432672Sache * If non-zero, duration is time in ms; 6532672Sache * If zero, bounded by 'transactions' above. 66191910Ssepotvin */ 6732672Sache uint32_t duration; 6832672Sache 6932672Sache /* If true, check for miscompares after a copy. */ 7032672Sache bool verify; 7132672Sache 7232672Sache /* DMA directly to/from some memory address */ 7332672Sache uint64_t raw_target; 7432672Sache void *raw_vtarget; 7532672Sache bool raw_write; 7632672Sache bool raw_is_virtual; 7732672Sache 7832672Sache bool zero_stats; 7932672Sache /* Configure coalesce period */ 8032672Sache uint16_t coalesce_period; 8132672Sache 8232672Sache /* Internal usage -- not test inputs */ 8332672Sache TAILQ_HEAD(, test_transaction) free_q; 8432672Sache TAILQ_HEAD(, test_transaction) pend_q; 8532672Sache volatile bool too_late; 8632672Sache}; 8732672Sache 8832672Sache#define IOAT_DMATEST _IOWR('i', 0, struct ioat_test) 8932672Sache 9032672Sache#endif /* __IOAT_TEST_H__ */ 9132672Sache