1/*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <sys/cdefs.h> 8#include "igc_api.h" 9 10static void igc_config_collision_dist_generic(struct igc_hw *hw); 11 12/** 13 * igc_init_mac_ops_generic - Initialize MAC function pointers 14 * @hw: pointer to the HW structure 15 * 16 * Setups up the function pointers to no-op functions 17 **/ 18void igc_init_mac_ops_generic(struct igc_hw *hw) 19{ 20 struct igc_mac_info *mac = &hw->mac; 21 DEBUGFUNC("igc_init_mac_ops_generic"); 22 23 /* General Setup */ 24 mac->ops.init_params = igc_null_ops_generic; 25 mac->ops.config_collision_dist = igc_config_collision_dist_generic; 26 mac->ops.rar_set = igc_rar_set_generic; 27} 28 29/** 30 * igc_null_ops_generic - No-op function, returns 0 31 * @hw: pointer to the HW structure 32 **/ 33s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw) 34{ 35 DEBUGFUNC("igc_null_ops_generic"); 36 return IGC_SUCCESS; 37} 38 39/** 40 * igc_null_mac_generic - No-op function, return void 41 * @hw: pointer to the HW structure 42 **/ 43void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw) 44{ 45 DEBUGFUNC("igc_null_mac_generic"); 46 return; 47} 48 49/** 50 * igc_null_link_info - No-op function, return 0 51 * @hw: pointer to the HW structure 52 * @s: dummy variable 53 * @d: dummy variable 54 **/ 55s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw, 56 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d) 57{ 58 DEBUGFUNC("igc_null_link_info"); 59 return IGC_SUCCESS; 60} 61 62/** 63 * igc_null_mng_mode - No-op function, return false 64 * @hw: pointer to the HW structure 65 **/ 66bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw) 67{ 68 DEBUGFUNC("igc_null_mng_mode"); 69 return false; 70} 71 72/** 73 * igc_null_update_mc - No-op function, return void 74 * @hw: pointer to the HW structure 75 * @h: dummy variable 76 * @a: dummy variable 77 **/ 78void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw, 79 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 80{ 81 DEBUGFUNC("igc_null_update_mc"); 82 return; 83} 84 85/** 86 * igc_null_write_vfta - No-op function, return void 87 * @hw: pointer to the HW structure 88 * @a: dummy variable 89 * @b: dummy variable 90 **/ 91void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw, 92 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b) 93{ 94 DEBUGFUNC("igc_null_write_vfta"); 95 return; 96} 97 98/** 99 * igc_null_rar_set - No-op function, return 0 100 * @hw: pointer to the HW structure 101 * @h: dummy variable 102 * @a: dummy variable 103 **/ 104int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw, 105 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 106{ 107 DEBUGFUNC("igc_null_rar_set"); 108 return IGC_SUCCESS; 109} 110 111/** 112 * igc_set_lan_id_single_port - Set LAN id for a single port device 113 * @hw: pointer to the HW structure 114 * 115 * Sets the LAN function id to zero for a single port device. 116 **/ 117void igc_set_lan_id_single_port(struct igc_hw *hw) 118{ 119 struct igc_bus_info *bus = &hw->bus; 120 121 bus->func = 0; 122} 123 124/** 125 * igc_clear_vfta_generic - Clear VLAN filter table 126 * @hw: pointer to the HW structure 127 * 128 * Clears the register array which contains the VLAN filter table by 129 * setting all the values to 0. 130 **/ 131void igc_clear_vfta_generic(struct igc_hw *hw) 132{ 133 u32 offset; 134 135 DEBUGFUNC("igc_clear_vfta_generic"); 136 137 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) { 138 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0); 139 IGC_WRITE_FLUSH(hw); 140 } 141} 142 143/** 144 * igc_write_vfta_generic - Write value to VLAN filter table 145 * @hw: pointer to the HW structure 146 * @offset: register offset in VLAN filter table 147 * @value: register value written to VLAN filter table 148 * 149 * Writes value at the given offset in the register array which stores 150 * the VLAN filter table. 151 **/ 152void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value) 153{ 154 DEBUGFUNC("igc_write_vfta_generic"); 155 156 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value); 157 IGC_WRITE_FLUSH(hw); 158} 159 160/** 161 * igc_init_rx_addrs_generic - Initialize receive address's 162 * @hw: pointer to the HW structure 163 * @rar_count: receive address registers 164 * 165 * Setup the receive address registers by setting the base receive address 166 * register to the devices MAC address and clearing all the other receive 167 * address registers to 0. 168 **/ 169void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count) 170{ 171 u32 i; 172 u8 mac_addr[ETH_ADDR_LEN] = {0}; 173 174 DEBUGFUNC("igc_init_rx_addrs_generic"); 175 176 /* Setup the receive address */ 177 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 178 179 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 180 181 /* Zero out the other (rar_entry_count - 1) receive addresses */ 182 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 183 for (i = 1; i < rar_count; i++) 184 hw->mac.ops.rar_set(hw, mac_addr, i); 185} 186 187/** 188 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr 189 * @hw: pointer to the HW structure 190 * 191 * Checks the nvm for an alternate MAC address. An alternate MAC address 192 * can be setup by pre-boot software and must be treated like a permanent 193 * address and must override the actual permanent MAC address. If an 194 * alternate MAC address is found it is programmed into RAR0, replacing 195 * the permanent address that was installed into RAR0 by the Si on reset. 196 * This function will return SUCCESS unless it encounters an error while 197 * reading the EEPROM. 198 **/ 199s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw) 200{ 201 u32 i; 202 s32 ret_val; 203 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 204 u8 alt_mac_addr[ETH_ADDR_LEN]; 205 206 DEBUGFUNC("igc_check_alt_mac_addr_generic"); 207 208 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 209 if (ret_val) 210 return ret_val; 211 212 213 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 214 &nvm_alt_mac_addr_offset); 215 if (ret_val) { 216 DEBUGOUT("NVM Read Error\n"); 217 return ret_val; 218 } 219 220 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 221 (nvm_alt_mac_addr_offset == 0x0000)) 222 /* There is no Alternate MAC Address */ 223 return IGC_SUCCESS; 224 225 if (hw->bus.func == IGC_FUNC_1) 226 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1; 227 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 228 offset = nvm_alt_mac_addr_offset + (i >> 1); 229 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 230 if (ret_val) { 231 DEBUGOUT("NVM Read Error\n"); 232 return ret_val; 233 } 234 235 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 236 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 237 } 238 239 /* if multicast bit is set, the alternate address will not be used */ 240 if (alt_mac_addr[0] & 0x01) { 241 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 242 return IGC_SUCCESS; 243 } 244 245 /* We have a valid alternate MAC address, and we want to treat it the 246 * same as the normal permanent MAC address stored by the HW into the 247 * RAR. Do this by mapping this address into RAR0. 248 */ 249 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 250 251 return IGC_SUCCESS; 252} 253 254/** 255 * igc_rar_set_generic - Set receive address register 256 * @hw: pointer to the HW structure 257 * @addr: pointer to the receive address 258 * @index: receive address array register 259 * 260 * Sets the receive address array register at index to the address passed 261 * in by addr. 262 **/ 263int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index) 264{ 265 u32 rar_low, rar_high; 266 267 DEBUGFUNC("igc_rar_set_generic"); 268 269 /* HW expects these in little endian so we reverse the byte order 270 * from network order (big endian) to little endian 271 */ 272 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 273 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 274 275 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 276 277 /* If MAC address zero, no need to set the AV bit */ 278 if (rar_low || rar_high) 279 rar_high |= IGC_RAH_AV; 280 281 /* Some bridges will combine consecutive 32-bit writes into 282 * a single burst write, which will malfunction on some parts. 283 * The flushes avoid this. 284 */ 285 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low); 286 IGC_WRITE_FLUSH(hw); 287 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high); 288 IGC_WRITE_FLUSH(hw); 289 290 return IGC_SUCCESS; 291} 292 293/** 294 * igc_hash_mc_addr_generic - Generate a multicast hash value 295 * @hw: pointer to the HW structure 296 * @mc_addr: pointer to a multicast address 297 * 298 * Generates a multicast address hash value which is used to determine 299 * the multicast filter table array address and new table value. 300 **/ 301u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr) 302{ 303 u32 hash_value, hash_mask; 304 u8 bit_shift = 0; 305 306 DEBUGFUNC("igc_hash_mc_addr_generic"); 307 308 /* Register count multiplied by bits per register */ 309 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 310 311 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 312 * where 0xFF would still fall within the hash mask. 313 */ 314 while (hash_mask >> bit_shift != 0xFF) 315 bit_shift++; 316 317 /* The portion of the address that is used for the hash table 318 * is determined by the mc_filter_type setting. 319 * The algorithm is such that there is a total of 8 bits of shifting. 320 * The bit_shift for a mc_filter_type of 0 represents the number of 321 * left-shifts where the MSB of mc_addr[5] would still fall within 322 * the hash_mask. Case 0 does this exactly. Since there are a total 323 * of 8 bits of shifting, then mc_addr[4] will shift right the 324 * remaining number of bits. Thus 8 - bit_shift. The rest of the 325 * cases are a variation of this algorithm...essentially raising the 326 * number of bits to shift mc_addr[5] left, while still keeping the 327 * 8-bit shifting total. 328 * 329 * For example, given the following Destination MAC Address and an 330 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 331 * we can see that the bit_shift for case 0 is 4. These are the hash 332 * values resulting from each mc_filter_type... 333 * [0] [1] [2] [3] [4] [5] 334 * 01 AA 00 12 34 56 335 * LSB MSB 336 * 337 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 338 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 339 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 340 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 341 */ 342 switch (hw->mac.mc_filter_type) { 343 default: 344 case 0: 345 break; 346 case 1: 347 bit_shift += 1; 348 break; 349 case 2: 350 bit_shift += 2; 351 break; 352 case 3: 353 bit_shift += 4; 354 break; 355 } 356 357 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 358 (((u16) mc_addr[5]) << bit_shift))); 359 360 return hash_value; 361} 362 363/** 364 * igc_update_mc_addr_list_generic - Update Multicast addresses 365 * @hw: pointer to the HW structure 366 * @mc_addr_list: array of multicast addresses to program 367 * @mc_addr_count: number of multicast addresses to program 368 * 369 * Updates entire Multicast Table Array. 370 * The caller must have a packed mc_addr_list of multicast addresses. 371 **/ 372void igc_update_mc_addr_list_generic(struct igc_hw *hw, 373 u8 *mc_addr_list, u32 mc_addr_count) 374{ 375 u32 hash_value, hash_bit, hash_reg; 376 int i; 377 378 DEBUGFUNC("igc_update_mc_addr_list_generic"); 379 380 /* clear mta_shadow */ 381 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 382 383 /* update mta_shadow from mc_addr_list */ 384 for (i = 0; (u32) i < mc_addr_count; i++) { 385 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list); 386 387 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 388 hash_bit = hash_value & 0x1F; 389 390 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 391 mc_addr_list += (ETH_ADDR_LEN); 392 } 393 394 /* replace the entire MTA table */ 395 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 396 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]); 397 IGC_WRITE_FLUSH(hw); 398} 399 400/** 401 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters 402 * @hw: pointer to the HW structure 403 * 404 * Clears the base hardware counters by reading the counter registers. 405 **/ 406void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw) 407{ 408 DEBUGFUNC("igc_clear_hw_cntrs_base_generic"); 409 410 IGC_READ_REG(hw, IGC_CRCERRS); 411 IGC_READ_REG(hw, IGC_MPC); 412 IGC_READ_REG(hw, IGC_SCC); 413 IGC_READ_REG(hw, IGC_ECOL); 414 IGC_READ_REG(hw, IGC_MCC); 415 IGC_READ_REG(hw, IGC_LATECOL); 416 IGC_READ_REG(hw, IGC_COLC); 417 IGC_READ_REG(hw, IGC_RERC); 418 IGC_READ_REG(hw, IGC_DC); 419 IGC_READ_REG(hw, IGC_RLEC); 420 IGC_READ_REG(hw, IGC_XONRXC); 421 IGC_READ_REG(hw, IGC_XONTXC); 422 IGC_READ_REG(hw, IGC_XOFFRXC); 423 IGC_READ_REG(hw, IGC_XOFFTXC); 424 IGC_READ_REG(hw, IGC_FCRUC); 425 IGC_READ_REG(hw, IGC_GPRC); 426 IGC_READ_REG(hw, IGC_BPRC); 427 IGC_READ_REG(hw, IGC_MPRC); 428 IGC_READ_REG(hw, IGC_GPTC); 429 IGC_READ_REG(hw, IGC_GORCL); 430 IGC_READ_REG(hw, IGC_GORCH); 431 IGC_READ_REG(hw, IGC_GOTCL); 432 IGC_READ_REG(hw, IGC_GOTCH); 433 IGC_READ_REG(hw, IGC_RNBC); 434 IGC_READ_REG(hw, IGC_RUC); 435 IGC_READ_REG(hw, IGC_RFC); 436 IGC_READ_REG(hw, IGC_ROC); 437 IGC_READ_REG(hw, IGC_RJC); 438 IGC_READ_REG(hw, IGC_TORL); 439 IGC_READ_REG(hw, IGC_TORH); 440 IGC_READ_REG(hw, IGC_TOTL); 441 IGC_READ_REG(hw, IGC_TOTH); 442 IGC_READ_REG(hw, IGC_TPR); 443 IGC_READ_REG(hw, IGC_TPT); 444 IGC_READ_REG(hw, IGC_MPTC); 445 IGC_READ_REG(hw, IGC_BPTC); 446 IGC_READ_REG(hw, IGC_TLPIC); 447 IGC_READ_REG(hw, IGC_RLPIC); 448 IGC_READ_REG(hw, IGC_RXDMTC); 449} 450 451/** 452 * igc_check_for_copper_link_generic - Check for link (Copper) 453 * @hw: pointer to the HW structure 454 * 455 * Checks to see of the link status of the hardware has changed. If a 456 * change in link status has been detected, then we read the PHY registers 457 * to get the current speed/duplex if link exists. 458 **/ 459s32 igc_check_for_copper_link_generic(struct igc_hw *hw) 460{ 461 struct igc_mac_info *mac = &hw->mac; 462 s32 ret_val; 463 bool link = false; 464 465 DEBUGFUNC("igc_check_for_copper_link"); 466 467 /* We only want to go out to the PHY registers to see if Auto-Neg 468 * has completed and/or if our link status has changed. The 469 * get_link_status flag is set upon receiving a Link Status 470 * Change or Rx Sequence Error interrupt. 471 */ 472 if (!mac->get_link_status) 473 return IGC_SUCCESS; 474 475 /* First we want to see if the MII Status Register reports 476 * link. If so, then we want to get the current speed/duplex 477 * of the PHY. 478 */ 479 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 480 if (ret_val) 481 return ret_val; 482 483 if (!link) 484 return IGC_SUCCESS; /* No link detected */ 485 486 mac->get_link_status = false; 487 488 /* Check if there was DownShift, must be checked 489 * immediately after link-up 490 */ 491 igc_check_downshift_generic(hw); 492 493 /* If we are forcing speed/duplex, then we simply return since 494 * we have already determined whether we have link or not. 495 */ 496 if (!mac->autoneg) 497 return -IGC_ERR_CONFIG; 498 499 /* Auto-Neg is enabled. Auto Speed Detection takes care 500 * of MAC speed/duplex configuration. So we only need to 501 * configure Collision Distance in the MAC. 502 */ 503 mac->ops.config_collision_dist(hw); 504 505 /* Configure Flow Control now that Auto-Neg has completed. 506 * First, we need to restore the desired flow control 507 * settings because we may have had to re-autoneg with a 508 * different link partner. 509 */ 510 ret_val = igc_config_fc_after_link_up_generic(hw); 511 if (ret_val) 512 DEBUGOUT("Error configuring flow control\n"); 513 514 return ret_val; 515} 516 517/** 518 * igc_setup_link_generic - Setup flow control and link settings 519 * @hw: pointer to the HW structure 520 * 521 * Determines which flow control settings to use, then configures flow 522 * control. Calls the appropriate media-specific link configuration 523 * function. Assuming the adapter has a valid link partner, a valid link 524 * should be established. Assumes the hardware has previously been reset 525 * and the transmitter and receiver are not enabled. 526 **/ 527s32 igc_setup_link_generic(struct igc_hw *hw) 528{ 529 s32 ret_val; 530 531 DEBUGFUNC("igc_setup_link_generic"); 532 533 /* In the case of the phy reset being blocked, we already have a link. 534 * We do not need to set it up again. 535 */ 536 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 537 return IGC_SUCCESS; 538 539 /* If requested flow control is set to default, set flow control 540 * for both 'rx' and 'tx' pause frames. 541 */ 542 if (hw->fc.requested_mode == igc_fc_default) { 543 hw->fc.requested_mode = igc_fc_full; 544 } 545 546 /* Save off the requested flow control mode for use later. Depending 547 * on the link partner's capabilities, we may or may not use this mode. 548 */ 549 hw->fc.current_mode = hw->fc.requested_mode; 550 551 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 552 hw->fc.current_mode); 553 554 /* Call the necessary media_type subroutine to configure the link. */ 555 ret_val = hw->mac.ops.setup_physical_interface(hw); 556 if (ret_val) 557 return ret_val; 558 559 /* Initialize the flow control address, type, and PAUSE timer 560 * registers to their default values. This is done even if flow 561 * control is disabled, because it does not hurt anything to 562 * initialize these registers. 563 */ 564 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 565 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE); 566 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 567 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 568 569 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); 570 571 return igc_set_fc_watermarks_generic(hw); 572} 573 574/** 575 * igc_config_collision_dist_generic - Configure collision distance 576 * @hw: pointer to the HW structure 577 * 578 * Configures the collision distance to the default value and is used 579 * during link setup. 580 **/ 581static void igc_config_collision_dist_generic(struct igc_hw *hw) 582{ 583 u32 tctl; 584 585 DEBUGFUNC("igc_config_collision_dist_generic"); 586 587 tctl = IGC_READ_REG(hw, IGC_TCTL); 588 589 tctl &= ~IGC_TCTL_COLD; 590 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 591 592 IGC_WRITE_REG(hw, IGC_TCTL, tctl); 593 IGC_WRITE_FLUSH(hw); 594} 595 596/** 597 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks 598 * @hw: pointer to the HW structure 599 * 600 * Sets the flow control high/low threshold (watermark) registers. If 601 * flow control XON frame transmission is enabled, then set XON frame 602 * transmission as well. 603 **/ 604s32 igc_set_fc_watermarks_generic(struct igc_hw *hw) 605{ 606 u32 fcrtl = 0, fcrth = 0; 607 608 DEBUGFUNC("igc_set_fc_watermarks_generic"); 609 610 /* Set the flow control receive threshold registers. Normally, 611 * these registers will be set to a default threshold that may be 612 * adjusted later by the driver's runtime code. However, if the 613 * ability to transmit pause frames is not enabled, then these 614 * registers will be set to 0. 615 */ 616 if (hw->fc.current_mode & igc_fc_tx_pause) { 617 /* We need to set up the Receive Threshold high and low water 618 * marks as well as (optionally) enabling the transmission of 619 * XON frames. 620 */ 621 fcrtl = hw->fc.low_water; 622 if (hw->fc.send_xon) 623 fcrtl |= IGC_FCRTL_XONE; 624 625 fcrth = hw->fc.high_water; 626 } 627 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl); 628 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth); 629 630 return IGC_SUCCESS; 631} 632 633/** 634 * igc_force_mac_fc_generic - Force the MAC's flow control settings 635 * @hw: pointer to the HW structure 636 * 637 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 638 * device control register to reflect the adapter settings. TFCE and RFCE 639 * need to be explicitly set by software when a copper PHY is used because 640 * autonegotiation is managed by the PHY rather than the MAC. Software must 641 * also configure these bits when link is forced on a fiber connection. 642 **/ 643s32 igc_force_mac_fc_generic(struct igc_hw *hw) 644{ 645 u32 ctrl; 646 647 DEBUGFUNC("igc_force_mac_fc_generic"); 648 649 ctrl = IGC_READ_REG(hw, IGC_CTRL); 650 651 /* Because we didn't get link via the internal auto-negotiation 652 * mechanism (we either forced link or we got link via PHY 653 * auto-neg), we have to manually enable/disable transmit an 654 * receive flow control. 655 * 656 * The "Case" statement below enables/disable flow control 657 * according to the "hw->fc.current_mode" parameter. 658 * 659 * The possible values of the "fc" parameter are: 660 * 0: Flow control is completely disabled 661 * 1: Rx flow control is enabled (we can receive pause 662 * frames but not send pause frames). 663 * 2: Tx flow control is enabled (we can send pause frames 664 * frames but we do not receive pause frames). 665 * 3: Both Rx and Tx flow control (symmetric) is enabled. 666 * other: No other values should be possible at this point. 667 */ 668 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 669 670 switch (hw->fc.current_mode) { 671 case igc_fc_none: 672 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 673 break; 674 case igc_fc_rx_pause: 675 ctrl &= (~IGC_CTRL_TFCE); 676 ctrl |= IGC_CTRL_RFCE; 677 break; 678 case igc_fc_tx_pause: 679 ctrl &= (~IGC_CTRL_RFCE); 680 ctrl |= IGC_CTRL_TFCE; 681 break; 682 case igc_fc_full: 683 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 684 break; 685 default: 686 DEBUGOUT("Flow control param set incorrectly\n"); 687 return -IGC_ERR_CONFIG; 688 } 689 690 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 691 692 return IGC_SUCCESS; 693} 694 695/** 696 * igc_config_fc_after_link_up_generic - Configures flow control after link 697 * @hw: pointer to the HW structure 698 * 699 * Checks the status of auto-negotiation after link up to ensure that the 700 * speed and duplex were not forced. If the link needed to be forced, then 701 * flow control needs to be forced also. If auto-negotiation is enabled 702 * and did not fail, then we configure flow control based on our link 703 * partner. 704 **/ 705s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw) 706{ 707 struct igc_mac_info *mac = &hw->mac; 708 s32 ret_val = IGC_SUCCESS; 709 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 710 u16 speed, duplex; 711 712 DEBUGFUNC("igc_config_fc_after_link_up_generic"); 713 714 if (ret_val) { 715 DEBUGOUT("Error forcing flow control settings\n"); 716 return ret_val; 717 } 718 719 /* Check for the case where we have copper media and auto-neg is 720 * enabled. In this case, we need to check and see if Auto-Neg 721 * has completed, and if so, how the PHY and link partner has 722 * flow control configured. 723 */ 724 if (mac->autoneg) { 725 /* Read the MII Status Register and check to see if AutoNeg 726 * has completed. We read this twice because this reg has 727 * some "sticky" (latched) bits. 728 */ 729 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 730 if (ret_val) 731 return ret_val; 732 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 733 if (ret_val) 734 return ret_val; 735 736 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 737 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 738 return ret_val; 739 } 740 741 /* The AutoNeg process has completed, so we now need to 742 * read both the Auto Negotiation Advertisement 743 * Register (Address 4) and the Auto_Negotiation Base 744 * Page Ability Register (Address 5) to determine how 745 * flow control was negotiated. 746 */ 747 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 748 &mii_nway_adv_reg); 749 if (ret_val) 750 return ret_val; 751 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 752 &mii_nway_lp_ability_reg); 753 if (ret_val) 754 return ret_val; 755 756 /* Two bits in the Auto Negotiation Advertisement Register 757 * (Address 4) and two bits in the Auto Negotiation Base 758 * Page Ability Register (Address 5) determine flow control 759 * for both the PHY and the link partner. The following 760 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 761 * 1999, describes these PAUSE resolution bits and how flow 762 * control is determined based upon these settings. 763 * NOTE: DC = Don't Care 764 * 765 * LOCAL DEVICE | LINK PARTNER 766 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 767 *-------|---------|-------|---------|-------------------- 768 * 0 | 0 | DC | DC | igc_fc_none 769 * 0 | 1 | 0 | DC | igc_fc_none 770 * 0 | 1 | 1 | 0 | igc_fc_none 771 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 772 * 1 | 0 | 0 | DC | igc_fc_none 773 * 1 | DC | 1 | DC | igc_fc_full 774 * 1 | 1 | 0 | 0 | igc_fc_none 775 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 776 * 777 * Are both PAUSE bits set to 1? If so, this implies 778 * Symmetric Flow Control is enabled at both ends. The 779 * ASM_DIR bits are irrelevant per the spec. 780 * 781 * For Symmetric Flow Control: 782 * 783 * LOCAL DEVICE | LINK PARTNER 784 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 785 *-------|---------|-------|---------|-------------------- 786 * 1 | DC | 1 | DC | IGC_fc_full 787 * 788 */ 789 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 790 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 791 /* Now we need to check if the user selected Rx ONLY 792 * of pause frames. In this case, we had to advertise 793 * FULL flow control because we could not advertise Rx 794 * ONLY. Hence, we must now check to see if we need to 795 * turn OFF the TRANSMISSION of PAUSE frames. 796 */ 797 if (hw->fc.requested_mode == igc_fc_full) { 798 hw->fc.current_mode = igc_fc_full; 799 DEBUGOUT("Flow Control = FULL.\n"); 800 } else { 801 hw->fc.current_mode = igc_fc_rx_pause; 802 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 803 } 804 } 805 /* For receiving PAUSE frames ONLY. 806 * 807 * LOCAL DEVICE | LINK PARTNER 808 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 809 *-------|---------|-------|---------|-------------------- 810 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 811 */ 812 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 813 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 814 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 815 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 816 hw->fc.current_mode = igc_fc_tx_pause; 817 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 818 } 819 /* For transmitting PAUSE frames ONLY. 820 * 821 * LOCAL DEVICE | LINK PARTNER 822 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 823 *-------|---------|-------|---------|-------------------- 824 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 825 */ 826 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 827 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 828 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 829 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 830 hw->fc.current_mode = igc_fc_rx_pause; 831 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 832 } else { 833 /* Per the IEEE spec, at this point flow control 834 * should be disabled. 835 */ 836 hw->fc.current_mode = igc_fc_none; 837 DEBUGOUT("Flow Control = NONE.\n"); 838 } 839 840 /* Now we need to do one last check... If we auto- 841 * negotiated to HALF DUPLEX, flow control should not be 842 * enabled per IEEE 802.3 spec. 843 */ 844 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 845 if (ret_val) { 846 DEBUGOUT("Error getting link speed and duplex\n"); 847 return ret_val; 848 } 849 850 if (duplex == HALF_DUPLEX) 851 hw->fc.current_mode = igc_fc_none; 852 853 /* Now we call a subroutine to actually force the MAC 854 * controller to use the correct flow control settings. 855 */ 856 ret_val = igc_force_mac_fc_generic(hw); 857 if (ret_val) { 858 DEBUGOUT("Error forcing flow control settings\n"); 859 return ret_val; 860 } 861 } 862 863 return IGC_SUCCESS; 864} 865 866/** 867 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 868 * @hw: pointer to the HW structure 869 * @speed: stores the current speed 870 * @duplex: stores the current duplex 871 * 872 * Read the status register for the current speed/duplex and store the current 873 * speed and duplex for copper connections. 874 **/ 875s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed, 876 u16 *duplex) 877{ 878 u32 status; 879 880 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic"); 881 882 status = IGC_READ_REG(hw, IGC_STATUS); 883 if (status & IGC_STATUS_SPEED_1000) { 884 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 885 * and 2.5 Gbps link modes. An additional bit is used 886 * to differentiate between 1 Gbps and 2.5 Gbps. 887 */ 888 if ((hw->mac.type == igc_i225) && 889 (status & IGC_STATUS_SPEED_2500)) { 890 *speed = SPEED_2500; 891 DEBUGOUT("2500 Mbs, "); 892 } else { 893 *speed = SPEED_1000; 894 DEBUGOUT("1000 Mbs, "); 895 } 896 } else if (status & IGC_STATUS_SPEED_100) { 897 *speed = SPEED_100; 898 DEBUGOUT("100 Mbs, "); 899 } else { 900 *speed = SPEED_10; 901 DEBUGOUT("10 Mbs, "); 902 } 903 904 if (status & IGC_STATUS_FD) { 905 *duplex = FULL_DUPLEX; 906 DEBUGOUT("Full Duplex\n"); 907 } else { 908 *duplex = HALF_DUPLEX; 909 DEBUGOUT("Half Duplex\n"); 910 } 911 912 return IGC_SUCCESS; 913} 914 915/** 916 * igc_get_hw_semaphore_generic - Acquire hardware semaphore 917 * @hw: pointer to the HW structure 918 * 919 * Acquire the HW semaphore to access the PHY or NVM 920 **/ 921s32 igc_get_hw_semaphore_generic(struct igc_hw *hw) 922{ 923 u32 swsm; 924 s32 timeout = hw->nvm.word_size + 1; 925 s32 i = 0; 926 927 DEBUGFUNC("igc_get_hw_semaphore_generic"); 928 929 /* Get the SW semaphore */ 930 while (i < timeout) { 931 swsm = IGC_READ_REG(hw, IGC_SWSM); 932 if (!(swsm & IGC_SWSM_SMBI)) 933 break; 934 935 usec_delay(50); 936 i++; 937 } 938 939 if (i == timeout) { 940 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 941 return -IGC_ERR_NVM; 942 } 943 944 /* Get the FW semaphore. */ 945 for (i = 0; i < timeout; i++) { 946 swsm = IGC_READ_REG(hw, IGC_SWSM); 947 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 948 949 /* Semaphore acquired if bit latched */ 950 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 951 break; 952 953 usec_delay(50); 954 } 955 956 if (i == timeout) { 957 /* Release semaphores */ 958 igc_put_hw_semaphore_generic(hw); 959 DEBUGOUT("Driver can't access the NVM\n"); 960 return -IGC_ERR_NVM; 961 } 962 963 return IGC_SUCCESS; 964} 965 966/** 967 * igc_put_hw_semaphore_generic - Release hardware semaphore 968 * @hw: pointer to the HW structure 969 * 970 * Release hardware semaphore used to access the PHY or NVM 971 **/ 972void igc_put_hw_semaphore_generic(struct igc_hw *hw) 973{ 974 u32 swsm; 975 976 DEBUGFUNC("igc_put_hw_semaphore_generic"); 977 978 swsm = IGC_READ_REG(hw, IGC_SWSM); 979 980 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 981 982 IGC_WRITE_REG(hw, IGC_SWSM, swsm); 983} 984 985/** 986 * igc_get_auto_rd_done_generic - Check for auto read completion 987 * @hw: pointer to the HW structure 988 * 989 * Check EEPROM for Auto Read done bit. 990 **/ 991s32 igc_get_auto_rd_done_generic(struct igc_hw *hw) 992{ 993 s32 i = 0; 994 995 DEBUGFUNC("igc_get_auto_rd_done_generic"); 996 997 while (i < AUTO_READ_DONE_TIMEOUT) { 998 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) 999 break; 1000 msec_delay(1); 1001 i++; 1002 } 1003 1004 if (i == AUTO_READ_DONE_TIMEOUT) { 1005 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1006 return -IGC_ERR_RESET; 1007 } 1008 1009 return IGC_SUCCESS; 1010} 1011 1012/** 1013 * igc_disable_pcie_master_generic - Disables PCI-express master access 1014 * @hw: pointer to the HW structure 1015 * 1016 * Returns IGC_SUCCESS if successful, else returns -10 1017 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1018 * the master requests to be disabled. 1019 * 1020 * Disables PCI-Express master access and verifies there are no pending 1021 * requests. 1022 **/ 1023s32 igc_disable_pcie_master_generic(struct igc_hw *hw) 1024{ 1025 u32 ctrl; 1026 s32 timeout = MASTER_DISABLE_TIMEOUT; 1027 1028 DEBUGFUNC("igc_disable_pcie_master_generic"); 1029 1030 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1031 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 1032 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 1033 1034 while (timeout) { 1035 if (!(IGC_READ_REG(hw, IGC_STATUS) & 1036 IGC_STATUS_GIO_MASTER_ENABLE)) 1037 break; 1038 usec_delay(100); 1039 timeout--; 1040 } 1041 1042 if (!timeout) { 1043 DEBUGOUT("Master requests are pending.\n"); 1044 return -IGC_ERR_MASTER_REQUESTS_PENDING; 1045 } 1046 1047 return IGC_SUCCESS; 1048} 1049