1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31#include "if_igc.h" 32#include <sys/sbuf.h> 33#include <machine/_inttypes.h> 34 35#ifdef RSS 36#include <net/rss_config.h> 37#include <netinet/in_rss.h> 38#endif 39 40/********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last entry must be all 0s 45 * 46 * { Vendor ID, Device ID, String } 47 *********************************************************************/ 48 49static const pci_vendor_info_t igc_vendor_info_array[] = 50{ 51 /* Intel(R) PRO/1000 Network Connection - igc */ 52 PVID(0x8086, IGC_DEV_ID_I225_LM, "Intel(R) Ethernet Controller I225-LM"), 53 PVID(0x8086, IGC_DEV_ID_I225_V, "Intel(R) Ethernet Controller I225-V"), 54 PVID(0x8086, IGC_DEV_ID_I225_K, "Intel(R) Ethernet Controller I225-K"), 55 PVID(0x8086, IGC_DEV_ID_I225_I, "Intel(R) Ethernet Controller I225-I"), 56 PVID(0x8086, IGC_DEV_ID_I220_V, "Intel(R) Ethernet Controller I220-V"), 57 PVID(0x8086, IGC_DEV_ID_I225_K2, "Intel(R) Ethernet Controller I225-K(2)"), 58 PVID(0x8086, IGC_DEV_ID_I225_LMVP, "Intel(R) Ethernet Controller I225-LMvP(2)"), 59 PVID(0x8086, IGC_DEV_ID_I226_K, "Intel(R) Ethernet Controller I226-K"), 60 PVID(0x8086, IGC_DEV_ID_I226_LMVP, "Intel(R) Ethernet Controller I226-LMvP"), 61 PVID(0x8086, IGC_DEV_ID_I225_IT, "Intel(R) Ethernet Controller I225-IT(2)"), 62 PVID(0x8086, IGC_DEV_ID_I226_LM, "Intel(R) Ethernet Controller I226-LM"), 63 PVID(0x8086, IGC_DEV_ID_I226_V, "Intel(R) Ethernet Controller I226-V"), 64 PVID(0x8086, IGC_DEV_ID_I226_IT, "Intel(R) Ethernet Controller I226-IT"), 65 PVID(0x8086, IGC_DEV_ID_I221_V, "Intel(R) Ethernet Controller I221-V"), 66 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, "Intel(R) Ethernet Controller I226(blankNVM)"), 67 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, "Intel(R) Ethernet Controller I225(blankNVM)"), 68 /* required last entry */ 69 PVID_END 70}; 71 72/********************************************************************* 73 * Function prototypes 74 *********************************************************************/ 75static void *igc_register(device_t dev); 76static int igc_if_attach_pre(if_ctx_t ctx); 77static int igc_if_attach_post(if_ctx_t ctx); 78static int igc_if_detach(if_ctx_t ctx); 79static int igc_if_shutdown(if_ctx_t ctx); 80static int igc_if_suspend(if_ctx_t ctx); 81static int igc_if_resume(if_ctx_t ctx); 82 83static int igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 84static int igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 85static void igc_if_queues_free(if_ctx_t ctx); 86 87static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 88static void igc_if_init(if_ctx_t ctx); 89static void igc_if_stop(if_ctx_t ctx); 90static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 91static int igc_if_media_change(if_ctx_t ctx); 92static int igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 93static void igc_if_timer(if_ctx_t ctx, uint16_t qid); 94static void igc_if_watchdog_reset(if_ctx_t ctx); 95static bool igc_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 96 97static void igc_identify_hardware(if_ctx_t ctx); 98static int igc_allocate_pci_resources(if_ctx_t ctx); 99static void igc_free_pci_resources(if_ctx_t ctx); 100static void igc_reset(if_ctx_t ctx); 101static int igc_setup_interface(if_ctx_t ctx); 102static int igc_setup_msix(if_ctx_t ctx); 103 104static void igc_initialize_transmit_unit(if_ctx_t ctx); 105static void igc_initialize_receive_unit(if_ctx_t ctx); 106 107static void igc_if_intr_enable(if_ctx_t ctx); 108static void igc_if_intr_disable(if_ctx_t ctx); 109static int igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 110static int igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 111static void igc_if_multi_set(if_ctx_t ctx); 112static void igc_if_update_admin_status(if_ctx_t ctx); 113static void igc_if_debug(if_ctx_t ctx); 114static void igc_update_stats_counters(struct igc_adapter *); 115static void igc_add_hw_stats(struct igc_adapter *adapter); 116static int igc_if_set_promisc(if_ctx_t ctx, int flags); 117static void igc_setup_vlan_hw_support(if_ctx_t ctx); 118static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 119static void igc_print_nvm_info(struct igc_adapter *); 120static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 121static int igc_get_rs(SYSCTL_HANDLER_ARGS); 122static void igc_print_debug_info(struct igc_adapter *); 123static int igc_is_valid_ether_addr(u8 *); 124static int igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 125static void igc_add_int_delay_sysctl(struct igc_adapter *, const char *, 126 const char *, struct igc_int_delay_info *, int, int); 127/* Management and WOL Support */ 128static void igc_get_hw_control(struct igc_adapter *); 129static void igc_release_hw_control(struct igc_adapter *); 130static void igc_get_wakeup(if_ctx_t ctx); 131static void igc_enable_wakeup(if_ctx_t ctx); 132 133int igc_intr(void *arg); 134 135/* MSI-X handlers */ 136static int igc_if_msix_intr_assign(if_ctx_t, int); 137static int igc_msix_link(void *); 138static void igc_handle_link(void *context); 139 140static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 141static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 142 143static int igc_get_regs(SYSCTL_HANDLER_ARGS); 144 145static void igc_configure_queues(struct igc_adapter *adapter); 146 147 148/********************************************************************* 149 * FreeBSD Device Interface Entry Points 150 *********************************************************************/ 151static device_method_t igc_methods[] = { 152 /* Device interface */ 153 DEVMETHOD(device_register, igc_register), 154 DEVMETHOD(device_probe, iflib_device_probe), 155 DEVMETHOD(device_attach, iflib_device_attach), 156 DEVMETHOD(device_detach, iflib_device_detach), 157 DEVMETHOD(device_shutdown, iflib_device_shutdown), 158 DEVMETHOD(device_suspend, iflib_device_suspend), 159 DEVMETHOD(device_resume, iflib_device_resume), 160 DEVMETHOD_END 161}; 162 163static driver_t igc_driver = { 164 "igc", igc_methods, sizeof(struct igc_adapter), 165}; 166 167DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 168 169MODULE_DEPEND(igc, pci, 1, 1, 1); 170MODULE_DEPEND(igc, ether, 1, 1, 1); 171MODULE_DEPEND(igc, iflib, 1, 1, 1); 172 173IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 174 175static device_method_t igc_if_methods[] = { 176 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 177 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 178 DEVMETHOD(ifdi_detach, igc_if_detach), 179 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 180 DEVMETHOD(ifdi_suspend, igc_if_suspend), 181 DEVMETHOD(ifdi_resume, igc_if_resume), 182 DEVMETHOD(ifdi_init, igc_if_init), 183 DEVMETHOD(ifdi_stop, igc_if_stop), 184 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 185 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 186 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 187 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 188 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 189 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 190 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 191 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 192 DEVMETHOD(ifdi_media_status, igc_if_media_status), 193 DEVMETHOD(ifdi_media_change, igc_if_media_change), 194 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 195 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 196 DEVMETHOD(ifdi_timer, igc_if_timer), 197 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset), 198 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 199 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 200 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 201 DEVMETHOD(ifdi_debug, igc_if_debug), 202 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 203 DEVMETHOD_END 204}; 205 206static driver_t igc_if_driver = { 207 "igc_if", igc_if_methods, sizeof(struct igc_adapter) 208}; 209 210/********************************************************************* 211 * Tunable default values. 212 *********************************************************************/ 213 214#define IGC_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 215#define IGC_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 216 217#define MAX_INTS_PER_SEC 8000 218#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 219 220/* Allow common code without TSO */ 221#ifndef CSUM_TSO 222#define CSUM_TSO 0 223#endif 224 225static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 226 "igc driver parameters"); 227 228static int igc_disable_crc_stripping = 0; 229SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 230 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 231 232static int igc_tx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TIDV_VAL); 233static int igc_rx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RDTR_VAL); 234SYSCTL_INT(_hw_igc, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &igc_tx_int_delay_dflt, 235 0, "Default transmit interrupt delay in usecs"); 236SYSCTL_INT(_hw_igc, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &igc_rx_int_delay_dflt, 237 0, "Default receive interrupt delay in usecs"); 238 239static int igc_tx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TADV_VAL); 240static int igc_rx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RADV_VAL); 241SYSCTL_INT(_hw_igc, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 242 &igc_tx_abs_int_delay_dflt, 0, 243 "Default transmit interrupt delay limit in usecs"); 244SYSCTL_INT(_hw_igc, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 245 &igc_rx_abs_int_delay_dflt, 0, 246 "Default receive interrupt delay limit in usecs"); 247 248static int igc_smart_pwr_down = false; 249SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down, 250 0, "Set to true to leave smart power down enabled on newer adapters"); 251 252/* Controls whether promiscuous also shows bad packets */ 253static int igc_debug_sbp = true; 254SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 255 "Show bad packets in promiscuous mode"); 256 257/* Energy efficient ethernet - default to OFF */ 258static int igc_eee_setting = 1; 259SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 260 "Enable Energy Efficient Ethernet"); 261 262/* 263** Tuneable Interrupt rate 264*/ 265static int igc_max_interrupt_rate = 20000; 266SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 267 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 268 269extern struct if_txrx igc_txrx; 270 271static struct if_shared_ctx igc_sctx_init = { 272 .isc_magic = IFLIB_MAGIC, 273 .isc_q_align = PAGE_SIZE, 274 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 275 .isc_tx_maxsegsize = PAGE_SIZE, 276 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 277 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 278 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 279 .isc_rx_nsegments = 1, 280 .isc_rx_maxsegsize = MJUM9BYTES, 281 .isc_nfl = 1, 282 .isc_nrxqs = 1, 283 .isc_ntxqs = 1, 284 .isc_admin_intrcnt = 1, 285 .isc_vendor_info = igc_vendor_info_array, 286 .isc_driver_version = "1", 287 .isc_driver = &igc_if_driver, 288 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 289 290 .isc_nrxd_min = {IGC_MIN_RXD}, 291 .isc_ntxd_min = {IGC_MIN_TXD}, 292 .isc_nrxd_max = {IGC_MAX_RXD}, 293 .isc_ntxd_max = {IGC_MAX_TXD}, 294 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 295 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 296}; 297 298/***************************************************************** 299 * 300 * Dump Registers 301 * 302 ****************************************************************/ 303#define IGC_REGS_LEN 739 304 305static int igc_get_regs(SYSCTL_HANDLER_ARGS) 306{ 307 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 308 struct igc_hw *hw = &adapter->hw; 309 struct sbuf *sb; 310 u32 *regs_buff; 311 int rc; 312 313 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 314 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 315 316 rc = sysctl_wire_old_buffer(req, 0); 317 MPASS(rc == 0); 318 if (rc != 0) { 319 free(regs_buff, M_DEVBUF); 320 return (rc); 321 } 322 323 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 324 MPASS(sb != NULL); 325 if (sb == NULL) { 326 free(regs_buff, M_DEVBUF); 327 return (ENOMEM); 328 } 329 330 /* General Registers */ 331 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 332 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 333 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 334 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 335 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 336 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 337 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 338 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 339 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 340 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 341 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 342 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 343 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 344 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 345 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 346 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 347 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 348 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 349 350 sbuf_printf(sb, "General Registers\n"); 351 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 352 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 353 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 354 355 sbuf_printf(sb, "Interrupt Registers\n"); 356 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 357 358 sbuf_printf(sb, "RX Registers\n"); 359 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 360 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 361 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 362 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 363 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 364 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 365 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 366 367 sbuf_printf(sb, "TX Registers\n"); 368 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 369 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 370 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 371 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 372 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 373 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 374 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 375 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 376 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 377 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 378 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 379 380 free(regs_buff, M_DEVBUF); 381 382#ifdef DUMP_DESCS 383 { 384 if_softc_ctx_t scctx = adapter->shared; 385 struct rx_ring *rxr = &rx_que->rxr; 386 struct tx_ring *txr = &tx_que->txr; 387 int ntxd = scctx->isc_ntxd[0]; 388 int nrxd = scctx->isc_nrxd[0]; 389 int j; 390 391 for (j = 0; j < nrxd; j++) { 392 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 393 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 394 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 395 } 396 397 for (j = 0; j < min(ntxd, 256); j++) { 398 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 399 400 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 401 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 402 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & IGC_TXD_STAT_DD : 0); 403 404 } 405 } 406#endif 407 408 rc = sbuf_finish(sb); 409 sbuf_delete(sb); 410 return(rc); 411} 412 413static void * 414igc_register(device_t dev) 415{ 416 return (&igc_sctx_init); 417} 418 419static int 420igc_set_num_queues(if_ctx_t ctx) 421{ 422 int maxqueues; 423 424 maxqueues = 4; 425 426 return (maxqueues); 427} 428 429#define IGC_CAPS \ 430 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 431 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \ 432 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 433 434/********************************************************************* 435 * Device initialization routine 436 * 437 * The attach entry point is called when the driver is being loaded. 438 * This routine identifies the type of hardware, allocates all resources 439 * and initializes the hardware. 440 * 441 * return 0 on success, positive on failure 442 *********************************************************************/ 443static int 444igc_if_attach_pre(if_ctx_t ctx) 445{ 446 struct igc_adapter *adapter; 447 if_softc_ctx_t scctx; 448 device_t dev; 449 struct igc_hw *hw; 450 int error = 0; 451 452 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 453 dev = iflib_get_dev(ctx); 454 adapter = iflib_get_softc(ctx); 455 456 adapter->ctx = adapter->osdep.ctx = ctx; 457 adapter->dev = adapter->osdep.dev = dev; 458 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 459 adapter->media = iflib_get_media(ctx); 460 hw = &adapter->hw; 461 462 /* SYSCTL stuff */ 463 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 464 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 465 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 466 adapter, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 467 468 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 469 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 470 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 471 adapter, 0, igc_sysctl_debug_info, "I", "Debug Information"); 472 473 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 474 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 475 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 476 adapter, 0, igc_set_flowcntl, "I", "Flow Control"); 477 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 480 OID_AUTO, "reg_dump", 481 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 482 igc_get_regs, "A", "Dump Registers"); 483 484 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 485 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 486 OID_AUTO, "rs_dump", 487 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 488 igc_get_rs, "I", "Dump RS indexes"); 489 490 /* Determine hardware and mac info */ 491 igc_identify_hardware(ctx); 492 493 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 494 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 495 if (bootverbose) 496 device_printf(dev, "attach_pre capping queues at %d\n", 497 scctx->isc_ntxqsets_max); 498 499 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 500 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 501 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 502 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 503 scctx->isc_txrx = &igc_txrx; 504 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 505 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 506 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 507 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 508 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 509 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 510 511 /* 512 ** Some new devices, as with ixgbe, now may 513 ** use a different BAR, so we need to keep 514 ** track of which is used. 515 */ 516 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 517 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 518 scctx->isc_msix_bar += 4; 519 520 /* Setup PCI resources */ 521 if (igc_allocate_pci_resources(ctx)) { 522 device_printf(dev, "Allocation of PCI resources failed\n"); 523 error = ENXIO; 524 goto err_pci; 525 } 526 527 /* Do Shared Code initialization */ 528 error = igc_setup_init_funcs(hw, true); 529 if (error) { 530 device_printf(dev, "Setup of Shared code failed, error %d\n", 531 error); 532 error = ENXIO; 533 goto err_pci; 534 } 535 536 igc_setup_msix(ctx); 537 igc_get_bus_info(hw); 538 539 /* Set up some sysctls for the tunable interrupt delays */ 540 igc_add_int_delay_sysctl(adapter, "rx_int_delay", 541 "receive interrupt delay in usecs", &adapter->rx_int_delay, 542 IGC_REGISTER(hw, IGC_RDTR), igc_rx_int_delay_dflt); 543 igc_add_int_delay_sysctl(adapter, "tx_int_delay", 544 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 545 IGC_REGISTER(hw, IGC_TIDV), igc_tx_int_delay_dflt); 546 igc_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 547 "receive interrupt delay limit in usecs", 548 &adapter->rx_abs_int_delay, 549 IGC_REGISTER(hw, IGC_RADV), 550 igc_rx_abs_int_delay_dflt); 551 igc_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 552 "transmit interrupt delay limit in usecs", 553 &adapter->tx_abs_int_delay, 554 IGC_REGISTER(hw, IGC_TADV), 555 igc_tx_abs_int_delay_dflt); 556 igc_add_int_delay_sysctl(adapter, "itr", 557 "interrupt delay limit in usecs/4", 558 &adapter->tx_itr, 559 IGC_REGISTER(hw, IGC_ITR), 560 DEFAULT_ITR); 561 562 hw->mac.autoneg = DO_AUTO_NEG; 563 hw->phy.autoneg_wait_to_complete = false; 564 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 565 566 /* Copper options */ 567 if (hw->phy.media_type == igc_media_type_copper) { 568 hw->phy.mdix = AUTO_ALL_MODES; 569 } 570 571 /* 572 * Set the frame limits assuming 573 * standard ethernet sized frames. 574 */ 575 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 576 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 577 578 /* Allocate multicast array memory. */ 579 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 580 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 581 if (adapter->mta == NULL) { 582 device_printf(dev, "Can not allocate multicast setup array\n"); 583 error = ENOMEM; 584 goto err_late; 585 } 586 587 /* Check SOL/IDER usage */ 588 if (igc_check_reset_block(hw)) 589 device_printf(dev, "PHY reset is blocked" 590 " due to SOL/IDER session.\n"); 591 592 /* Sysctl for setting Energy Efficient Ethernet */ 593 adapter->hw.dev_spec._i225.eee_disable = igc_eee_setting; 594 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 595 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 596 OID_AUTO, "eee_control", 597 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 598 adapter, 0, igc_sysctl_eee, "I", 599 "Disable Energy Efficient Ethernet"); 600 601 /* 602 ** Start from a known state, this is 603 ** important in reading the nvm and 604 ** mac from that. 605 */ 606 igc_reset_hw(hw); 607 608 /* Make sure we have a good EEPROM before we read from it */ 609 if (igc_validate_nvm_checksum(hw) < 0) { 610 /* 611 ** Some PCI-E parts fail the first check due to 612 ** the link being in sleep state, call it again, 613 ** if it fails a second time its a real issue. 614 */ 615 if (igc_validate_nvm_checksum(hw) < 0) { 616 device_printf(dev, 617 "The EEPROM Checksum Is Not Valid\n"); 618 error = EIO; 619 goto err_late; 620 } 621 } 622 623 /* Copy the permanent MAC address out of the EEPROM */ 624 if (igc_read_mac_addr(hw) < 0) { 625 device_printf(dev, "EEPROM read error while reading MAC" 626 " address\n"); 627 error = EIO; 628 goto err_late; 629 } 630 631 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 632 device_printf(dev, "Invalid MAC address\n"); 633 error = EIO; 634 goto err_late; 635 } 636 637 /* 638 * Get Wake-on-Lan and Management info for later use 639 */ 640 igc_get_wakeup(ctx); 641 642 /* Enable only WOL MAGIC by default */ 643 scctx->isc_capenable &= ~IFCAP_WOL; 644 if (adapter->wol != 0) 645 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 646 647 iflib_set_mac(ctx, hw->mac.addr); 648 649 return (0); 650 651err_late: 652 igc_release_hw_control(adapter); 653err_pci: 654 igc_free_pci_resources(ctx); 655 free(adapter->mta, M_DEVBUF); 656 657 return (error); 658} 659 660static int 661igc_if_attach_post(if_ctx_t ctx) 662{ 663 struct igc_adapter *adapter = iflib_get_softc(ctx); 664 struct igc_hw *hw = &adapter->hw; 665 int error = 0; 666 667 /* Setup OS specific network interface */ 668 error = igc_setup_interface(ctx); 669 if (error != 0) { 670 goto err_late; 671 } 672 673 igc_reset(ctx); 674 675 /* Initialize statistics */ 676 igc_update_stats_counters(adapter); 677 hw->mac.get_link_status = true; 678 igc_if_update_admin_status(ctx); 679 igc_add_hw_stats(adapter); 680 681 /* the driver can now take control from firmware */ 682 igc_get_hw_control(adapter); 683 684 INIT_DEBUGOUT("igc_if_attach_post: end"); 685 686 return (error); 687 688err_late: 689 igc_release_hw_control(adapter); 690 igc_free_pci_resources(ctx); 691 igc_if_queues_free(ctx); 692 free(adapter->mta, M_DEVBUF); 693 694 return (error); 695} 696 697/********************************************************************* 698 * Device removal routine 699 * 700 * The detach entry point is called when the driver is being removed. 701 * This routine stops the adapter and deallocates all the resources 702 * that were allocated for driver operation. 703 * 704 * return 0 on success, positive on failure 705 *********************************************************************/ 706static int 707igc_if_detach(if_ctx_t ctx) 708{ 709 struct igc_adapter *adapter = iflib_get_softc(ctx); 710 711 INIT_DEBUGOUT("igc_if_detach: begin"); 712 713 igc_phy_hw_reset(&adapter->hw); 714 715 igc_release_hw_control(adapter); 716 igc_free_pci_resources(ctx); 717 718 return (0); 719} 720 721/********************************************************************* 722 * 723 * Shutdown entry point 724 * 725 **********************************************************************/ 726 727static int 728igc_if_shutdown(if_ctx_t ctx) 729{ 730 return igc_if_suspend(ctx); 731} 732 733/* 734 * Suspend/resume device methods. 735 */ 736static int 737igc_if_suspend(if_ctx_t ctx) 738{ 739 struct igc_adapter *adapter = iflib_get_softc(ctx); 740 741 igc_release_hw_control(adapter); 742 igc_enable_wakeup(ctx); 743 return (0); 744} 745 746static int 747igc_if_resume(if_ctx_t ctx) 748{ 749 igc_if_init(ctx); 750 751 return(0); 752} 753 754static int 755igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 756{ 757 int max_frame_size; 758 struct igc_adapter *adapter = iflib_get_softc(ctx); 759 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 760 761 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 762 763 /* 9K Jumbo Frame size */ 764 max_frame_size = 9234; 765 766 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 767 return (EINVAL); 768 } 769 770 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 771 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 772 return (0); 773} 774 775/********************************************************************* 776 * Init entry point 777 * 778 * This routine is used in two ways. It is used by the stack as 779 * init entry point in network interface structure. It is also used 780 * by the driver as a hw/sw initialization routine to get to a 781 * consistent state. 782 * 783 **********************************************************************/ 784static void 785igc_if_init(if_ctx_t ctx) 786{ 787 struct igc_adapter *adapter = iflib_get_softc(ctx); 788 if_softc_ctx_t scctx = adapter->shared; 789 if_t ifp = iflib_get_ifp(ctx); 790 struct igc_tx_queue *tx_que; 791 int i; 792 793 INIT_DEBUGOUT("igc_if_init: begin"); 794 795 /* Get the latest mac address, User can use a LAA */ 796 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 797 ETHER_ADDR_LEN); 798 799 /* Put the address into the Receive Address Array */ 800 igc_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 801 802 /* Initialize the hardware */ 803 igc_reset(ctx); 804 igc_if_update_admin_status(ctx); 805 806 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 807 struct tx_ring *txr = &tx_que->txr; 808 809 txr->tx_rs_cidx = txr->tx_rs_pidx; 810 811 /* Initialize the last processed descriptor to be the end of 812 * the ring, rather than the start, so that we avoid an 813 * off-by-one error when calculating how many descriptors are 814 * done in the credits_update function. 815 */ 816 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 817 } 818 819 /* Setup VLAN support, basic and offload if available */ 820 IGC_WRITE_REG(&adapter->hw, IGC_VET, ETHERTYPE_VLAN); 821 822 /* Prepare transmit descriptors and buffers */ 823 igc_initialize_transmit_unit(ctx); 824 825 /* Setup Multicast table */ 826 igc_if_multi_set(ctx); 827 828 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 829 igc_initialize_receive_unit(ctx); 830 831 /* Set up VLAN support */ 832 igc_setup_vlan_hw_support(ctx); 833 834 /* Don't lose promiscuous settings */ 835 igc_if_set_promisc(ctx, if_getflags(ifp)); 836 igc_clear_hw_cntrs_base_generic(&adapter->hw); 837 838 if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 839 igc_configure_queues(adapter); 840 841 /* this clears any pending interrupts */ 842 IGC_READ_REG(&adapter->hw, IGC_ICR); 843 IGC_WRITE_REG(&adapter->hw, IGC_ICS, IGC_ICS_LSC); 844 845 /* the driver can now take control from firmware */ 846 igc_get_hw_control(adapter); 847 848 /* Set Energy Efficient Ethernet */ 849 igc_set_eee_i225(&adapter->hw, true, true, true); 850} 851 852/********************************************************************* 853 * 854 * Fast Legacy/MSI Combined Interrupt Service routine 855 * 856 *********************************************************************/ 857int 858igc_intr(void *arg) 859{ 860 struct igc_adapter *adapter = arg; 861 if_ctx_t ctx = adapter->ctx; 862 u32 reg_icr; 863 864 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 865 866 /* Hot eject? */ 867 if (reg_icr == 0xffffffff) 868 return FILTER_STRAY; 869 870 /* Definitely not our interrupt. */ 871 if (reg_icr == 0x0) 872 return FILTER_STRAY; 873 874 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 875 return FILTER_STRAY; 876 877 /* 878 * Only MSI-X interrupts have one-shot behavior by taking advantage 879 * of the EIAC register. Thus, explicitly disable interrupts. This 880 * also works around the MSI message reordering errata on certain 881 * systems. 882 */ 883 IFDI_INTR_DISABLE(ctx); 884 885 /* Link status change */ 886 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 887 igc_handle_link(ctx); 888 889 if (reg_icr & IGC_ICR_RXO) 890 adapter->rx_overruns++; 891 892 return (FILTER_SCHEDULE_THREAD); 893} 894 895static int 896igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 897{ 898 struct igc_adapter *adapter = iflib_get_softc(ctx); 899 struct igc_rx_queue *rxq = &adapter->rx_queues[rxqid]; 900 901 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, rxq->eims); 902 return (0); 903} 904 905static int 906igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 907{ 908 struct igc_adapter *adapter = iflib_get_softc(ctx); 909 struct igc_tx_queue *txq = &adapter->tx_queues[txqid]; 910 911 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, txq->eims); 912 return (0); 913} 914 915/********************************************************************* 916 * 917 * MSI-X RX Interrupt Service routine 918 * 919 **********************************************************************/ 920static int 921igc_msix_que(void *arg) 922{ 923 struct igc_rx_queue *que = arg; 924 925 ++que->irqs; 926 927 return (FILTER_SCHEDULE_THREAD); 928} 929 930/********************************************************************* 931 * 932 * MSI-X Link Fast Interrupt Service routine 933 * 934 **********************************************************************/ 935static int 936igc_msix_link(void *arg) 937{ 938 struct igc_adapter *adapter = arg; 939 u32 reg_icr; 940 941 ++adapter->link_irq; 942 MPASS(adapter->hw.back != NULL); 943 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 944 945 if (reg_icr & IGC_ICR_RXO) 946 adapter->rx_overruns++; 947 948 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 949 igc_handle_link(adapter->ctx); 950 } 951 952 IGC_WRITE_REG(&adapter->hw, IGC_IMS, IGC_IMS_LSC); 953 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, adapter->link_mask); 954 955 return (FILTER_HANDLED); 956} 957 958static void 959igc_handle_link(void *context) 960{ 961 if_ctx_t ctx = context; 962 struct igc_adapter *adapter = iflib_get_softc(ctx); 963 964 adapter->hw.mac.get_link_status = true; 965 iflib_admin_intr_deferred(ctx); 966} 967 968/********************************************************************* 969 * 970 * Media Ioctl callback 971 * 972 * This routine is called whenever the user queries the status of 973 * the interface using ifconfig. 974 * 975 **********************************************************************/ 976static void 977igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 978{ 979 struct igc_adapter *adapter = iflib_get_softc(ctx); 980 981 INIT_DEBUGOUT("igc_if_media_status: begin"); 982 983 iflib_admin_intr_deferred(ctx); 984 985 ifmr->ifm_status = IFM_AVALID; 986 ifmr->ifm_active = IFM_ETHER; 987 988 if (!adapter->link_active) { 989 return; 990 } 991 992 ifmr->ifm_status |= IFM_ACTIVE; 993 994 switch (adapter->link_speed) { 995 case 10: 996 ifmr->ifm_active |= IFM_10_T; 997 break; 998 case 100: 999 ifmr->ifm_active |= IFM_100_TX; 1000 break; 1001 case 1000: 1002 ifmr->ifm_active |= IFM_1000_T; 1003 break; 1004 case 2500: 1005 ifmr->ifm_active |= IFM_2500_T; 1006 break; 1007 } 1008 1009 if (adapter->link_duplex == FULL_DUPLEX) 1010 ifmr->ifm_active |= IFM_FDX; 1011 else 1012 ifmr->ifm_active |= IFM_HDX; 1013} 1014 1015/********************************************************************* 1016 * 1017 * Media Ioctl callback 1018 * 1019 * This routine is called when the user changes speed/duplex using 1020 * media/mediopt option with ifconfig. 1021 * 1022 **********************************************************************/ 1023static int 1024igc_if_media_change(if_ctx_t ctx) 1025{ 1026 struct igc_adapter *adapter = iflib_get_softc(ctx); 1027 struct ifmedia *ifm = iflib_get_media(ctx); 1028 1029 INIT_DEBUGOUT("igc_if_media_change: begin"); 1030 1031 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1032 return (EINVAL); 1033 1034 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1035 1036 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1037 case IFM_AUTO: 1038 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1039 break; 1040 case IFM_2500_T: 1041 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1042 break; 1043 case IFM_1000_T: 1044 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1045 break; 1046 case IFM_100_TX: 1047 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1048 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1049 else 1050 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1051 break; 1052 case IFM_10_T: 1053 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1054 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1055 else 1056 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1057 break; 1058 default: 1059 device_printf(adapter->dev, "Unsupported media type\n"); 1060 } 1061 1062 igc_if_init(ctx); 1063 1064 return (0); 1065} 1066 1067static int 1068igc_if_set_promisc(if_ctx_t ctx, int flags) 1069{ 1070 struct igc_adapter *adapter = iflib_get_softc(ctx); 1071 if_t ifp = iflib_get_ifp(ctx); 1072 u32 reg_rctl; 1073 int mcnt = 0; 1074 1075 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1076 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1077 if (flags & IFF_ALLMULTI) 1078 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1079 else 1080 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1081 1082 /* Don't disable if in MAX groups */ 1083 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1084 reg_rctl &= (~IGC_RCTL_MPE); 1085 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1086 1087 if (flags & IFF_PROMISC) { 1088 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1089 /* Turn this on if you want to see bad packets */ 1090 if (igc_debug_sbp) 1091 reg_rctl |= IGC_RCTL_SBP; 1092 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1093 } else if (flags & IFF_ALLMULTI) { 1094 reg_rctl |= IGC_RCTL_MPE; 1095 reg_rctl &= ~IGC_RCTL_UPE; 1096 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1097 } 1098 return (0); 1099} 1100 1101static u_int 1102igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1103{ 1104 u8 *mta = arg; 1105 1106 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1107 return (0); 1108 1109 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1110 1111 return (1); 1112} 1113 1114/********************************************************************* 1115 * Multicast Update 1116 * 1117 * This routine is called whenever multicast address list is updated. 1118 * 1119 **********************************************************************/ 1120 1121static void 1122igc_if_multi_set(if_ctx_t ctx) 1123{ 1124 struct igc_adapter *adapter = iflib_get_softc(ctx); 1125 if_t ifp = iflib_get_ifp(ctx); 1126 u8 *mta; /* Multicast array memory */ 1127 u32 reg_rctl = 0; 1128 int mcnt = 0; 1129 1130 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1131 1132 mta = adapter->mta; 1133 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1134 1135 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1136 1137 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1138 1139 if (if_getflags(ifp) & IFF_PROMISC) { 1140 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1141 /* Turn this on if you want to see bad packets */ 1142 if (igc_debug_sbp) 1143 reg_rctl |= IGC_RCTL_SBP; 1144 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1145 if_getflags(ifp) & IFF_ALLMULTI) { 1146 reg_rctl |= IGC_RCTL_MPE; 1147 reg_rctl &= ~IGC_RCTL_UPE; 1148 } else 1149 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1150 1151 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1152 igc_update_mc_addr_list(&adapter->hw, mta, mcnt); 1153 1154 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1155} 1156 1157/********************************************************************* 1158 * Timer routine 1159 * 1160 * This routine schedules igc_if_update_admin_status() to check for 1161 * link status and to gather statistics as well as to perform some 1162 * controller-specific hardware patting. 1163 * 1164 **********************************************************************/ 1165static void 1166igc_if_timer(if_ctx_t ctx, uint16_t qid) 1167{ 1168 1169 if (qid != 0) 1170 return; 1171 1172 iflib_admin_intr_deferred(ctx); 1173} 1174 1175static void 1176igc_if_update_admin_status(if_ctx_t ctx) 1177{ 1178 struct igc_adapter *adapter = iflib_get_softc(ctx); 1179 struct igc_hw *hw = &adapter->hw; 1180 device_t dev = iflib_get_dev(ctx); 1181 u32 link_check, thstat, ctrl; 1182 1183 link_check = thstat = ctrl = 0; 1184 /* Get the cached link value or read phy for real */ 1185 switch (hw->phy.media_type) { 1186 case igc_media_type_copper: 1187 if (hw->mac.get_link_status == true) { 1188 /* Do the work to read phy */ 1189 igc_check_for_link(hw); 1190 link_check = !hw->mac.get_link_status; 1191 } else 1192 link_check = true; 1193 break; 1194 case igc_media_type_unknown: 1195 igc_check_for_link(hw); 1196 link_check = !hw->mac.get_link_status; 1197 /* FALLTHROUGH */ 1198 default: 1199 break; 1200 } 1201 1202 /* Now check for a transition */ 1203 if (link_check && (adapter->link_active == 0)) { 1204 igc_get_speed_and_duplex(hw, &adapter->link_speed, 1205 &adapter->link_duplex); 1206 if (bootverbose) 1207 device_printf(dev, "Link is up %d Mbps %s\n", 1208 adapter->link_speed, 1209 ((adapter->link_duplex == FULL_DUPLEX) ? 1210 "Full Duplex" : "Half Duplex")); 1211 adapter->link_active = 1; 1212 iflib_link_state_change(ctx, LINK_STATE_UP, 1213 IF_Mbps(adapter->link_speed)); 1214 } else if (!link_check && (adapter->link_active == 1)) { 1215 adapter->link_speed = 0; 1216 adapter->link_duplex = 0; 1217 adapter->link_active = 0; 1218 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1219 } 1220 igc_update_stats_counters(adapter); 1221} 1222 1223static void 1224igc_if_watchdog_reset(if_ctx_t ctx) 1225{ 1226 struct igc_adapter *adapter = iflib_get_softc(ctx); 1227 1228 /* 1229 * Just count the event; iflib(4) will already trigger a 1230 * sufficient reset of the controller. 1231 */ 1232 adapter->watchdog_events++; 1233} 1234 1235/********************************************************************* 1236 * 1237 * This routine disables all traffic on the adapter by issuing a 1238 * global reset on the MAC. 1239 * 1240 **********************************************************************/ 1241static void 1242igc_if_stop(if_ctx_t ctx) 1243{ 1244 struct igc_adapter *adapter = iflib_get_softc(ctx); 1245 1246 INIT_DEBUGOUT("igc_if_stop: begin"); 1247 1248 igc_reset_hw(&adapter->hw); 1249 IGC_WRITE_REG(&adapter->hw, IGC_WUC, 0); 1250} 1251 1252/********************************************************************* 1253 * 1254 * Determine hardware revision. 1255 * 1256 **********************************************************************/ 1257static void 1258igc_identify_hardware(if_ctx_t ctx) 1259{ 1260 device_t dev = iflib_get_dev(ctx); 1261 struct igc_adapter *adapter = iflib_get_softc(ctx); 1262 1263 /* Make sure our PCI config space has the necessary stuff set */ 1264 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1265 1266 /* Save off the information about this board */ 1267 adapter->hw.vendor_id = pci_get_vendor(dev); 1268 adapter->hw.device_id = pci_get_device(dev); 1269 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1270 adapter->hw.subsystem_vendor_id = 1271 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1272 adapter->hw.subsystem_device_id = 1273 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1274 1275 /* Do Shared Code Init and Setup */ 1276 if (igc_set_mac_type(&adapter->hw)) { 1277 device_printf(dev, "Setup init failure\n"); 1278 return; 1279 } 1280} 1281 1282static int 1283igc_allocate_pci_resources(if_ctx_t ctx) 1284{ 1285 struct igc_adapter *adapter = iflib_get_softc(ctx); 1286 device_t dev = iflib_get_dev(ctx); 1287 int rid; 1288 1289 rid = PCIR_BAR(0); 1290 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1291 &rid, RF_ACTIVE); 1292 if (adapter->memory == NULL) { 1293 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1294 return (ENXIO); 1295 } 1296 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1297 adapter->osdep.mem_bus_space_handle = 1298 rman_get_bushandle(adapter->memory); 1299 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1300 1301 adapter->hw.back = &adapter->osdep; 1302 1303 return (0); 1304} 1305 1306/********************************************************************* 1307 * 1308 * Set up the MSI-X Interrupt handlers 1309 * 1310 **********************************************************************/ 1311static int 1312igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1313{ 1314 struct igc_adapter *adapter = iflib_get_softc(ctx); 1315 struct igc_rx_queue *rx_que = adapter->rx_queues; 1316 struct igc_tx_queue *tx_que = adapter->tx_queues; 1317 int error, rid, i, vector = 0, rx_vectors; 1318 char buf[16]; 1319 1320 /* First set up ring resources */ 1321 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1322 rid = vector + 1; 1323 snprintf(buf, sizeof(buf), "rxq%d", i); 1324 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1325 if (error) { 1326 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1327 adapter->rx_num_queues = i + 1; 1328 goto fail; 1329 } 1330 1331 rx_que->msix = vector; 1332 1333 /* 1334 * Set the bit to enable interrupt 1335 * in IGC_IMS -- bits 20 and 21 1336 * are for RX0 and RX1, note this has 1337 * NOTHING to do with the MSI-X vector 1338 */ 1339 rx_que->eims = 1 << vector; 1340 } 1341 rx_vectors = vector; 1342 1343 vector = 0; 1344 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1345 snprintf(buf, sizeof(buf), "txq%d", i); 1346 tx_que = &adapter->tx_queues[i]; 1347 iflib_softirq_alloc_generic(ctx, 1348 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1349 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1350 1351 tx_que->msix = (vector % adapter->rx_num_queues); 1352 1353 /* 1354 * Set the bit to enable interrupt 1355 * in IGC_IMS -- bits 22 and 23 1356 * are for TX0 and TX1, note this has 1357 * NOTHING to do with the MSI-X vector 1358 */ 1359 tx_que->eims = 1 << i; 1360 } 1361 1362 /* Link interrupt */ 1363 rid = rx_vectors + 1; 1364 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, igc_msix_link, adapter, 0, "aq"); 1365 1366 if (error) { 1367 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1368 goto fail; 1369 } 1370 adapter->linkvec = rx_vectors; 1371 return (0); 1372fail: 1373 iflib_irq_free(ctx, &adapter->irq); 1374 rx_que = adapter->rx_queues; 1375 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1376 iflib_irq_free(ctx, &rx_que->que_irq); 1377 return (error); 1378} 1379 1380static void 1381igc_configure_queues(struct igc_adapter *adapter) 1382{ 1383 struct igc_hw *hw = &adapter->hw; 1384 struct igc_rx_queue *rx_que; 1385 struct igc_tx_queue *tx_que; 1386 u32 ivar = 0, newitr = 0; 1387 1388 /* First turn on RSS capability */ 1389 IGC_WRITE_REG(hw, IGC_GPIE, 1390 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1391 IGC_GPIE_NSICR); 1392 1393 /* Turn on MSI-X */ 1394 /* RX entries */ 1395 for (int i = 0; i < adapter->rx_num_queues; i++) { 1396 u32 index = i >> 1; 1397 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1398 rx_que = &adapter->rx_queues[i]; 1399 if (i & 1) { 1400 ivar &= 0xFF00FFFF; 1401 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1402 } else { 1403 ivar &= 0xFFFFFF00; 1404 ivar |= rx_que->msix | IGC_IVAR_VALID; 1405 } 1406 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1407 } 1408 /* TX entries */ 1409 for (int i = 0; i < adapter->tx_num_queues; i++) { 1410 u32 index = i >> 1; 1411 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1412 tx_que = &adapter->tx_queues[i]; 1413 if (i & 1) { 1414 ivar &= 0x00FFFFFF; 1415 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1416 } else { 1417 ivar &= 0xFFFF00FF; 1418 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1419 } 1420 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1421 adapter->que_mask |= tx_que->eims; 1422 } 1423 1424 /* And for the link interrupt */ 1425 ivar = (adapter->linkvec | IGC_IVAR_VALID) << 8; 1426 adapter->link_mask = 1 << adapter->linkvec; 1427 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1428 1429 /* Set the starting interrupt rate */ 1430 if (igc_max_interrupt_rate > 0) 1431 newitr = (4000000 / igc_max_interrupt_rate) & 0x7FFC; 1432 1433 newitr |= IGC_EITR_CNT_IGNR; 1434 1435 for (int i = 0; i < adapter->rx_num_queues; i++) { 1436 rx_que = &adapter->rx_queues[i]; 1437 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); 1438 } 1439 1440 return; 1441} 1442 1443static void 1444igc_free_pci_resources(if_ctx_t ctx) 1445{ 1446 struct igc_adapter *adapter = iflib_get_softc(ctx); 1447 struct igc_rx_queue *que = adapter->rx_queues; 1448 device_t dev = iflib_get_dev(ctx); 1449 1450 /* Release all MSI-X queue resources */ 1451 if (adapter->intr_type == IFLIB_INTR_MSIX) 1452 iflib_irq_free(ctx, &adapter->irq); 1453 1454 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 1455 iflib_irq_free(ctx, &que->que_irq); 1456 } 1457 1458 if (adapter->memory != NULL) { 1459 bus_release_resource(dev, SYS_RES_MEMORY, 1460 rman_get_rid(adapter->memory), adapter->memory); 1461 adapter->memory = NULL; 1462 } 1463 1464 if (adapter->flash != NULL) { 1465 bus_release_resource(dev, SYS_RES_MEMORY, 1466 rman_get_rid(adapter->flash), adapter->flash); 1467 adapter->flash = NULL; 1468 } 1469 1470 if (adapter->ioport != NULL) { 1471 bus_release_resource(dev, SYS_RES_IOPORT, 1472 rman_get_rid(adapter->ioport), adapter->ioport); 1473 adapter->ioport = NULL; 1474 } 1475} 1476 1477/* Set up MSI or MSI-X */ 1478static int 1479igc_setup_msix(if_ctx_t ctx) 1480{ 1481 return (0); 1482} 1483 1484/********************************************************************* 1485 * 1486 * Initialize the DMA Coalescing feature 1487 * 1488 **********************************************************************/ 1489static void 1490igc_init_dmac(struct igc_adapter *adapter, u32 pba) 1491{ 1492 device_t dev = adapter->dev; 1493 struct igc_hw *hw = &adapter->hw; 1494 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 1495 u16 hwm; 1496 u16 max_frame_size; 1497 int status; 1498 1499 max_frame_size = adapter->shared->isc_max_frame_size; 1500 1501 if (adapter->dmac == 0) { /* Disabling it */ 1502 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1503 return; 1504 } else 1505 device_printf(dev, "DMA Coalescing enabled\n"); 1506 1507 /* Set starting threshold */ 1508 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 1509 1510 hwm = 64 * pba - max_frame_size / 16; 1511 if (hwm < 64 * (pba - 6)) 1512 hwm = 64 * (pba - 6); 1513 reg = IGC_READ_REG(hw, IGC_FCRTC); 1514 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 1515 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 1516 & IGC_FCRTC_RTH_COAL_MASK); 1517 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 1518 1519 dmac = pba - max_frame_size / 512; 1520 if (dmac < pba - 10) 1521 dmac = pba - 10; 1522 reg = IGC_READ_REG(hw, IGC_DMACR); 1523 reg &= ~IGC_DMACR_DMACTHR_MASK; 1524 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 1525 & IGC_DMACR_DMACTHR_MASK); 1526 1527 /* transition to L0x or L1 if available..*/ 1528 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 1529 1530 /* Check if status is 2.5Gb backplane connection 1531 * before configuration of watchdog timer, which is 1532 * in msec values in 12.8usec intervals 1533 * watchdog timer= msec values in 32usec intervals 1534 * for non 2.5Gb connection 1535 */ 1536 status = IGC_READ_REG(hw, IGC_STATUS); 1537 if ((status & IGC_STATUS_2P5_SKU) && 1538 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1539 reg |= ((adapter->dmac * 5) >> 6); 1540 else 1541 reg |= (adapter->dmac >> 5); 1542 1543 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1544 1545 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 1546 1547 /* Set the interval before transition */ 1548 reg = IGC_READ_REG(hw, IGC_DMCTLX); 1549 reg |= IGC_DMCTLX_DCFLUSH_DIS; 1550 1551 /* 1552 ** in 2.5Gb connection, TTLX unit is 0.4 usec 1553 ** which is 0x4*2 = 0xA. But delay is still 4 usec 1554 */ 1555 status = IGC_READ_REG(hw, IGC_STATUS); 1556 if ((status & IGC_STATUS_2P5_SKU) && 1557 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1558 reg |= 0xA; 1559 else 1560 reg |= 0x4; 1561 1562 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 1563 1564 /* free space in tx packet buffer to wake from DMA coal */ 1565 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 1566 (2 * max_frame_size)) >> 6); 1567 1568 /* make low power state decision controlled by DMA coal */ 1569 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 1570 reg &= ~IGC_PCIEMISC_LX_DECISION; 1571 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 1572} 1573 1574/********************************************************************* 1575 * 1576 * Initialize the hardware to a configuration as specified by the 1577 * adapter structure. 1578 * 1579 **********************************************************************/ 1580static void 1581igc_reset(if_ctx_t ctx) 1582{ 1583 device_t dev = iflib_get_dev(ctx); 1584 struct igc_adapter *adapter = iflib_get_softc(ctx); 1585 struct igc_hw *hw = &adapter->hw; 1586 u32 rx_buffer_size; 1587 u32 pba; 1588 1589 INIT_DEBUGOUT("igc_reset: begin"); 1590 /* Let the firmware know the OS is in control */ 1591 igc_get_hw_control(adapter); 1592 1593 /* 1594 * Packet Buffer Allocation (PBA) 1595 * Writing PBA sets the receive portion of the buffer 1596 * the remainder is used for the transmit buffer. 1597 */ 1598 pba = IGC_PBA_34K; 1599 1600 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 1601 1602 /* 1603 * These parameters control the automatic generation (Tx) and 1604 * response (Rx) to Ethernet PAUSE frames. 1605 * - High water mark should allow for at least two frames to be 1606 * received after sending an XOFF. 1607 * - Low water mark works best when it is very near the high water mark. 1608 * This allows the receiver to restart by sending XON when it has 1609 * drained a bit. Here we use an arbitrary value of 1500 which will 1610 * restart after one full frame is pulled from the buffer. There 1611 * could be several smaller frames in the buffer and if so they will 1612 * not trigger the XON until their total number reduces the buffer 1613 * by 1500. 1614 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1615 */ 1616 rx_buffer_size = (pba & 0xffff) << 10; 1617 hw->fc.high_water = rx_buffer_size - 1618 roundup2(adapter->hw.mac.max_frame_size, 1024); 1619 /* 16-byte granularity */ 1620 hw->fc.low_water = hw->fc.high_water - 16; 1621 1622 if (adapter->fc) /* locally set flow control value? */ 1623 hw->fc.requested_mode = adapter->fc; 1624 else 1625 hw->fc.requested_mode = igc_fc_full; 1626 1627 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 1628 1629 hw->fc.send_xon = true; 1630 1631 /* Issue a global reset */ 1632 igc_reset_hw(hw); 1633 IGC_WRITE_REG(hw, IGC_WUC, 0); 1634 1635 /* and a re-init */ 1636 if (igc_init_hw(hw) < 0) { 1637 device_printf(dev, "Hardware Initialization Failed\n"); 1638 return; 1639 } 1640 1641 /* Setup DMA Coalescing */ 1642 igc_init_dmac(adapter, pba); 1643 1644 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 1645 igc_get_phy_info(hw); 1646 igc_check_for_link(hw); 1647} 1648 1649/* 1650 * Initialise the RSS mapping for NICs that support multiple transmit/ 1651 * receive rings. 1652 */ 1653 1654#define RSSKEYLEN 10 1655static void 1656igc_initialize_rss_mapping(struct igc_adapter *adapter) 1657{ 1658 struct igc_hw *hw = &adapter->hw; 1659 int i; 1660 int queue_id; 1661 u32 reta; 1662 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 1663 1664 /* 1665 * The redirection table controls which destination 1666 * queue each bucket redirects traffic to. 1667 * Each DWORD represents four queues, with the LSB 1668 * being the first queue in the DWORD. 1669 * 1670 * This just allocates buckets to queues using round-robin 1671 * allocation. 1672 * 1673 * NOTE: It Just Happens to line up with the default 1674 * RSS allocation method. 1675 */ 1676 1677 /* Warning FM follows */ 1678 reta = 0; 1679 for (i = 0; i < 128; i++) { 1680#ifdef RSS 1681 queue_id = rss_get_indirection_to_bucket(i); 1682 /* 1683 * If we have more queues than buckets, we'll 1684 * end up mapping buckets to a subset of the 1685 * queues. 1686 * 1687 * If we have more buckets than queues, we'll 1688 * end up instead assigning multiple buckets 1689 * to queues. 1690 * 1691 * Both are suboptimal, but we need to handle 1692 * the case so we don't go out of bounds 1693 * indexing arrays and such. 1694 */ 1695 queue_id = queue_id % adapter->rx_num_queues; 1696#else 1697 queue_id = (i % adapter->rx_num_queues); 1698#endif 1699 /* Adjust if required */ 1700 queue_id = queue_id << shift; 1701 1702 /* 1703 * The low 8 bits are for hash value (n+0); 1704 * The next 8 bits are for hash value (n+1), etc. 1705 */ 1706 reta = reta >> 8; 1707 reta = reta | ( ((uint32_t) queue_id) << 24); 1708 if ((i & 3) == 3) { 1709 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 1710 reta = 0; 1711 } 1712 } 1713 1714 /* Now fill in hash table */ 1715 1716 /* 1717 * MRQC: Multiple Receive Queues Command 1718 * Set queuing to RSS control, number depends on the device. 1719 */ 1720 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 1721 1722#ifdef RSS 1723 /* XXX ew typecasting */ 1724 rss_getkey((uint8_t *) &rss_key); 1725#else 1726 arc4rand(&rss_key, sizeof(rss_key), 0); 1727#endif 1728 for (i = 0; i < RSSKEYLEN; i++) 1729 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 1730 1731 /* 1732 * Configure the RSS fields to hash upon. 1733 */ 1734 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 1735 IGC_MRQC_RSS_FIELD_IPV4_TCP); 1736 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 1737 IGC_MRQC_RSS_FIELD_IPV6_TCP); 1738 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 1739 IGC_MRQC_RSS_FIELD_IPV6_UDP); 1740 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 1741 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 1742 1743 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 1744} 1745 1746/********************************************************************* 1747 * 1748 * Setup networking device structure and register interface media. 1749 * 1750 **********************************************************************/ 1751static int 1752igc_setup_interface(if_ctx_t ctx) 1753{ 1754 if_t ifp = iflib_get_ifp(ctx); 1755 struct igc_adapter *adapter = iflib_get_softc(ctx); 1756 if_softc_ctx_t scctx = adapter->shared; 1757 1758 INIT_DEBUGOUT("igc_setup_interface: begin"); 1759 1760 /* Single Queue */ 1761 if (adapter->tx_num_queues == 1) { 1762 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 1763 if_setsendqready(ifp); 1764 } 1765 1766 /* 1767 * Specify the media types supported by this adapter and register 1768 * callbacks to update media and link information 1769 */ 1770 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 1771 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1772 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1773 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1774 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1775 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1776 ifmedia_add(adapter->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1777 1778 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1779 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 1780 return (0); 1781} 1782 1783static int 1784igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 1785{ 1786 struct igc_adapter *adapter = iflib_get_softc(ctx); 1787 if_softc_ctx_t scctx = adapter->shared; 1788 int error = IGC_SUCCESS; 1789 struct igc_tx_queue *que; 1790 int i, j; 1791 1792 MPASS(adapter->tx_num_queues > 0); 1793 MPASS(adapter->tx_num_queues == ntxqsets); 1794 1795 /* First allocate the top level queue structs */ 1796 if (!(adapter->tx_queues = 1797 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 1798 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1799 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1800 return(ENOMEM); 1801 } 1802 1803 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 1804 /* Set up some basics */ 1805 1806 struct tx_ring *txr = &que->txr; 1807 txr->adapter = que->adapter = adapter; 1808 que->me = txr->me = i; 1809 1810 /* Allocate report status array */ 1811 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 1812 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 1813 error = ENOMEM; 1814 goto fail; 1815 } 1816 for (j = 0; j < scctx->isc_ntxd[0]; j++) 1817 txr->tx_rsq[j] = QIDX_INVALID; 1818 /* get the virtual and physical address of the hardware queues */ 1819 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 1820 txr->tx_paddr = paddrs[i*ntxqs]; 1821 } 1822 1823 if (bootverbose) 1824 device_printf(iflib_get_dev(ctx), 1825 "allocated for %d tx_queues\n", adapter->tx_num_queues); 1826 return (0); 1827fail: 1828 igc_if_queues_free(ctx); 1829 return (error); 1830} 1831 1832static int 1833igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 1834{ 1835 struct igc_adapter *adapter = iflib_get_softc(ctx); 1836 int error = IGC_SUCCESS; 1837 struct igc_rx_queue *que; 1838 int i; 1839 1840 MPASS(adapter->rx_num_queues > 0); 1841 MPASS(adapter->rx_num_queues == nrxqsets); 1842 1843 /* First allocate the top level queue structs */ 1844 if (!(adapter->rx_queues = 1845 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 1846 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1847 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1848 error = ENOMEM; 1849 goto fail; 1850 } 1851 1852 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 1853 /* Set up some basics */ 1854 struct rx_ring *rxr = &que->rxr; 1855 rxr->adapter = que->adapter = adapter; 1856 rxr->que = que; 1857 que->me = rxr->me = i; 1858 1859 /* get the virtual and physical address of the hardware queues */ 1860 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 1861 rxr->rx_paddr = paddrs[i*nrxqs]; 1862 } 1863 1864 if (bootverbose) 1865 device_printf(iflib_get_dev(ctx), 1866 "allocated for %d rx_queues\n", adapter->rx_num_queues); 1867 1868 return (0); 1869fail: 1870 igc_if_queues_free(ctx); 1871 return (error); 1872} 1873 1874static void 1875igc_if_queues_free(if_ctx_t ctx) 1876{ 1877 struct igc_adapter *adapter = iflib_get_softc(ctx); 1878 struct igc_tx_queue *tx_que = adapter->tx_queues; 1879 struct igc_rx_queue *rx_que = adapter->rx_queues; 1880 1881 if (tx_que != NULL) { 1882 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1883 struct tx_ring *txr = &tx_que->txr; 1884 if (txr->tx_rsq == NULL) 1885 break; 1886 1887 free(txr->tx_rsq, M_DEVBUF); 1888 txr->tx_rsq = NULL; 1889 } 1890 free(adapter->tx_queues, M_DEVBUF); 1891 adapter->tx_queues = NULL; 1892 } 1893 1894 if (rx_que != NULL) { 1895 free(adapter->rx_queues, M_DEVBUF); 1896 adapter->rx_queues = NULL; 1897 } 1898 1899 igc_release_hw_control(adapter); 1900 1901 if (adapter->mta != NULL) { 1902 free(adapter->mta, M_DEVBUF); 1903 } 1904} 1905 1906/********************************************************************* 1907 * 1908 * Enable transmit unit. 1909 * 1910 **********************************************************************/ 1911static void 1912igc_initialize_transmit_unit(if_ctx_t ctx) 1913{ 1914 struct igc_adapter *adapter = iflib_get_softc(ctx); 1915 if_softc_ctx_t scctx = adapter->shared; 1916 struct igc_tx_queue *que; 1917 struct tx_ring *txr; 1918 struct igc_hw *hw = &adapter->hw; 1919 u32 tctl, txdctl = 0; 1920 1921 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 1922 1923 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 1924 u64 bus_addr; 1925 caddr_t offp, endp; 1926 1927 que = &adapter->tx_queues[i]; 1928 txr = &que->txr; 1929 bus_addr = txr->tx_paddr; 1930 1931 /* Clear checksum offload context. */ 1932 offp = (caddr_t)&txr->csum_flags; 1933 endp = (caddr_t)(txr + 1); 1934 bzero(offp, endp - offp); 1935 1936 /* Base and Len of TX Ring */ 1937 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1938 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 1939 IGC_WRITE_REG(hw, IGC_TDBAH(i), 1940 (u32)(bus_addr >> 32)); 1941 IGC_WRITE_REG(hw, IGC_TDBAL(i), 1942 (u32)bus_addr); 1943 /* Init the HEAD/TAIL indices */ 1944 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1945 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1946 1947 HW_DEBUGOUT2("Base = %x, Length = %x\n", 1948 IGC_READ_REG(&adapter->hw, IGC_TDBAL(i)), 1949 IGC_READ_REG(&adapter->hw, IGC_TDLEN(i))); 1950 1951 txdctl = 0; /* clear txdctl */ 1952 txdctl |= 0x1f; /* PTHRESH */ 1953 txdctl |= 1 << 8; /* HTHRESH */ 1954 txdctl |= 1 << 16;/* WTHRESH */ 1955 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1956 txdctl |= IGC_TXDCTL_GRAN; 1957 txdctl |= 1 << 25; /* LWTHRESH */ 1958 1959 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1960 } 1961 1962 /* Program the Transmit Control Register */ 1963 tctl = IGC_READ_REG(&adapter->hw, IGC_TCTL); 1964 tctl &= ~IGC_TCTL_CT; 1965 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1966 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1967 1968 /* This write will effectively turn on the transmit unit. */ 1969 IGC_WRITE_REG(&adapter->hw, IGC_TCTL, tctl); 1970} 1971 1972/********************************************************************* 1973 * 1974 * Enable receive unit. 1975 * 1976 **********************************************************************/ 1977#define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1) 1978 1979static void 1980igc_initialize_receive_unit(if_ctx_t ctx) 1981{ 1982 struct igc_adapter *adapter = iflib_get_softc(ctx); 1983 if_softc_ctx_t scctx = adapter->shared; 1984 if_t ifp = iflib_get_ifp(ctx); 1985 struct igc_hw *hw = &adapter->hw; 1986 struct igc_rx_queue *que; 1987 int i; 1988 u32 psize, rctl, rxcsum, srrctl = 0; 1989 1990 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 1991 1992 /* 1993 * Make sure receives are disabled while setting 1994 * up the descriptor ring 1995 */ 1996 rctl = IGC_READ_REG(hw, IGC_RCTL); 1997 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 1998 1999 /* Setup the Receive Control Register */ 2000 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2001 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2002 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 2003 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2004 2005 /* Do not store bad packets */ 2006 rctl &= ~IGC_RCTL_SBP; 2007 2008 /* Enable Long Packet receive */ 2009 if (if_getmtu(ifp) > ETHERMTU) 2010 rctl |= IGC_RCTL_LPE; 2011 else 2012 rctl &= ~IGC_RCTL_LPE; 2013 2014 /* Strip the CRC */ 2015 if (!igc_disable_crc_stripping) 2016 rctl |= IGC_RCTL_SECRC; 2017 2018 /* 2019 * Set the interrupt throttling rate. Value is calculated 2020 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2021 */ 2022 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR); 2023 2024 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2025 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2026 rxcsum |= IGC_RXCSUM_CRCOFL; 2027 if (adapter->tx_num_queues > 1) 2028 rxcsum |= IGC_RXCSUM_PCSD; 2029 else 2030 rxcsum |= IGC_RXCSUM_IPPCSE; 2031 } else { 2032 if (adapter->tx_num_queues > 1) 2033 rxcsum |= IGC_RXCSUM_PCSD; 2034 else 2035 rxcsum &= ~IGC_RXCSUM_TUOFL; 2036 } 2037 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2038 2039 if (adapter->rx_num_queues > 1) 2040 igc_initialize_rss_mapping(adapter); 2041 2042 if (if_getmtu(ifp) > ETHERMTU) { 2043 psize = scctx->isc_max_frame_size; 2044 /* are we on a vlan? */ 2045 if (if_vlantrunkinuse(ifp)) 2046 psize += VLAN_TAG_SIZE; 2047 IGC_WRITE_REG(&adapter->hw, IGC_RLPML, psize); 2048 } 2049 2050 /* Set maximum packet buffer len */ 2051 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 2052 IGC_SRRCTL_BSIZEPKT_SHIFT; 2053 /* srrctl above overrides this but set the register to a sane value */ 2054 rctl |= IGC_RCTL_SZ_2048; 2055 2056 /* 2057 * If TX flow control is disabled and there's >1 queue defined, 2058 * enable DROP. 2059 * 2060 * This drops frames rather than hanging the RX MAC for all queues. 2061 */ 2062 if ((adapter->rx_num_queues > 1) && 2063 (adapter->fc == igc_fc_none || 2064 adapter->fc == igc_fc_rx_pause)) { 2065 srrctl |= IGC_SRRCTL_DROP_EN; 2066 } 2067 2068 /* Setup the Base and Length of the Rx Descriptor Rings */ 2069 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2070 struct rx_ring *rxr = &que->rxr; 2071 u64 bus_addr = rxr->rx_paddr; 2072 u32 rxdctl; 2073 2074#ifdef notyet 2075 /* Configure for header split? -- ignore for now */ 2076 rxr->hdr_split = igc_header_split; 2077#else 2078 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2079#endif 2080 2081 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2082 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2083 IGC_WRITE_REG(hw, IGC_RDBAH(i), 2084 (uint32_t)(bus_addr >> 32)); 2085 IGC_WRITE_REG(hw, IGC_RDBAL(i), 2086 (uint32_t)bus_addr); 2087 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2088 /* Setup the Head and Tail Descriptor Pointers */ 2089 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2090 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2091 /* Enable this Queue */ 2092 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2093 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2094 rxdctl &= 0xFFF00000; 2095 rxdctl |= IGC_RX_PTHRESH; 2096 rxdctl |= IGC_RX_HTHRESH << 8; 2097 rxdctl |= IGC_RX_WTHRESH << 16; 2098 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2099 } 2100 2101 /* Make sure VLAN Filters are off */ 2102 rctl &= ~IGC_RCTL_VFE; 2103 2104 /* Write out the settings */ 2105 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2106 2107 return; 2108} 2109 2110static void 2111igc_setup_vlan_hw_support(if_ctx_t ctx) 2112{ 2113 struct igc_adapter *adapter = iflib_get_softc(ctx); 2114 struct igc_hw *hw = &adapter->hw; 2115 struct ifnet *ifp = iflib_get_ifp(ctx); 2116 u32 reg; 2117 2118 /* igc hardware doesn't seem to implement VFTA for HWFILTER */ 2119 2120 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2121 !igc_disable_crc_stripping) { 2122 reg = IGC_READ_REG(hw, IGC_CTRL); 2123 reg |= IGC_CTRL_VME; 2124 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2125 } else { 2126 reg = IGC_READ_REG(hw, IGC_CTRL); 2127 reg &= ~IGC_CTRL_VME; 2128 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2129 } 2130} 2131 2132static void 2133igc_if_intr_enable(if_ctx_t ctx) 2134{ 2135 struct igc_adapter *adapter = iflib_get_softc(ctx); 2136 struct igc_hw *hw = &adapter->hw; 2137 u32 mask; 2138 2139 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2140 mask = (adapter->que_mask | adapter->link_mask); 2141 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2142 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2143 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2144 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 2145 } else 2146 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK); 2147 IGC_WRITE_FLUSH(hw); 2148} 2149 2150static void 2151igc_if_intr_disable(if_ctx_t ctx) 2152{ 2153 struct igc_adapter *adapter = iflib_get_softc(ctx); 2154 struct igc_hw *hw = &adapter->hw; 2155 2156 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2157 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2158 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2159 } 2160 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2161 IGC_WRITE_FLUSH(hw); 2162} 2163 2164/* 2165 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2166 * For ASF and Pass Through versions of f/w this means 2167 * that the driver is loaded. For AMT version type f/w 2168 * this means that the network i/f is open. 2169 */ 2170static void 2171igc_get_hw_control(struct igc_adapter *adapter) 2172{ 2173 u32 ctrl_ext; 2174 2175 if (adapter->vf_ifp) 2176 return; 2177 2178 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2179 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2180 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2181} 2182 2183/* 2184 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2185 * For ASF and Pass Through versions of f/w this means that 2186 * the driver is no longer loaded. For AMT versions of the 2187 * f/w this means that the network i/f is closed. 2188 */ 2189static void 2190igc_release_hw_control(struct igc_adapter *adapter) 2191{ 2192 u32 ctrl_ext; 2193 2194 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2195 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2196 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2197 return; 2198} 2199 2200static int 2201igc_is_valid_ether_addr(u8 *addr) 2202{ 2203 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2204 2205 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2206 return (false); 2207 } 2208 2209 return (true); 2210} 2211 2212/* 2213** Parse the interface capabilities with regard 2214** to both system management and wake-on-lan for 2215** later use. 2216*/ 2217static void 2218igc_get_wakeup(if_ctx_t ctx) 2219{ 2220 struct igc_adapter *adapter = iflib_get_softc(ctx); 2221 u16 eeprom_data = 0, apme_mask; 2222 2223 apme_mask = IGC_WUC_APME; 2224 eeprom_data = IGC_READ_REG(&adapter->hw, IGC_WUC); 2225 2226 if (eeprom_data & apme_mask) 2227 adapter->wol = IGC_WUFC_LNKC; 2228} 2229 2230 2231/* 2232 * Enable PCI Wake On Lan capability 2233 */ 2234static void 2235igc_enable_wakeup(if_ctx_t ctx) 2236{ 2237 struct igc_adapter *adapter = iflib_get_softc(ctx); 2238 device_t dev = iflib_get_dev(ctx); 2239 if_t ifp = iflib_get_ifp(ctx); 2240 int error = 0; 2241 u32 pmc, ctrl, rctl; 2242 u16 status; 2243 2244 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 2245 return; 2246 2247 /* 2248 * Determine type of Wakeup: note that wol 2249 * is set with all bits on by default. 2250 */ 2251 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 2252 adapter->wol &= ~IGC_WUFC_MAG; 2253 2254 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 2255 adapter->wol &= ~IGC_WUFC_EX; 2256 2257 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 2258 adapter->wol &= ~IGC_WUFC_MC; 2259 else { 2260 rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 2261 rctl |= IGC_RCTL_MPE; 2262 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, rctl); 2263 } 2264 2265 if (!(adapter->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) 2266 goto pme; 2267 2268 /* Advertise the wakeup capability */ 2269 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 2270 ctrl |= IGC_CTRL_ADVD3WUC; 2271 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 2272 2273 /* Enable wakeup by the MAC */ 2274 IGC_WRITE_REG(&adapter->hw, IGC_WUC, IGC_WUC_PME_EN); 2275 IGC_WRITE_REG(&adapter->hw, IGC_WUFC, adapter->wol); 2276 2277pme: 2278 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 2279 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2280 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 2281 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2282 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 2283 2284 return; 2285} 2286 2287/********************************************************************** 2288 * 2289 * Update the board statistics counters. 2290 * 2291 **********************************************************************/ 2292static void 2293igc_update_stats_counters(struct igc_adapter *adapter) 2294{ 2295 u64 prev_xoffrxc = adapter->stats.xoffrxc; 2296 2297 adapter->stats.crcerrs += IGC_READ_REG(&adapter->hw, IGC_CRCERRS); 2298 adapter->stats.mpc += IGC_READ_REG(&adapter->hw, IGC_MPC); 2299 adapter->stats.scc += IGC_READ_REG(&adapter->hw, IGC_SCC); 2300 adapter->stats.ecol += IGC_READ_REG(&adapter->hw, IGC_ECOL); 2301 2302 adapter->stats.mcc += IGC_READ_REG(&adapter->hw, IGC_MCC); 2303 adapter->stats.latecol += IGC_READ_REG(&adapter->hw, IGC_LATECOL); 2304 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_COLC); 2305 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_RERC); 2306 adapter->stats.dc += IGC_READ_REG(&adapter->hw, IGC_DC); 2307 adapter->stats.rlec += IGC_READ_REG(&adapter->hw, IGC_RLEC); 2308 adapter->stats.xonrxc += IGC_READ_REG(&adapter->hw, IGC_XONRXC); 2309 adapter->stats.xontxc += IGC_READ_REG(&adapter->hw, IGC_XONTXC); 2310 adapter->stats.xoffrxc += IGC_READ_REG(&adapter->hw, IGC_XOFFRXC); 2311 /* 2312 * For watchdog management we need to know if we have been 2313 * paused during the last interval, so capture that here. 2314 */ 2315 if (adapter->stats.xoffrxc != prev_xoffrxc) 2316 adapter->shared->isc_pause_frames = 1; 2317 adapter->stats.xofftxc += IGC_READ_REG(&adapter->hw, IGC_XOFFTXC); 2318 adapter->stats.fcruc += IGC_READ_REG(&adapter->hw, IGC_FCRUC); 2319 adapter->stats.prc64 += IGC_READ_REG(&adapter->hw, IGC_PRC64); 2320 adapter->stats.prc127 += IGC_READ_REG(&adapter->hw, IGC_PRC127); 2321 adapter->stats.prc255 += IGC_READ_REG(&adapter->hw, IGC_PRC255); 2322 adapter->stats.prc511 += IGC_READ_REG(&adapter->hw, IGC_PRC511); 2323 adapter->stats.prc1023 += IGC_READ_REG(&adapter->hw, IGC_PRC1023); 2324 adapter->stats.prc1522 += IGC_READ_REG(&adapter->hw, IGC_PRC1522); 2325 adapter->stats.tlpic += IGC_READ_REG(&adapter->hw, IGC_TLPIC); 2326 adapter->stats.rlpic += IGC_READ_REG(&adapter->hw, IGC_RLPIC); 2327 adapter->stats.gprc += IGC_READ_REG(&adapter->hw, IGC_GPRC); 2328 adapter->stats.bprc += IGC_READ_REG(&adapter->hw, IGC_BPRC); 2329 adapter->stats.mprc += IGC_READ_REG(&adapter->hw, IGC_MPRC); 2330 adapter->stats.gptc += IGC_READ_REG(&adapter->hw, IGC_GPTC); 2331 2332 /* For the 64-bit byte counters the low dword must be read first. */ 2333 /* Both registers clear on the read of the high dword */ 2334 2335 adapter->stats.gorc += IGC_READ_REG(&adapter->hw, IGC_GORCL) + 2336 ((u64)IGC_READ_REG(&adapter->hw, IGC_GORCH) << 32); 2337 adapter->stats.gotc += IGC_READ_REG(&adapter->hw, IGC_GOTCL) + 2338 ((u64)IGC_READ_REG(&adapter->hw, IGC_GOTCH) << 32); 2339 2340 adapter->stats.rnbc += IGC_READ_REG(&adapter->hw, IGC_RNBC); 2341 adapter->stats.ruc += IGC_READ_REG(&adapter->hw, IGC_RUC); 2342 adapter->stats.rfc += IGC_READ_REG(&adapter->hw, IGC_RFC); 2343 adapter->stats.roc += IGC_READ_REG(&adapter->hw, IGC_ROC); 2344 adapter->stats.rjc += IGC_READ_REG(&adapter->hw, IGC_RJC); 2345 2346 adapter->stats.tor += IGC_READ_REG(&adapter->hw, IGC_TORH); 2347 adapter->stats.tot += IGC_READ_REG(&adapter->hw, IGC_TOTH); 2348 2349 adapter->stats.tpr += IGC_READ_REG(&adapter->hw, IGC_TPR); 2350 adapter->stats.tpt += IGC_READ_REG(&adapter->hw, IGC_TPT); 2351 adapter->stats.ptc64 += IGC_READ_REG(&adapter->hw, IGC_PTC64); 2352 adapter->stats.ptc127 += IGC_READ_REG(&adapter->hw, IGC_PTC127); 2353 adapter->stats.ptc255 += IGC_READ_REG(&adapter->hw, IGC_PTC255); 2354 adapter->stats.ptc511 += IGC_READ_REG(&adapter->hw, IGC_PTC511); 2355 adapter->stats.ptc1023 += IGC_READ_REG(&adapter->hw, IGC_PTC1023); 2356 adapter->stats.ptc1522 += IGC_READ_REG(&adapter->hw, IGC_PTC1522); 2357 adapter->stats.mptc += IGC_READ_REG(&adapter->hw, IGC_MPTC); 2358 adapter->stats.bptc += IGC_READ_REG(&adapter->hw, IGC_BPTC); 2359 2360 /* Interrupt Counts */ 2361 adapter->stats.iac += IGC_READ_REG(&adapter->hw, IGC_IAC); 2362 adapter->stats.rxdmtc += IGC_READ_REG(&adapter->hw, IGC_RXDMTC); 2363 2364 adapter->stats.algnerrc += IGC_READ_REG(&adapter->hw, IGC_ALGNERRC); 2365 adapter->stats.tncrs += IGC_READ_REG(&adapter->hw, IGC_TNCRS); 2366 adapter->stats.htdpmc += IGC_READ_REG(&adapter->hw, IGC_HTDPMC); 2367 adapter->stats.tsctc += IGC_READ_REG(&adapter->hw, IGC_TSCTC); 2368} 2369 2370static uint64_t 2371igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2372{ 2373 struct igc_adapter *adapter = iflib_get_softc(ctx); 2374 if_t ifp = iflib_get_ifp(ctx); 2375 2376 switch (cnt) { 2377 case IFCOUNTER_COLLISIONS: 2378 return (adapter->stats.colc); 2379 case IFCOUNTER_IERRORS: 2380 return (adapter->dropped_pkts + adapter->stats.rxerrc + 2381 adapter->stats.crcerrs + adapter->stats.algnerrc + 2382 adapter->stats.ruc + adapter->stats.roc + 2383 adapter->stats.mpc + adapter->stats.htdpmc); 2384 case IFCOUNTER_OERRORS: 2385 return (adapter->stats.ecol + adapter->stats.latecol + 2386 adapter->watchdog_events); 2387 default: 2388 return (if_get_counter_default(ifp, cnt)); 2389 } 2390} 2391 2392/* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 2393 * @ctx: iflib context 2394 * @event: event code to check 2395 * 2396 * Defaults to returning false for unknown events. 2397 * 2398 * @returns true if iflib needs to reinit the interface 2399 */ 2400static bool 2401igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 2402{ 2403 switch (event) { 2404 case IFLIB_RESTART_VLAN_CONFIG: 2405 default: 2406 return (false); 2407 } 2408} 2409 2410/* Export a single 32-bit register via a read-only sysctl. */ 2411static int 2412igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 2413{ 2414 struct igc_adapter *adapter; 2415 u_int val; 2416 2417 adapter = oidp->oid_arg1; 2418 val = IGC_READ_REG(&adapter->hw, oidp->oid_arg2); 2419 return (sysctl_handle_int(oidp, &val, 0, req)); 2420} 2421 2422/* 2423 * Add sysctl variables, one per statistic, to the system. 2424 */ 2425static void 2426igc_add_hw_stats(struct igc_adapter *adapter) 2427{ 2428 device_t dev = iflib_get_dev(adapter->ctx); 2429 struct igc_tx_queue *tx_que = adapter->tx_queues; 2430 struct igc_rx_queue *rx_que = adapter->rx_queues; 2431 2432 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2433 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2434 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2435 struct igc_hw_stats *stats = &adapter->stats; 2436 2437 struct sysctl_oid *stat_node, *queue_node, *int_node; 2438 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 2439 2440#define QUEUE_NAME_LEN 32 2441 char namebuf[QUEUE_NAME_LEN]; 2442 2443 /* Driver Statistics */ 2444 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2445 CTLFLAG_RD, &adapter->dropped_pkts, 2446 "Driver dropped packets"); 2447 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2448 CTLFLAG_RD, &adapter->link_irq, 2449 "Link MSI-X IRQ Handled"); 2450 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 2451 CTLFLAG_RD, &adapter->rx_overruns, 2452 "RX overruns"); 2453 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 2454 CTLFLAG_RD, &adapter->watchdog_events, 2455 "Watchdog timeouts"); 2456 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 2457 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2458 adapter, IGC_CTRL, igc_sysctl_reg_handler, "IU", 2459 "Device Control Register"); 2460 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 2461 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2462 adapter, IGC_RCTL, igc_sysctl_reg_handler, "IU", 2463 "Receiver Control Register"); 2464 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 2465 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 2466 "Flow Control High Watermark"); 2467 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 2468 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 2469 "Flow Control Low Watermark"); 2470 2471 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2472 struct tx_ring *txr = &tx_que->txr; 2473 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 2474 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2475 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 2476 queue_list = SYSCTL_CHILDREN(queue_node); 2477 2478 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2479 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2480 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 2481 "Transmit Descriptor Head"); 2482 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2483 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2484 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 2485 "Transmit Descriptor Tail"); 2486 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 2487 CTLFLAG_RD, &txr->tx_irq, 2488 "Queue MSI-X Transmit Interrupts"); 2489 } 2490 2491 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 2492 struct rx_ring *rxr = &rx_que->rxr; 2493 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 2494 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2495 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 2496 queue_list = SYSCTL_CHILDREN(queue_node); 2497 2498 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2499 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2500 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 2501 "Receive Descriptor Head"); 2502 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2503 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2504 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 2505 "Receive Descriptor Tail"); 2506 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 2507 CTLFLAG_RD, &rxr->rx_irq, 2508 "Queue MSI-X Receive Interrupts"); 2509 } 2510 2511 /* MAC stats get their own sub node */ 2512 2513 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2514 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 2515 stat_list = SYSCTL_CHILDREN(stat_node); 2516 2517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 2518 CTLFLAG_RD, &stats->ecol, 2519 "Excessive collisions"); 2520 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 2521 CTLFLAG_RD, &stats->scc, 2522 "Single collisions"); 2523 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 2524 CTLFLAG_RD, &stats->mcc, 2525 "Multiple collisions"); 2526 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 2527 CTLFLAG_RD, &stats->latecol, 2528 "Late collisions"); 2529 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 2530 CTLFLAG_RD, &stats->colc, 2531 "Collision Count"); 2532 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 2533 CTLFLAG_RD, &adapter->stats.symerrs, 2534 "Symbol Errors"); 2535 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 2536 CTLFLAG_RD, &adapter->stats.sec, 2537 "Sequence Errors"); 2538 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 2539 CTLFLAG_RD, &adapter->stats.dc, 2540 "Defer Count"); 2541 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 2542 CTLFLAG_RD, &adapter->stats.mpc, 2543 "Missed Packets"); 2544 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 2545 CTLFLAG_RD, &adapter->stats.rnbc, 2546 "Receive No Buffers"); 2547 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 2548 CTLFLAG_RD, &adapter->stats.ruc, 2549 "Receive Undersize"); 2550 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2551 CTLFLAG_RD, &adapter->stats.rfc, 2552 "Fragmented Packets Received "); 2553 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 2554 CTLFLAG_RD, &adapter->stats.roc, 2555 "Oversized Packets Received"); 2556 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 2557 CTLFLAG_RD, &adapter->stats.rjc, 2558 "Recevied Jabber"); 2559 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 2560 CTLFLAG_RD, &adapter->stats.rxerrc, 2561 "Receive Errors"); 2562 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2563 CTLFLAG_RD, &adapter->stats.crcerrs, 2564 "CRC errors"); 2565 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 2566 CTLFLAG_RD, &adapter->stats.algnerrc, 2567 "Alignment Errors"); 2568 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2569 CTLFLAG_RD, &adapter->stats.xonrxc, 2570 "XON Received"); 2571 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2572 CTLFLAG_RD, &adapter->stats.xontxc, 2573 "XON Transmitted"); 2574 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2575 CTLFLAG_RD, &adapter->stats.xoffrxc, 2576 "XOFF Received"); 2577 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2578 CTLFLAG_RD, &adapter->stats.xofftxc, 2579 "XOFF Transmitted"); 2580 2581 /* Packet Reception Stats */ 2582 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 2583 CTLFLAG_RD, &adapter->stats.tpr, 2584 "Total Packets Received "); 2585 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 2586 CTLFLAG_RD, &adapter->stats.gprc, 2587 "Good Packets Received"); 2588 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 2589 CTLFLAG_RD, &adapter->stats.bprc, 2590 "Broadcast Packets Received"); 2591 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 2592 CTLFLAG_RD, &adapter->stats.mprc, 2593 "Multicast Packets Received"); 2594 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2595 CTLFLAG_RD, &adapter->stats.prc64, 2596 "64 byte frames received "); 2597 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2598 CTLFLAG_RD, &adapter->stats.prc127, 2599 "65-127 byte frames received"); 2600 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2601 CTLFLAG_RD, &adapter->stats.prc255, 2602 "128-255 byte frames received"); 2603 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2604 CTLFLAG_RD, &adapter->stats.prc511, 2605 "256-511 byte frames received"); 2606 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2607 CTLFLAG_RD, &adapter->stats.prc1023, 2608 "512-1023 byte frames received"); 2609 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2610 CTLFLAG_RD, &adapter->stats.prc1522, 2611 "1023-1522 byte frames received"); 2612 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 2613 CTLFLAG_RD, &adapter->stats.gorc, 2614 "Good Octets Received"); 2615 2616 /* Packet Transmission Stats */ 2617 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2618 CTLFLAG_RD, &adapter->stats.gotc, 2619 "Good Octets Transmitted"); 2620 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2621 CTLFLAG_RD, &adapter->stats.tpt, 2622 "Total Packets Transmitted"); 2623 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2624 CTLFLAG_RD, &adapter->stats.gptc, 2625 "Good Packets Transmitted"); 2626 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2627 CTLFLAG_RD, &adapter->stats.bptc, 2628 "Broadcast Packets Transmitted"); 2629 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2630 CTLFLAG_RD, &adapter->stats.mptc, 2631 "Multicast Packets Transmitted"); 2632 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2633 CTLFLAG_RD, &adapter->stats.ptc64, 2634 "64 byte frames transmitted "); 2635 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2636 CTLFLAG_RD, &adapter->stats.ptc127, 2637 "65-127 byte frames transmitted"); 2638 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2639 CTLFLAG_RD, &adapter->stats.ptc255, 2640 "128-255 byte frames transmitted"); 2641 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2642 CTLFLAG_RD, &adapter->stats.ptc511, 2643 "256-511 byte frames transmitted"); 2644 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2645 CTLFLAG_RD, &adapter->stats.ptc1023, 2646 "512-1023 byte frames transmitted"); 2647 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2648 CTLFLAG_RD, &adapter->stats.ptc1522, 2649 "1024-1522 byte frames transmitted"); 2650 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 2651 CTLFLAG_RD, &adapter->stats.tsctc, 2652 "TSO Contexts Transmitted"); 2653 2654 /* Interrupt Stats */ 2655 2656 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 2657 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 2658 int_list = SYSCTL_CHILDREN(int_node); 2659 2660 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 2661 CTLFLAG_RD, &adapter->stats.iac, 2662 "Interrupt Assertion Count"); 2663 2664 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 2665 CTLFLAG_RD, &adapter->stats.rxdmtc, 2666 "Rx Desc Min Thresh Count"); 2667} 2668 2669/********************************************************************** 2670 * 2671 * This routine provides a way to dump out the adapter eeprom, 2672 * often a useful debug/service tool. This only dumps the first 2673 * 32 words, stuff that matters is in that extent. 2674 * 2675 **********************************************************************/ 2676static int 2677igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 2678{ 2679 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 2680 int error; 2681 int result; 2682 2683 result = -1; 2684 error = sysctl_handle_int(oidp, &result, 0, req); 2685 2686 if (error || !req->newptr) 2687 return (error); 2688 2689 /* 2690 * This value will cause a hex dump of the 2691 * first 32 16-bit words of the EEPROM to 2692 * the screen. 2693 */ 2694 if (result == 1) 2695 igc_print_nvm_info(adapter); 2696 2697 return (error); 2698} 2699 2700static void 2701igc_print_nvm_info(struct igc_adapter *adapter) 2702{ 2703 u16 eeprom_data; 2704 int i, j, row = 0; 2705 2706 /* Its a bit crude, but it gets the job done */ 2707 printf("\nInterface EEPROM Dump:\n"); 2708 printf("Offset\n0x0000 "); 2709 for (i = 0, j = 0; i < 32; i++, j++) { 2710 if (j == 8) { /* Make the offset block */ 2711 j = 0; ++row; 2712 printf("\n0x00%x0 ",row); 2713 } 2714 igc_read_nvm(&adapter->hw, i, 1, &eeprom_data); 2715 printf("%04x ", eeprom_data); 2716 } 2717 printf("\n"); 2718} 2719 2720static int 2721igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 2722{ 2723 struct igc_int_delay_info *info; 2724 struct igc_adapter *adapter; 2725 u32 regval; 2726 int error, usecs, ticks; 2727 2728 info = (struct igc_int_delay_info *) arg1; 2729 usecs = info->value; 2730 error = sysctl_handle_int(oidp, &usecs, 0, req); 2731 if (error != 0 || req->newptr == NULL) 2732 return (error); 2733 if (usecs < 0 || usecs > IGC_TICKS_TO_USECS(65535)) 2734 return (EINVAL); 2735 info->value = usecs; 2736 ticks = IGC_USECS_TO_TICKS(usecs); 2737 if (info->offset == IGC_ITR) /* units are 256ns here */ 2738 ticks *= 4; 2739 2740 adapter = info->adapter; 2741 2742 regval = IGC_READ_OFFSET(&adapter->hw, info->offset); 2743 regval = (regval & ~0xffff) | (ticks & 0xffff); 2744 /* Handle a few special cases. */ 2745 switch (info->offset) { 2746 case IGC_RDTR: 2747 break; 2748 case IGC_TIDV: 2749 if (ticks == 0) { 2750 adapter->txd_cmd &= ~IGC_TXD_CMD_IDE; 2751 /* Don't write 0 into the TIDV register. */ 2752 regval++; 2753 } else 2754 adapter->txd_cmd |= IGC_TXD_CMD_IDE; 2755 break; 2756 } 2757 IGC_WRITE_OFFSET(&adapter->hw, info->offset, regval); 2758 return (0); 2759} 2760 2761static void 2762igc_add_int_delay_sysctl(struct igc_adapter *adapter, const char *name, 2763 const char *description, struct igc_int_delay_info *info, 2764 int offset, int value) 2765{ 2766 info->adapter = adapter; 2767 info->offset = offset; 2768 info->value = value; 2769 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 2770 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 2771 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2772 info, 0, igc_sysctl_int_delay, "I", description); 2773} 2774 2775/* 2776 * Set flow control using sysctl: 2777 * Flow control values: 2778 * 0 - off 2779 * 1 - rx pause 2780 * 2 - tx pause 2781 * 3 - full 2782 */ 2783static int 2784igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 2785{ 2786 int error; 2787 static int input = 3; /* default is full */ 2788 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2789 2790 error = sysctl_handle_int(oidp, &input, 0, req); 2791 2792 if ((error) || (req->newptr == NULL)) 2793 return (error); 2794 2795 if (input == adapter->fc) /* no change? */ 2796 return (error); 2797 2798 switch (input) { 2799 case igc_fc_rx_pause: 2800 case igc_fc_tx_pause: 2801 case igc_fc_full: 2802 case igc_fc_none: 2803 adapter->hw.fc.requested_mode = input; 2804 adapter->fc = input; 2805 break; 2806 default: 2807 /* Do nothing */ 2808 return (error); 2809 } 2810 2811 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 2812 igc_force_mac_fc(&adapter->hw); 2813 return (error); 2814} 2815 2816/* 2817 * Manage Energy Efficient Ethernet: 2818 * Control values: 2819 * 0/1 - enabled/disabled 2820 */ 2821static int 2822igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 2823{ 2824 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2825 int error, value; 2826 2827 value = adapter->hw.dev_spec._i225.eee_disable; 2828 error = sysctl_handle_int(oidp, &value, 0, req); 2829 if (error || req->newptr == NULL) 2830 return (error); 2831 2832 adapter->hw.dev_spec._i225.eee_disable = (value != 0); 2833 igc_if_init(adapter->ctx); 2834 2835 return (0); 2836} 2837 2838static int 2839igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 2840{ 2841 struct igc_adapter *adapter; 2842 int error; 2843 int result; 2844 2845 result = -1; 2846 error = sysctl_handle_int(oidp, &result, 0, req); 2847 2848 if (error || !req->newptr) 2849 return (error); 2850 2851 if (result == 1) { 2852 adapter = (struct igc_adapter *) arg1; 2853 igc_print_debug_info(adapter); 2854 } 2855 2856 return (error); 2857} 2858 2859static int 2860igc_get_rs(SYSCTL_HANDLER_ARGS) 2861{ 2862 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2863 int error; 2864 int result; 2865 2866 result = 0; 2867 error = sysctl_handle_int(oidp, &result, 0, req); 2868 2869 if (error || !req->newptr || result != 1) 2870 return (error); 2871 igc_dump_rs(adapter); 2872 2873 return (error); 2874} 2875 2876static void 2877igc_if_debug(if_ctx_t ctx) 2878{ 2879 igc_dump_rs(iflib_get_softc(ctx)); 2880} 2881 2882/* 2883 * This routine is meant to be fluid, add whatever is 2884 * needed for debugging a problem. -jfv 2885 */ 2886static void 2887igc_print_debug_info(struct igc_adapter *adapter) 2888{ 2889 device_t dev = iflib_get_dev(adapter->ctx); 2890 if_t ifp = iflib_get_ifp(adapter->ctx); 2891 struct tx_ring *txr = &adapter->tx_queues->txr; 2892 struct rx_ring *rxr = &adapter->rx_queues->rxr; 2893 2894 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2895 printf("Interface is RUNNING "); 2896 else 2897 printf("Interface is NOT RUNNING\n"); 2898 2899 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 2900 printf("and INACTIVE\n"); 2901 else 2902 printf("and ACTIVE\n"); 2903 2904 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2905 device_printf(dev, "TX Queue %d ------\n", i); 2906 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 2907 IGC_READ_REG(&adapter->hw, IGC_TDH(i)), 2908 IGC_READ_REG(&adapter->hw, IGC_TDT(i))); 2909 2910 } 2911 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 2912 device_printf(dev, "RX Queue %d ------\n", j); 2913 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 2914 IGC_READ_REG(&adapter->hw, IGC_RDH(j)), 2915 IGC_READ_REG(&adapter->hw, IGC_RDT(j))); 2916 } 2917} 2918