1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003 Peter Wemm 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Register defintions for the i8259A programmable interrupt controller. 31 */ 32 33#ifndef _DEV_IC_I8259_H_ 34#define _DEV_IC_I8259_H_ 35 36/* Initialization control word 1. Written to even address. */ 37#define ICW1_IC4 0x01 /* ICW4 present */ 38#define ICW1_SNGL 0x02 /* 1 = single, 0 = cascaded */ 39#define ICW1_ADI 0x04 /* 1 = 4, 0 = 8 byte vectors */ 40#define ICW1_LTIM 0x08 /* 1 = level trigger, 0 = edge */ 41#define ICW1_RESET 0x10 /* must be 1 */ 42/* 0x20 - 0x80 - in 8080/8085 mode only */ 43 44/* Initialization control word 2. Written to the odd address. */ 45/* No definitions, it is the base vector of the IDT for 8086 mode */ 46 47/* Initialization control word 3. Written to the odd address. */ 48/* For a master PIC, bitfield indicating a slave 8259 on given input */ 49/* For slave, lower 3 bits are the slave's ID binary id on master */ 50 51/* Initialization control word 4. Written to the odd address. */ 52#define ICW4_8086 0x01 /* 1 = 8086, 0 = 8080 */ 53#define ICW4_AEOI 0x02 /* 1 = Auto EOI */ 54#define ICW4_MS 0x04 /* 1 = buffered master, 0 = slave */ 55#define ICW4_BUF 0x08 /* 1 = enable buffer mode */ 56#define ICW4_SFNM 0x10 /* 1 = special fully nested mode */ 57 58/* Operation control words. Written after initialization. */ 59 60/* Operation control word type 1 */ 61/* 62 * No definitions. Written to the odd address. Bitmask for interrupts. 63 * 1 = disabled. 64 */ 65 66/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */ 67#define OCW2_L0 0x01 /* Level */ 68#define OCW2_L1 0x02 69#define OCW2_L2 0x04 70/* 0x08 must be 0 to select OCW2 vs OCW3 */ 71/* 0x10 must be 0 to select OCW2 vs ICW1 */ 72#define OCW2_EOI 0x20 /* 1 = EOI */ 73#define OCW2_SL 0x40 /* EOI mode */ 74#define OCW2_R 0x80 /* EOI mode */ 75 76/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */ 77#define OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */ 78#define OCW3_RR 0x02 /* register read */ 79#define OCW3_P 0x04 /* poll mode command */ 80/* 0x08 must be 1 to select OCW3 vs OCW2 */ 81#define OCW3_SEL 0x08 /* must be 1 */ 82/* 0x10 must be 0 to select OCW3 vs ICW1 */ 83#define OCW3_SMM 0x20 /* special mode mask */ 84#define OCW3_ESMM 0x40 /* enable SMM */ 85 86#endif /* !_DEV_IC_I8259_H_ */ 87