1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1993 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp 32 */ 33 34/* 35 * Register definitions for the Intel 8253 Programmable Interval Timer. 36 * 37 * This chip has three independent 16-bit down counters that can be 38 * read on the fly. There are three mode registers and three countdown 39 * registers. The countdown registers are addressed directly, via the 40 * first three I/O ports. The three mode registers are accessed via 41 * the fourth I/O port, with two bits in the mode byte indicating the 42 * register. (Why are hardware interfaces always so braindead?). 43 * 44 * To write a value into the countdown register, the mode register 45 * is first programmed with a command indicating the which byte of 46 * the two byte register is to be modified. The three possibilities 47 * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then 48 * msb (TMR_MR_BOTH). 49 * 50 * To read the current value ("on the fly") from the countdown register, 51 * you write a "latch" command into the mode register, then read the stable 52 * value from the corresponding I/O port. For example, you write 53 * TMR_MR_LATCH into the corresponding mode register. Presumably, 54 * after doing this, a write operation to the I/O port would result 55 * in undefined behavior (but hopefully not fry the chip). 56 * Reading in this manner has no side effects. 57 */ 58 59/* 60 * Macros for specifying values to be written into a mode register. 61 */ 62#define TIMER_REG_CNTR0 0 /* timer 0 counter port */ 63#define TIMER_REG_CNTR1 1 /* timer 1 counter port */ 64#define TIMER_REG_CNTR2 2 /* timer 2 counter port */ 65#define TIMER_REG_MODE 3 /* timer mode port */ 66#define TIMER_SEL0 0x00 /* select counter 0 */ 67#define TIMER_SEL1 0x40 /* select counter 1 */ 68#define TIMER_SEL2 0x80 /* select counter 2 */ 69#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 70#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 71#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 72#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 73#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 74#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 75#define TIMER_LATCH 0x00 /* latch counter for reading */ 76#define TIMER_LSB 0x10 /* r/w counter LSB */ 77#define TIMER_MSB 0x20 /* r/w counter MSB */ 78#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 79#define TIMER_BCD 0x01 /* count in BCD */ 80