1/* 2 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all copies. 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 13 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16#ifndef __AR40XX_REG_H__ 17#define __AR40XX_REG_H__ 18 19/* 20 * Register manipulation macros that expect bit field defines 21 * to follow the convention that an _S suffix is appended for 22 * a shift count, while the field mask has no suffix. 23 */ 24#define SM(_v, _f) (((_v) << _f##_S) & (_f)) 25#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) 26 27#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s) 28#define BIT(_n) (1UL << (_n)) 29 30#define AR40XX_PORT_LINK_UP 1 31#define AR40XX_PORT_LINK_DOWN 0 32#define AR40XX_QM_NOT_EMPTY 1 33#define AR40XX_QM_EMPTY 0 34 35#define AR40XX_LAN_VLAN 1 36#define AR40XX_WAN_VLAN 2 37 38enum ar40xx_port_wrapper_cfg { 39 PORT_WRAPPER_PSGMII = 0, 40}; 41 42struct ar40xx_mib_desc { 43 uint32_t size; 44 uint32_t offset; 45 const char *name; 46}; 47 48#define AR40XX_PORT_CPU 0 49 50#define AR40XX_PSGMII_MODE_CONTROL 0x1b4 51#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0) 52 53#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288 54 55#define AR40XX_MII_ATH_MMD_ADDR 0x0d 56#define AR40XX_MII_ATH_MMD_DATA 0x0e 57#define AR40XX_MII_ATH_DBG_ADDR 0x1d 58#define AR40XX_MII_ATH_DBG_DATA 0x1e 59 60#define AR40XX_STATS_RXBROAD 0x00 61#define AR40XX_STATS_RXPAUSE 0x04 62#define AR40XX_STATS_RXMULTI 0x08 63#define AR40XX_STATS_RXFCSERR 0x0c 64#define AR40XX_STATS_RXALIGNERR 0x10 65#define AR40XX_STATS_RXRUNT 0x14 66#define AR40XX_STATS_RXFRAGMENT 0x18 67#define AR40XX_STATS_RX64BYTE 0x1c 68#define AR40XX_STATS_RX128BYTE 0x20 69#define AR40XX_STATS_RX256BYTE 0x24 70#define AR40XX_STATS_RX512BYTE 0x28 71#define AR40XX_STATS_RX1024BYTE 0x2c 72#define AR40XX_STATS_RX1518BYTE 0x30 73#define AR40XX_STATS_RXMAXBYTE 0x34 74#define AR40XX_STATS_RXTOOLONG 0x38 75#define AR40XX_STATS_RXGOODBYTE 0x3c 76#define AR40XX_STATS_RXBADBYTE 0x44 77#define AR40XX_STATS_RXOVERFLOW 0x4c 78#define AR40XX_STATS_FILTERED 0x50 79#define AR40XX_STATS_TXBROAD 0x54 80#define AR40XX_STATS_TXPAUSE 0x58 81#define AR40XX_STATS_TXMULTI 0x5c 82#define AR40XX_STATS_TXUNDERRUN 0x60 83#define AR40XX_STATS_TX64BYTE 0x64 84#define AR40XX_STATS_TX128BYTE 0x68 85#define AR40XX_STATS_TX256BYTE 0x6c 86#define AR40XX_STATS_TX512BYTE 0x70 87#define AR40XX_STATS_TX1024BYTE 0x74 88#define AR40XX_STATS_TX1518BYTE 0x78 89#define AR40XX_STATS_TXMAXBYTE 0x7c 90#define AR40XX_STATS_TXOVERSIZE 0x80 91#define AR40XX_STATS_TXBYTE 0x84 92#define AR40XX_STATS_TXCOLLISION 0x8c 93#define AR40XX_STATS_TXABORTCOL 0x90 94#define AR40XX_STATS_TXMULTICOL 0x94 95#define AR40XX_STATS_TXSINGLECOL 0x98 96#define AR40XX_STATS_TXEXCDEFER 0x9c 97#define AR40XX_STATS_TXDEFER 0xa0 98#define AR40XX_STATS_TXLATECOL 0xa4 99 100#define AR40XX_REG_MODULE_EN 0x030 101#define AR40XX_MODULE_EN_MIB BIT(0) 102 103#define AR40XX_REG_MIB_FUNC 0x034 104#define AR40XX_MIB_BUSY BIT(17) 105#define AR40XX_MIB_CPU_KEEP BIT(20) 106#define AR40XX_MIB_FUNC BITS(24, 3) 107#define AR40XX_MIB_FUNC_S 24 108#define AR40XX_MIB_FUNC_NO_OP 0x0 109#define AR40XX_MIB_FUNC_FLUSH 0x1 110 111#define AR40XX_ESS_SERVICE_TAG 0x48 112#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17) 113 114#define AR40XX_REG_SW_MAC_ADDR0 0x60 115#define AR40XX_REG_SW_MAC_ADDR0_BYTE4 BITS(8, 8) 116#define AR40XX_REG_SW_MAC_ADDR0_BYTE4_S 8 117#define AR40XX_REG_SW_MAC_ADDR0_BYTE5 BITS(0, 8) 118#define AR40XX_REG_SW_MAC_ADDR0_BYTE5_S 0 119 120#define AR40XX_REG_SW_MAC_ADDR1 0x64 121#define AR40XX_REG_SW_MAC_ADDR1_BYTE0 BITS(24, 8) 122#define AR40XX_REG_SW_MAC_ADDR1_BYTE0_S 24 123#define AR40XX_REG_SW_MAC_ADDR1_BYTE1 BITS(16, 8) 124#define AR40XX_REG_SW_MAC_ADDR1_BYTE1_S 16 125#define AR40XX_REG_SW_MAC_ADDR1_BYTE2 BITS(8, 8) 126#define AR40XX_REG_SW_MAC_ADDR1_BYTE2_S 8 127#define AR40XX_REG_SW_MAC_ADDR1_BYTE3 BITS(0, 8) 128#define AR40XX_REG_SW_MAC_ADDR1_BYTE3_S 0 129 130#define AR40XX_REG_MAX_FRAME_SIZE 0x078 131#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14) 132 133#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 134#define AR40XX_PORT_SPEED BITS(0, 2) 135#define AR40XX_PORT_STATUS_SPEED_S 0 136#define AR40XX_PORT_TX_EN BIT(2) 137#define AR40XX_PORT_RX_EN BIT(3) 138#define AR40XX_PORT_STATUS_TXFLOW BIT(4) 139#define AR40XX_PORT_STATUS_RXFLOW BIT(5) 140#define AR40XX_PORT_DUPLEX BIT(6) 141#define AR40XX_PORT_TXHALF_FLOW BIT(7) 142#define AR40XX_PORT_STATUS_LINK_UP BIT(8) 143#define AR40XX_PORT_AUTO_LINK_EN BIT(9) 144#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12) 145 146#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) 147 148#define AR40XX_REG_EEE_CTRL 0x100 149#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) 150 151#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) 152#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12) 153#define AR40XX_PORT_VLAN0_DEF_SVID_S 0 154#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12) 155#define AR40XX_PORT_VLAN0_DEF_CVID_S 16 156 157#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) 158#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9) 159#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7) 160#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6) 161#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2) 162#define AR40XX_PORT_VLAN1_OUT_MODE_S 12 163#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0 164#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1 165#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2 166#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3 167 168#define AR40XX_REG_ATU_DATA0 0x600 169#define AR40XX_ATU_DATA0_MAC_ADDR3 BITS(0, 8) 170#define AR40XX_ATU_DATA0_MAC_ADDR3_S 0 171#define AR40XX_ATU_DATA0_MAC_ADDR2 BITS(8, 8) 172#define AR40XX_ATU_DATA0_MAC_ADDR2_S 8 173#define AR40XX_ATU_DATA0_MAC_ADDR1 BITS(16, 8) 174#define AR40XX_ATU_DATA0_MAC_ADDR1_S 16 175#define AR40XX_ATU_DATA0_MAC_ADDR0 BITS(24, 8) 176#define AR40XX_ATU_DATA0_MAC_ADDR0_S 24 177 178#define AR40XX_REG_ATU_DATA1 0x604 179#define AR40XX_ATU_DATA1_MAC_ADDR4 BITS(0, 8) 180#define AR40XX_ATU_DATA1_MAC_ADDR4_S 0 181#define AR40XX_ATU_DATA1_MAC_ADDR5 BITS(8, 8) 182#define AR40XX_ATU_DATA1_MAC_ADDR5_S 8 183#define AR40XX_ATU_DATA1_DEST_PORT BITS(16, 7) 184#define AR40XX_ATU_DATA1_DEST_PORT_S 16 185#define AR40XX_ATU_DATA1_CROSS_PORT_STATE_EN BIT(23) 186#define AR40XX_ATU_DATA1_PRI BITS(24, 3) 187#define AR40XX_ATU_DATA1_SVL_ENTRY BIT(27) 188#define AR40XX_ATU_DATA1_PRI_OVER_EN BIT(28) 189#define AR40XX_ATU_DATA1_MIRROR_EN BIT(29) 190#define AR40XX_ATU_DATA1_SA_DROP_EN BIT(30) 191#define AR40XX_ATU_DATA1_HASH_HIGH_ADDR BIT(31) 192 193#define AR40XX_REG_ATU_DATA2 0x608 194#define AR40XX_ATU_FUNC_DATA2_STATUS BITS(0, 4) 195#define AR40XX_ATU_FUNC_DATA2_STATUS_S 0 196#define AR40XX_ATU_FUNC_DATA2_VLAN_LEAKY_EN BIT(4) 197#define AR40XX_ATU_FUNC_DATA2_REDIRECT_TO_CPU BIT(5) 198#define AR40XX_ATU_FUNC_DATA2_COPY_TO_CPU BIT(6) 199#define AR40XX_ATU_FUNC_DATA2_SHORT_LOOP BIT(7) 200#define AR40XX_ATU_FUNC_DATA2_ATU_VID BITS(8, 12) 201#define AR40XX_ATU_FUNC_DATA2_ATU_VID_S 8 202 203#define AR40XX_REG_ATU_FUNC 0x60c 204#define AR40XX_ATU_FUNC_OP BITS(0, 4) 205#define AR40XX_ATU_FUNC_OP_NOOP 0x0 206#define AR40XX_ATU_FUNC_OP_FLUSH 0x1 207#define AR40XX_ATU_FUNC_OP_LOAD 0x2 208#define AR40XX_ATU_FUNC_OP_PURGE 0x3 209#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4 210#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5 211#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6 212#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7 213#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8 214#define AR40XX_ATU_FUNC_PORT_NUM BITS(8, 4) 215#define AR40XX_ATU_FUNC_PORT_NUM_S 8 216#define AR40XX_ATU_FUNC_BUSY BIT(31) 217 218 219 220#define AR40XX_REG_VTU_FUNC0 0x0610 221#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14) 222#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 223#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0 224#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1 225#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2 226#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3 227#define AR40XX_VTU_FUNC0_IVL BIT(19) 228#define AR40XX_VTU_FUNC0_VALID BIT(20) 229 230#define AR40XX_REG_VTU_FUNC1 0x0614 231#define AR40XX_VTU_FUNC1_OP BITS(0, 3) 232#define AR40XX_VTU_FUNC1_OP_NOOP 0 233#define AR40XX_VTU_FUNC1_OP_FLUSH 1 234#define AR40XX_VTU_FUNC1_OP_LOAD 2 235#define AR40XX_VTU_FUNC1_OP_PURGE 3 236#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4 237#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5 238#define AR40XX_VTU_FUNC1_OP_GET_ONE 6 239#define AR40XX_VTU_FUNC1_FULL BIT(4) 240#define AR40XX_VTU_FUNC1_PORT BIT(8, 4) 241#define AR40XX_VTU_FUNC1_PORT_S 8 242#define AR40XX_VTU_FUNC1_VID BIT(16, 12) 243#define AR40XX_VTU_FUNC1_VID_S 16 244#define AR40XX_VTU_FUNC1_BUSY BIT(31) 245 246#define AR40XX_REG_FWD_CTRL0 0x620 247#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10) 248#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4) 249#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4 250 251#define AR40XX_REG_FWD_CTRL1 0x624 252#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7) 253#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0 254#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7) 255#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8 256#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7) 257#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16 258#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7) 259#define AR40XX_FWD_CTRL1_IGMP_S 24 260 261#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) 262#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7) 263#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2) 264#define AR40XX_PORT_LOOKUP_IN_MODE_S 8 265#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3) 266#define AR40XX_PORT_LOOKUP_STATE_S 16 267#define AR40XX_PORT_LOOKUP_LEARN BIT(20) 268#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21) 269#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25) 270 271#define AR40XX_REG_QM_DEBUG_ADDR 0x820 272#define AR40XX_REG_QM_DEBUG_VALUE 0x824 273#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d 274#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e 275 276#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) 277#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) 278 279#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4) 280#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60 281#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90 282 283#define AR40XX_PHY_DEBUG_0 0 284#define AR40XX_PHY_MANU_CTRL_EN BIT(12) 285 286#define AR40XX_PHY_DEBUG_2 2 287 288#define AR40XX_PHY_SPEC_STATUS 0x11 289#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10) 290#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13) 291#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2) 292 293/* port forwarding state */ 294enum { 295 AR40XX_PORT_STATE_DISABLED = 0, 296 AR40XX_PORT_STATE_BLOCK = 1, 297 AR40XX_PORT_STATE_LISTEN = 2, 298 AR40XX_PORT_STATE_LEARN = 3, 299 AR40XX_PORT_STATE_FORWARD = 4 300}; 301 302/* ingress 802.1q mode */ 303enum { 304 AR40XX_IN_PORT_ONLY = 0, 305 AR40XX_IN_PORT_FALLBACK = 1, 306 AR40XX_IN_VLAN_ONLY = 2, 307 AR40XX_IN_SECURE = 3 308}; 309 310/* egress 802.1q mode */ 311enum { 312 AR40XX_OUT_KEEP = 0, 313 AR40XX_OUT_STRIP_VLAN = 1, 314 AR40XX_OUT_ADD_VLAN = 2 315}; 316 317/* port speed */ 318enum { 319 AR40XX_PORT_SPEED_10M = 0, 320 AR40XX_PORT_SPEED_100M = 1, 321 AR40XX_PORT_SPEED_1000M = 2, 322 AR40XX_PORT_SPEED_ERR = 3, 323}; 324 325#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */ 326 327#define AR40XX_QM_WORK_DELAY 100 328 329#define AR40XX_MIB_FUNC_CAPTURE 0x3 330 331#define AR40XX_REG_PORT_STATS_START 0x1000 332#define AR40XX_REG_PORT_STATS_LEN 0x100 333 334#define AR40XX_PORTS_ALL 0x3f 335 336#define AR40XX_PSGMII_ID 5 337#define AR40XX_PSGMII_CALB_NUM 100 338#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d 339#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c 340#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a 341#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380 342#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280 343#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a 344#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb 345#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a 346#define AR40XX_MALIBU_PHY_LAST_ADDR 4 347 348#endif /* __AR40XX_REG_H__ */ 349