11541Srgrimes/* SPDX-License-Identifier: BSD-3-Clause 21541Srgrimes * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 31541Srgrimes * Copyright 2007 Nuova Systems, Inc. All rights reserved. 41541Srgrimes */ 51541Srgrimes 61541Srgrimes#ifndef _VNIC_ENIC_H_ 71541Srgrimes#define _VNIC_ENIC_H_ 81541Srgrimes 91541Srgrimes/* Hardware intr coalesce timer is in units of 1.5us */ 101541Srgrimes#define INTR_COALESCE_USEC_TO_HW(usec) ((usec) * 2 / 3) 111541Srgrimes#define INTR_COALESCE_HW_TO_USEC(usec) ((usec) * 3 / 2) 121541Srgrimes 131541Srgrimes/* Device-specific region: enet configuration */ 141541Srgrimesstruct vnic_enet_config { 151541Srgrimes u32 flags; 161541Srgrimes u32 wq_desc_count; 171541Srgrimes u32 rq_desc_count; 181541Srgrimes u16 mtu; 191541Srgrimes u16 intr_timer_deprecated; 201541Srgrimes u8 intr_timer_type; 211541Srgrimes u8 intr_mode; 221541Srgrimes char devname[16]; 231541Srgrimes u32 intr_timer_usec; 241541Srgrimes u16 loop_tag; 251541Srgrimes u16 vf_rq_count; 261541Srgrimes u16 num_arfs; 271541Srgrimes u64 mem_paddr; 281541Srgrimes u16 rdma_qp_id; 291541Srgrimes u16 rdma_qp_count; 301541Srgrimes u16 rdma_resgrp; 311541Srgrimes u32 rdma_mr_id; 321541Srgrimes u32 rdma_mr_count; 331541Srgrimes u32 max_pkt_size; 341541Srgrimes}; 351541Srgrimes 361541Srgrimes#define VENETF_TSO 0x1 /* TSO enabled */ 3712588Sbde#define VENETF_LRO 0x2 /* LRO enabled */ 381541Srgrimes#define VENETF_RXCSUM 0x4 /* RX csum enabled */ 391541Srgrimes#define VENETF_TXCSUM 0x8 /* TX csum enabled */ 401541Srgrimes#define VENETF_RSS 0x10 /* RSS enabled */ 411541Srgrimes#define VENETF_RSSHASH_IPV4 0x20 /* Hash on IPv4 fields */ 421541Srgrimes#define VENETF_RSSHASH_TCPIPV4 0x40 /* Hash on TCP + IPv4 fields */ 431541Srgrimes#define VENETF_RSSHASH_IPV6 0x80 /* Hash on IPv6 fields */ 441541Srgrimes#define VENETF_RSSHASH_TCPIPV6 0x100 /* Hash on TCP + IPv6 fields */ 451541Srgrimes#define VENETF_RSSHASH_IPV6_EX 0x200 /* Hash on IPv6 extended fields */ 461541Srgrimes#define VENETF_RSSHASH_TCPIPV6_EX 0x400 /* Hash on TCP + IPv6 ext. fields */ 471541Srgrimes#define VENETF_LOOP 0x800 /* Loopback enabled */ 481541Srgrimes#define VENETF_FAILOVER 0x1000 /* Fabric failover enabled */ 491541Srgrimes#define VENETF_USPACE_NIC 0x2000 /* vHPC enabled */ 501541Srgrimes#define VENETF_VMQ 0x4000 /* VMQ enabled */ 511541Srgrimes#define VENETF_ARFS 0x8000 /* ARFS enabled */ 523305Sphk#define VENETF_VXLAN 0x10000 /* VxLAN offload */ 531541Srgrimes#define VENETF_NVGRE 0x20000 /* NVGRE offload */ 541541Srgrimes#define VENETF_GRPINTR 0x40000 /* group interrupt */ 557090Sbde#define VENETF_NICSWITCH 0x80000 /* NICSWITCH enabled */ 567090Sbde#define VENETF_RSSHASH_UDPIPV4 0x100000 /* Hash on UDP + IPv4 fields */ 571541Srgrimes#define VENETF_RSSHASH_UDPIPV6 0x200000 /* Hash on UDP + IPv6 fields */ 581541Srgrimes 591541Srgrimes#define VENET_INTR_TYPE_MIN 0 /* Timer specs min interrupt spacing */ 601541Srgrimes#define VENET_INTR_TYPE_IDLE 1 /* Timer specs idle time before irq */ 611541Srgrimes 629336Sdfr#define VENET_INTR_MODE_ANY 0 /* Try MSI-X, then MSI, then INTx */ 631541Srgrimes#define VENET_INTR_MODE_MSI 1 /* Try MSI then INTx */ 649336Sdfr#define VENET_INTR_MODE_INTX 2 /* Try INTx only */ 651541Srgrimes 661541Srgrimes#endif /* _VNIC_ENIC_H_ */ 671541Srgrimes