1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Alstom Group.
5 * Copyright (c) 2021 Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef _ENETC_MDIO_H_
29#define _ENETC_MDIO_H_
30
31/* MDIO registers */
32#define ENETC_MDIO_CFG		0x0	/* MDIO configuration and status */
33#define MDIO_CFG_CLKDIV(x)	((((x) >> 1) & 0xff) << 8)
34
35#define ENETC_MDIO_CTL		0x4	/* MDIO control */
36#define MDIO_CTL_DEV_ADDR(x)	((x) & 0x1f)
37#define MDIO_CTL_PORT_ADDR(x)	(((x) & 0x1f) << 5)
38
39#define ENETC_MDIO_DATA		0x8	/* MDIO data */
40#define MDIO_DATA(x)		((x) & 0xffff)
41
42#define ENETC_MDIO_ADDR		0xc	/* MDIO address */
43
44#define MDIO_CFG_BSY		BIT(0)
45#define MDIO_CFG_RD_ER		BIT(1)
46#define MDIO_CFG_ENC45		BIT(6)
47#define MDIO_CFG_NEG		BIT(23)
48#define MDIO_CTL_READ		BIT(15)
49#define MII_ADDR_C45		BIT(30)
50
51/* MDIO configuration and helpers */
52#define ENETC_MDC_DIV		258
53#define ENETC_TIMEOUT		1000
54
55int enetc_mdio_write(struct resource*, int, int, int, int);
56int enetc_mdio_read(struct resource*, int, int, int);
57
58#endif
59