1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2021 Alstom Group.
5 * Copyright (c) 2021 Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27#ifndef _ENETC_H_
28#define _ENETC_H_
29
30#include <sys/param.h>
31
32#include <dev/enetc/enetc_hw.h>
33
34struct enetc_softc;
35struct enetc_rx_queue {
36	struct enetc_softc	*sc;
37	uint16_t		qid;
38
39	union enetc_rx_bd	*ring;
40	uint64_t		ring_paddr;
41
42	struct if_irq		irq;
43	bool			enabled;
44};
45
46struct enetc_tx_queue {
47	struct enetc_softc	*sc;
48
49	union enetc_tx_bd	*ring;
50	uint64_t		ring_paddr;
51
52	qidx_t			cidx;
53
54	struct if_irq		irq;
55};
56
57struct enetc_ctrl_queue {
58	qidx_t			pidx;
59
60	struct iflib_dma_info	dma;
61	struct enetc_cbd	*ring;
62
63	struct if_irq		irq;
64};
65
66struct enetc_softc {
67	device_t	dev;
68
69	struct mtx	mii_lock;
70
71	if_ctx_t	ctx;
72	if_softc_ctx_t	shared;
73#define tx_num_queues	shared->isc_ntxqsets
74#define rx_num_queues	shared->isc_nrxqsets
75#define tx_queue_size	shared->isc_ntxd[0]
76#define rx_queue_size	shared->isc_nrxd[0]
77
78	struct resource	*regs;
79
80	device_t	miibus;
81
82	struct enetc_tx_queue	*tx_queues;
83	struct enetc_rx_queue	*rx_queues;
84	struct enetc_ctrl_queue	ctrl_queue;
85
86	/* Default RX queue configuration. */
87	uint32_t		rbmr;
88	/*
89	 * Hardware VLAN hash based filtering uses a 64bit bitmap.
90	 * We need to know how many vids are in given position to
91	 * know when to remove the bit from the bitmap.
92	 */
93#define	VLAN_BITMAP_SIZE	64
94	uint8_t			vlan_bitmap[64];
95
96	struct if_irq		admin_irq;
97	int			phy_addr;
98
99	struct ifmedia		fixed_ifmedia;
100	bool			fixed_link;
101};
102
103#define ENETC_RD4(sc, reg)	\
104	bus_read_4((sc)->regs, reg)
105#define ENETC_WR4(sc, reg, value)	\
106	bus_write_4((sc)->regs, reg, value)
107
108#define ENETC_PORT_RD8(sc, reg) \
109	bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg))
110#define ENETC_PORT_RD4(sc, reg) \
111	bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg))
112#define ENETC_PORT_WR4(sc, reg, value) \
113	bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value)
114#define ENETC_PORT_RD2(sc, reg) \
115	bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg))
116#define ENETC_PORT_WR2(sc, reg, value) \
117	bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value)
118
119#define ENETC_TXQ_RD4(sc, q, reg) \
120	ENETC_RD4((sc), ENETC_BDR(TX, q, reg))
121#define ENETC_TXQ_WR4(sc, q, reg, value) \
122	ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value)
123#define ENETC_RXQ_RD4(sc, q, reg) \
124	ENETC_RD4((sc), ENETC_BDR(RX, q, reg))
125#define ENETC_RXQ_WR4(sc, q, reg, value) \
126	ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value)
127
128/* Device constants */
129
130#define ENETC_MAX_FRAME_LEN	9600
131
132#define ENETC_MAX_QUEUES	4
133
134/* Max supported nr of descriptors per frame. */
135#define ENETC_MAX_SCATTER	15
136
137/*
138 * Up to 4096 transmit/receive descriptors are supported,
139 * their number has to be a multiple of 64.
140 */
141#define ENETC_MIN_DESC		64
142#define ENETC_MAX_DESC		4096
143#define ENETC_DEFAULT_DESC	512
144#define ENETC_DESC_ALIGN	64
145
146/* Rings have to be 128B aligned. */
147#define ENETC_RING_ALIGN	128
148
149#define ENETC_MSIX_COUNT	32
150
151#define ENETC_RX_INTR_PKT_THR	16
152
153/* Rx threshold irq timeout, 100us */
154#define ENETC_RX_INTR_TIME_THR	((100ULL * ENETC_CLK) / 1000000ULL)
155
156#define ENETC_RX_IP_ALIGN	2
157
158#endif
159