1/****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33******************************************************************************/ 34 35#include "e1000_api.h" 36 37static void e1000_reload_nvm_generic(struct e1000_hw *hw); 38 39/** 40 * e1000_init_nvm_ops_generic - Initialize NVM function pointers 41 * @hw: pointer to the HW structure 42 * 43 * Setups up the function pointers to no-op functions 44 **/ 45void e1000_init_nvm_ops_generic(struct e1000_hw *hw) 46{ 47 struct e1000_nvm_info *nvm = &hw->nvm; 48 DEBUGFUNC("e1000_init_nvm_ops_generic"); 49 50 /* Initialize function pointers */ 51 nvm->ops.init_params = e1000_null_ops_generic; 52 nvm->ops.acquire = e1000_null_ops_generic; 53 nvm->ops.read = e1000_null_read_nvm; 54 nvm->ops.release = e1000_null_nvm_generic; 55 nvm->ops.reload = e1000_reload_nvm_generic; 56 nvm->ops.update = e1000_null_ops_generic; 57 nvm->ops.valid_led_default = e1000_null_led_default; 58 nvm->ops.validate = e1000_null_ops_generic; 59 nvm->ops.write = e1000_null_write_nvm; 60} 61 62/** 63 * e1000_null_nvm_read - No-op function, return 0 64 * @hw: pointer to the HW structure 65 * @a: dummy variable 66 * @b: dummy variable 67 * @c: dummy variable 68 **/ 69s32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw, 70 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, 71 u16 E1000_UNUSEDARG *c) 72{ 73 DEBUGFUNC("e1000_null_read_nvm"); 74 return E1000_SUCCESS; 75} 76 77/** 78 * e1000_null_nvm_generic - No-op function, return void 79 * @hw: pointer to the HW structure 80 **/ 81void e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw) 82{ 83 DEBUGFUNC("e1000_null_nvm_generic"); 84 return; 85} 86 87/** 88 * e1000_null_led_default - No-op function, return 0 89 * @hw: pointer to the HW structure 90 * @data: dummy variable 91 **/ 92s32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw, 93 u16 E1000_UNUSEDARG *data) 94{ 95 DEBUGFUNC("e1000_null_led_default"); 96 return E1000_SUCCESS; 97} 98 99/** 100 * e1000_null_write_nvm - No-op function, return 0 101 * @hw: pointer to the HW structure 102 * @a: dummy variable 103 * @b: dummy variable 104 * @c: dummy variable 105 **/ 106s32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw, 107 u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b, 108 u16 E1000_UNUSEDARG *c) 109{ 110 DEBUGFUNC("e1000_null_write_nvm"); 111 return E1000_SUCCESS; 112} 113 114/** 115 * e1000_raise_eec_clk - Raise EEPROM clock 116 * @hw: pointer to the HW structure 117 * @eecd: pointer to the EEPROM 118 * 119 * Enable/Raise the EEPROM clock bit. 120 **/ 121static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 122{ 123 *eecd = *eecd | E1000_EECD_SK; 124 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 125 E1000_WRITE_FLUSH(hw); 126 usec_delay(hw->nvm.delay_usec); 127} 128 129/** 130 * e1000_lower_eec_clk - Lower EEPROM clock 131 * @hw: pointer to the HW structure 132 * @eecd: pointer to the EEPROM 133 * 134 * Clear/Lower the EEPROM clock bit. 135 **/ 136static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 137{ 138 *eecd = *eecd & ~E1000_EECD_SK; 139 E1000_WRITE_REG(hw, E1000_EECD, *eecd); 140 E1000_WRITE_FLUSH(hw); 141 usec_delay(hw->nvm.delay_usec); 142} 143 144/** 145 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM 146 * @hw: pointer to the HW structure 147 * @data: data to send to the EEPROM 148 * @count: number of bits to shift out 149 * 150 * We need to shift 'count' bits out to the EEPROM. So, the value in the 151 * "data" parameter will be shifted out to the EEPROM one bit at a time. 152 * In order to do this, "data" must be broken down into bits. 153 **/ 154static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 155{ 156 struct e1000_nvm_info *nvm = &hw->nvm; 157 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 158 u32 mask; 159 160 DEBUGFUNC("e1000_shift_out_eec_bits"); 161 162 mask = 0x01 << (count - 1); 163 if (nvm->type == e1000_nvm_eeprom_microwire) 164 eecd &= ~E1000_EECD_DO; 165 else 166 if (nvm->type == e1000_nvm_eeprom_spi) 167 eecd |= E1000_EECD_DO; 168 169 do { 170 eecd &= ~E1000_EECD_DI; 171 172 if (data & mask) 173 eecd |= E1000_EECD_DI; 174 175 E1000_WRITE_REG(hw, E1000_EECD, eecd); 176 E1000_WRITE_FLUSH(hw); 177 178 usec_delay(nvm->delay_usec); 179 180 e1000_raise_eec_clk(hw, &eecd); 181 e1000_lower_eec_clk(hw, &eecd); 182 183 mask >>= 1; 184 } while (mask); 185 186 eecd &= ~E1000_EECD_DI; 187 E1000_WRITE_REG(hw, E1000_EECD, eecd); 188} 189 190/** 191 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM 192 * @hw: pointer to the HW structure 193 * @count: number of bits to shift in 194 * 195 * In order to read a register from the EEPROM, we need to shift 'count' bits 196 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 197 * the EEPROM (setting the SK bit), and then reading the value of the data out 198 * "DO" bit. During this "shifting in" process the data in "DI" bit should 199 * always be clear. 200 **/ 201static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 202{ 203 u32 eecd; 204 u32 i; 205 u16 data; 206 207 DEBUGFUNC("e1000_shift_in_eec_bits"); 208 209 eecd = E1000_READ_REG(hw, E1000_EECD); 210 211 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 212 data = 0; 213 214 for (i = 0; i < count; i++) { 215 data <<= 1; 216 e1000_raise_eec_clk(hw, &eecd); 217 218 eecd = E1000_READ_REG(hw, E1000_EECD); 219 220 eecd &= ~E1000_EECD_DI; 221 if (eecd & E1000_EECD_DO) 222 data |= 1; 223 224 e1000_lower_eec_clk(hw, &eecd); 225 } 226 227 return data; 228} 229 230/** 231 * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion 232 * @hw: pointer to the HW structure 233 * @ee_reg: EEPROM flag for polling 234 * 235 * Polls the EEPROM status bit for either read or write completion based 236 * upon the value of 'ee_reg'. 237 **/ 238s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 239{ 240 u32 attempts = 100000; 241 u32 i, reg = 0; 242 243 DEBUGFUNC("e1000_poll_eerd_eewr_done"); 244 245 for (i = 0; i < attempts; i++) { 246 if (ee_reg == E1000_NVM_POLL_READ) 247 reg = E1000_READ_REG(hw, E1000_EERD); 248 else 249 reg = E1000_READ_REG(hw, E1000_EEWR); 250 251 if (reg & E1000_NVM_RW_REG_DONE) 252 return E1000_SUCCESS; 253 254 usec_delay(5); 255 } 256 257 return -E1000_ERR_NVM; 258} 259 260/** 261 * e1000_acquire_nvm_generic - Generic request for access to EEPROM 262 * @hw: pointer to the HW structure 263 * 264 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 265 * Return successful if access grant bit set, else clear the request for 266 * EEPROM access and return -E1000_ERR_NVM (-1). 267 **/ 268s32 e1000_acquire_nvm_generic(struct e1000_hw *hw) 269{ 270 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 271 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 272 273 DEBUGFUNC("e1000_acquire_nvm_generic"); 274 275 E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ); 276 eecd = E1000_READ_REG(hw, E1000_EECD); 277 278 while (timeout) { 279 if (eecd & E1000_EECD_GNT) 280 break; 281 usec_delay(5); 282 eecd = E1000_READ_REG(hw, E1000_EECD); 283 timeout--; 284 } 285 286 if (!timeout) { 287 eecd &= ~E1000_EECD_REQ; 288 E1000_WRITE_REG(hw, E1000_EECD, eecd); 289 DEBUGOUT("Could not acquire NVM grant\n"); 290 return -E1000_ERR_NVM; 291 } 292 293 return E1000_SUCCESS; 294} 295 296/** 297 * e1000_standby_nvm - Return EEPROM to standby state 298 * @hw: pointer to the HW structure 299 * 300 * Return the EEPROM to a standby state. 301 **/ 302static void e1000_standby_nvm(struct e1000_hw *hw) 303{ 304 struct e1000_nvm_info *nvm = &hw->nvm; 305 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 306 307 DEBUGFUNC("e1000_standby_nvm"); 308 309 if (nvm->type == e1000_nvm_eeprom_microwire) { 310 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 311 E1000_WRITE_REG(hw, E1000_EECD, eecd); 312 E1000_WRITE_FLUSH(hw); 313 usec_delay(nvm->delay_usec); 314 315 e1000_raise_eec_clk(hw, &eecd); 316 317 /* Select EEPROM */ 318 eecd |= E1000_EECD_CS; 319 E1000_WRITE_REG(hw, E1000_EECD, eecd); 320 E1000_WRITE_FLUSH(hw); 321 usec_delay(nvm->delay_usec); 322 323 e1000_lower_eec_clk(hw, &eecd); 324 } else if (nvm->type == e1000_nvm_eeprom_spi) { 325 /* Toggle CS to flush commands */ 326 eecd |= E1000_EECD_CS; 327 E1000_WRITE_REG(hw, E1000_EECD, eecd); 328 E1000_WRITE_FLUSH(hw); 329 usec_delay(nvm->delay_usec); 330 eecd &= ~E1000_EECD_CS; 331 E1000_WRITE_REG(hw, E1000_EECD, eecd); 332 E1000_WRITE_FLUSH(hw); 333 usec_delay(nvm->delay_usec); 334 } 335} 336 337/** 338 * e1000_stop_nvm - Terminate EEPROM command 339 * @hw: pointer to the HW structure 340 * 341 * Terminates the current command by inverting the EEPROM's chip select pin. 342 **/ 343void e1000_stop_nvm(struct e1000_hw *hw) 344{ 345 u32 eecd; 346 347 DEBUGFUNC("e1000_stop_nvm"); 348 349 eecd = E1000_READ_REG(hw, E1000_EECD); 350 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 351 /* Pull CS high */ 352 eecd |= E1000_EECD_CS; 353 e1000_lower_eec_clk(hw, &eecd); 354 } else if (hw->nvm.type == e1000_nvm_eeprom_microwire) { 355 /* CS on Microwire is active-high */ 356 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 357 E1000_WRITE_REG(hw, E1000_EECD, eecd); 358 e1000_raise_eec_clk(hw, &eecd); 359 e1000_lower_eec_clk(hw, &eecd); 360 } 361} 362 363/** 364 * e1000_release_nvm_generic - Release exclusive access to EEPROM 365 * @hw: pointer to the HW structure 366 * 367 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 368 **/ 369void e1000_release_nvm_generic(struct e1000_hw *hw) 370{ 371 u32 eecd; 372 373 DEBUGFUNC("e1000_release_nvm_generic"); 374 375 e1000_stop_nvm(hw); 376 377 eecd = E1000_READ_REG(hw, E1000_EECD); 378 eecd &= ~E1000_EECD_REQ; 379 E1000_WRITE_REG(hw, E1000_EECD, eecd); 380} 381 382/** 383 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write 384 * @hw: pointer to the HW structure 385 * 386 * Setups the EEPROM for reading and writing. 387 **/ 388static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) 389{ 390 struct e1000_nvm_info *nvm = &hw->nvm; 391 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 392 u8 spi_stat_reg; 393 394 DEBUGFUNC("e1000_ready_nvm_eeprom"); 395 396 if (nvm->type == e1000_nvm_eeprom_microwire) { 397 /* Clear SK and DI */ 398 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 399 E1000_WRITE_REG(hw, E1000_EECD, eecd); 400 /* Set CS */ 401 eecd |= E1000_EECD_CS; 402 E1000_WRITE_REG(hw, E1000_EECD, eecd); 403 } else if (nvm->type == e1000_nvm_eeprom_spi) { 404 u16 timeout = NVM_MAX_RETRY_SPI; 405 406 /* Clear SK and CS */ 407 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 408 E1000_WRITE_REG(hw, E1000_EECD, eecd); 409 E1000_WRITE_FLUSH(hw); 410 usec_delay(1); 411 412 /* Read "Status Register" repeatedly until the LSB is cleared. 413 * The EEPROM will signal that the command has been completed 414 * by clearing bit 0 of the internal status register. If it's 415 * not cleared within 'timeout', then error out. 416 */ 417 while (timeout) { 418 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 419 hw->nvm.opcode_bits); 420 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8); 421 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 422 break; 423 424 usec_delay(5); 425 e1000_standby_nvm(hw); 426 timeout--; 427 } 428 429 if (!timeout) { 430 DEBUGOUT("SPI NVM Status error\n"); 431 return -E1000_ERR_NVM; 432 } 433 } 434 435 return E1000_SUCCESS; 436} 437 438/** 439 * e1000_read_nvm_spi - Read EEPROM's using SPI 440 * @hw: pointer to the HW structure 441 * @offset: offset of word in the EEPROM to read 442 * @words: number of words to read 443 * @data: word read from the EEPROM 444 * 445 * Reads a 16 bit word from the EEPROM. 446 **/ 447s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 448{ 449 struct e1000_nvm_info *nvm = &hw->nvm; 450 u32 i = 0; 451 s32 ret_val; 452 u16 word_in; 453 u8 read_opcode = NVM_READ_OPCODE_SPI; 454 455 DEBUGFUNC("e1000_read_nvm_spi"); 456 457 /* A check for invalid values: offset too large, too many words, 458 * and not enough words. 459 */ 460 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 461 (words == 0)) { 462 DEBUGOUT("nvm parameter(s) out of bounds\n"); 463 return -E1000_ERR_NVM; 464 } 465 466 ret_val = nvm->ops.acquire(hw); 467 if (ret_val) 468 return ret_val; 469 470 ret_val = e1000_ready_nvm_eeprom(hw); 471 if (ret_val) 472 goto release; 473 474 e1000_standby_nvm(hw); 475 476 if ((nvm->address_bits == 8) && (offset >= 128)) 477 read_opcode |= NVM_A8_OPCODE_SPI; 478 479 /* Send the READ command (opcode + addr) */ 480 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 481 e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 482 483 /* Read the data. SPI NVMs increment the address with each byte 484 * read and will roll over if reading beyond the end. This allows 485 * us to read the whole NVM from any offset 486 */ 487 for (i = 0; i < words; i++) { 488 word_in = e1000_shift_in_eec_bits(hw, 16); 489 data[i] = (word_in >> 8) | (word_in << 8); 490 } 491 492release: 493 nvm->ops.release(hw); 494 495 return ret_val; 496} 497 498/** 499 * e1000_read_nvm_microwire - Reads EEPROM's using microwire 500 * @hw: pointer to the HW structure 501 * @offset: offset of word in the EEPROM to read 502 * @words: number of words to read 503 * @data: word read from the EEPROM 504 * 505 * Reads a 16 bit word from the EEPROM. 506 **/ 507s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 508 u16 *data) 509{ 510 struct e1000_nvm_info *nvm = &hw->nvm; 511 u32 i = 0; 512 s32 ret_val; 513 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE; 514 515 DEBUGFUNC("e1000_read_nvm_microwire"); 516 517 /* A check for invalid values: offset too large, too many words, 518 * and not enough words. 519 */ 520 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 521 (words == 0)) { 522 DEBUGOUT("nvm parameter(s) out of bounds\n"); 523 return -E1000_ERR_NVM; 524 } 525 526 ret_val = nvm->ops.acquire(hw); 527 if (ret_val) 528 return ret_val; 529 530 ret_val = e1000_ready_nvm_eeprom(hw); 531 if (ret_val) 532 goto release; 533 534 for (i = 0; i < words; i++) { 535 /* Send the READ command (opcode + addr) */ 536 e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 537 e1000_shift_out_eec_bits(hw, (u16)(offset + i), 538 nvm->address_bits); 539 540 /* Read the data. For microwire, each word requires the 541 * overhead of setup and tear-down. 542 */ 543 data[i] = e1000_shift_in_eec_bits(hw, 16); 544 e1000_standby_nvm(hw); 545 } 546 547release: 548 nvm->ops.release(hw); 549 550 return ret_val; 551} 552 553/** 554 * e1000_read_nvm_eerd - Reads EEPROM using EERD register 555 * @hw: pointer to the HW structure 556 * @offset: offset of word in the EEPROM to read 557 * @words: number of words to read 558 * @data: word read from the EEPROM 559 * 560 * Reads a 16 bit word from the EEPROM using the EERD register. 561 **/ 562s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 563{ 564 struct e1000_nvm_info *nvm = &hw->nvm; 565 u32 i, eerd = 0; 566 s32 ret_val = E1000_SUCCESS; 567 568 DEBUGFUNC("e1000_read_nvm_eerd"); 569 570 /* A check for invalid values: offset too large, too many words, 571 * too many words for the offset, and not enough words. 572 */ 573 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 574 (words == 0)) { 575 DEBUGOUT("nvm parameter(s) out of bounds\n"); 576 return -E1000_ERR_NVM; 577 } 578 579 for (i = 0; i < words; i++) { 580 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) + 581 E1000_NVM_RW_REG_START; 582 583 E1000_WRITE_REG(hw, E1000_EERD, eerd); 584 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 585 if (ret_val) 586 break; 587 588 data[i] = (E1000_READ_REG(hw, E1000_EERD) >> 589 E1000_NVM_RW_REG_DATA); 590 } 591 592 if (ret_val) 593 DEBUGOUT1("NVM read error: %d\n", ret_val); 594 595 return ret_val; 596} 597 598/** 599 * e1000_write_nvm_spi - Write to EEPROM using SPI 600 * @hw: pointer to the HW structure 601 * @offset: offset within the EEPROM to be written to 602 * @words: number of words to write 603 * @data: 16 bit word(s) to be written to the EEPROM 604 * 605 * Writes data to EEPROM at offset using SPI interface. 606 * 607 * If e1000_update_nvm_checksum is not called after this function , the 608 * EEPROM will most likely contain an invalid checksum. 609 **/ 610s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 611{ 612 struct e1000_nvm_info *nvm = &hw->nvm; 613 s32 ret_val = -E1000_ERR_NVM; 614 u16 widx = 0; 615 616 DEBUGFUNC("e1000_write_nvm_spi"); 617 618 /* A check for invalid values: offset too large, too many words, 619 * and not enough words. 620 */ 621 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 622 (words == 0)) { 623 DEBUGOUT("nvm parameter(s) out of bounds\n"); 624 return -E1000_ERR_NVM; 625 } 626 627 while (widx < words) { 628 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 629 630 ret_val = nvm->ops.acquire(hw); 631 if (ret_val) 632 return ret_val; 633 634 ret_val = e1000_ready_nvm_eeprom(hw); 635 if (ret_val) { 636 nvm->ops.release(hw); 637 return ret_val; 638 } 639 640 e1000_standby_nvm(hw); 641 642 /* Send the WRITE ENABLE command (8 bit opcode) */ 643 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 644 nvm->opcode_bits); 645 646 e1000_standby_nvm(hw); 647 648 /* Some SPI eeproms use the 8th address bit embedded in the 649 * opcode 650 */ 651 if ((nvm->address_bits == 8) && (offset >= 128)) 652 write_opcode |= NVM_A8_OPCODE_SPI; 653 654 /* Send the Write command (8-bit opcode + addr) */ 655 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 656 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 657 nvm->address_bits); 658 659 /* Loop to allow for up to whole page write of eeprom */ 660 while (widx < words) { 661 u16 word_out = data[widx]; 662 word_out = (word_out >> 8) | (word_out << 8); 663 e1000_shift_out_eec_bits(hw, word_out, 16); 664 widx++; 665 666 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 667 e1000_standby_nvm(hw); 668 break; 669 } 670 } 671 msec_delay(10); 672 nvm->ops.release(hw); 673 } 674 675 return ret_val; 676} 677 678/** 679 * e1000_write_nvm_microwire - Writes EEPROM using microwire 680 * @hw: pointer to the HW structure 681 * @offset: offset within the EEPROM to be written to 682 * @words: number of words to write 683 * @data: 16 bit word(s) to be written to the EEPROM 684 * 685 * Writes data to EEPROM at offset using microwire interface. 686 * 687 * If e1000_update_nvm_checksum is not called after this function , the 688 * EEPROM will most likely contain an invalid checksum. 689 **/ 690s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words, 691 u16 *data) 692{ 693 struct e1000_nvm_info *nvm = &hw->nvm; 694 s32 ret_val; 695 u32 eecd; 696 u16 words_written = 0; 697 u16 widx = 0; 698 699 DEBUGFUNC("e1000_write_nvm_microwire"); 700 701 /* A check for invalid values: offset too large, too many words, 702 * and not enough words. 703 */ 704 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 705 (words == 0)) { 706 DEBUGOUT("nvm parameter(s) out of bounds\n"); 707 return -E1000_ERR_NVM; 708 } 709 710 ret_val = nvm->ops.acquire(hw); 711 if (ret_val) 712 return ret_val; 713 714 ret_val = e1000_ready_nvm_eeprom(hw); 715 if (ret_val) 716 goto release; 717 718 e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE, 719 (u16)(nvm->opcode_bits + 2)); 720 721 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 722 723 e1000_standby_nvm(hw); 724 725 while (words_written < words) { 726 e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE, 727 nvm->opcode_bits); 728 729 e1000_shift_out_eec_bits(hw, (u16)(offset + words_written), 730 nvm->address_bits); 731 732 e1000_shift_out_eec_bits(hw, data[words_written], 16); 733 734 e1000_standby_nvm(hw); 735 736 for (widx = 0; widx < 200; widx++) { 737 eecd = E1000_READ_REG(hw, E1000_EECD); 738 if (eecd & E1000_EECD_DO) 739 break; 740 usec_delay(50); 741 } 742 743 if (widx == 200) { 744 DEBUGOUT("NVM Write did not complete\n"); 745 ret_val = -E1000_ERR_NVM; 746 goto release; 747 } 748 749 e1000_standby_nvm(hw); 750 751 words_written++; 752 } 753 754 e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE, 755 (u16)(nvm->opcode_bits + 2)); 756 757 e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2)); 758 759release: 760 nvm->ops.release(hw); 761 762 return ret_val; 763} 764 765/** 766 * e1000_read_pba_string_generic - Read device part number 767 * @hw: pointer to the HW structure 768 * @pba_num: pointer to device part number 769 * @pba_num_size: size of part number buffer 770 * 771 * Reads the product board assembly (PBA) number from the EEPROM and stores 772 * the value in pba_num. 773 **/ 774s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, 775 u32 pba_num_size) 776{ 777 s32 ret_val; 778 u16 nvm_data; 779 u16 pba_ptr; 780 u16 offset; 781 u16 length; 782 783 DEBUGFUNC("e1000_read_pba_string_generic"); 784 785 if ((hw->mac.type == e1000_i210 || 786 hw->mac.type == e1000_i211) && 787 !e1000_get_flash_presence_i210(hw)) { 788 DEBUGOUT("Flashless no PBA string\n"); 789 return -E1000_ERR_NVM_PBA_SECTION; 790 } 791 792 if (pba_num == NULL) { 793 DEBUGOUT("PBA string buffer was null\n"); 794 return -E1000_ERR_INVALID_ARGUMENT; 795 } 796 797 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 798 if (ret_val) { 799 DEBUGOUT("NVM Read Error\n"); 800 return ret_val; 801 } 802 803 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 804 if (ret_val) { 805 DEBUGOUT("NVM Read Error\n"); 806 return ret_val; 807 } 808 809 /* if nvm_data is not ptr guard the PBA must be in legacy format which 810 * means pba_ptr is actually our second data word for the PBA number 811 * and we can decode it into an ascii string 812 */ 813 if (nvm_data != NVM_PBA_PTR_GUARD) { 814 DEBUGOUT("NVM PBA number is not stored as string\n"); 815 816 /* make sure callers buffer is big enough to store the PBA */ 817 if (pba_num_size < E1000_PBANUM_LENGTH) { 818 DEBUGOUT("PBA string buffer too small\n"); 819 return E1000_ERR_NO_SPACE; 820 } 821 822 /* extract hex string from data and pba_ptr */ 823 pba_num[0] = (nvm_data >> 12) & 0xF; 824 pba_num[1] = (nvm_data >> 8) & 0xF; 825 pba_num[2] = (nvm_data >> 4) & 0xF; 826 pba_num[3] = nvm_data & 0xF; 827 pba_num[4] = (pba_ptr >> 12) & 0xF; 828 pba_num[5] = (pba_ptr >> 8) & 0xF; 829 pba_num[6] = '-'; 830 pba_num[7] = 0; 831 pba_num[8] = (pba_ptr >> 4) & 0xF; 832 pba_num[9] = pba_ptr & 0xF; 833 834 /* put a null character on the end of our string */ 835 pba_num[10] = '\0'; 836 837 /* switch all the data but the '-' to hex char */ 838 for (offset = 0; offset < 10; offset++) { 839 if (pba_num[offset] < 0xA) 840 pba_num[offset] += '0'; 841 else if (pba_num[offset] < 0x10) 842 pba_num[offset] += 'A' - 0xA; 843 } 844 845 return E1000_SUCCESS; 846 } 847 848 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 849 if (ret_val) { 850 DEBUGOUT("NVM Read Error\n"); 851 return ret_val; 852 } 853 854 if (length == 0xFFFF || length == 0) { 855 DEBUGOUT("NVM PBA number section invalid length\n"); 856 return -E1000_ERR_NVM_PBA_SECTION; 857 } 858 /* check if pba_num buffer is big enough */ 859 if (pba_num_size < (((u32)length * 2) - 1)) { 860 DEBUGOUT("PBA string buffer too small\n"); 861 return -E1000_ERR_NO_SPACE; 862 } 863 864 /* trim pba length from start of string */ 865 pba_ptr++; 866 length--; 867 868 for (offset = 0; offset < length; offset++) { 869 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data); 870 if (ret_val) { 871 DEBUGOUT("NVM Read Error\n"); 872 return ret_val; 873 } 874 pba_num[offset * 2] = (u8)(nvm_data >> 8); 875 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 876 } 877 pba_num[offset * 2] = '\0'; 878 879 return E1000_SUCCESS; 880} 881 882/** 883 * e1000_read_pba_length_generic - Read device part number length 884 * @hw: pointer to the HW structure 885 * @pba_num_size: size of part number buffer 886 * 887 * Reads the product board assembly (PBA) number length from the EEPROM and 888 * stores the value in pba_num_size. 889 **/ 890s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size) 891{ 892 s32 ret_val; 893 u16 nvm_data; 894 u16 pba_ptr; 895 u16 length; 896 897 DEBUGFUNC("e1000_read_pba_length_generic"); 898 899 if (pba_num_size == NULL) { 900 DEBUGOUT("PBA buffer size was null\n"); 901 return -E1000_ERR_INVALID_ARGUMENT; 902 } 903 904 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 905 if (ret_val) { 906 DEBUGOUT("NVM Read Error\n"); 907 return ret_val; 908 } 909 910 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); 911 if (ret_val) { 912 DEBUGOUT("NVM Read Error\n"); 913 return ret_val; 914 } 915 916 /* if data is not ptr guard the PBA must be in legacy format */ 917 if (nvm_data != NVM_PBA_PTR_GUARD) { 918 *pba_num_size = E1000_PBANUM_LENGTH; 919 return E1000_SUCCESS; 920 } 921 922 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length); 923 if (ret_val) { 924 DEBUGOUT("NVM Read Error\n"); 925 return ret_val; 926 } 927 928 if (length == 0xFFFF || length == 0) { 929 DEBUGOUT("NVM PBA number section invalid length\n"); 930 return -E1000_ERR_NVM_PBA_SECTION; 931 } 932 933 /* Convert from length in u16 values to u8 chars, add 1 for NULL, 934 * and subtract 2 because length field is included in length. 935 */ 936 *pba_num_size = ((u32)length * 2) - 1; 937 938 return E1000_SUCCESS; 939} 940 941/** 942 * e1000_read_pba_num_generic - Read device part number 943 * @hw: pointer to the HW structure 944 * @pba_num: pointer to device part number 945 * 946 * Reads the product board assembly (PBA) number from the EEPROM and stores 947 * the value in pba_num. 948 **/ 949s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num) 950{ 951 s32 ret_val; 952 u16 nvm_data; 953 954 DEBUGFUNC("e1000_read_pba_num_generic"); 955 956 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 957 if (ret_val) { 958 DEBUGOUT("NVM Read Error\n"); 959 return ret_val; 960 } else if (nvm_data == NVM_PBA_PTR_GUARD) { 961 DEBUGOUT("NVM Not Supported\n"); 962 return -E1000_NOT_IMPLEMENTED; 963 } 964 *pba_num = (u32)(nvm_data << 16); 965 966 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 967 if (ret_val) { 968 DEBUGOUT("NVM Read Error\n"); 969 return ret_val; 970 } 971 *pba_num |= nvm_data; 972 973 return E1000_SUCCESS; 974} 975 976 977/** 978 * e1000_read_pba_raw 979 * @hw: pointer to the HW structure 980 * @eeprom_buf: optional pointer to EEPROM image 981 * @eeprom_buf_size: size of EEPROM image in words 982 * @max_pba_block_size: PBA block size limit 983 * @pba: pointer to output PBA structure 984 * 985 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 986 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 987 * 988 **/ 989s32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 990 u32 eeprom_buf_size, u16 max_pba_block_size, 991 struct e1000_pba *pba) 992{ 993 s32 ret_val; 994 u16 pba_block_size; 995 996 if (pba == NULL) 997 return -E1000_ERR_PARAM; 998 999 if (eeprom_buf == NULL) { 1000 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, 1001 &pba->word[0]); 1002 if (ret_val) 1003 return ret_val; 1004 } else { 1005 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1006 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 1007 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 1008 } else { 1009 return -E1000_ERR_PARAM; 1010 } 1011 } 1012 1013 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 1014 if (pba->pba_block == NULL) 1015 return -E1000_ERR_PARAM; 1016 1017 ret_val = e1000_get_pba_block_size(hw, eeprom_buf, 1018 eeprom_buf_size, 1019 &pba_block_size); 1020 if (ret_val) 1021 return ret_val; 1022 1023 if (pba_block_size > max_pba_block_size) 1024 return -E1000_ERR_PARAM; 1025 1026 if (eeprom_buf == NULL) { 1027 ret_val = e1000_read_nvm(hw, pba->word[1], 1028 pba_block_size, 1029 pba->pba_block); 1030 if (ret_val) 1031 return ret_val; 1032 } else { 1033 if (eeprom_buf_size > (u32)(pba->word[1] + 1034 pba_block_size)) { 1035 memcpy(pba->pba_block, 1036 &eeprom_buf[pba->word[1]], 1037 pba_block_size * sizeof(u16)); 1038 } else { 1039 return -E1000_ERR_PARAM; 1040 } 1041 } 1042 } 1043 1044 return E1000_SUCCESS; 1045} 1046 1047/** 1048 * e1000_write_pba_raw 1049 * @hw: pointer to the HW structure 1050 * @eeprom_buf: optional pointer to EEPROM image 1051 * @eeprom_buf_size: size of EEPROM image in words 1052 * @pba: pointer to PBA structure 1053 * 1054 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 1055 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 1056 * 1057 **/ 1058s32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf, 1059 u32 eeprom_buf_size, struct e1000_pba *pba) 1060{ 1061 s32 ret_val; 1062 1063 if (pba == NULL) 1064 return -E1000_ERR_PARAM; 1065 1066 if (eeprom_buf == NULL) { 1067 ret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2, 1068 &pba->word[0]); 1069 if (ret_val) 1070 return ret_val; 1071 } else { 1072 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1073 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0]; 1074 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1]; 1075 } else { 1076 return -E1000_ERR_PARAM; 1077 } 1078 } 1079 1080 if (pba->word[0] == NVM_PBA_PTR_GUARD) { 1081 if (pba->pba_block == NULL) 1082 return -E1000_ERR_PARAM; 1083 1084 if (eeprom_buf == NULL) { 1085 ret_val = e1000_write_nvm(hw, pba->word[1], 1086 pba->pba_block[0], 1087 pba->pba_block); 1088 if (ret_val) 1089 return ret_val; 1090 } else { 1091 if (eeprom_buf_size > (u32)(pba->word[1] + 1092 pba->pba_block[0])) { 1093 memcpy(&eeprom_buf[pba->word[1]], 1094 pba->pba_block, 1095 pba->pba_block[0] * sizeof(u16)); 1096 } else { 1097 return -E1000_ERR_PARAM; 1098 } 1099 } 1100 } 1101 1102 return E1000_SUCCESS; 1103} 1104 1105/** 1106 * e1000_get_pba_block_size 1107 * @hw: pointer to the HW structure 1108 * @eeprom_buf: optional pointer to EEPROM image 1109 * @eeprom_buf_size: size of EEPROM image in words 1110 * @pba_data_size: pointer to output variable 1111 * 1112 * Returns the size of the PBA block in words. Function operates on EEPROM 1113 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 1114 * EEPROM device. 1115 * 1116 **/ 1117s32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf, 1118 u32 eeprom_buf_size, u16 *pba_block_size) 1119{ 1120 s32 ret_val; 1121 u16 pba_word[2]; 1122 u16 length; 1123 1124 DEBUGFUNC("e1000_get_pba_block_size"); 1125 1126 if (eeprom_buf == NULL) { 1127 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]); 1128 if (ret_val) 1129 return ret_val; 1130 } else { 1131 if (eeprom_buf_size > NVM_PBA_OFFSET_1) { 1132 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0]; 1133 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1]; 1134 } else { 1135 return -E1000_ERR_PARAM; 1136 } 1137 } 1138 1139 if (pba_word[0] == NVM_PBA_PTR_GUARD) { 1140 if (eeprom_buf == NULL) { 1141 ret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1, 1142 &length); 1143 if (ret_val) 1144 return ret_val; 1145 } else { 1146 if (eeprom_buf_size > pba_word[1]) 1147 length = eeprom_buf[pba_word[1] + 0]; 1148 else 1149 return -E1000_ERR_PARAM; 1150 } 1151 1152 if (length == 0xFFFF || length == 0) 1153 return -E1000_ERR_NVM_PBA_SECTION; 1154 } else { 1155 /* PBA number in legacy format, there is no PBA Block. */ 1156 length = 0; 1157 } 1158 1159 if (pba_block_size != NULL) 1160 *pba_block_size = length; 1161 1162 return E1000_SUCCESS; 1163} 1164 1165/** 1166 * e1000_read_mac_addr_generic - Read device MAC address 1167 * @hw: pointer to the HW structure 1168 * 1169 * Reads the device MAC address from the EEPROM and stores the value. 1170 * Since devices with two ports use the same EEPROM, we increment the 1171 * last bit in the MAC address for the second port. 1172 **/ 1173s32 e1000_read_mac_addr_generic(struct e1000_hw *hw) 1174{ 1175 u32 rar_high; 1176 u32 rar_low; 1177 u16 i; 1178 1179 rar_high = E1000_READ_REG(hw, E1000_RAH(0)); 1180 rar_low = E1000_READ_REG(hw, E1000_RAL(0)); 1181 1182 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 1183 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 1184 1185 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 1186 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 1187 1188 for (i = 0; i < ETHER_ADDR_LEN; i++) 1189 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1190 1191 return E1000_SUCCESS; 1192} 1193 1194/** 1195 * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum 1196 * @hw: pointer to the HW structure 1197 * 1198 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 1199 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 1200 **/ 1201s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw) 1202{ 1203 s32 ret_val; 1204 u16 checksum = 0; 1205 u16 i, nvm_data; 1206 1207 DEBUGFUNC("e1000_validate_nvm_checksum_generic"); 1208 1209 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 1210 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1211 if (ret_val) { 1212 DEBUGOUT("NVM Read Error\n"); 1213 return ret_val; 1214 } 1215 checksum += nvm_data; 1216 } 1217 1218 if (checksum != (u16) NVM_SUM) { 1219 DEBUGOUT("NVM Checksum Invalid\n"); 1220 return -E1000_ERR_NVM; 1221 } 1222 1223 return E1000_SUCCESS; 1224} 1225 1226/** 1227 * e1000_update_nvm_checksum_generic - Update EEPROM checksum 1228 * @hw: pointer to the HW structure 1229 * 1230 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1231 * up to the checksum. Then calculates the EEPROM checksum and writes the 1232 * value to the EEPROM. 1233 **/ 1234s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw) 1235{ 1236 s32 ret_val; 1237 u16 checksum = 0; 1238 u16 i, nvm_data; 1239 1240 DEBUGFUNC("e1000_update_nvm_checksum"); 1241 1242 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 1243 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1244 if (ret_val) { 1245 DEBUGOUT("NVM Read Error while updating checksum.\n"); 1246 return ret_val; 1247 } 1248 checksum += nvm_data; 1249 } 1250 checksum = (u16) NVM_SUM - checksum; 1251 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 1252 if (ret_val) 1253 DEBUGOUT("NVM Write Error while updating checksum.\n"); 1254 1255 return ret_val; 1256} 1257 1258/** 1259 * e1000_reload_nvm_generic - Reloads EEPROM 1260 * @hw: pointer to the HW structure 1261 * 1262 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the 1263 * extended control register. 1264 **/ 1265static void e1000_reload_nvm_generic(struct e1000_hw *hw) 1266{ 1267 u32 ctrl_ext; 1268 1269 DEBUGFUNC("e1000_reload_nvm_generic"); 1270 1271 usec_delay(10); 1272 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1273 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 1274 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1275 E1000_WRITE_FLUSH(hw); 1276} 1277 1278/** 1279 * e1000_get_fw_version - Get firmware version information 1280 * @hw: pointer to the HW structure 1281 * @fw_vers: pointer to output version structure 1282 * 1283 * unsupported/not present features return 0 in version structure 1284 **/ 1285void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) 1286{ 1287 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version; 1288 u8 q, hval, rem, result; 1289 u16 comb_verh, comb_verl, comb_offset; 1290 1291 memset(fw_vers, 0, sizeof(struct e1000_fw_version)); 1292 1293 /* basic eeprom version numbers, bits used vary by part and by tool 1294 * used to create the nvm images */ 1295 /* Check which data format we have */ 1296 switch (hw->mac.type) { 1297 case e1000_i211: 1298 e1000_read_invm_version(hw, fw_vers); 1299 return; 1300 case e1000_82575: 1301 case e1000_82576: 1302 case e1000_82580: 1303 case e1000_i354: 1304 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1305 /* Use this format, unless EETRACK ID exists, 1306 * then use alternate format 1307 */ 1308 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { 1309 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 1310 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 1311 >> NVM_MAJOR_SHIFT; 1312 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) 1313 >> NVM_MINOR_SHIFT; 1314 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); 1315 goto etrack_id; 1316 } 1317 break; 1318 case e1000_i210: 1319 if (!(e1000_get_flash_presence_i210(hw))) { 1320 e1000_read_invm_version(hw, fw_vers); 1321 return; 1322 } 1323 /* FALLTHROUGH */ 1324 case e1000_i350: 1325 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1326 /* find combo image version */ 1327 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 1328 if ((comb_offset != 0x0) && 1329 (comb_offset != NVM_VER_INVALID)) { 1330 1331 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 1332 + 1), 1, &comb_verh); 1333 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 1334 1, &comb_verl); 1335 1336 /* get Option Rom version if it exists and is valid */ 1337 if ((comb_verh && comb_verl) && 1338 ((comb_verh != NVM_VER_INVALID) && 1339 (comb_verl != NVM_VER_INVALID))) { 1340 1341 fw_vers->or_valid = true; 1342 fw_vers->or_major = 1343 comb_verl >> NVM_COMB_VER_SHFT; 1344 fw_vers->or_build = 1345 (comb_verl << NVM_COMB_VER_SHFT) 1346 | (comb_verh >> NVM_COMB_VER_SHFT); 1347 fw_vers->or_patch = 1348 comb_verh & NVM_COMB_VER_MASK; 1349 } 1350 } 1351 break; 1352 default: 1353 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 1354 return; 1355 } 1356 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 1357 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 1358 >> NVM_MAJOR_SHIFT; 1359 1360 /* check for old style version format in newer images*/ 1361 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { 1362 eeprom_verl = (fw_version & NVM_COMB_VER_MASK); 1363 } else { 1364 eeprom_verl = (fw_version & NVM_MINOR_MASK) 1365 >> NVM_MINOR_SHIFT; 1366 } 1367 /* Convert minor value to hex before assigning to output struct 1368 * Val to be converted will not be higher than 99, per tool output 1369 */ 1370 q = eeprom_verl / NVM_HEX_CONV; 1371 hval = q * NVM_HEX_TENS; 1372 rem = eeprom_verl % NVM_HEX_CONV; 1373 result = hval + rem; 1374 fw_vers->eep_minor = result; 1375 1376etrack_id: 1377 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) { 1378 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); 1379 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); 1380 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) 1381 | eeprom_verl; 1382 } else if ((etrack_test & NVM_ETRACK_VALID) == 0) { 1383 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh); 1384 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl); 1385 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | 1386 eeprom_verl; 1387 } 1388} 1389 1390 1391