1158979Snetchild/*- 2166322Sjoel * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3166322Sjoel * 4158979Snetchild * This software was developed by SRI International and the University of 5158979Snetchild * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 6166322Sjoel * ("CTSRD"), as part of the DARPA CRASH research programme. 7166322Sjoel * 8166322Sjoel * Redistribution and use in source and binary forms, with or without 9166322Sjoel * modification, are permitted provided that the following conditions 10166322Sjoel * are met: 11166322Sjoel * 1. Redistributions of source code must retain the above copyright 12166322Sjoel * notice, this list of conditions and the following disclaimer. 13158979Snetchild * 2. Redistributions in binary form must reproduce the above copyright 14166322Sjoel * notice, this list of conditions and the following disclaimer in the 15166322Sjoel * documentation and/or other materials provided with the distribution. 16166322Sjoel * 17166322Sjoel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18166322Sjoel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19166322Sjoel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20166322Sjoel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21166322Sjoel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22158979Snetchild * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23158979Snetchild * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24158979Snetchild * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25158979Snetchild * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26158979Snetchild * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27158979Snetchild * SUCH DAMAGE. 28158979Snetchild */ 29158979Snetchild 30158979Snetchild#ifndef __DWC1000_DMA_H__ 31158979Snetchild#define __DWC1000_DMA_H__ 32158979Snetchild 33158979Snetchild/* 34158979Snetchild * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor 35158979Snetchild * layout, but the bits in the fields have different meanings. 36158979Snetchild */ 37158979Snetchildstruct dwc_hwdesc 38158979Snetchild{ 39158979Snetchild uint32_t desc0; 40158979Snetchild uint32_t desc1; 41158979Snetchild uint32_t addr1; /* ptr to first buffer data */ 42158979Snetchild uint32_t addr2; /* ptr to next descriptor / second buffer data*/ 43158979Snetchild}; 44158979Snetchild 45158979Snetchildint dma1000_init(struct dwc_softc *sc); 46158979Snetchildvoid dma1000_free(struct dwc_softc *sc); 47158979Snetchildvoid dma1000_start(struct dwc_softc *sc); 48158979Snetchildvoid dma1000_stop(struct dwc_softc *sc); 49158979Snetchildint dma1000_reset(struct dwc_softc *sc); 50158979Snetchildint dma1000_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp); 51158979Snetchildvoid dma1000_txfinish_locked(struct dwc_softc *sc); 52158979Snetchildvoid dma1000_rxfinish_locked(struct dwc_softc *sc); 53158979Snetchildvoid dma1000_txstart(struct dwc_softc *sc); 54158979Snetchildint dma1000_intr(struct dwc_softc *sc); 55158979Snetchild 56158979Snetchild#endif /* __DWC1000_DMA_H__ */ 57158979Snetchild