1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright �� 2021-2022 Dmitry Salychev
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#ifndef	_DPAA2_MCP_H
29#define	_DPAA2_MCP_H
30
31#include <sys/rman.h>
32#include <sys/mutex.h>
33
34#include "dpaa2_types.h"
35
36/*
37 * DPAA2 MC command interface helper routines.
38 */
39
40#define DPAA2_PORTAL_TIMEOUT		100000	/* us */
41#define DPAA2_MCP_MEM_WIDTH		0x40 /* Minimal size of the MC portal. */
42#define DPAA2_MCP_MAX_RESOURCES		1 /* resources per DPMCP: 1 SYS_MEM */
43
44/*
45 * Portal flags.
46 *
47 * TODO: Use the same flags for both MC and software portals.
48 */
49#define DPAA2_PORTAL_DEF		0x0u
50#define DPAA2_PORTAL_NOWAIT_ALLOC	0x2u	/* Do not sleep during init */
51#define DPAA2_PORTAL_LOCKED		0x4000u	/* Wait till portal's unlocked */
52#define DPAA2_PORTAL_DESTROYED		0x8000u /* Terminate any operations */
53
54/* Command flags. */
55#define DPAA2_CMD_DEF			0x0u
56#define DPAA2_CMD_HIGH_PRIO		0x80u	/* High priority command */
57#define DPAA2_CMD_INTR_DIS		0x100u	/* Disable cmd finished intr */
58#define DPAA2_CMD_NOWAIT_ALLOC		0x8000u	/* Do not sleep during init */
59
60/* DPAA2 command return codes. */
61#define DPAA2_CMD_STAT_OK		0x0	/* Set by MC on success */
62#define DPAA2_CMD_STAT_READY		0x1	/* Ready to be processed */
63#define DPAA2_CMD_STAT_AUTH_ERR		0x3	/* Illegal object-portal-icid */
64#define DPAA2_CMD_STAT_NO_PRIVILEGE	0x4	/* No privilege */
65#define DPAA2_CMD_STAT_DMA_ERR		0x5	/* DMA or I/O error */
66#define DPAA2_CMD_STAT_CONFIG_ERR	0x6	/* Invalid/conflicting params */
67#define DPAA2_CMD_STAT_TIMEOUT		0x7	/* Command timed out */
68#define DPAA2_CMD_STAT_NO_RESOURCE	0x8	/* No DPAA2 resources */
69#define DPAA2_CMD_STAT_NO_MEMORY	0x9	/* No memory available */
70#define DPAA2_CMD_STAT_BUSY		0xA	/* Device is busy */
71#define DPAA2_CMD_STAT_UNSUPPORTED_OP	0xB	/* Unsupported operation */
72#define DPAA2_CMD_STAT_INVALID_STATE	0xC	/* Invalid state */
73/* Driver-specific return codes. */
74#define DPAA2_CMD_STAT_UNKNOWN_OBJ	0xFD	/* Unknown DPAA2 object. */
75#define DPAA2_CMD_STAT_EINVAL		0xFE	/* Invalid argument */
76#define DPAA2_CMD_STAT_ERR		0xFF	/* General error */
77
78/* Object's memory region flags. */
79#define DPAA2_RC_REG_CACHEABLE		0x1	/* Cacheable memory mapping */
80
81#define DPAA2_HW_FLAG_HIGH_PRIO		0x80u
82#define DPAA2_SW_FLAG_INTR_DIS		0x01u
83
84#define DPAA2_CMD_PARAMS_N		7u
85#define DPAA2_LABEL_SZ			16
86
87/* ------------------------- MNG command IDs -------------------------------- */
88#define CMD_MNG_BASE_VERSION	1
89#define CMD_MNG_ID_OFFSET	4
90
91#define CMD_MNG(id)	(((id) << CMD_MNG_ID_OFFSET) | CMD_MNG_BASE_VERSION)
92
93#define CMDID_MNG_GET_VER			CMD_MNG(0x831)
94#define CMDID_MNG_GET_SOC_VER			CMD_MNG(0x832)
95#define CMDID_MNG_GET_CONT_ID			CMD_MNG(0x830)
96
97/* ------------------------- DPRC command IDs ------------------------------- */
98#define CMD_RC_BASE_VERSION	1
99#define CMD_RC_2ND_VERSION	2
100#define CMD_RC_3RD_VERSION	3
101#define CMD_RC_ID_OFFSET	4
102
103#define CMD_RC(id)	(((id) << CMD_RC_ID_OFFSET) | CMD_RC_BASE_VERSION)
104#define CMD_RC_V2(id)	(((id) << CMD_RC_ID_OFFSET) | CMD_RC_2ND_VERSION)
105#define CMD_RC_V3(id)	(((id) << CMD_RC_ID_OFFSET) | CMD_RC_3RD_VERSION)
106
107#define CMDID_RC_OPEN				CMD_RC(0x805)
108#define CMDID_RC_CLOSE				CMD_RC(0x800)
109#define CMDID_RC_GET_API_VERSION		CMD_RC(0xA05)
110#define CMDID_RC_GET_ATTR			CMD_RC(0x004)
111#define CMDID_RC_RESET_CONT			CMD_RC(0x005)
112#define CMDID_RC_RESET_CONT_V2			CMD_RC_V2(0x005)
113#define CMDID_RC_SET_IRQ			CMD_RC(0x010)
114#define CMDID_RC_SET_IRQ_ENABLE			CMD_RC(0x012)
115#define CMDID_RC_SET_IRQ_MASK			CMD_RC(0x014)
116#define CMDID_RC_GET_IRQ_STATUS			CMD_RC(0x016)
117#define CMDID_RC_CLEAR_IRQ_STATUS		CMD_RC(0x017)
118#define CMDID_RC_GET_CONT_ID			CMD_RC(0x830)
119#define CMDID_RC_GET_OBJ_COUNT			CMD_RC(0x159)
120#define CMDID_RC_GET_OBJ			CMD_RC(0x15A)
121#define CMDID_RC_GET_OBJ_DESC			CMD_RC(0x162)
122#define CMDID_RC_GET_OBJ_REG			CMD_RC(0x15E)
123#define CMDID_RC_GET_OBJ_REG_V2			CMD_RC_V2(0x15E)
124#define CMDID_RC_GET_OBJ_REG_V3			CMD_RC_V3(0x15E)
125#define CMDID_RC_SET_OBJ_IRQ			CMD_RC(0x15F)
126#define CMDID_RC_GET_CONN			CMD_RC(0x16C)
127
128/* ------------------------- DPIO command IDs ------------------------------- */
129#define CMD_IO_BASE_VERSION	1
130#define CMD_IO_ID_OFFSET	4
131
132#define CMD_IO(id)	(((id) << CMD_IO_ID_OFFSET) | CMD_IO_BASE_VERSION)
133
134#define CMDID_IO_OPEN				CMD_IO(0x803)
135#define CMDID_IO_CLOSE				CMD_IO(0x800)
136#define CMDID_IO_ENABLE				CMD_IO(0x002)
137#define CMDID_IO_DISABLE			CMD_IO(0x003)
138#define CMDID_IO_GET_ATTR			CMD_IO(0x004)
139#define CMDID_IO_RESET				CMD_IO(0x005)
140#define CMDID_IO_SET_IRQ_ENABLE			CMD_IO(0x012)
141#define CMDID_IO_SET_IRQ_MASK			CMD_IO(0x014)
142#define CMDID_IO_GET_IRQ_STATUS			CMD_IO(0x016)
143#define CMDID_IO_ADD_STATIC_DQ_CHAN		CMD_IO(0x122)
144
145/* ------------------------- DPNI command IDs ------------------------------- */
146#define CMD_NI_BASE_VERSION	1
147#define CMD_NI_2ND_VERSION	2
148#define CMD_NI_4TH_VERSION	4
149#define CMD_NI_ID_OFFSET	4
150
151#define CMD_NI(id)	(((id) << CMD_NI_ID_OFFSET) | CMD_NI_BASE_VERSION)
152#define CMD_NI_V2(id)	(((id) << CMD_NI_ID_OFFSET) | CMD_NI_2ND_VERSION)
153#define CMD_NI_V4(id)	(((id) << CMD_NI_ID_OFFSET) | CMD_NI_4TH_VERSION)
154
155#define CMDID_NI_OPEN				CMD_NI(0x801)
156#define CMDID_NI_CLOSE				CMD_NI(0x800)
157#define CMDID_NI_ENABLE				CMD_NI(0x002)
158#define CMDID_NI_DISABLE			CMD_NI(0x003)
159#define CMDID_NI_GET_API_VER			CMD_NI(0xA01)
160#define CMDID_NI_RESET				CMD_NI(0x005)
161#define CMDID_NI_GET_ATTR			CMD_NI(0x004)
162#define CMDID_NI_SET_BUF_LAYOUT			CMD_NI(0x265)
163#define CMDID_NI_GET_TX_DATA_OFF		CMD_NI(0x212)
164#define CMDID_NI_GET_PORT_MAC_ADDR		CMD_NI(0x263)
165#define CMDID_NI_SET_PRIM_MAC_ADDR		CMD_NI(0x224)
166#define CMDID_NI_GET_PRIM_MAC_ADDR		CMD_NI(0x225)
167#define CMDID_NI_SET_LINK_CFG			CMD_NI(0x21A)
168#define CMDID_NI_GET_LINK_CFG			CMD_NI(0x278)
169#define CMDID_NI_GET_LINK_STATE			CMD_NI(0x215)
170#define CMDID_NI_SET_QOS_TABLE			CMD_NI(0x240)
171#define CMDID_NI_CLEAR_QOS_TABLE		CMD_NI(0x243)
172#define CMDID_NI_SET_POOLS			CMD_NI(0x200)
173#define CMDID_NI_SET_ERR_BEHAVIOR		CMD_NI(0x20B)
174#define CMDID_NI_GET_QUEUE			CMD_NI(0x25F)
175#define CMDID_NI_SET_QUEUE			CMD_NI(0x260)
176#define CMDID_NI_GET_QDID			CMD_NI(0x210)
177#define CMDID_NI_ADD_MAC_ADDR			CMD_NI(0x226)
178#define CMDID_NI_REMOVE_MAC_ADDR		CMD_NI(0x227)
179#define CMDID_NI_CLEAR_MAC_FILTERS		CMD_NI(0x228)
180#define CMDID_NI_SET_MFL			CMD_NI(0x216)
181#define CMDID_NI_SET_OFFLOAD			CMD_NI(0x26C)
182#define CMDID_NI_SET_IRQ_MASK			CMD_NI(0x014)
183#define CMDID_NI_SET_IRQ_ENABLE			CMD_NI(0x012)
184#define CMDID_NI_GET_IRQ_STATUS			CMD_NI(0x016)
185#define CMDID_NI_SET_UNI_PROMISC		CMD_NI(0x222)
186#define CMDID_NI_SET_MULTI_PROMISC		CMD_NI(0x220)
187#define CMDID_NI_GET_STATISTICS			CMD_NI(0x25D)
188#define CMDID_NI_SET_RX_TC_DIST			CMD_NI(0x235)
189
190/* ------------------------- DPBP command IDs ------------------------------- */
191#define CMD_BP_BASE_VERSION	1
192#define CMD_BP_ID_OFFSET	4
193
194#define CMD_BP(id)	(((id) << CMD_BP_ID_OFFSET) | CMD_BP_BASE_VERSION)
195
196#define CMDID_BP_OPEN				CMD_BP(0x804)
197#define CMDID_BP_CLOSE				CMD_BP(0x800)
198#define CMDID_BP_ENABLE				CMD_BP(0x002)
199#define CMDID_BP_DISABLE			CMD_BP(0x003)
200#define CMDID_BP_GET_ATTR			CMD_BP(0x004)
201#define CMDID_BP_RESET				CMD_BP(0x005)
202
203/* ------------------------- DPMAC command IDs ------------------------------ */
204#define CMD_MAC_BASE_VERSION	1
205#define CMD_MAC_2ND_VERSION	2
206#define CMD_MAC_ID_OFFSET	4
207
208#define CMD_MAC(id)	(((id) << CMD_MAC_ID_OFFSET) | CMD_MAC_BASE_VERSION)
209#define CMD_MAC_V2(id)	(((id) << CMD_MAC_ID_OFFSET) | CMD_MAC_2ND_VERSION)
210
211#define CMDID_MAC_OPEN				CMD_MAC(0x80C)
212#define CMDID_MAC_CLOSE				CMD_MAC(0x800)
213#define CMDID_MAC_RESET				CMD_MAC(0x005)
214#define CMDID_MAC_MDIO_READ			CMD_MAC(0x0C0)
215#define CMDID_MAC_MDIO_WRITE			CMD_MAC(0x0C1)
216#define CMDID_MAC_GET_ADDR			CMD_MAC(0x0C5)
217#define CMDID_MAC_GET_ATTR			CMD_MAC(0x004)
218#define CMDID_MAC_SET_LINK_STATE		CMD_MAC_V2(0x0C3)
219#define CMDID_MAC_SET_IRQ_MASK			CMD_MAC(0x014)
220#define CMDID_MAC_SET_IRQ_ENABLE		CMD_MAC(0x012)
221#define CMDID_MAC_GET_IRQ_STATUS		CMD_MAC(0x016)
222
223/* ------------------------- DPCON command IDs ------------------------------ */
224#define CMD_CON_BASE_VERSION	1
225#define CMD_CON_ID_OFFSET	4
226
227#define CMD_CON(id)	(((id) << CMD_CON_ID_OFFSET) | CMD_CON_BASE_VERSION)
228
229#define CMDID_CON_OPEN				CMD_CON(0x808)
230#define CMDID_CON_CLOSE				CMD_CON(0x800)
231#define CMDID_CON_ENABLE			CMD_CON(0x002)
232#define CMDID_CON_DISABLE			CMD_CON(0x003)
233#define CMDID_CON_GET_ATTR			CMD_CON(0x004)
234#define CMDID_CON_RESET				CMD_CON(0x005)
235#define CMDID_CON_SET_NOTIF			CMD_CON(0x100)
236
237/* ------------------------- DPMCP command IDs ------------------------------ */
238#define CMD_MCP_BASE_VERSION	1
239#define CMD_MCP_2ND_VERSION	2
240#define CMD_MCP_ID_OFFSET	4
241
242#define CMD_MCP(id)	(((id) << CMD_MCP_ID_OFFSET) | CMD_MCP_BASE_VERSION)
243#define CMD_MCP_V2(id)	(((id) << CMD_MCP_ID_OFFSET) | CMD_MCP_2ND_VERSION)
244
245#define CMDID_MCP_CREATE			CMD_MCP_V2(0x90B)
246#define CMDID_MCP_DESTROY			CMD_MCP(0x98B)
247#define CMDID_MCP_OPEN				CMD_MCP(0x80B)
248#define CMDID_MCP_CLOSE				CMD_MCP(0x800)
249#define CMDID_MCP_RESET				CMD_MCP(0x005)
250
251#define DPAA2_MCP_LOCK(__mcp, __flags) do {		\
252	mtx_assert(&(__mcp)->lock, MA_NOTOWNED);	\
253	mtx_lock(&(__mcp)->lock);			\
254	*(__flags) = (__mcp)->flags;			\
255	(__mcp)->flags |= DPAA2_PORTAL_LOCKED;		\
256} while (0)
257
258#define DPAA2_MCP_UNLOCK(__mcp) do {		\
259	mtx_assert(&(__mcp)->lock, MA_OWNED);	\
260	(__mcp)->flags &= ~DPAA2_PORTAL_LOCKED;	\
261	mtx_unlock(&(__mcp)->lock);		\
262} while (0)
263
264enum dpaa2_rc_region_type {
265	DPAA2_RC_REG_MC_PORTAL,
266	DPAA2_RC_REG_QBMAN_PORTAL
267};
268
269/**
270 * @brief Helper object to interact with the MC portal.
271 *
272 * res:			Unmapped portal's I/O memory.
273 * map:			Mapped portal's I/O memory.
274 * lock:		Lock to send a command to the portal and wait for the
275 *			result.
276 * flags:		Current state of the object.
277 * rc_api_major:	Major version of the DPRC API.
278 * rc_api_minor:	Minor version of the DPRC API.
279 */
280struct dpaa2_mcp {
281	struct resource *res;
282	struct resource_map *map;
283	struct mtx	lock;
284	uint16_t	flags;
285	uint16_t	rc_api_major;
286	uint16_t	rc_api_minor;
287};
288
289/**
290 * @brief Command object holds data to be written to the MC portal.
291 *
292 * header:	8 least significant bytes of the MC portal.
293 * params:	Parameters to pass together with the command to MC. Might keep
294 *		command execution results.
295 *
296 * NOTE: 64 bytes.
297 */
298struct dpaa2_cmd {
299	uint64_t	header;
300	uint64_t	params[DPAA2_CMD_PARAMS_N];
301};
302
303/**
304 * @brief Helper object to access fields of the MC command header.
305 *
306 * srcid:	The SoC architected source ID of the submitter. This field is
307 *		reserved and cannot be written by the driver.
308 * flags_hw:	Bits from 8 to 15 of the command header. Most of them are
309 *		reserved at the moment.
310 * status:	Command ready/status. This field is used as the handshake field
311 *		between MC and the driver. MC reports command completion with
312 *		success/error codes in this field.
313 * flags_sw:	...
314 * token:	...
315 * cmdid:	...
316 *
317 * NOTE: 8 bytes.
318 */
319struct dpaa2_cmd_header {
320	uint8_t		srcid;
321	uint8_t		flags_hw;
322	uint8_t		status;
323	uint8_t		flags_sw;
324	uint16_t	token;
325	uint16_t	cmdid;
326} __packed;
327
328/**
329 * @brief Information about DPAA2 object.
330 *
331 * id:		ID of a logical object resource.
332 * vendor:	Object vendor identifier.
333 * irq_count:	Number of interrupts supported by the object.
334 * reg_count:	Number of mappable regions supported by the object.
335 * state:	Object state (combination of states).
336 * ver_major:	Major version of the object.
337 * ver_minor:	Minor version of the object.
338 * flags:	Object attributes flags.
339 * type:	...
340 * label:	...
341 */
342struct dpaa2_obj {
343	uint32_t	id;
344	uint16_t	vendor;
345	uint8_t		irq_count;
346	uint8_t		reg_count;
347	uint32_t	state;
348	uint16_t	ver_major;
349	uint16_t	ver_minor;
350	uint16_t	flags;
351	uint8_t		label[DPAA2_LABEL_SZ];
352	enum dpaa2_dev_type type;
353};
354
355/**
356 * @brief Attributes of the DPRC object.
357 *
358 * cont_id:	Container ID.
359 * portal_id:	Container's portal ID.
360 * options:	Container's options as set at container's creation.
361 * icid:	Container's isolation context ID.
362 */
363struct dpaa2_rc_attr {
364	uint32_t	cont_id;
365	uint32_t	portal_id;
366	uint32_t	options;
367	uint32_t	icid;
368};
369
370/**
371 * @brief Description of the object's memory region.
372 *
373 * base_paddr:	Region base physical address.
374 * base_offset:	Region base offset.
375 * size:	Region size (in bytes).
376 * flags:	Region flags (cacheable, etc.)
377 * type:	Type of a software portal this region belongs to.
378 */
379struct dpaa2_rc_obj_region {
380	uint64_t	base_paddr;
381	uint64_t	base_offset;
382	uint32_t	size;
383	uint32_t	flags;
384	enum dpaa2_rc_region_type type;
385};
386
387/**
388 * @brief DPAA2 endpoint descriptor.
389 *
390 * obj_id:	Endpoint object ID.
391 * if_id:	Interface ID; for endpoints with multiple interfaces
392 *		(DPSW, DPDMUX), 0 - otherwise.
393 * type:	Endpoint object type, null-terminated string.
394 */
395struct dpaa2_ep_desc {
396	uint32_t	obj_id;
397	uint32_t	if_id;
398	enum dpaa2_dev_type type;
399};
400
401/**
402 * @brief Configuration of the channel data availability notification (CDAN).
403 *
404 * qman_ctx:	Context value provided with each CDAN message.
405 * dpio_id:	DPIO object ID configured with a notification channel.
406 * prior:	Priority selection within the DPIO channel; valid values
407 *		are 0-7, depending on the number of priorities in that channel.
408 */
409struct dpaa2_con_notif_cfg {
410	uint64_t	qman_ctx;
411	uint32_t	dpio_id;
412	uint8_t		prior;
413};
414
415/**
416 * @brief Attributes of the DPMCP object.
417 *
418 * id:		 DPMCP object ID.
419 * options:	 Options of the MC portal (disabled high-prio commands, etc.).
420 */
421struct dpaa2_mcp_attr {
422	uint32_t		id;
423	uint32_t		options;
424};
425
426/**
427 * @brief Software context for the DPAA2 MC portal.
428 */
429struct dpaa2_mcp_softc {
430	device_t		 dev;
431	struct dpaa2_mcp_attr	 attr;
432
433	struct resource 	*res[DPAA2_MCP_MAX_RESOURCES];
434	struct resource_map	 map[DPAA2_MCP_MAX_RESOURCES];
435};
436
437int	dpaa2_mcp_init_portal(struct dpaa2_mcp **mcp, struct resource *res,
438	    struct resource_map *map, uint16_t flags);
439void	dpaa2_mcp_free_portal(struct dpaa2_mcp *mcp);
440
441/* to quickly update command token */
442struct dpaa2_cmd *dpaa2_mcp_tk(struct dpaa2_cmd *cmd, const uint16_t token);
443/* to quickly update command flags */
444struct dpaa2_cmd *dpaa2_mcp_f(struct dpaa2_cmd *cmd, const uint16_t flags);
445
446#define DPAA2_CMD_INIT_FLAGS(__cmd, __flags) do {			\
447	KASSERT((__cmd) != NULL, ("%s:%d: failed", __func__, __LINE__)); \
448	struct dpaa2_cmd_header *__hdr;					\
449	uint32_t __dcpi;						\
450									\
451	__hdr = (struct dpaa2_cmd_header *)&((__cmd)->header);		\
452	__hdr->srcid = 0;						\
453	__hdr->status = DPAA2_CMD_STAT_OK;				\
454	__hdr->token = 0;						\
455	__hdr->cmdid = 0;						\
456	__hdr->flags_hw = DPAA2_CMD_DEF;				\
457	__hdr->flags_sw = DPAA2_CMD_DEF;				\
458	if ((__flags) & DPAA2_CMD_HIGH_PRIO) {				\
459		__hdr->flags_hw |= DPAA2_HW_FLAG_HIGH_PRIO;		\
460	}								\
461	if ((__flags) & DPAA2_CMD_INTR_DIS) {				\
462		__hdr->flags_sw |= DPAA2_SW_FLAG_INTR_DIS;		\
463	}								\
464	for (__dcpi = 0; __dcpi < DPAA2_CMD_PARAMS_N; __dcpi++) {	\
465		(__cmd)->params[__dcpi] = 0;				\
466	}								\
467} while (0)
468#define DPAA2_CMD_INIT(c)	DPAA2_CMD_INIT_FLAGS((c), DPAA2_CMD_DEF)
469#define DPAA2_CMD_TK(c, t)	dpaa2_mcp_tk((c), (t))
470#define DPAA2_CMD_F(c, f)	dpaa2_mcp_f((c), (f))
471
472#endif /* _DPAA2_MCP_H */
473