198937Sdes/*- 298937Sdes * SPDX-License-Identifier: BSD-2-Clause 398937Sdes * 498937Sdes * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 598937Sdes * 698937Sdes * Redistribution and use in source and binary forms, with or without 798937Sdes * modification, are permitted provided that the following conditions 898937Sdes * are met: 998937Sdes * 1098937Sdes * 1. Redistributions of source code must retain the above copyright 1198937Sdes * notice, this list of conditions and the following disclaimer. 1298937Sdes * 2. Redistributions in binary form must reproduce the above copyright 1398937Sdes * notice, this list of conditions and the following disclaimer in the 1498937Sdes * documentation and/or other materials provided with the distribution. 1598937Sdes * 1698937Sdes * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1798937Sdes * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1898937Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1998937Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 2098937Sdes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2198937Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2298937Sdes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2398937Sdes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2498937Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2598937Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 2698937Sdes * THE POSSIBILITY OF SUCH DAMAGE. 2798937Sdes */ 2898937Sdes 2998937Sdes#include <sys/cdefs.h> 3098937Sdes#ifndef ECORE_INIT_H 3198937Sdes#define ECORE_INIT_H 3298937Sdes 3398937Sdes/* Init operation types and structures */ 34162852Sdesenum { 35162852Sdes OP_RD = 0x1, /* read a single register */ 36162852Sdes OP_WR, /* write a single register */ 37162852Sdes OP_SW, /* copy a string to the device */ 3898937Sdes OP_ZR, /* clear memory */ 3998937Sdes OP_ZP, /* unzip then copy with DMAE */ 4098937Sdes OP_WR_64, /* write 64 bit pattern */ 4198937Sdes OP_WB, /* copy a string using DMAE */ 4298937Sdes#ifndef FW_ZIP_SUPPORT 4398937Sdes OP_FW, /* copy an array from fw data (only used with unzipped FW) */ 4498937Sdes#endif 4598937Sdes OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */ 4698937Sdes OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */ 4798937Sdes OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */ 4898937Sdes OP_IF_PHASE, 4998937Sdes OP_RT, 5098937Sdes OP_DELAY, 5198937Sdes OP_VERIFY, 5298937Sdes OP_MAX 5398937Sdes}; 5498937Sdes 5598937Sdesenum { 5698937Sdes STAGE_START, 5798937Sdes STAGE_END, 5898937Sdes}; 5998937Sdes 6098937Sdes/* Returns the index of start or end of a specific block stage in ops array*/ 6198937Sdes#define BLOCK_OPS_IDX(block, stage, end) \ 6298937Sdes (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) 6398937Sdes 6498937Sdes 6598937Sdes/* structs for the various opcodes */ 6698937Sdesstruct raw_op { 6798937Sdes uint32_t op:8; 6898937Sdes uint32_t offset:24; 6998937Sdes uint32_t raw_data; 7098937Sdes}; 7198937Sdes 7298937Sdesstruct op_read { 7398937Sdes uint32_t op:8; 7498937Sdes uint32_t offset:24; 7598937Sdes uint32_t val; 7698937Sdes}; 7798937Sdes 7898937Sdesstruct op_write { 7998937Sdes uint32_t op:8; 8098937Sdes uint32_t offset:24; 8198937Sdes uint32_t val; 8298937Sdes}; 8398937Sdes 8498937Sdesstruct op_arr_write { 8598937Sdes uint32_t op:8; 8698937Sdes uint32_t offset:24; 8798937Sdes#ifdef __BIG_ENDIAN 8898937Sdes uint16_t data_len; 8998937Sdes uint16_t data_off; 9098937Sdes#else /* __LITTLE_ENDIAN */ 9198937Sdes uint16_t data_off; 9298937Sdes uint16_t data_len; 9398937Sdes#endif 9498937Sdes}; 9598937Sdes 9698937Sdesstruct op_zero { 9798937Sdes uint32_t op:8; 9898937Sdes uint32_t offset:24; 9998937Sdes uint32_t len; 10098937Sdes}; 10198937Sdes 10298937Sdesstruct op_if_mode { 10398937Sdes uint32_t op:8; 10498937Sdes uint32_t cmd_offset:24; 10598937Sdes uint32_t mode_bit_map; 10698937Sdes}; 10798937Sdes 10898937Sdesstruct op_if_phase { 10998937Sdes uint32_t op:8; 11098937Sdes uint32_t cmd_offset:24; 11198937Sdes uint32_t phase_bit_map; 11298937Sdes}; 11398937Sdes 11498937Sdesstruct op_delay { 11598937Sdes uint32_t op:8; 11698937Sdes uint32_t reserved:24; 11798937Sdes uint32_t delay; 11898937Sdes}; 11998937Sdes 12098937Sdesunion init_op { 12198937Sdes struct op_read read; 12298937Sdes struct op_write write; 12398937Sdes struct op_arr_write arr_wr; 12498937Sdes struct op_zero zero; 12598937Sdes struct raw_op raw; 12698937Sdes struct op_if_mode if_mode; 12798937Sdes struct op_if_phase if_phase; 12898937Sdes struct op_delay delay; 12998937Sdes}; 13098937Sdes 13198937Sdes 13298937Sdes/* Init Phases */ 13398937Sdesenum { 13498937Sdes PHASE_COMMON, 13598937Sdes PHASE_PORT0, 13698937Sdes PHASE_PORT1, 13798937Sdes PHASE_PF0, 13898937Sdes PHASE_PF1, 13998937Sdes PHASE_PF2, 14098937Sdes PHASE_PF3, 14198937Sdes PHASE_PF4, 14298937Sdes PHASE_PF5, 14398937Sdes PHASE_PF6, 14498937Sdes PHASE_PF7, 14598937Sdes NUM_OF_INIT_PHASES 14698937Sdes}; 14798937Sdes 14898937Sdes/* Init Modes */ 14998937Sdesenum { 15098937Sdes MODE_ASIC = 0x00000001, 15198937Sdes MODE_FPGA = 0x00000002, 15298937Sdes MODE_EMUL = 0x00000004, 15398937Sdes MODE_E2 = 0x00000008, 15498937Sdes MODE_E3 = 0x00000010, 15598937Sdes MODE_PORT2 = 0x00000020, 15698937Sdes MODE_PORT4 = 0x00000040, 15798937Sdes MODE_SF = 0x00000080, 15898937Sdes MODE_MF = 0x00000100, 15998937Sdes MODE_MF_SD = 0x00000200, 16098937Sdes MODE_MF_SI = 0x00000400, 16198937Sdes MODE_MF_AFEX = 0x00000800, 16298937Sdes MODE_E3_A0 = 0x00001000, 16398937Sdes MODE_E3_B0 = 0x00002000, 16498937Sdes MODE_COS3 = 0x00004000, 16598937Sdes MODE_COS6 = 0x00008000, 16698937Sdes MODE_LITTLE_ENDIAN = 0x00010000, 16798937Sdes MODE_BIG_ENDIAN = 0x00020000, 16898937Sdes}; 16998937Sdes 17098937Sdes/* Init Blocks */ 17198937Sdesenum { 17298937Sdes BLOCK_ATC, 17398937Sdes BLOCK_BRB1, 17498937Sdes BLOCK_CCM, 17598937Sdes BLOCK_CDU, 17698937Sdes BLOCK_CFC, 17798937Sdes BLOCK_CSDM, 17898937Sdes BLOCK_CSEM, 17998937Sdes BLOCK_DBG, 18098937Sdes BLOCK_DMAE, 18198937Sdes BLOCK_DORQ, 18298937Sdes BLOCK_HC, 18398937Sdes BLOCK_IGU, 18498937Sdes BLOCK_MISC, 18598937Sdes BLOCK_NIG, 18698937Sdes BLOCK_PBF, 18798937Sdes BLOCK_PGLUE_B, 18898937Sdes BLOCK_PRS, 18998937Sdes BLOCK_PXP2, 19098937Sdes BLOCK_PXP, 19198937Sdes BLOCK_QM, 19298937Sdes BLOCK_SRC, 19398937Sdes BLOCK_TCM, 19498937Sdes BLOCK_TM, 19598937Sdes BLOCK_TSDM, 19698937Sdes BLOCK_TSEM, 19798937Sdes BLOCK_UCM, 19898937Sdes BLOCK_UPB, 19998937Sdes BLOCK_USDM, 20098937Sdes BLOCK_USEM, 20198937Sdes BLOCK_XCM, 20298937Sdes BLOCK_XPB, 20398937Sdes BLOCK_XSDM, 20498937Sdes BLOCK_XSEM, 20598937Sdes BLOCK_MISC_AEU, 20698937Sdes NUM_OF_INIT_BLOCKS 20798937Sdes}; 20898937Sdes 20998937Sdes 21098937Sdes 21198937Sdes 21298937Sdes 21398937Sdes 21498937Sdes 21598937Sdes 21698937Sdes/* Vnics per mode */ 21798937Sdes#define ECORE_PORT2_MODE_NUM_VNICS 4 21898937Sdes 21998937Sdes 22098937Sdes/* QM queue numbers */ 22198937Sdes#define ECORE_ETH_Q 0 22298937Sdes#define ECORE_TOE_Q 3 22398937Sdes#define ECORE_TOE_ACK_Q 6 22498937Sdes#define ECORE_ISCSI_Q 9 22598937Sdes#define ECORE_ISCSI_ACK_Q 11 22698937Sdes#define ECORE_FCOE_Q 10 22798937Sdes 22898937Sdes/* Vnics per mode */ 22998937Sdes#define ECORE_PORT4_MODE_NUM_VNICS 2 23098937Sdes 23198937Sdes/* COS offset for port1 in E3 B0 4port mode */ 23298937Sdes#define ECORE_E3B0_PORT1_COS_OFFSET 3 23398937Sdes 23498937Sdes/* QM Register addresses */ 23598937Sdes#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\ 23698937Sdes (QM_REG_QVOQIDX_0 + 4 * (pf_q_num)) 23798937Sdes#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\ 23898937Sdes (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5))) 23998937Sdes#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\ 24098937Sdes (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4)) 24198937Sdes 24298937Sdes/* extracts the QM queue number for the specified port and vnic */ 24398937Sdes#define ECORE_PF_Q_NUM(q_num, port, vnic)\ 24498937Sdes ((((port) << 1) | (vnic)) * 16 + (q_num)) 24598937Sdes 24698937Sdes 24798937Sdes/* Maps the specified queue to the specified COS */ 24898937Sdesstatic inline void ecore_map_q_cos(struct bxe_softc *sc, uint32_t q_num, uint32_t new_cos) 24998937Sdes{ 25098937Sdes /* find current COS mapping */ 25198937Sdes uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4); 25298937Sdes 25398937Sdes /* check if queue->COS mapping has changed */ 25498937Sdes if (curr_cos != new_cos) { 25598937Sdes uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS; 25698937Sdes uint32_t reg_addr, reg_bit_map, vnic; 25798937Sdes 25898937Sdes /* update parameters for 4port mode */ 25998937Sdes if (INIT_MODE_FLAGS(sc) & MODE_PORT4) { 26098937Sdes num_vnics = ECORE_PORT4_MODE_NUM_VNICS; 26198937Sdes if (PORT_ID(sc)) { 26298937Sdes curr_cos += ECORE_E3B0_PORT1_COS_OFFSET; 26398937Sdes new_cos += ECORE_E3B0_PORT1_COS_OFFSET; 26498937Sdes } 26598937Sdes } 26698937Sdes 26798937Sdes /* change queue mapping for each VNIC */ 26898937Sdes for (vnic = 0; vnic < num_vnics; vnic++) { 26998937Sdes uint32_t pf_q_num = 27098937Sdes ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic); 27198937Sdes uint32_t q_bit_map = 1 << (pf_q_num & 0x1f); 27298937Sdes 27398937Sdes /* overwrite queue->VOQ mapping */ 27498937Sdes REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); 27598937Sdes 27698937Sdes /* clear queue bit from current COS bit map */ 27798937Sdes reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); 27898937Sdes reg_bit_map = REG_RD(sc, reg_addr); 27998937Sdes REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); 28098937Sdes 28198937Sdes /* set queue bit in new COS bit map */ 28298937Sdes reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); 28398937Sdes reg_bit_map = REG_RD(sc, reg_addr); 28498937Sdes REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); 28598937Sdes 28698937Sdes /* set/clear queue bit in command-queue bit map 28798937Sdes (E2/E3A0 only, valid COS values are 0/1) */ 288124208Sdes if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) { 28998937Sdes reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); 29098937Sdes reg_bit_map = REG_RD(sc, reg_addr); 29198937Sdes q_bit_map = 1 << (2 * (pf_q_num & 0xf)); 29298937Sdes reg_bit_map = new_cos ? 29398937Sdes (reg_bit_map | q_bit_map) : 29498937Sdes (reg_bit_map & (~q_bit_map)); 29598937Sdes REG_WR(sc, reg_addr, reg_bit_map); 29698937Sdes } 29798937Sdes } 29898937Sdes } 29998937Sdes} 30098937Sdes 30198937Sdes/* Configures the QM according to the specified per-traffic-type COSes */ 30298937Sdesstatic inline void ecore_dcb_config_qm(struct bxe_softc *sc, enum cos_mode mode, 30398937Sdes struct priority_cos *traffic_cos) 30498937Sdes{ 30598937Sdes ecore_map_q_cos(sc, ECORE_FCOE_Q, 30698937Sdes traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos); 30798937Sdes ecore_map_q_cos(sc, ECORE_ISCSI_Q, 30898937Sdes traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos); 309 ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q, 310 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos); 311 if (mode != STATIC_COS) { 312 /* required only in OVERRIDE_COS mode */ 313 ecore_map_q_cos(sc, ECORE_ETH_Q, 314 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); 315 ecore_map_q_cos(sc, ECORE_TOE_Q, 316 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); 317 ecore_map_q_cos(sc, ECORE_TOE_ACK_Q, 318 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); 319 } 320} 321 322 323/* 324 * congestion management port init api description 325 * the api works as follows: 326 * the driver should pass the cmng_init_input struct, the port_init function 327 * will prepare the required internal ram structure which will be passed back 328 * to the driver (cmng_init) that will write it into the internal ram. 329 * 330 * IMPORTANT REMARKS: 331 * 1. the cmng_init struct does not represent the contiguous internal ram 332 * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET 333 * offset in order to write the port sub struct and the 334 * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other 335 * words - don't use memcpy!). 336 * 2. although the cmng_init struct is filled for the maximal vnic number 337 * possible, the driver should only write the valid vnics into the internal 338 * ram according to the appropriate port mode. 339 */ 340#define BITS_TO_BYTES(x) ((x)/8) 341 342/* CMNG constants, as derived from system spec calculations */ 343 344/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */ 345#define DEF_MIN_RATE 100 346 347/* resolution of the rate shaping timer - 400 usec */ 348#define RS_PERIODIC_TIMEOUT_USEC 400 349 350/* 351 * number of bytes in single QM arbitration cycle - 352 * coefficient for calculating the fairness timer 353 */ 354#define QM_ARB_BYTES 160000 355 356/* resolution of Min algorithm 1:100 */ 357#define MIN_RES 100 358 359/* 360 * how many bytes above threshold for 361 * the minimal credit of Min algorithm 362 */ 363#define MIN_ABOVE_THRESH 32768 364 365/* 366 * Fairness algorithm integration time coefficient - 367 * for calculating the actual Tfair 368 */ 369#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 370 371/* Memory of fairness algorithm - 2 cycles */ 372#define FAIR_MEM 2 373#define SAFC_TIMEOUT_USEC 52 374 375#define SDM_TICKS 4 376 377 378static inline void ecore_init_max(const struct cmng_init_input *input_data, 379 uint32_t r_param, struct cmng_init *ram_data) 380{ 381 uint32_t vnic; 382 struct cmng_vnic *vdata = &ram_data->vnic; 383 struct cmng_struct_per_port *pdata = &ram_data->port; 384 /* 385 * rate shaping per-port variables 386 * 100 micro seconds in SDM ticks = 25 387 * since each tick is 4 microSeconds 388 */ 389 390 pdata->rs_vars.rs_periodic_timeout = 391 RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS; 392 393 /* this is the threshold below which no timer arming will occur. 394 * 1.25 coefficient is for the threshold to be a little bigger 395 * then the real time to compensate for timer in-accuracy 396 */ 397 pdata->rs_vars.rs_threshold = 398 (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4; 399 400 /* rate shaping per-vnic variables */ 401 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { 402 /* global vnic counter */ 403 vdata->vnic_max_rate[vnic].vn_counter.rate = 404 input_data->vnic_max_rate[vnic]; 405 /* 406 * maximal Mbps for this vnic 407 * the quota in each timer period - number of bytes 408 * transmitted in this period 409 */ 410 vdata->vnic_max_rate[vnic].vn_counter.quota = 411 RS_PERIODIC_TIMEOUT_USEC * 412 (uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8; 413 } 414 415} 416 417static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate, 418 struct rate_shaping_vars_per_vn *ram_data) 419{ 420 /* global vnic counter */ 421 ram_data->vn_counter.rate = vnic_max_rate; 422 423 /* 424 * maximal Mbps for this vnic 425 * the quota in each timer period - number of bytes 426 * transmitted in this period 427 */ 428 ram_data->vn_counter.quota = 429 RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8; 430} 431 432static inline void ecore_init_min(const struct cmng_init_input *input_data, 433 uint32_t r_param, struct cmng_init *ram_data) 434{ 435 uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair; 436 struct cmng_vnic *vdata = &ram_data->vnic; 437 struct cmng_struct_per_port *pdata = &ram_data->port; 438 439 /* this is the resolution of the fairness timer */ 440 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 441 442 /* 443 * fairness per-port variables 444 * for 10G it is 1000usec. for 1G it is 10000usec. 445 */ 446 tFair = T_FAIR_COEF / input_data->port_rate; 447 448 /* this is the threshold below which we won't arm the timer anymore */ 449 pdata->fair_vars.fair_threshold = QM_ARB_BYTES; 450 451 /* 452 * we multiply by 1e3/8 to get bytes/msec. We don't want the credits 453 * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution) 454 */ 455 pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM; 456 457 /* since each tick is 4 microSeconds */ 458 pdata->fair_vars.fairness_timeout = 459 fair_periodic_timeout_usec / SDM_TICKS; 460 461 /* calculate sum of weights */ 462 vnicWeightSum = 0; 463 464 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) 465 vnicWeightSum += input_data->vnic_min_rate[vnic]; 466 467 /* global vnic counter */ 468 if (vnicWeightSum > 0) { 469 /* fairness per-vnic variables */ 470 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { 471 /* 472 * this is the credit for each period of the fairness 473 * algorithm - number of bytes in T_FAIR (this vnic 474 * share of the port rate) 475 */ 476 vdata->vnic_min_rate[vnic].vn_credit_delta = 477 ((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 * 478 (T_FAIR_COEF / (8 * 100 * vnicWeightSum))); 479 if (vdata->vnic_min_rate[vnic].vn_credit_delta < 480 pdata->fair_vars.fair_threshold + 481 MIN_ABOVE_THRESH) { 482 vdata->vnic_min_rate[vnic].vn_credit_delta = 483 pdata->fair_vars.fair_threshold + 484 MIN_ABOVE_THRESH; 485 } 486 } 487 } 488} 489 490static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data, 491 uint32_t r_param, struct cmng_init *ram_data) 492{ 493 uint32_t vnic, cos; 494 uint32_t cosWeightSum = 0; 495 struct cmng_vnic *vdata = &ram_data->vnic; 496 struct cmng_struct_per_port *pdata = &ram_data->port; 497 498 for (cos = 0; cos < MAX_COS_NUMBER; cos++) 499 cosWeightSum += input_data->cos_min_rate[cos]; 500 501 if (cosWeightSum > 0) { 502 503 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { 504 /* 505 * Since cos and vnic shouldn't work together the rate 506 * to divide between the coses is the port rate. 507 */ 508 uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta; 509 for (cos = 0; cos < MAX_COS_NUMBER; cos++) { 510 /* 511 * this is the credit for each period of 512 * the fairness algorithm - number of bytes 513 * in T_FAIR (this cos share of the vnic rate) 514 */ 515 ccd[cos] = 516 ((uint32_t)input_data->cos_min_rate[cos] * 100 * 517 (T_FAIR_COEF / (8 * 100 * cosWeightSum))); 518 if (ccd[cos] < pdata->fair_vars.fair_threshold 519 + MIN_ABOVE_THRESH) { 520 ccd[cos] = 521 pdata->fair_vars.fair_threshold + 522 MIN_ABOVE_THRESH; 523 } 524 } 525 } 526 } 527} 528 529static inline void ecore_init_safc(const struct cmng_init_input *input_data, 530 struct cmng_init *ram_data) 531{ 532 /* in microSeconds */ 533 ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC; 534} 535 536/* Congestion management port init */ 537static inline void ecore_init_cmng(const struct cmng_init_input *input_data, 538 struct cmng_init *ram_data) 539{ 540 uint32_t r_param; 541 ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init)); 542 543 ram_data->port.flags = input_data->flags; 544 545 /* 546 * number of bytes transmitted in a rate of 10Gbps 547 * in one usec = 1.25KB. 548 */ 549 r_param = BITS_TO_BYTES(input_data->port_rate); 550 ecore_init_max(input_data, r_param, ram_data); 551 ecore_init_min(input_data, r_param, ram_data); 552 ecore_init_fw_wrr(input_data, r_param, ram_data); 553 ecore_init_safc(input_data, ram_data); 554} 555 556 557 558 559/* Returns the index of start or end of a specific block stage in ops array*/ 560#define BLOCK_OPS_IDX(block, stage, end) \ 561 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) 562 563 564#define INITOP_SET 0 /* set the HW directly */ 565#define INITOP_CLEAR 1 /* clear the HW directly */ 566#define INITOP_INIT 2 /* set the init-value array */ 567 568/**************************************************************************** 569* ILT management 570****************************************************************************/ 571struct ilt_line { 572 ecore_dma_addr_t page_mapping; 573 void *page; 574 uint32_t size; 575}; 576 577struct ilt_client_info { 578 uint32_t page_size; 579 uint16_t start; 580 uint16_t end; 581 uint16_t client_num; 582 uint16_t flags; 583#define ILT_CLIENT_SKIP_INIT 0x1 584#define ILT_CLIENT_SKIP_MEM 0x2 585}; 586 587struct ecore_ilt { 588 uint32_t start_line; 589 struct ilt_line *lines; 590 struct ilt_client_info clients[4]; 591#define ILT_CLIENT_CDU 0 592#define ILT_CLIENT_QM 1 593#define ILT_CLIENT_SRC 2 594#define ILT_CLIENT_TM 3 595}; 596 597/**************************************************************************** 598* SRC configuration 599****************************************************************************/ 600struct src_ent { 601 uint8_t opaque[56]; 602 uint64_t next; 603}; 604 605/**************************************************************************** 606* Parity configuration 607****************************************************************************/ 608#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ 609{ \ 610 block##_REG_##block##_PRTY_MASK, \ 611 block##_REG_##block##_PRTY_STS_CLR, \ 612 en_mask, {m1, m1h, m2, m3}, #block \ 613} 614 615#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ 616{ \ 617 block##_REG_##block##_PRTY_MASK_0, \ 618 block##_REG_##block##_PRTY_STS_CLR_0, \ 619 en_mask, {m1, m1h, m2, m3}, #block"_0" \ 620} 621 622#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ 623{ \ 624 block##_REG_##block##_PRTY_MASK_1, \ 625 block##_REG_##block##_PRTY_STS_CLR_1, \ 626 en_mask, {m1, m1h, m2, m3}, #block"_1" \ 627} 628 629static const struct { 630 uint32_t mask_addr; 631 uint32_t sts_clr_addr; 632 uint32_t en_mask; /* Mask to enable parity attentions */ 633 struct { 634 uint32_t e1; /* 57710 */ 635 uint32_t e1h; /* 57711 */ 636 uint32_t e2; /* 57712 */ 637 uint32_t e3; /* 578xx */ 638 } reg_mask; /* Register mask (all valid bits) */ 639 char name[8]; /* Block's longest name is 7 characters long 640 * (name + suffix) 641 */ 642} ecore_blocks_parity_data[] = { 643 /* bit 19 masked */ 644 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */ 645 /* bit 5,18,20-31 */ 646 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */ 647 /* bit 5 */ 648 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */ 649 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */ 650 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */ 651 652 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't 653 * want to handle "system kill" flow at the moment. 654 */ 655 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff, 656 0x7ffffff), 657 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 658 0xffffffff), 659 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff), 660 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0), 661 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0), 662 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff), 663 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff), 664 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff), 665 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1), 666 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff), 667 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f), 668 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3), 669 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3), 670 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 671 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf, 672 {0xf, 0xf, 0xf, 0xf}, "UPB"}, 673 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 674 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0, 675 {0xf, 0xf, 0xf, 0xf}, "XPB"}, 676 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7), 677 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f), 678 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f), 679 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1), 680 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf), 681 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf), 682 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff), 683 BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff), 684 BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f), 685 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 686 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 687 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 688 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 689 BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), 690 BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), 691 BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), 692 BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff), 693 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 694 0xffffffff), 695 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f), 696 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 697 0xffffffff), 698 BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f), 699 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 700 0xffffffff), 701 BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f), 702 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 703 0xffffffff), 704 BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f), 705}; 706 707 708/* [28] MCP Latched rom_parity 709 * [29] MCP Latched ump_rx_parity 710 * [30] MCP Latched ump_tx_parity 711 * [31] MCP Latched scpad_parity 712 */ 713#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \ 714 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 715 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 716 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) 717 718#define MISC_AEU_ENABLE_MCP_PRTY_BITS \ 719 (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \ 720 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 721 722/* Below registers control the MCP parity attention output. When 723 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are 724 * enabled, when cleared - disabled. 725 */ 726static const struct { 727 uint32_t addr; 728 uint32_t bits; 729} mcp_attn_ctl_regs[] = { 730 { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 731 MISC_AEU_ENABLE_MCP_PRTY_BITS }, 732 { MISC_REG_AEU_ENABLE4_NIG_0, 733 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }, 734 { MISC_REG_AEU_ENABLE4_PXP_0, 735 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }, 736 { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 737 MISC_AEU_ENABLE_MCP_PRTY_BITS }, 738 { MISC_REG_AEU_ENABLE4_NIG_1, 739 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }, 740 { MISC_REG_AEU_ENABLE4_PXP_1, 741 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS } 742}; 743 744static inline void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable) 745{ 746 int i; 747 uint32_t reg_val; 748 749 for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) { 750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); 751 752 if (enable) 753 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ 754 else 755 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ 756 757 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); 758 } 759} 760 761static inline uint32_t ecore_parity_reg_mask(struct bxe_softc *sc, int idx) 762{ 763 if (CHIP_IS_E1(sc)) 764 return ecore_blocks_parity_data[idx].reg_mask.e1; 765 else if (CHIP_IS_E1H(sc)) 766 return ecore_blocks_parity_data[idx].reg_mask.e1h; 767 else if (CHIP_IS_E2(sc)) 768 return ecore_blocks_parity_data[idx].reg_mask.e2; 769 else /* CHIP_IS_E3 */ 770 return ecore_blocks_parity_data[idx].reg_mask.e3; 771} 772 773static inline void ecore_disable_blocks_parity(struct bxe_softc *sc) 774{ 775 int i; 776 777 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { 778 uint32_t dis_mask = ecore_parity_reg_mask(sc, i); 779 780 if (dis_mask) { 781 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr, 782 dis_mask); 783 ECORE_MSG(sc, "Setting parity mask " 784 "for %s to\t\t0x%x\n", 785 ecore_blocks_parity_data[i].name, dis_mask); 786 } 787 } 788 789 /* Disable MCP parity attentions */ 790 ecore_set_mcp_parity(sc, FALSE); 791} 792 793/** 794 * Clear the parity error status registers. 795 */ 796static inline void ecore_clear_blocks_parity(struct bxe_softc *sc) 797{ 798 int i; 799 uint32_t reg_val, mcp_aeu_bits = 800 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | 801 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY | 802 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | 803 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY; 804 805 /* Clear SEM_FAST parities */ 806 REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 807 REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 808 REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 809 REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 810 811 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { 812 uint32_t reg_mask = ecore_parity_reg_mask(sc, i); 813 814 if (reg_mask) { 815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. 816 sts_clr_addr); 817 if (reg_val & reg_mask) 818 ECORE_MSG(sc, 819 "Parity errors in %s: 0x%x\n", 820 ecore_blocks_parity_data[i].name, 821 reg_val & reg_mask); 822 } 823 } 824 825 /* Check if there were parity attentions in MCP */ 826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); 827 if (reg_val & mcp_aeu_bits) 828 ECORE_MSG(sc, "Parity error in MCP: 0x%x\n", 829 reg_val & mcp_aeu_bits); 830 831 /* Clear parity attentions in MCP: 832 * [7] clears Latched rom_parity 833 * [8] clears Latched ump_rx_parity 834 * [9] clears Latched ump_tx_parity 835 * [10] clears Latched scpad_parity (both ports) 836 */ 837 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); 838} 839 840static inline void ecore_enable_blocks_parity(struct bxe_softc *sc) 841{ 842 int i; 843 844 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { 845 uint32_t reg_mask = ecore_parity_reg_mask(sc, i); 846 847 if (reg_mask) 848 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr, 849 ecore_blocks_parity_data[i].en_mask & reg_mask); 850 } 851 852 /* Enable MCP parity attentions */ 853 ecore_set_mcp_parity(sc, TRUE); 854} 855 856 857#endif /* ECORE_INIT_H */ 858 859