1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __BXE_H__ 30#define __BXE_H__ 31 32#include <sys/param.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/lock.h> 36#include <sys/mutex.h> 37#include <sys/sx.h> 38#include <sys/module.h> 39#include <sys/endian.h> 40#include <sys/types.h> 41#include <sys/malloc.h> 42#include <sys/kobj.h> 43#include <sys/bus.h> 44#include <sys/rman.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/smp.h> 49#include <sys/bitstring.h> 50#include <sys/limits.h> 51#include <sys/queue.h> 52#include <sys/taskqueue.h> 53#include <contrib/zlib/zlib.h> 54 55#include <net/debugnet.h> 56#include <net/if.h> 57#include <net/if_types.h> 58#include <net/if_arp.h> 59#include <net/ethernet.h> 60#include <net/if_dl.h> 61#include <net/if_var.h> 62#include <net/if_media.h> 63#include <net/if_vlan_var.h> 64#include <net/bpf.h> 65 66#include <netinet/in.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/udp.h> 71 72#include <dev/pci/pcireg.h> 73#include <dev/pci/pcivar.h> 74 75#include <machine/atomic.h> 76#include <machine/resource.h> 77#include <machine/endian.h> 78#include <machine/bus.h> 79#include <machine/in_cksum.h> 80 81#include "device_if.h" 82#include "bus_if.h" 83#include "pci_if.h" 84 85#if _BYTE_ORDER == _LITTLE_ENDIAN 86#ifndef LITTLE_ENDIAN 87#define LITTLE_ENDIAN 88#endif 89#ifndef __LITTLE_ENDIAN 90#define __LITTLE_ENDIAN 91#endif 92#undef BIG_ENDIAN 93#undef __BIG_ENDIAN 94#else /* _BIG_ENDIAN */ 95#ifndef BIG_ENDIAN 96#define BIG_ENDIAN 97#endif 98#ifndef __BIG_ENDIAN 99#define __BIG_ENDIAN 100#endif 101#undef LITTLE_ENDIAN 102#undef __LITTLE_ENDIAN 103#endif 104 105#include "ecore_mfw_req.h" 106#include "ecore_fw_defs.h" 107#include "ecore_hsi.h" 108#include "ecore_reg.h" 109#include "bxe_dcb.h" 110#include "bxe_stats.h" 111 112#include "bxe_elink.h" 113 114#define VF_MAC_CREDIT_CNT 0 115#define VF_VLAN_CREDIT_CNT (0) 116 117#ifndef ARRAY_SIZE 118#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 119#endif 120#ifndef ARRSIZE 121#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 122#endif 123#ifndef DIV_ROUND_UP 124#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 125#endif 126#ifndef roundup 127#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 128#endif 129 130#include "ecore_sp.h" 131 132#define BRCM_VENDORID 0x14e4 133#define QLOGIC_VENDORID 0x1077 134#define PCI_ANY_ID (uint16_t)(~0U) 135 136struct bxe_device_type 137{ 138 uint16_t bxe_vid; 139 uint16_t bxe_did; 140 uint16_t bxe_svid; 141 uint16_t bxe_sdid; 142 char *bxe_name; 143}; 144 145#define BCM_PAGE_SHIFT 12 146#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 147#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 148#define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 149 150#if BCM_PAGE_SIZE != 4096 151#error Page sizes other than 4KB are unsupported! 152#endif 153 154#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 155#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 156#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 157#else 158#define U64_LO(addr) ((uint32_t)(addr)) 159#define U64_HI(addr) (0) 160#endif 161#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 162 163#define SET_FLAG(value, mask, flag) \ 164 do { \ 165 (value) &= ~(mask); \ 166 (value) |= ((flag) << (mask##_SHIFT)); \ 167 } while (0) 168 169#define GET_FLAG(value, mask) \ 170 (((value) & (mask)) >> (mask##_SHIFT)) 171 172#define GET_FIELD(value, fname) \ 173 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 174 175#define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 176#define BXE_TSO_MAX_SEGMENTS 32 177#define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 178#define BXE_TSO_MAX_SEG_SIZE 4096 179 180/* dropless fc FW/HW related params */ 181#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 182#define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 183 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 184 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 185#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 186#define FW_PREFETCH_CNT 16 187#define DROPLESS_FC_HEADROOM 100 188 189/******************/ 190/* RX SGE defines */ 191/******************/ 192 193#define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 194#define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 195#define RX_SGE_NEXT_PAGE_DESC_CNT 2 196#define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 197#define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 198#define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 199#define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 200#define RX_SGE_MAX (RX_SGE_TOTAL - 1) 201#define RX_SGE(x) ((x) & RX_SGE_MAX) 202 203#define RX_SGE_NEXT(x) \ 204 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 205 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 206 207#define RX_SGE_MASK_ELEM_SZ 64 208#define RX_SGE_MASK_ELEM_SHIFT 6 209#define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 210 211/* 212 * Creates a bitmask of all ones in less significant bits. 213 * idx - index of the most significant bit in the created mask. 214 */ 215#define RX_SGE_ONES_MASK(idx) \ 216 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 217#define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 218 219/* Number of uint64_t elements in SGE mask array. */ 220#define RX_SGE_MASK_LEN \ 221 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 222#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 223#define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 224 225/* 226 * dropless fc calculations for SGEs 227 * Number of required SGEs is the sum of two: 228 * 1. Number of possible opened aggregations (next packet for 229 * these aggregations will probably consume SGE immidiatelly) 230 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 231 * after placement on BD for new TPA aggregation) 232 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 233 */ 234#define NUM_SGE_REQ(sc) \ 235 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 236#define NUM_SGE_PG_REQ(sc) \ 237 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 238#define SGE_TH_LO(sc) \ 239 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 240#define SGE_TH_HI(sc) \ 241 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 242 243#define PAGES_PER_SGE_SHIFT 0 244#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 245#define SGE_PAGE_SIZE BCM_PAGE_SIZE 246#define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 247#define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 248#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 249#define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 250 251/*****************/ 252/* TX BD defines */ 253/*****************/ 254 255#define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 256#define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 257#define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 258#define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 259#define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 260#define TX_BD_MAX (TX_BD_TOTAL - 1) 261 262#define TX_BD_NEXT(x) \ 263 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 264 ((x) + 2) : ((x) + 1)) 265#define TX_BD(x) ((x) & TX_BD_MAX) 266#define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 267#define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 268 269/* 270 * Trigger pending transmits when the number of available BDs is greater 271 * than 1/8 of the total number of usable BDs. 272 */ 273#define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 274#define BXE_TX_TIMEOUT 5 275 276/*****************/ 277/* RX BD defines */ 278/*****************/ 279 280#define RX_BD_NUM_PAGES 8 /* power of 2 */ 281#define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 282#define RX_BD_NEXT_PAGE_DESC_CNT 2 283#define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 284#define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 285#define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 286#define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 287#define RX_BD_MAX (RX_BD_TOTAL - 1) 288 289#define RX_BD_NEXT(x) \ 290 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 291 ((x) + 3) : ((x) + 1)) 292#define RX_BD(x) ((x) & RX_BD_MAX) 293#define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 294#define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 295 296/* 297 * dropless fc calculations for BDs 298 * Number of BDs should be as number of buffers in BRB: 299 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 300 * "next" elements on each page 301 */ 302#define NUM_BD_REQ(sc) \ 303 BRB_SIZE(sc) 304#define NUM_BD_PG_REQ(sc) \ 305 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 306#define BD_TH_LO(sc) \ 307 (NUM_BD_REQ(sc) + \ 308 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 309 FW_DROP_LEVEL(sc)) 310#define BD_TH_HI(sc) \ 311 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 312#define MIN_RX_AVAIL(sc) \ 313 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 314#define MIN_RX_SIZE_TPA_HW(sc) \ 315 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 316 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 317#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 318#define MIN_RX_SIZE_TPA(sc) \ 319 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 320#define MIN_RX_SIZE_NONTPA(sc) \ 321 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 322 323/***************/ 324/* RCQ defines */ 325/***************/ 326 327/* 328 * As long as CQE is X times bigger than BD entry we have to allocate X times 329 * more pages for CQ ring in order to keep it balanced with BD ring 330 */ 331#define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 332 sizeof(struct eth_rx_bd)) 333#define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 334#define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 335#define RCQ_NEXT_PAGE_DESC_CNT 1 336#define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 337#define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 338#define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 339#define RCQ_MAX (RCQ_TOTAL - 1) 340 341#define RCQ_NEXT(x) \ 342 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 343 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 344#define RCQ(x) ((x) & RCQ_MAX) 345#define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 346#define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 347 348/* 349 * dropless fc calculations for RCQs 350 * Number of RCQs should be as number of buffers in BRB: 351 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 352 * "next" elements on each page 353 */ 354#define NUM_RCQ_REQ(sc) \ 355 BRB_SIZE(sc) 356#define NUM_RCQ_PG_REQ(sc) \ 357 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 358#define RCQ_TH_LO(sc) \ 359 (NUM_RCQ_REQ(sc) + \ 360 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 361 FW_DROP_LEVEL(sc)) 362#define RCQ_TH_HI(sc) \ 363 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 364 365/* This is needed for determening of last_max */ 366#define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 367 368#define __SGE_MASK_SET_BIT(el, bit) \ 369 do { \ 370 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 371 } while (0) 372 373#define __SGE_MASK_CLEAR_BIT(el, bit) \ 374 do { \ 375 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 376 } while (0) 377 378#define SGE_MASK_SET_BIT(fp, idx) \ 379 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 380 ((idx) & RX_SGE_MASK_ELEM_MASK)) 381 382#define SGE_MASK_CLEAR_BIT(fp, idx) \ 383 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 384 ((idx) & RX_SGE_MASK_ELEM_MASK)) 385 386/* Load / Unload modes */ 387#define LOAD_NORMAL 0 388#define LOAD_OPEN 1 389#define LOAD_DIAG 2 390#define LOAD_LOOPBACK_EXT 3 391#define UNLOAD_NORMAL 0 392#define UNLOAD_CLOSE 1 393#define UNLOAD_RECOVERY 2 394 395/* Some constants... */ 396//#define MAX_PATH_NUM 2 397//#define E2_MAX_NUM_OF_VFS 64 398//#define E1H_FUNC_MAX 8 399//#define E2_FUNC_MAX 4 /* per path */ 400#define MAX_VNIC_NUM 4 401#define MAX_FUNC_NUM 8 /* common to all chips */ 402//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 403#define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 404#define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 405 406#define ILT_NUM_PAGE_ENTRIES 3072 407/* 408 * 57710/11 we use whole table since we have 8 functions. 409 * 57712 we have only 4 functions, but use same size per func, so only half 410 * of the table is used. 411 */ 412#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 413#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 414/* 415 * the phys address is shifted right 12 bits and has an added 416 * 1=valid bit added to the 53rd bit 417 * then since this is a wide register(TM) 418 * we split it into two 32 bit writes 419 */ 420#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 421#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 422 423/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 424#define ETH_HLEN 14 425#define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 426#define ETH_MIN_PACKET_SIZE 60 427#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 428#define ETH_MAX_JUMBO_PACKET_SIZE 9600 429/* TCP with Timestamp Option (32) + IPv6 (40) */ 430#define ETH_MAX_TPA_HEADER_SIZE 72 431 432/* max supported alignment is 256 (8 shift) */ 433//#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 434#define BXE_RX_ALIGN_SHIFT 8 435/* FW uses 2 cache lines alignment for start packet and size */ 436#define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 437#define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 438 439#define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 440#define BXE_SET_ERROR_BIT(sc, error) \ 441{ \ 442 (sc)->error_status |= (error); \ 443} 444 445struct bxe_bar { 446 struct resource *resource; 447 int rid; 448 bus_space_tag_t tag; 449 bus_space_handle_t handle; 450 vm_offset_t kva; 451}; 452 453struct bxe_intr { 454 struct resource *resource; 455 int rid; 456 void *tag; 457}; 458 459/* Used to manage DMA allocations. */ 460struct bxe_dma { 461 struct bxe_softc *sc; 462 bus_addr_t paddr; 463 void *vaddr; 464 bus_dma_tag_t tag; 465 bus_dmamap_t map; 466 bus_dma_segment_t seg; 467 bus_size_t size; 468 int nseg; 469 char msg[32]; 470}; 471 472/* attn group wiring */ 473#define MAX_DYNAMIC_ATTN_GRPS 8 474 475struct attn_route { 476 uint32_t sig[5]; 477}; 478 479struct iro { 480 uint32_t base; 481 uint16_t m1; 482 uint16_t m2; 483 uint16_t m3; 484 uint16_t size; 485}; 486 487union bxe_host_hc_status_block { 488 /* pointer to fp status block e2 */ 489 struct host_hc_status_block_e2 *e2_sb; 490 /* pointer to fp status block e1x */ 491 struct host_hc_status_block_e1x *e1x_sb; 492}; 493 494union bxe_db_prod { 495 struct doorbell_set_prod data; 496 uint32_t raw; 497}; 498 499struct bxe_sw_tx_bd { 500 struct mbuf *m; 501 bus_dmamap_t m_map; 502 uint16_t first_bd; 503 uint8_t flags; 504/* set on the first BD descriptor when there is a split BD */ 505#define BXE_TSO_SPLIT_BD (1 << 0) 506}; 507 508struct bxe_sw_rx_bd { 509 struct mbuf *m; 510 bus_dmamap_t m_map; 511}; 512 513struct bxe_sw_tpa_info { 514 struct bxe_sw_rx_bd bd; 515 bus_dma_segment_t seg; 516 uint8_t state; 517#define BXE_TPA_STATE_START 1 518#define BXE_TPA_STATE_STOP 2 519 uint8_t placement_offset; 520 uint16_t parsing_flags; 521 uint16_t vlan_tag; 522 uint16_t len_on_bd; 523}; 524 525/* 526 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 527 * instances of the fastpath structure when using multiple queues. 528 */ 529struct bxe_fastpath { 530 /* pointer back to parent structure */ 531 struct bxe_softc *sc; 532 533 struct mtx tx_mtx; 534 char tx_mtx_name[32]; 535 struct mtx rx_mtx; 536 char rx_mtx_name[32]; 537 538#define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 539#define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 540#define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 541#define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 542 543#define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 544#define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 545#define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 546 547 /* status block */ 548 struct bxe_dma sb_dma; 549 union bxe_host_hc_status_block status_block; 550 551 /* transmit chain (tx bds) */ 552 struct bxe_dma tx_dma; 553 union eth_tx_bd_types *tx_chain; 554 555 /* receive chain (rx bds) */ 556 struct bxe_dma rx_dma; 557 struct eth_rx_bd *rx_chain; 558 559 /* receive completion queue chain (rcq bds) */ 560 struct bxe_dma rcq_dma; 561 union eth_rx_cqe *rcq_chain; 562 563 /* receive scatter/gather entry chain (for TPA) */ 564 struct bxe_dma rx_sge_dma; 565 struct eth_rx_sge *rx_sge_chain; 566 567 /* tx mbufs */ 568 bus_dma_tag_t tx_mbuf_tag; 569 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 570 571 /* rx mbufs */ 572 bus_dma_tag_t rx_mbuf_tag; 573 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 574 bus_dmamap_t rx_mbuf_spare_map; 575 576 /* rx sge mbufs */ 577 bus_dma_tag_t rx_sge_mbuf_tag; 578 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 579 bus_dmamap_t rx_sge_mbuf_spare_map; 580 581 /* rx tpa mbufs (use the larger size for TPA queue length) */ 582 int tpa_enable; /* disabled per fastpath upon error */ 583 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 584 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 585 uint64_t rx_tpa_queue_used; 586 587 uint16_t *sb_index_values; 588 uint16_t *sb_running_index; 589 uint32_t ustorm_rx_prods_offset; 590 591 uint8_t igu_sb_id; /* status block number in HW */ 592 uint8_t fw_sb_id; /* status block number in FW */ 593 594 uint32_t rx_buf_size; 595 int mbuf_alloc_size; 596 597 int state; 598#define BXE_FP_STATE_CLOSED 0x01 599#define BXE_FP_STATE_IRQ 0x02 600#define BXE_FP_STATE_OPENING 0x04 601#define BXE_FP_STATE_OPEN 0x08 602#define BXE_FP_STATE_HALTING 0x10 603#define BXE_FP_STATE_HALTED 0x20 604 605 /* reference back to this fastpath queue number */ 606 uint8_t index; /* this is also the 'cid' */ 607#define FP_IDX(fp) (fp->index) 608 609 /* interrupt taskqueue (fast) */ 610 struct task tq_task; 611 struct taskqueue *tq; 612 char tq_name[32]; 613 614 struct task tx_task; 615 struct timeout_task tx_timeout_task; 616 617 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 618 uint8_t cl_id; 619#define FP_CL_ID(fp) (fp->cl_id) 620 uint8_t cl_qzone_id; 621 622 uint16_t fp_hc_idx; 623 624 /* driver copy of the receive buffer descriptor prod/cons indices */ 625 uint16_t rx_bd_prod; 626 uint16_t rx_bd_cons; 627 628 /* driver copy of the receive completion queue prod/cons indices */ 629 uint16_t rx_cq_prod; 630 uint16_t rx_cq_cons; 631 632 union bxe_db_prod tx_db; 633 634 /* Transmit packet producer index (used in eth_tx_bd). */ 635 uint16_t tx_pkt_prod; 636 uint16_t tx_pkt_cons; 637 638 /* Transmit buffer descriptor producer index. */ 639 uint16_t tx_bd_prod; 640 uint16_t tx_bd_cons; 641 642 uint64_t sge_mask[RX_SGE_MASK_LEN]; 643 uint16_t rx_sge_prod; 644 645 struct tstorm_per_queue_stats old_tclient; 646 struct ustorm_per_queue_stats old_uclient; 647 struct xstorm_per_queue_stats old_xclient; 648 struct bxe_eth_q_stats eth_q_stats; 649 struct bxe_eth_q_stats_old eth_q_stats_old; 650 651 /* Pointer to the receive consumer in the status block */ 652 uint16_t *rx_cq_cons_sb; 653 654 /* Pointer to the transmit consumer in the status block */ 655 uint16_t *tx_cons_sb; 656 657 /* transmit timeout until chip reset */ 658 int watchdog_timer; 659 660 /* Free/used buffer descriptor counters. */ 661 //uint16_t used_tx_bd; 662 663 /* Last maximal completed SGE */ 664 uint16_t last_max_sge; 665 666 //uint16_t rx_sge_free_idx; 667 668 //uint8_t segs; 669 670#define BXE_BR_SIZE 4096 671 struct buf_ring *tx_br; 672}; /* struct bxe_fastpath */ 673 674/* sriov XXX */ 675#define BXE_MAX_NUM_OF_VFS 64 676#define BXE_VF_CID_WND 0 677#define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 678#define BXE_CLIENTS_PER_VF 1 679#define BXE_FIRST_VF_CID 256 680#define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 681#define BXE_VF_ID_INVALID 0xFF 682#define IS_SRIOV(sc) 0 683 684#define GET_NUM_VFS_PER_PATH(sc) 0 685#define GET_NUM_VFS_PER_PF(sc) 0 686 687/* maximum number of fast-path interrupt contexts */ 688#define FP_SB_MAX_E1x 16 689#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 690 691union cdu_context { 692 struct eth_context eth; 693 char pad[1024]; 694}; 695 696/* CDU host DB constants */ 697#define CDU_ILT_PAGE_SZ_HW 2 698#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 699#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 700 701#define CNIC_ISCSI_CID_MAX 256 702#define CNIC_FCOE_CID_MAX 2048 703#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 704#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 705 706#define QM_ILT_PAGE_SZ_HW 0 707#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 708#define QM_CID_ROUND 1024 709 710/* TM (timers) host DB constants */ 711#define TM_ILT_PAGE_SZ_HW 0 712#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 713/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 714#define TM_CONN_NUM 1024 715#define TM_ILT_SZ (8 * TM_CONN_NUM) 716#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 717 718/* SRC (Searcher) host DB constants */ 719#define SRC_ILT_PAGE_SZ_HW 0 720#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 721#define SRC_HASH_BITS 10 722#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 723#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 724#define SRC_T2_SZ SRC_ILT_SZ 725#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 726 727struct hw_context { 728 struct bxe_dma vcxt_dma; 729 union cdu_context *vcxt; 730 //bus_addr_t cxt_mapping; 731 size_t size; 732}; 733 734#define SM_RX_ID 0 735#define SM_TX_ID 1 736 737/* defines for multiple tx priority indices */ 738#define FIRST_TX_ONLY_COS_INDEX 1 739#define FIRST_TX_COS_INDEX 0 740 741#define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 742 743#define HC_INDEX_ETH_RX_CQ_CONS 1 744#define HC_INDEX_OOO_TX_CQ_CONS 4 745#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 746#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 747#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 748#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 749 750/* congestion management fairness mode */ 751#define CMNG_FNS_NONE 0 752#define CMNG_FNS_MINMAX 1 753 754/* CMNG constants, as derived from system spec calculations */ 755/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 756#define DEF_MIN_RATE 100 757/* resolution of the rate shaping timer - 400 usec */ 758#define RS_PERIODIC_TIMEOUT_USEC 400 759/* number of bytes in single QM arbitration cycle - 760 * coefficient for calculating the fairness timer */ 761#define QM_ARB_BYTES 160000 762/* resolution of Min algorithm 1:100 */ 763#define MIN_RES 100 764/* how many bytes above threshold for the minimal credit of Min algorithm*/ 765#define MIN_ABOVE_THRESH 32768 766/* fairness algorithm integration time coefficient - 767 * for calculating the actual Tfair */ 768#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 769/* memory of fairness algorithm - 2 cycles */ 770#define FAIR_MEM 2 771 772#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 773#define HC_SEG_ACCESS_ATTN 4 774#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 775 776/* 777 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 778 * control by the number of fast-path status blocks supported by the 779 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 780 * status block represents an independent interrupts context that can 781 * serve a regular L2 networking queue. However special L2 queues such 782 * as the FCoE queue do not require a FP-SB and other components like 783 * the CNIC may consume FP-SB reducing the number of possible L2 queues 784 * 785 * If the maximum number of FP-SB available is X then: 786 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 787 * regular L2 queues is Y=X-1 788 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 789 * c. If the FCoE L2 queue is supported the actual number of L2 queues 790 * is Y+1 791 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 792 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 793 * FP interrupt context for the CNIC). 794 * e. The number of HW context (CID count) is always X or X+1 if FCoE 795 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 796 * 797 * So this is quite simple for now as no ULPs are supported yet. :-) 798 */ 799#define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 800#define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 801#define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 802#define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 803 804#define FOR_EACH_QUEUE(sc, var) \ 805 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 806 807#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 808 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 809 810#define FOR_EACH_ETH_QUEUE(sc, var) \ 811 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 812 813#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 814 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 815 816#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 817 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 818 819#define FOR_EACH_CNIC_QUEUE(sc, var) \ 820 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 821 (var) < BXE_NUM_QUEUES(sc); \ 822 (var)++) 823 824enum { 825 OOO_IDX_OFFSET, 826 FCOE_IDX_OFFSET, 827 FWD_IDX_OFFSET, 828}; 829 830#define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 831#define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 832#define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 833#define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 834#define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 835#define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 836 837#define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 838#define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 839#define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 840#define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 841#define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 842 843#define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 844#define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 845#define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 846#define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 847#define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 848#define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 849 850#define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 851#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 852#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 853#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 854#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 855#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 856#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 857 858enum { 859 BXE_PORT_QUERY_IDX, 860 BXE_PF_QUERY_IDX, 861 BXE_FCOE_QUERY_IDX, 862 BXE_FIRST_QUEUE_QUERY_IDX, 863}; 864 865struct bxe_fw_stats_req { 866 struct stats_query_header hdr; 867 struct stats_query_entry query[FP_SB_MAX_E1x + 868 BXE_FIRST_QUEUE_QUERY_IDX]; 869}; 870 871struct bxe_fw_stats_data { 872 struct stats_counter storm_counters; 873 struct per_port_stats port; 874 struct per_pf_stats pf; 875 //struct fcoe_statistics_params fcoe; 876 struct per_queue_stats queue_stats[1]; 877}; 878 879/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 880#define BXE_IGU_STAS_MSG_VF_CNT 64 881#define BXE_IGU_STAS_MSG_PF_CNT 4 882 883#define MAX_DMAE_C 8 884 885/* 886 * For the main interface up/down code paths, a not-so-fine-grained CORE 887 * mutex lock is used. Inside this code are various calls to kernel routines 888 * that can cause a sleep to occur. Namely memory allocations and taskqueue 889 * handling. If using an MTX lock we are *not* allowed to sleep but we can 890 * with an SX lock. This define forces the CORE lock to use and SX lock. 891 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 892 * path can cause problems since it's called by a non-sleepable thread. To 893 * alleviate a potential sleep, any IOCTL processing that results in the 894 * chip/interface being started/stopped/reinitialized, the actual work is 895 * offloaded to a taskqueue. 896 */ 897#define BXE_CORE_LOCK_SX 898 899/* 900 * This is the slowpath data structure. It is mapped into non-paged memory 901 * so that the hardware can access it's contents directly and must be page 902 * aligned. 903 */ 904struct bxe_slowpath { 905 906 /* used by the DMAE command executer */ 907 struct dmae_cmd dmae[MAX_DMAE_C]; 908 909 /* statistics completion */ 910 uint32_t stats_comp; 911 912 /* firmware defined statistics blocks */ 913 union mac_stats mac_stats; 914 struct nig_stats nig_stats; 915 struct host_port_stats port_stats; 916 struct host_func_stats func_stats; 917 //struct host_func_stats func_stats_base; 918 919 /* DMAE completion value and data source/sink */ 920 uint32_t wb_comp; 921 uint32_t wb_data[4]; 922 923 union { 924 struct mac_configuration_cmd e1x; 925 struct eth_classify_rules_ramrod_data e2; 926 } mac_rdata; 927 928 union { 929 struct tstorm_eth_mac_filter_config e1x; 930 struct eth_filter_rules_ramrod_data e2; 931 } rx_mode_rdata; 932 933 struct eth_rss_update_ramrod_data rss_rdata; 934 935 union { 936 struct mac_configuration_cmd e1; 937 struct eth_multicast_rules_ramrod_data e2; 938 } mcast_rdata; 939 940 union { 941 struct function_start_data func_start; 942 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 943 } func_rdata; 944 945 /* Queue State related ramrods */ 946 union { 947 struct client_init_ramrod_data init_data; 948 struct client_update_ramrod_data update_data; 949 } q_rdata; 950 951 /* 952 * AFEX ramrod can not be a part of func_rdata union because these 953 * events might arrive in parallel to other events from func_rdata. 954 * If they were defined in the same union the data can get corrupted. 955 */ 956 struct afex_vif_list_ramrod_data func_afex_rdata; 957 958 union drv_info_to_mcp drv_info_to_mcp; 959}; /* struct bxe_slowpath */ 960 961/* 962 * Port specifc data structure. 963 */ 964struct bxe_port { 965 /* 966 * Port Management Function (for 57711E only). 967 * When this field is set the driver instance is 968 * responsible for managing port specifc 969 * configurations such as handling link attentions. 970 */ 971 uint32_t pmf; 972 973 /* Ethernet maximum transmission unit. */ 974 uint16_t ether_mtu; 975 976 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 977 978 uint32_t ext_phy_config; 979 980 /* Port feature config.*/ 981 uint32_t config; 982 983 /* Defines the features supported by the PHY. */ 984 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 985 986 /* Defines the features advertised by the PHY. */ 987 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 988#define ADVERTISED_10baseT_Half (1 << 1) 989#define ADVERTISED_10baseT_Full (1 << 2) 990#define ADVERTISED_100baseT_Half (1 << 3) 991#define ADVERTISED_100baseT_Full (1 << 4) 992#define ADVERTISED_1000baseT_Half (1 << 5) 993#define ADVERTISED_1000baseT_Full (1 << 6) 994#define ADVERTISED_TP (1 << 7) 995#define ADVERTISED_FIBRE (1 << 8) 996#define ADVERTISED_Autoneg (1 << 9) 997#define ADVERTISED_Asym_Pause (1 << 10) 998#define ADVERTISED_Pause (1 << 11) 999#define ADVERTISED_2500baseX_Full (1 << 15) 1000#define ADVERTISED_10000baseT_Full (1 << 16) 1001 1002 uint32_t phy_addr; 1003 1004 /* Used to synchronize phy accesses. */ 1005 struct mtx phy_mtx; 1006 char phy_mtx_name[32]; 1007 1008#define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1009#define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1010#define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1011 1012 /* 1013 * MCP scratchpad address for port specific statistics. 1014 * The device is responsible for writing statistcss 1015 * back to the MCP for use with management firmware such 1016 * as UMP/NC-SI. 1017 */ 1018 uint32_t port_stx; 1019 1020 struct nig_stats old_nig_stats; 1021}; /* struct bxe_port */ 1022 1023struct bxe_mf_info { 1024 uint32_t mf_config[E1HVN_MAX]; 1025 1026 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1027 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1028 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1029 1030#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1031#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1032#define VNICS_PER_PATH(sc) \ 1033 ((sc)->devinfo.mf_info.vnics_per_port * \ 1034 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1035 1036 uint8_t min_bw[MAX_VNIC_NUM]; 1037 uint8_t max_bw[MAX_VNIC_NUM]; 1038 1039 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1040#define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1041#define INVALID_VIF_ID 0xFFFF 1042#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1043#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1044 1045 uint16_t default_vlan; 1046#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1047 1048 uint8_t niv_allowed_priorities; 1049#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1050 1051 uint8_t niv_default_cos; 1052#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1053 1054 uint8_t niv_mba_enabled; 1055 1056 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1057#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1058 int afex_def_vlan_tag; 1059 uint32_t pending_max; 1060 1061 uint16_t flags; 1062#define MF_INFO_VALID_MAC 0x0001 1063 1064 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1065#define IS_MF(sc) \ 1066 (IS_MULTI_VNIC(sc) && \ 1067 ((sc)->devinfo.mf_info.mf_mode != 0)) 1068#define IS_MF_SD(sc) \ 1069 (IS_MULTI_VNIC(sc) && \ 1070 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1071#define IS_MF_SI(sc) \ 1072 (IS_MULTI_VNIC(sc) && \ 1073 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1074#define IS_MF_AFEX(sc) \ 1075 (IS_MULTI_VNIC(sc) && \ 1076 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1077#define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1078#define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1079#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1080 1081 uint32_t mf_protos_supported; 1082 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1083 #define MF_PROTO_SUPPORT_ISCSI 0x2 1084 #define MF_PROTO_SUPPORT_FCOE 0x4 1085}; /* struct bxe_mf_info */ 1086 1087/* Device information data structure. */ 1088struct bxe_devinfo { 1089 /* PCIe info */ 1090 uint16_t vendor_id; 1091 uint16_t device_id; 1092 uint16_t subvendor_id; 1093 uint16_t subdevice_id; 1094 1095 /* 1096 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1097 * C = Chip Number (bits 16-31) 1098 * R = Chip Revision (bits 12-15) 1099 * M = Chip Metal (bits 4-11) 1100 * B = Chip Bond ID (bits 0-3) 1101 */ 1102 uint32_t chip_id; 1103#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1104#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1105/* device ids */ 1106#define CHIP_NUM_57710 0x164e 1107#define CHIP_NUM_57711 0x164f 1108#define CHIP_NUM_57711E 0x1650 1109#define CHIP_NUM_57712 0x1662 1110#define CHIP_NUM_57712_MF 0x1663 1111#define CHIP_NUM_57712_VF 0x166f 1112#define CHIP_NUM_57800 0x168a 1113#define CHIP_NUM_57800_MF 0x16a5 1114#define CHIP_NUM_57800_VF 0x16a9 1115#define CHIP_NUM_57810 0x168e 1116#define CHIP_NUM_57810_MF 0x16ae 1117#define CHIP_NUM_57810_VF 0x16af 1118#define CHIP_NUM_57811 0x163d 1119#define CHIP_NUM_57811_MF 0x163e 1120#define CHIP_NUM_57811_VF 0x163f 1121#define CHIP_NUM_57840_OBS 0x168d 1122#define CHIP_NUM_57840_OBS_MF 0x16ab 1123#define CHIP_NUM_57840_4_10 0x16a1 1124#define CHIP_NUM_57840_2_20 0x16a2 1125#define CHIP_NUM_57840_MF 0x16a4 1126#define CHIP_NUM_57840_VF 0x16ad 1127 1128#define CHIP_REV_SHIFT 12 1129#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1130#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1131 1132#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1133#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1134#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1135 1136#define CHIP_REV_IS_SLOW(sc) \ 1137 (CHIP_REV(sc) > 0x00005000) 1138#define CHIP_REV_IS_FPGA(sc) \ 1139 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1140#define CHIP_REV_IS_EMUL(sc) \ 1141 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1142#define CHIP_REV_IS_ASIC(sc) \ 1143 (!CHIP_REV_IS_SLOW(sc)) 1144 1145#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1146#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1147 1148#define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1149#define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1150#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1151#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1152#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1153 (CHIP_IS_57711E(sc))) 1154#define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1155 CHIP_IS_E1H((sc))) 1156 1157#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1158#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1159#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1160#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1161 CHIP_IS_57712_MF(sc)) 1162 1163#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1164#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1165#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1166#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1167#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1168#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1169#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1170#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1171#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1172#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1173 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1174 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1175#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1176 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1177#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1178 1179#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1180 CHIP_IS_57800_MF(sc) || \ 1181 CHIP_IS_57800_VF(sc) || \ 1182 CHIP_IS_57810(sc) || \ 1183 CHIP_IS_57810_MF(sc) || \ 1184 CHIP_IS_57810_VF(sc) || \ 1185 CHIP_IS_57811(sc) || \ 1186 CHIP_IS_57811_MF(sc) || \ 1187 CHIP_IS_57811_VF(sc) || \ 1188 CHIP_IS_57840(sc) || \ 1189 CHIP_IS_57840_MF(sc) || \ 1190 CHIP_IS_57840_VF(sc)) 1191#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1192 (CHIP_REV(sc) == CHIP_REV_Ax)) 1193#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1194 (CHIP_REV(sc) == CHIP_REV_Bx)) 1195 1196#define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1197#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1198 CHIP_IS_E3(sc)) 1199 1200#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1201 CHIP_IS_57712_MF(sc) || \ 1202 CHIP_IS_E3(sc)) 1203 1204#define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1205 CHIP_IS_57800_VF(sc) || \ 1206 CHIP_IS_57810_VF(sc) || \ 1207 CHIP_IS_57840_VF(sc)) 1208#define IS_PF(sc) (!IS_VF(sc)) 1209 1210/* 1211 * This define is used in two main places: 1212 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1213 * to nic-only mode or to offload mode. Offload mode is configured if either 1214 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1215 * already registered for this port (which means that the user wants storage 1216 * services). 1217 * 2. During cnic-related load, to know if offload mode is already configured 1218 * in the HW or needs to be configrued. Since the transition from nic-mode to 1219 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1220 * in ports on which storage services where never requested. 1221 */ 1222#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1223 1224 uint8_t chip_port_mode; 1225#define CHIP_4_PORT_MODE 0x0 1226#define CHIP_2_PORT_MODE 0x1 1227#define CHIP_PORT_MODE_NONE 0x2 1228#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1229#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1230 1231 uint8_t int_block; 1232#define INT_BLOCK_HC 0 1233#define INT_BLOCK_IGU 1 1234#define INT_BLOCK_MODE_NORMAL 0 1235#define INT_BLOCK_MODE_BW_COMP 2 1236#define CHIP_INT_MODE_IS_NBC(sc) \ 1237 (!CHIP_IS_E1x(sc) && \ 1238 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1239#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1240 1241 uint32_t shmem_base; 1242 uint32_t shmem2_base; 1243 uint32_t bc_ver; 1244 char bc_ver_str[32]; 1245 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1246 struct bxe_mf_info mf_info; 1247 1248 int flash_size; 1249#define NVRAM_1MB_SIZE 0x20000 1250#define NVRAM_TIMEOUT_COUNT 30000 1251#define NVRAM_PAGE_SIZE 256 1252 1253 /* PCIe capability information */ 1254 uint32_t pcie_cap_flags; 1255#define BXE_PM_CAPABLE_FLAG 0x00000001 1256#define BXE_PCIE_CAPABLE_FLAG 0x00000002 1257#define BXE_MSI_CAPABLE_FLAG 0x00000004 1258#define BXE_MSIX_CAPABLE_FLAG 0x00000008 1259 uint16_t pcie_pm_cap_reg; 1260 uint16_t pcie_pcie_cap_reg; 1261 //uint16_t pcie_devctl; 1262 uint16_t pcie_link_width; 1263 uint16_t pcie_link_speed; 1264 uint16_t pcie_msi_cap_reg; 1265 uint16_t pcie_msix_cap_reg; 1266 1267 /* device configuration read from bootcode shared memory */ 1268 uint32_t hw_config; 1269 uint32_t hw_config2; 1270}; /* struct bxe_devinfo */ 1271 1272struct bxe_sp_objs { 1273 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1274 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1275}; /* struct bxe_sp_objs */ 1276 1277/* 1278 * Data that will be used to create a link report message. We will keep the 1279 * data used for the last link report in order to prevent reporting the same 1280 * link parameters twice. 1281 */ 1282struct bxe_link_report_data { 1283 uint16_t line_speed; /* Effective line speed */ 1284 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1285}; 1286enum { 1287 BXE_LINK_REPORT_FULL_DUPLEX, 1288 BXE_LINK_REPORT_LINK_DOWN, 1289 BXE_LINK_REPORT_RX_FC_ON, 1290 BXE_LINK_REPORT_TX_FC_ON 1291}; 1292 1293/* Top level device private data structure. */ 1294struct bxe_softc { 1295 /* 1296 * First entry must be a pointer to the BSD ifnet struct which 1297 * has a first element of 'void *if_softc' (which is us). XXX 1298 */ 1299 if_t ifp; 1300 struct ifmedia ifmedia; /* network interface media structure */ 1301 int media; 1302 1303 volatile int state; /* device state */ 1304#define BXE_STATE_CLOSED 0x0000 1305#define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1306#define BXE_STATE_OPENING_WAITING_PORT 0x2000 1307#define BXE_STATE_OPEN 0x3000 1308#define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1309#define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1310#define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1311#define BXE_STATE_DISABLED 0xD000 1312#define BXE_STATE_DIAG 0xE000 1313#define BXE_STATE_ERROR 0xF000 1314 1315 int flags; 1316#define BXE_ONE_PORT_FLAG 0x00000001 1317#define BXE_NO_ISCSI 0x00000002 1318#define BXE_NO_FCOE 0x00000004 1319#define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1320//#define BXE_NO_WOL_FLAG 0x00000008 1321//#define BXE_USING_DAC_FLAG 0x00000010 1322//#define BXE_USING_MSIX_FLAG 0x00000020 1323//#define BXE_USING_MSI_FLAG 0x00000040 1324//#define BXE_DISABLE_MSI_FLAG 0x00000080 1325#define BXE_NO_MCP_FLAG 0x00000200 1326#define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1327//#define BXE_SAFC_TX_FLAG 0x00000400 1328#define BXE_MF_FUNC_DIS 0x00000800 1329#define BXE_TX_SWITCHING 0x00001000 1330#define BXE_NO_PULSE 0x00002000 1331 1332 unsigned long debug; /* per-instance debug logging config */ 1333 1334#define MAX_BARS 5 1335 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1336 1337 uint16_t doorbell_size; 1338 1339 /* periodic timer callout */ 1340#define PERIODIC_STOP 0 1341#define PERIODIC_GO 1 1342 volatile unsigned long periodic_flags; 1343 struct callout periodic_callout; 1344 1345 /* chip start/stop/reset taskqueue */ 1346#define CHIP_TQ_NONE 0 1347#define CHIP_TQ_START 1 1348#define CHIP_TQ_STOP 2 1349#define CHIP_TQ_REINIT 3 1350 volatile unsigned long chip_tq_flags; 1351 struct task chip_tq_task; 1352 struct taskqueue *chip_tq; 1353 char chip_tq_name[32]; 1354 1355 struct timeout_task sp_err_timeout_task; 1356 1357 /* slowpath interrupt taskqueue */ 1358 struct task sp_tq_task; 1359 struct taskqueue *sp_tq; 1360 char sp_tq_name[32]; 1361 1362 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1363 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1364 1365 device_t dev; /* parent device handle */ 1366 uint8_t unit; /* driver instance number */ 1367 1368 int pcie_bus; /* PCIe bus number */ 1369 int pcie_device; /* PCIe device/slot number */ 1370 int pcie_func; /* PCIe function number */ 1371 1372 uint8_t pfunc_rel; /* function relative */ 1373 uint8_t pfunc_abs; /* function absolute */ 1374 uint8_t path_id; /* function absolute */ 1375#define SC_PATH(sc) (sc->path_id) 1376#define SC_PORT(sc) (sc->pfunc_rel & 1) 1377#define SC_FUNC(sc) (sc->pfunc_rel) 1378#define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1379#define SC_VN(sc) (sc->pfunc_rel >> 1) 1380#define SC_L_ID(sc) (SC_VN(sc) << 2) 1381#define PORT_ID(sc) SC_PORT(sc) 1382#define PATH_ID(sc) SC_PATH(sc) 1383#define VNIC_ID(sc) SC_VN(sc) 1384#define FUNC_ID(sc) SC_FUNC(sc) 1385#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1386#define SC_FW_MB_IDX_VN(sc, vn) \ 1387 (SC_PORT(sc) + (vn) * \ 1388 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1389#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1390 1391 int if_capen; /* enabled interface capabilities */ 1392 1393 struct bxe_devinfo devinfo; 1394 char fw_ver_str[32]; 1395 char mf_mode_str[32]; 1396 char pci_link_str[32]; 1397 1398 const struct iro *iro_array; 1399 1400#ifdef BXE_CORE_LOCK_SX 1401 struct sx core_sx; 1402 char core_sx_name[32]; 1403#else 1404 struct mtx core_mtx; 1405 char core_mtx_name[32]; 1406#endif 1407 struct mtx sp_mtx; 1408 char sp_mtx_name[32]; 1409 struct mtx dmae_mtx; 1410 char dmae_mtx_name[32]; 1411 struct mtx fwmb_mtx; 1412 char fwmb_mtx_name[32]; 1413 struct mtx print_mtx; 1414 char print_mtx_name[32]; 1415 struct mtx stats_mtx; 1416 char stats_mtx_name[32]; 1417 struct mtx mcast_mtx; 1418 char mcast_mtx_name[32]; 1419 1420#ifdef BXE_CORE_LOCK_SX 1421#define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1422#define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1423#define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1424#define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1425#else 1426#define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1427#define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1428#define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1429#define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1430#endif 1431 1432#define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1433#define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1434#define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1435 1436#define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1437#define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1438#define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1439 1440#define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1441#define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1442#define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1443 1444#define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1445#define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1446#define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1447 1448#define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1449#define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1450#define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1451 1452#define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx); 1453#define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx); 1454#define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1455 1456 int dmae_ready; 1457#define DMAE_READY(sc) (sc->dmae_ready) 1458 1459 struct ecore_credit_pool_obj vlans_pool; 1460 struct ecore_credit_pool_obj macs_pool; 1461 struct ecore_rx_mode_obj rx_mode_obj; 1462 struct ecore_mcast_obj mcast_obj; 1463 struct ecore_rss_config_obj rss_conf_obj; 1464 struct ecore_func_sp_obj func_obj; 1465 1466 uint16_t fw_seq; 1467 uint16_t fw_drv_pulse_wr_seq; 1468 uint32_t func_stx; 1469 1470 struct elink_params link_params; 1471 struct elink_vars link_vars; 1472 uint32_t link_cnt; 1473 struct bxe_link_report_data last_reported_link; 1474 char mac_addr_str[32]; 1475 1476 int last_reported_link_state; 1477 1478 int tx_ring_size; 1479 int rx_ring_size; 1480 int wol; 1481 1482 int is_leader; 1483 int recovery_state; 1484#define BXE_RECOVERY_DONE 1 1485#define BXE_RECOVERY_INIT 2 1486#define BXE_RECOVERY_WAIT 3 1487#define BXE_RECOVERY_FAILED 4 1488#define BXE_RECOVERY_NIC_LOADING 5 1489 1490#define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ 1491#define BXE_ERR_MISC 0x2 /* MISC ERR */ 1492#define BXE_ERR_PARITY 0x4 /* Parity error detected. */ 1493#define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ 1494#define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ 1495#define BXE_ERR_PANIC 0x20 /* Driver asserted. */ 1496#define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ 1497#define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ 1498 uint32_t error_status; 1499 1500 uint32_t rx_mode; 1501#define BXE_RX_MODE_NONE 0 1502#define BXE_RX_MODE_NORMAL 1 1503#define BXE_RX_MODE_ALLMULTI 2 1504#define BXE_RX_MODE_PROMISC 3 1505#define BXE_MAX_MULTICAST 64 1506 1507 struct bxe_port port; 1508 1509 struct cmng_init cmng; 1510 1511 /* user configs */ 1512 int num_queues; 1513 int max_rx_bufs; 1514 int hc_rx_ticks; 1515 int hc_tx_ticks; 1516 int rx_budget; 1517 int max_aggregation_size; 1518 int mrrs; 1519 int autogreeen; 1520#define AUTO_GREEN_HW_DEFAULT 0 1521#define AUTO_GREEN_FORCE_ON 1 1522#define AUTO_GREEN_FORCE_OFF 2 1523 int interrupt_mode; 1524#define INTR_MODE_INTX 0 1525#define INTR_MODE_MSI 1 1526#define INTR_MODE_MSIX 2 1527 int udp_rss; 1528 1529 /* interrupt allocations */ 1530 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1531 int intr_count; 1532 uint8_t igu_dsb_id; 1533 uint8_t igu_base_sb; 1534 uint8_t igu_sb_cnt; 1535 //uint8_t min_msix_vec_cnt; 1536 uint32_t igu_base_addr; 1537 //bus_addr_t def_status_blk_mapping; 1538 uint8_t base_fw_ndsb; 1539#define DEF_SB_IGU_ID 16 1540#define DEF_SB_ID HC_SP_SB_ID 1541 1542 /* parent bus DMA tag */ 1543 bus_dma_tag_t parent_dma_tag; 1544 1545 /* default status block */ 1546 struct bxe_dma def_sb_dma; 1547 struct host_sp_status_block *def_sb; 1548 uint16_t def_idx; 1549 uint16_t def_att_idx; 1550 uint32_t attn_state; 1551 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1552 1553/* general SP events - stats query, cfc delete, etc */ 1554#define HC_SP_INDEX_ETH_DEF_CONS 3 1555/* EQ completions */ 1556#define HC_SP_INDEX_EQ_CONS 7 1557/* FCoE L2 connection completions */ 1558#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1559#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1560/* iSCSI L2 */ 1561#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1562#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1563 1564 /* event queue */ 1565 struct bxe_dma eq_dma; 1566 union event_ring_elem *eq; 1567 uint16_t eq_prod; 1568 uint16_t eq_cons; 1569 uint16_t *eq_cons_sb; 1570#define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1571#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1572#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1573#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1574#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1575#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1576/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1577#define NEXT_EQ_IDX(x) \ 1578 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1579 ((x) + 2) : ((x) + 1)) 1580/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1581#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1582 1583 /* slow path */ 1584 struct bxe_dma sp_dma; 1585 struct bxe_slowpath *sp; 1586 unsigned long sp_state; 1587 1588 /* slow path queue */ 1589 struct bxe_dma spq_dma; 1590 struct eth_spe *spq; 1591#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1592#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1593#define MAX_SPQ_PENDING 8 1594 1595 uint16_t spq_prod_idx; 1596 struct eth_spe *spq_prod_bd; 1597 struct eth_spe *spq_last_bd; 1598 uint16_t *dsb_sp_prod; 1599 //uint16_t *spq_hw_con; 1600 //uint16_t spq_left; 1601 1602 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1603 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1604 1605 /* fw decompression buffer */ 1606 struct bxe_dma gz_buf_dma; 1607 void *gz_buf; 1608 z_streamp gz_strm; 1609 uint32_t gz_outlen; 1610#define GUNZIP_BUF(sc) (sc->gz_buf) 1611#define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1612#define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1613#define FW_BUF_SIZE 0x40000 1614 1615 const struct raw_op *init_ops; 1616 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1617 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1618 uint32_t init_mode_flags; 1619#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1620 /* PRAM blobs - raw data */ 1621 const uint8_t *tsem_int_table_data; 1622 const uint8_t *tsem_pram_data; 1623 const uint8_t *usem_int_table_data; 1624 const uint8_t *usem_pram_data; 1625 const uint8_t *xsem_int_table_data; 1626 const uint8_t *xsem_pram_data; 1627 const uint8_t *csem_int_table_data; 1628 const uint8_t *csem_pram_data; 1629#define INIT_OPS(sc) (sc->init_ops) 1630#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1631#define INIT_DATA(sc) (sc->init_data) 1632#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1633#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1634#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1635#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1636#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1637#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1638#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1639#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1640 1641 /* ILT 1642 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1643 * context size we need 8 ILT entries. 1644 */ 1645#define ILT_MAX_L2_LINES 8 1646 struct hw_context context[ILT_MAX_L2_LINES]; 1647 struct ecore_ilt *ilt; 1648#define ILT_MAX_LINES 256 1649 1650/* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1651#define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1652/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1653#if 1 1654#define BXE_L2_MAX_CID(sc) \ 1655 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1656#else 1657#define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1658 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1659#endif 1660#if 1 1661#define BXE_L2_CID_COUNT(sc) \ 1662 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1663#else 1664#define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1665 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1666#endif 1667#define L2_ILT_LINES(sc) \ 1668 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1669 1670 int qm_cid_count; 1671 1672 uint8_t dropless_fc; 1673 1674 /* total number of FW statistics requests */ 1675 uint8_t fw_stats_num; 1676 /* 1677 * This is a memory buffer that will contain both statistics ramrod 1678 * request and data. 1679 */ 1680 struct bxe_dma fw_stats_dma; 1681 /* 1682 * FW statistics request shortcut (points at the beginning of fw_stats 1683 * buffer). 1684 */ 1685 int fw_stats_req_size; 1686 struct bxe_fw_stats_req *fw_stats_req; 1687 bus_addr_t fw_stats_req_mapping; 1688 /* 1689 * FW statistics data shortcut (points at the beginning of fw_stats 1690 * buffer + fw_stats_req_size). 1691 */ 1692 int fw_stats_data_size; 1693 struct bxe_fw_stats_data *fw_stats_data; 1694 bus_addr_t fw_stats_data_mapping; 1695 1696 /* tracking a pending STAT_QUERY ramrod */ 1697 uint16_t stats_pending; 1698 /* number of completed statistics ramrods */ 1699 uint16_t stats_comp; 1700 uint16_t stats_counter; 1701 uint8_t stats_init; 1702 int stats_state; 1703 1704 struct bxe_eth_stats eth_stats; 1705 struct host_func_stats func_stats; 1706 struct bxe_eth_stats_old eth_stats_old; 1707 struct bxe_net_stats_old net_stats_old; 1708 struct bxe_fw_port_stats_old fw_stats_old; 1709 1710 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1711 int executer_idx; 1712 1713 int mtu; 1714 1715 /* LLDP params */ 1716 struct bxe_config_lldp_params lldp_config_params; 1717 /* DCB support on/off */ 1718 int dcb_state; 1719#define BXE_DCB_STATE_OFF 0 1720#define BXE_DCB_STATE_ON 1 1721 /* DCBX engine mode */ 1722 int dcbx_enabled; 1723#define BXE_DCBX_ENABLED_OFF 0 1724#define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1725#define BXE_DCBX_ENABLED_ON_NEG_ON 2 1726#define BXE_DCBX_ENABLED_INVALID -1 1727 uint8_t dcbx_mode_uset; 1728 struct bxe_config_dcbx_params dcbx_config_params; 1729 struct bxe_dcbx_port_params dcbx_port_params; 1730 int dcb_version; 1731 1732 uint8_t cnic_support; 1733 uint8_t cnic_enabled; 1734 uint8_t cnic_loaded; 1735#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1736#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1737#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1738 1739 /* multiple tx classes of service */ 1740 uint8_t max_cos; 1741#define BXE_MAX_PRIORITY 8 1742 /* priority to cos mapping */ 1743 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1744 1745 int panic; 1746 1747 struct cdev *ioctl_dev; 1748 1749 void *grc_dump; 1750 unsigned int trigger_grcdump; 1751 unsigned int grcdump_done; 1752 unsigned int grcdump_started; 1753 int bxe_pause_param; 1754 void *eeprom; 1755}; /* struct bxe_softc */ 1756 1757/* IOCTL sub-commands for edebug and firmware upgrade */ 1758#define BXE_IOC_RD_NVRAM 1 1759#define BXE_IOC_WR_NVRAM 2 1760#define BXE_IOC_STATS_SHOW_NUM 3 1761#define BXE_IOC_STATS_SHOW_STR 4 1762#define BXE_IOC_STATS_SHOW_CNT 5 1763 1764struct bxe_nvram_data { 1765 uint32_t op; /* ioctl sub-command */ 1766 uint32_t offset; 1767 uint32_t len; 1768 uint32_t value[1]; /* variable */ 1769}; 1770 1771union bxe_stats_show_data { 1772 uint32_t op; /* ioctl sub-command */ 1773 1774 struct { 1775 uint32_t num; /* return number of stats */ 1776 uint32_t len; /* length of each string item */ 1777 } desc; 1778 1779 /* variable length... */ 1780 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1781 1782 /* variable length... */ 1783 uint64_t stats[1]; /* holds all stats */ 1784}; 1785 1786/* function init flags */ 1787#define FUNC_FLG_RSS 0x0001 1788#define FUNC_FLG_STATS 0x0002 1789/* FUNC_FLG_UNMATCHED 0x0004 */ 1790#define FUNC_FLG_TPA 0x0008 1791#define FUNC_FLG_SPQ 0x0010 1792#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1793 1794struct bxe_func_init_params { 1795 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1796 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1797 uint16_t func_flgs; 1798 uint16_t func_id; /* abs function id */ 1799 uint16_t pf_id; 1800 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1801}; 1802 1803/* memory resources reside at BARs 0, 2, 4 */ 1804/* Run `pciconf -lb` to see mappings */ 1805#define BAR0 0 1806#define BAR1 2 1807#define BAR2 4 1808 1809#ifdef BXE_REG_NO_INLINE 1810 1811uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1812uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1813uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1814 1815void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1816void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1817void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1818 1819#define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1820#define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1821#define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1822 1823#define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1824#define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1825#define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1826 1827#else /* not BXE_REG_NO_INLINE */ 1828 1829#define REG_WR8(sc, offset, val) \ 1830 bus_space_write_1(sc->bar[BAR0].tag, \ 1831 sc->bar[BAR0].handle, \ 1832 offset, val) 1833 1834#define REG_WR16(sc, offset, val) \ 1835 bus_space_write_2(sc->bar[BAR0].tag, \ 1836 sc->bar[BAR0].handle, \ 1837 offset, val) 1838 1839#define REG_WR32(sc, offset, val) \ 1840 bus_space_write_4(sc->bar[BAR0].tag, \ 1841 sc->bar[BAR0].handle, \ 1842 offset, val) 1843 1844#define REG_RD8(sc, offset) \ 1845 bus_space_read_1(sc->bar[BAR0].tag, \ 1846 sc->bar[BAR0].handle, \ 1847 offset) 1848 1849#define REG_RD16(sc, offset) \ 1850 bus_space_read_2(sc->bar[BAR0].tag, \ 1851 sc->bar[BAR0].handle, \ 1852 offset) 1853 1854#define REG_RD32(sc, offset) \ 1855 bus_space_read_4(sc->bar[BAR0].tag, \ 1856 sc->bar[BAR0].handle, \ 1857 offset) 1858 1859#endif /* BXE_REG_NO_INLINE */ 1860 1861#define REG_RD(sc, offset) REG_RD32(sc, offset) 1862#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1863 1864#define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1865#define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1866 1867#define BXE_SP(sc, var) (&(sc)->sp->var) 1868#define BXE_SP_MAPPING(sc, var) \ 1869 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1870 1871#define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1872#define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1873 1874#define REG_RD_DMAE(sc, offset, valp, len32) \ 1875 do { \ 1876 bxe_read_dmae(sc, offset, len32); \ 1877 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1878 } while (0) 1879 1880#define REG_WR_DMAE(sc, offset, valp, len32) \ 1881 do { \ 1882 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1883 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1884 } while (0) 1885 1886#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1887 REG_WR_DMAE(sc, offset, valp, len32) 1888 1889#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1890 REG_RD_DMAE(sc, offset, valp, len32) 1891 1892#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1893 do { \ 1894 /* if (le32_swap) { */ \ 1895 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1896 /* } */ \ 1897 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1898 ecore_write_big_buf_wb(sc, addr, len32); \ 1899 } while (0) 1900 1901#define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1902#define BXE_DB_SHIFT 7 /* 128 bytes */ 1903#if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1904#error "Minimum DB doorbell stride is 8" 1905#endif 1906#define DPM_TRIGGER_TYPE 0x40 1907#define DOORBELL(sc, cid, val) \ 1908 do { \ 1909 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1910 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1911 (uint32_t)val); \ 1912 } while(0) 1913 1914#define SHMEM_ADDR(sc, field) \ 1915 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1916#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1917#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1918#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1919 1920#define SHMEM2_ADDR(sc, field) \ 1921 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1922#define SHMEM2_HAS(sc, field) \ 1923 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1924 offsetof(struct shmem2_region, field))) 1925#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1926#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1927 1928#define MFCFG_ADDR(sc, field) \ 1929 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1930#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1931#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1932#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1933 1934/* DMAE command defines */ 1935 1936#define DMAE_TIMEOUT -1 1937#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1938#define DMAE_NOT_RDY -3 1939#define DMAE_PCI_ERR_FLAG 0x80000000 1940 1941#define DMAE_SRC_PCI 0 1942#define DMAE_SRC_GRC 1 1943 1944#define DMAE_DST_NONE 0 1945#define DMAE_DST_PCI 1 1946#define DMAE_DST_GRC 2 1947 1948#define DMAE_COMP_PCI 0 1949#define DMAE_COMP_GRC 1 1950 1951#define DMAE_COMP_REGULAR 0 1952#define DMAE_COM_SET_ERR 1 1953 1954#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 1955#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 1956#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 1957#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 1958 1959#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 1960#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 1961 1962#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 1963#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 1964#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 1965#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 1966 1967#define DMAE_CMD_PORT_0 0 1968#define DMAE_CMD_PORT_1 DMAE_CMD_PORT 1969 1970#define DMAE_SRC_PF 0 1971#define DMAE_SRC_VF 1 1972 1973#define DMAE_DST_PF 0 1974#define DMAE_DST_VF 1 1975 1976#define DMAE_C_SRC 0 1977#define DMAE_C_DST 1 1978 1979#define DMAE_LEN32_RD_MAX 0x80 1980#define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 1981 1982#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 1983 1984#define MAX_DMAE_C_PER_PORT 8 1985#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 1986#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 1987 1988static const uint32_t dmae_reg_go_c[] = { 1989 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 1990 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 1991 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 1992 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 1993}; 1994 1995#define ATTN_NIG_FOR_FUNC (1L << 8) 1996#define ATTN_SW_TIMER_4_FUNC (1L << 9) 1997#define GPIO_2_FUNC (1L << 10) 1998#define GPIO_3_FUNC (1L << 11) 1999#define GPIO_4_FUNC (1L << 12) 2000#define ATTN_GENERAL_ATTN_1 (1L << 13) 2001#define ATTN_GENERAL_ATTN_2 (1L << 14) 2002#define ATTN_GENERAL_ATTN_3 (1L << 15) 2003#define ATTN_GENERAL_ATTN_4 (1L << 13) 2004#define ATTN_GENERAL_ATTN_5 (1L << 14) 2005#define ATTN_GENERAL_ATTN_6 (1L << 15) 2006#define ATTN_HARD_WIRED_MASK 0xff00 2007#define ATTENTION_ID 4 2008 2009#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2010 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2011 2012#define MAX_IGU_ATTN_ACK_TO 100 2013 2014#define STORM_ASSERT_ARRAY_SIZE 50 2015 2016#define BXE_PMF_LINK_ASSERT(sc) \ 2017 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2018 2019#define BXE_MC_ASSERT_BITS \ 2020 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2021 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2022 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2023 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2024 2025#define BXE_MCP_ASSERT \ 2026 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2027 2028#define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2029#define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2030 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2031 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2032 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2033 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2034 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2035 2036#define MULTI_MASK 0x7f 2037 2038#define PFS_PER_PORT(sc) \ 2039 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2040#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2041 2042#define FIRST_ABS_FUNC_IN_PORT(sc) \ 2043 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2044 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2045 2046#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2047 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2048 (i) < MAX_FUNC_NUM; \ 2049 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2050 2051#define BXE_SWCID_SHIFT 17 2052#define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2053 2054#define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2055#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2056 2057#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2058#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2059#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2060#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2061#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2062 2063/* must be used on a CID before placing it on a HW ring */ 2064#define HW_CID(sc, x) \ 2065 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2066 2067#define SPEED_10 10 2068#define SPEED_100 100 2069#define SPEED_1000 1000 2070#define SPEED_2500 2500 2071#define SPEED_10000 10000 2072 2073#define PCI_PM_D0 1 2074#define PCI_PM_D3hot 2 2075 2076#ifndef DUPLEX_UNKNOWN 2077#define DUPLEX_UNKNOWN (0xff) 2078#endif 2079 2080#ifndef SPEED_UNKNOWN 2081#define SPEED_UNKNOWN (-1) 2082#endif 2083 2084/* Enable or disable autonegotiation. */ 2085#define AUTONEG_DISABLE 0x00 2086#define AUTONEG_ENABLE 0x01 2087 2088/* Which connector port. */ 2089#define PORT_TP 0x00 2090#define PORT_AUI 0x01 2091#define PORT_MII 0x02 2092#define PORT_FIBRE 0x03 2093#define PORT_BNC 0x04 2094#define PORT_DA 0x05 2095#define PORT_NONE 0xef 2096#define PORT_OTHER 0xff 2097 2098int bxe_test_bit(int nr, volatile unsigned long * addr); 2099void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2100void bxe_clear_bit(int nr, volatile unsigned long * addr); 2101int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2102int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2103int bxe_cmpxchg(volatile int *addr, int old, int new); 2104 2105void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2106 uint32_t val); 2107uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2108 2109 2110int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2111 struct bxe_dma *dma, const char *msg); 2112void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2113 2114uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2115uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2116uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2117 uint8_t dst_type, uint8_t with_comp, 2118 uint8_t comp_type); 2119void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2120void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2121void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2122 uint32_t dst_addr, uint32_t len32); 2123void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2124 uint32_t addr, uint32_t len); 2125 2126void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2127 uint32_t cid); 2128void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2129 uint8_t sb_index, uint8_t disable, 2130 uint16_t usec); 2131 2132int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2133 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2134 2135void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2136 uint8_t segment, uint16_t index, uint8_t op, 2137 uint8_t update); 2138 2139void ecore_init_e1_firmware(struct bxe_softc *sc); 2140void ecore_init_e1h_firmware(struct bxe_softc *sc); 2141void ecore_init_e2_firmware(struct bxe_softc *sc); 2142 2143void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2144 size_t size, uint32_t *data); 2145 2146/*********************/ 2147/* LOGGING AND DEBUG */ 2148/*********************/ 2149 2150/* debug logging codepaths */ 2151#define DBG_LOAD 0x00000001 /* load and unload */ 2152#define DBG_INTR 0x00000002 /* interrupt handling */ 2153#define DBG_SP 0x00000004 /* slowpath handling */ 2154#define DBG_STATS 0x00000008 /* stats updates */ 2155#define DBG_TX 0x00000010 /* packet transmit */ 2156#define DBG_RX 0x00000020 /* packet receive */ 2157#define DBG_PHY 0x00000040 /* phy/link handling */ 2158#define DBG_IOCTL 0x00000080 /* ioctl handling */ 2159#define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2160#define DBG_REGS 0x00000200 /* register access */ 2161#define DBG_LRO 0x00000400 /* lro processing */ 2162#define DBG_ASSERT 0x80000000 /* debug assert */ 2163#define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2164 2165#define DBASSERT(sc, exp, msg) \ 2166 do { \ 2167 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2168 if (__predict_false(!(exp))) { \ 2169 panic msg; \ 2170 } \ 2171 } \ 2172 } while (0) 2173 2174/* log a debug message */ 2175#define BLOGD(sc, codepath, format, args...) \ 2176 do { \ 2177 if (__predict_false(sc->debug & (codepath))) { \ 2178 device_printf((sc)->dev, \ 2179 "%s(%s:%d) " format, \ 2180 __FUNCTION__, \ 2181 __FILE__, \ 2182 __LINE__, \ 2183 ## args); \ 2184 } \ 2185 } while(0) 2186 2187/* log a info message */ 2188#define BLOGI(sc, format, args...) \ 2189 do { \ 2190 if (__predict_false(sc->debug)) { \ 2191 device_printf((sc)->dev, \ 2192 "%s(%s:%d) " format, \ 2193 __FUNCTION__, \ 2194 __FILE__, \ 2195 __LINE__, \ 2196 ## args); \ 2197 } else { \ 2198 device_printf((sc)->dev, \ 2199 format, \ 2200 ## args); \ 2201 } \ 2202 } while(0) 2203 2204/* log a warning message */ 2205#define BLOGW(sc, format, args...) \ 2206 do { \ 2207 if (__predict_false(sc->debug)) { \ 2208 device_printf((sc)->dev, \ 2209 "%s(%s:%d) WARNING: " format, \ 2210 __FUNCTION__, \ 2211 __FILE__, \ 2212 __LINE__, \ 2213 ## args); \ 2214 } else { \ 2215 device_printf((sc)->dev, \ 2216 "WARNING: " format, \ 2217 ## args); \ 2218 } \ 2219 } while(0) 2220 2221/* log a error message */ 2222#define BLOGE(sc, format, args...) \ 2223 do { \ 2224 if (__predict_false(sc->debug)) { \ 2225 device_printf((sc)->dev, \ 2226 "%s(%s:%d) ERROR: " format, \ 2227 __FUNCTION__, \ 2228 __FILE__, \ 2229 __LINE__, \ 2230 ## args); \ 2231 } else { \ 2232 device_printf((sc)->dev, \ 2233 "ERROR: " format, \ 2234 ## args); \ 2235 } \ 2236 } while(0) 2237 2238#ifdef ECORE_STOP_ON_ERROR 2239 2240#define bxe_panic(sc, msg) \ 2241 do { \ 2242 panic msg; \ 2243 } while (0) 2244 2245#else 2246 2247#define bxe_panic(sc, msg) \ 2248 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2249 2250#endif 2251 2252#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2253#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2254 2255void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2256 uint8_t *mem, uint32_t len); 2257void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2258 struct mbuf *m, uint8_t contents); 2259 2260#define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2261#define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2262 2263/***********/ 2264/* INLINES */ 2265/***********/ 2266 2267static inline uint32_t 2268reg_poll(struct bxe_softc *sc, 2269 uint32_t reg, 2270 uint32_t expected, 2271 int ms, 2272 int wait) 2273{ 2274 uint32_t val; 2275 2276 do { 2277 val = REG_RD(sc, reg); 2278 if (val == expected) { 2279 break; 2280 } 2281 ms -= wait; 2282 DELAY(wait * 1000); 2283 } while (ms > 0); 2284 2285 return (val); 2286} 2287 2288static inline void 2289bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2290{ 2291 mb(); /* status block is written to by the chip */ 2292 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2293} 2294 2295static inline void 2296bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2297 uint8_t igu_sb_id, 2298 uint8_t segment, 2299 uint16_t index, 2300 uint8_t op, 2301 uint8_t update, 2302 uint32_t igu_addr) 2303{ 2304 struct igu_regular cmd_data = {0}; 2305 2306 cmd_data.sb_id_and_flags = 2307 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2308 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2309 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2310 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2311 2312 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2313 cmd_data.sb_id_and_flags, igu_addr); 2314 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2315 2316 /* Make sure that ACK is written */ 2317 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2318 BUS_SPACE_BARRIER_WRITE); 2319 mb(); 2320} 2321 2322static inline void 2323bxe_hc_ack_sb(struct bxe_softc *sc, 2324 uint8_t sb_id, 2325 uint8_t storm, 2326 uint16_t index, 2327 uint8_t op, 2328 uint8_t update) 2329{ 2330 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2331 COMMAND_REG_INT_ACK); 2332 struct igu_ack_register igu_ack; 2333 2334 igu_ack.status_block_index = index; 2335 igu_ack.sb_id_and_flags = 2336 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2337 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2338 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2339 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2340 2341 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2342 2343 /* Make sure that ACK is written */ 2344 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2345 BUS_SPACE_BARRIER_WRITE); 2346 mb(); 2347} 2348 2349static inline void 2350bxe_ack_sb(struct bxe_softc *sc, 2351 uint8_t igu_sb_id, 2352 uint8_t storm, 2353 uint16_t index, 2354 uint8_t op, 2355 uint8_t update) 2356{ 2357 if (sc->devinfo.int_block == INT_BLOCK_HC) 2358 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2359 else { 2360 uint8_t segment; 2361 if (CHIP_INT_MODE_IS_BC(sc)) { 2362 segment = storm; 2363 } else if (igu_sb_id != sc->igu_dsb_id) { 2364 segment = IGU_SEG_ACCESS_DEF; 2365 } else if (storm == ATTENTION_ID) { 2366 segment = IGU_SEG_ACCESS_ATTN; 2367 } else { 2368 segment = IGU_SEG_ACCESS_DEF; 2369 } 2370 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2371 } 2372} 2373 2374static inline uint16_t 2375bxe_hc_ack_int(struct bxe_softc *sc) 2376{ 2377 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2378 COMMAND_REG_SIMD_MASK); 2379 uint32_t result = REG_RD(sc, hc_addr); 2380 2381 mb(); 2382 return (result); 2383} 2384 2385static inline uint16_t 2386bxe_igu_ack_int(struct bxe_softc *sc) 2387{ 2388 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2389 uint32_t result = REG_RD(sc, igu_addr); 2390 2391 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2392 result, igu_addr); 2393 2394 mb(); 2395 return (result); 2396} 2397 2398static inline uint16_t 2399bxe_ack_int(struct bxe_softc *sc) 2400{ 2401 mb(); 2402 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2403 return (bxe_hc_ack_int(sc)); 2404 } else { 2405 return (bxe_igu_ack_int(sc)); 2406 } 2407} 2408 2409static inline int 2410func_by_vn(struct bxe_softc *sc, 2411 int vn) 2412{ 2413 return (2 * vn + SC_PORT(sc)); 2414} 2415 2416/* 2417 * Statistics ID are global per chip/path, while Client IDs for E1x 2418 * are per port. 2419 */ 2420static inline uint8_t 2421bxe_stats_id(struct bxe_fastpath *fp) 2422{ 2423 struct bxe_softc *sc = fp->sc; 2424 2425 if (!CHIP_IS_E1x(sc)) { 2426 return (fp->cl_id); 2427 } 2428 2429 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2430} 2431 2432#endif /* __BXE_H__ */ 2433 2434