1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer,
12 *    without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 *    redistribution must be conditioned upon including a substantially
16 *    similar Disclaimer requirement for further binary redistribution.
17 *
18 * NO WARRANTY
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
30 *
31 */
32
33#ifndef _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_
34#define _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_
35
36/*
37 * PCI/PCIe-Gen1 Host Bridge definitions.
38 */
39
40#include <sys/param.h>
41#include <sys/bus.h>
42
43#include "bhnd_pcivar.h"
44
45DECLARE_CLASS(bhnd_pci_hostb_driver);
46
47/**
48 * PCI/PCIe-Gen1 endpoint-mode device quirks
49 */
50enum {
51	/** No quirks */
52	BHND_PCI_QUIRK_NONE			= 0,
53
54	/**
55	 * SBTOPCI_PREF and SBTOPCI_BURST must be set on the
56	 * SSB_PCICORE_SBTOPCI2 register.
57	 */
58	BHND_PCI_QUIRK_SBTOPCI2_PREF_BURST	= (1<<1),
59
60	/**
61	 * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2
62	 * register.
63	 */
64	BHND_PCI_QUIRK_SBTOPCI2_READMULTI	= (1<<2),
65
66	/**
67	 * PCI CLKRUN# should be disabled on attach (via CLKRUN_DSBL).
68	 *
69	 * The purpose of this work-around is unclear; there is some
70	 * documentation regarding earlier Broadcom drivers supporting
71	 * a "force CLKRUN#" *enable* registry key for use on mobile
72	 * hardware.
73	 */
74	BHND_PCI_QUIRK_CLKRUN_DSBL		= (1<<3),
75
76	/**
77	 * On PCI-attached BCM4321CB* boards, the PCI latency timer must be set
78	 * to 960ns on initial attach.
79	 */
80	BHND_PCI_QUIRK_960NS_LATTIM_OVR		= (1<<4),
81
82	/**
83	 * TLP workaround for unmatched address handling is required.
84	 *
85	 * This TLP workaround will enable setting of the PCIe UR status bit
86	 * on memory access to an unmatched address.
87	 */
88	BHND_PCIE_QUIRK_UR_STATUS_FIX		= (1<<5),
89
90	/**
91	 * PCI-PM power management must be explicitly enabled via
92	 * the data link control register.
93	 */
94	BHND_PCIE_QUIRK_PCIPM_REQEN		= (1<<6),
95
96	/**
97	 * Fix L0s to L0 exit transition on SerDes <= rev9 devices.
98	 *
99	 * On these devices, PCIe/SerDes symbol lock can be lost if the
100	 * reference clock has not fully stabilized during the L0s to L0
101	 * exit transition, triggering an internal reset of the chip.
102	 *
103	 * The SerDes RX CDR phase lock timers and proportional/integral
104	 * filters must be tweaked to ensure the CDR has fully stabilized
105	 * before asserting receive sequencer completion.
106	 */
107	BHND_PCIE_QUIRK_SDR9_L0s_HANG		= (1<<7),
108
109	/**
110	 * The idle time for entering L1 low-power state must be
111	 * explicitly set (to 114ns) to fix slow L1->L0 transition issues.
112	 */
113	BHND_PCIE_QUIRK_L1_IDLE_THRESH		= (1<<8),
114
115	/**
116	 * The ASPM L1 entry timer should be extended for better performance,
117	 * and restored for better power savings.
118	 */
119	BHND_PCIE_QUIRK_L1_TIMER_PERF		= (1<<9),
120
121	/**
122	 * ASPM and ECPM settings must be overridden manually.
123	 * Applies to 4311B0/4321B1 chipset revisions.
124	 *
125	 * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR
126	 * flag; if set, ASPM and CLKREQ should be explicitly disabled. If not
127	 * set, they should be explicitly enabled.
128	 *
129	 * Attach/Resume:
130	 *   - Update SRSH_ASPM_ENB flag in the SPROM ASPM register.
131	 *   - Update SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5
132	 *     register.
133	 *   - Update ASPM L0S/L1 flags in PCIER_LINK_CTL register.
134	 *   - Clear CLKREQ (ECPM) flag in PCIER_LINK_CTL register.
135	 *
136	 * Suspend:
137	 *   - Clear ASPM L1 flag in the PCIER_LINK_CTL register.
138	 *   - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register.
139	 *
140	 * Detach:
141	 *   - Set CLKREQ (ECPM) flag in the PCIER_LINK_CTL register.
142	 */
143	BHND_PCIE_QUIRK_ASPM_OVR		= (1<<10),
144
145	/**
146	 * A subset of Apple devices did not set the BHND_BFL2_PCIEWAR_OVR
147	 * flag in SPROM; on these devices, the BHND_BFL2_PCIEWAR_OVR flag
148	 * should always be treated as if set.
149	 */
150	BHND_PCIE_QUIRK_BFL2_PCIEWAR_EN		= (1<<11),
151
152	/**
153	 * Fix SerDes polarity on SerDes <= rev9 devices.
154	 *
155	 * The SerDes polarity must be saved at device attachment, and
156	 * restored on suspend/resume.
157	 */
158	BHND_PCIE_QUIRK_SDR9_POLARITY		= (1<<12),
159
160	/**
161	 * SerDes PLL down flag must be manually disabled (by ChipCommon) on
162	 * resume.
163	 */
164	BHND_PCIE_QUIRK_SERDES_NOPLLDOWN	= (1<<13),
165
166        /**
167	 * On attach and resume, consult the SPROM to determine whether
168	 * the L2/L3-Ready w/o PCI RESET work-around must be applied.
169	 *
170	 * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it
171	 */
172	BHND_PCIE_QUIRK_SPROM_L23_PCI_RESET	= (1<<14),
173
174	/**
175	 * The PCIe SerDes PLL must be configured to not retry the startup
176	 * sequence upon frequency detection failure on SerDes <= rev9 devices
177	 *
178	 * The issue this workaround resolves is unknown.
179	 */
180	BHND_PCIE_QUIRK_SDR9_NO_FREQRETRY	= (1<<15),
181
182	/**
183	 * Common flag for quirks that require PCIe SerDes TX
184	 * drive strength adjustment.
185	 *
186	 * Only applies to PCIe >= rev10 devices.
187	 */
188	BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST	= (1<<16),
189
190	/**
191	 * On Apple BCM94322X9 devices, the PCIe SerDes TX drive strength
192	 * should be set to 700mV.
193	 *
194	 * The exact issue is unknown, but presumably this workaround
195	 * resolves signal integrity issues with these devices.
196	 *
197	 * Only applies to PCIe >= rev10 devices.
198	 */
199	BHND_PCIE_QUIRK_SERDES_TXDRV_700MV	= (1<<17) |
200	    BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST,
201
202	/**
203	 * On some Apple BCM4331-based devices, the PCIe SerDes TX drive
204	 * strength should be set to its maximum.
205	 *
206	 * The exact issue is unknown, but presumably this workaround
207	 * resolves signal integrity issues with these devices.
208	 */
209	BHND_PCIE_QUIRK_SERDES_TXDRV_MAX	= (1<<18) |
210	    BHND_PCIE_QUIRK_SERDES_TXDRV_ADJUST,
211
212	/**
213	 * PCIe cores prior to rev18 do not support an MRRS larger than
214	 * 128 bytes.
215	 */
216	BHND_PCIE_QUIRK_MAX_MRRS_128		= (1<<19),
217
218	/**
219	 * The PCIe core should be configured with an MRRS of 512 bytes.
220	 */
221	BHND_PCIE_QUIRK_DEFAULT_MRRS_512	= (1<<20),
222};
223
224/**
225 * bhnd_pci_hostb driver instance state.
226 */
227struct bhnd_pcihb_softc {
228	struct bhnd_pci_softc	common;		/**< common bhnd_pci state */
229	device_t		dev;
230	device_t		pci_dev;	/**< host PCI device */
231	uint32_t		quirks;		/**< hostb device quirks */
232
233	/** BHND_PCIE_QUIRK_ASPM_OVR state. */
234	struct {
235		/**
236		 * ASPM/CLKREQ override setting.
237		 *
238		 * If true, ASPM/CLKREQ should be overridden as enabled.
239		 * If false, ASPM/CLKREQ should be overridden as disabled.
240		 */
241		bool aspm_en;
242	} aspm_quirk_override;
243
244	/** BHND_PCIE_QUIRK_SDR9_POLARITY state. */
245	struct {
246		/**
247		 * PCIe SerDes RX polarity.
248		 *
249		 * Initialized to the PCIe link's RX polarity
250		 * at attach time. This is used to restore the
251		 * correct polarity on resume */
252		bool	inv;
253	} sdr9_quirk_polarity;
254};
255
256#endif /* _BHND_CORES_PCI_BHND_PCI_HOSTBVAR_H_ */
257