1/* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114#ifndef __XGBE_H__ 115#define __XGBE_H__ 116 117#include <sys/param.h> 118#include <sys/kernel.h> 119#include <sys/bus.h> 120#include <sys/socket.h> 121#include <sys/bitstring.h> 122 123#include <net/if.h> 124#include <net/if_media.h> 125 126#include <dev/mii/mii.h> 127#include <dev/mii/miivar.h> 128 129#include "xgbe_osdep.h" 130 131/* From linux/dcbnl.h */ 132#define IEEE_8021QAZ_MAX_TCS 8 133 134#define XGBE_DRV_NAME "amd-xgbe" 135#define XGBE_DRV_VERSION "1.0.3" 136#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 137 138/* Descriptor related defines */ 139#define XGBE_TX_DESC_CNT 512 140#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 141#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 142#define XGBE_RX_DESC_CNT 512 143 144#define XGBE_TX_DESC_CNT_MIN 64 145#define XGBE_TX_DESC_CNT_MAX 4096 146#define XGBE_RX_DESC_CNT_MIN 64 147#define XGBE_RX_DESC_CNT_MAX 4096 148#define XGBE_TX_DESC_CNT_DEFAULT 512 149#define XGBE_RX_DESC_CNT_DEFAULT 512 150 151#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 152 153/* Descriptors required for maximum contiguous TSO/GSO packet */ 154#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 155 156/* Maximum possible descriptors needed for an SKB: 157 * - Maximum number of SKB frags 158 * - Maximum descriptors for contiguous TSO/GSO packet 159 * - Possible context descriptor 160 * - Possible TSO header descriptor 161 */ 162#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 163 164#define XGBE_RX_MIN_BUF_SIZE 1522 165#define XGBE_RX_BUF_ALIGN 64 166#define XGBE_SKB_ALLOC_SIZE 256 167#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZ */ 168 169#define XGBE_MAX_DMA_CHANNELS 16 170#define XGBE_MAX_QUEUES 16 171#define XGBE_PRIORITY_QUEUES 8 172#define XGBE_DMA_STOP_TIMEOUT 5 173 174/* DMA cache settings - Outer sharable, write-back, write-allocate */ 175#define XGBE_DMA_OS_ARCR 0x002b2b2b 176#define XGBE_DMA_OS_AWCR 0x2f2f2f2f 177 178/* DMA cache settings - System, no caches used */ 179#define XGBE_DMA_SYS_ARCR 0x00303030 180#define XGBE_DMA_SYS_AWCR 0x30303030 181 182/* DMA cache settings - PCI device */ 183#define XGBE_DMA_PCI_ARCR 0x000f0f0f 184#define XGBE_DMA_PCI_AWCR 0x0f0f0f0f 185#define XGBE_DMA_PCI_AWARCR 0x00000f0f 186 187/* DMA channel interrupt modes */ 188#define XGBE_IRQ_MODE_EDGE 0 189#define XGBE_IRQ_MODE_LEVEL 1 190 191#define XGMAC_MIN_PACKET 60 192#define XGMAC_STD_PACKET_MTU 1500 193#define XGMAC_MAX_STD_PACKET 1518 194#define XGMAC_JUMBO_PACKET_MTU 9000 195#define XGMAC_MAX_JUMBO_PACKET 9018 196#define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 197 198#define XGMAC_PFC_DATA_LEN 46 199#define XGMAC_PFC_DELAYS 14000 200 201#define XGMAC_PRIO_QUEUES(_cnt) \ 202 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 203 204/* Common property names */ 205#define XGBE_MAC_ADDR_PROPERTY "mac-address" 206#define XGBE_PHY_MODE_PROPERTY "phy-mode" 207#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 208#define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 209#define XGBE_BLWC_PROPERTY "amd,serdes-blwc" 210#define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" 211#define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" 212#define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp" 213#define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config" 214#define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable" 215 216/* Device-tree clock names */ 217#define XGBE_DMA_CLOCK "dma_clk" 218#define XGBE_PTP_CLOCK "ptp_clk" 219 220/* ACPI property names */ 221#define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 222#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 223 224/* PCI BAR mapping */ 225#define XGBE_XGMAC_BAR 0 226#define XGBE_XPCS_BAR 1 227#define XGBE_MAC_PROP_OFFSET 0x1d000 228#define XGBE_I2C_CTRL_OFFSET 0x1e000 229 230/* PCI MSI/MSIx support */ 231#define XGBE_MSI_BASE_COUNT 4 232#define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 233 234/* PCI clock frequencies */ 235#define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 236#define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 237 238/* Timestamp support - values based on 50MHz PTP clock 239 * 50MHz => 20 nsec 240 */ 241#define XGBE_TSTAMP_SSINC 20 242#define XGBE_TSTAMP_SNSINC 0 243 244/* Driver PMT macros */ 245#define XGMAC_DRIVER_CONTEXT 1 246#define XGMAC_IOCTL_CONTEXT 2 247 248#define XGMAC_FIFO_MIN_ALLOC 2048 249#define XGMAC_FIFO_UNIT 256 250#define XGMAC_FIFO_ALIGN(_x) \ 251 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 252#define XGMAC_FIFO_FC_OFF 2048 253#define XGMAC_FIFO_FC_MIN 4096 254#define XGBE_FIFO_MAX 81920 255 256#define XGBE_TC_MIN_QUANTUM 10 257 258/* Helper macro for descriptor handling 259 * Always use XGBE_GET_DESC_DATA to access the descriptor data 260 * since the index is free-running and needs to be and-ed 261 * with the descriptor count value of the ring to index to 262 * the proper descriptor data. 263 */ 264#define XGBE_GET_DESC_DATA(_ring, _idx) \ 265 ((_ring)->rdata + \ 266 ((_idx) & ((_ring)->rdesc_count - 1))) 267 268/* Default coalescing parameters */ 269#define XGMAC_INIT_DMA_TX_USECS 1000 270#define XGMAC_INIT_DMA_TX_FRAMES 25 271 272#define XGMAC_MAX_DMA_RIWT 0xff 273#define XGMAC_INIT_DMA_RX_USECS 30 274#define XGMAC_INIT_DMA_RX_FRAMES 25 275 276/* Flow control queue count */ 277#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 278 279/* Flow control threshold units */ 280#define XGMAC_FLOW_CONTROL_UNIT 512 281#define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 282 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 283#define XGMAC_FLOW_CONTROL_VALUE(_x) \ 284 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 285#define XGMAC_FLOW_CONTROL_MAX 33280 286 287/* Maximum MAC address hash table size (256 bits = 8 bytes) */ 288#define XGBE_MAC_HASH_TABLE_SIZE 8 289 290/* Receive Side Scaling */ 291#define XGBE_RSS_HASH_KEY_SIZE 40 292#define XGBE_RSS_MAX_TABLE_SIZE 256 293#define XGBE_RSS_LOOKUP_TABLE_TYPE 0 294#define XGBE_RSS_HASH_KEY_TYPE 1 295 296/* Auto-negotiation */ 297#define XGBE_AN_MS_TIMEOUT 500 298#define XGBE_LINK_TIMEOUT 10 299 300#define XGBE_SGMII_AN_LINK_STATUS BIT(1) 301#define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 302#define XGBE_SGMII_AN_LINK_SPEED_100 0x04 303#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 304#define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 305 306/* ECC correctable error notification window (seconds) */ 307#define XGBE_ECC_LIMIT 60 308 309#define XGBE_AN_INT_CMPLT 0x01 310#define XGBE_AN_INC_LINK 0x02 311#define XGBE_AN_PG_RCV 0x04 312#define XGBE_AN_INT_MASK 0x07 313 314#define XGBE_SGMII_AN_LINK_STATUS BIT(1) 315#define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 316#define XGBE_SGMII_AN_LINK_SPEED_100 0x04 317#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 318#define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 319 320/* Rate-change complete wait/retry count */ 321#define XGBE_RATECHANGE_COUNT 500 322 323/* Default SerDes settings */ 324#define XGBE_SPEED_10000_BLWC 0 325#define XGBE_SPEED_10000_CDR 0x7 326#define XGBE_SPEED_10000_PLL 0x1 327#define XGBE_SPEED_10000_PQ 0x12 328#define XGBE_SPEED_10000_RATE 0x0 329#define XGBE_SPEED_10000_TXAMP 0xa 330#define XGBE_SPEED_10000_WORD 0x7 331#define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1 332#define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f 333 334#define XGBE_SPEED_2500_BLWC 1 335#define XGBE_SPEED_2500_CDR 0x2 336#define XGBE_SPEED_2500_PLL 0x0 337#define XGBE_SPEED_2500_PQ 0xa 338#define XGBE_SPEED_2500_RATE 0x1 339#define XGBE_SPEED_2500_TXAMP 0xf 340#define XGBE_SPEED_2500_WORD 0x1 341#define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3 342#define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0 343 344#define XGBE_SPEED_1000_BLWC 1 345#define XGBE_SPEED_1000_CDR 0x2 346#define XGBE_SPEED_1000_PLL 0x0 347#define XGBE_SPEED_1000_PQ 0xa 348#define XGBE_SPEED_1000_RATE 0x3 349#define XGBE_SPEED_1000_TXAMP 0xf 350#define XGBE_SPEED_1000_WORD 0x1 351#define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3 352#define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0 353 354/* TSO related macros */ 355#define XGBE_TSO_MAX_SIZE UINT16_MAX 356 357/* MDIO port types */ 358#define XGMAC_MAX_C22_PORT 3 359 360/* Link mode bit operations */ 361#define XGBE_ZERO_SUP(_phy) \ 362 ((_phy)->supported = 0) 363 364#define XGBE_SET_SUP(_phy, _mode) \ 365 ((_phy)->supported |= SUPPORTED_##_mode) 366 367#define XGBE_CLR_SUP(_phy, _mode) \ 368 ((_phy)->supported &= ~SUPPORTED_##_mode) 369 370#define XGBE_IS_SUP(_phy, _mode) \ 371 ((_phy)->supported & SUPPORTED_##_mode) 372 373#define XGBE_ZERO_ADV(_phy) \ 374 ((_phy)->advertising = 0) 375 376#define XGBE_SET_ADV(_phy, _mode) \ 377 ((_phy)->advertising |= ADVERTISED_##_mode) 378 379#define XGBE_CLR_ADV(_phy, _mode) \ 380 ((_phy)->advertising &= ~ADVERTISED_##_mode) 381 382#define XGBE_ADV(_phy, _mode) \ 383 ((_phy)->advertising & ADVERTISED_##_mode) 384 385#define XGBE_ZERO_LP_ADV(_phy) \ 386 ((_phy)->lp_advertising = 0) 387 388#define XGBE_SET_LP_ADV(_phy, _mode) \ 389 ((_phy)->lp_advertising |= ADVERTISED_##_mode) 390 391#define XGBE_CLR_LP_ADV(_phy, _mode) \ 392 ((_phy)->lp_advertising &= ~ADVERTISED_##_mode) 393 394#define XGBE_LP_ADV(_phy, _mode) \ 395 ((_phy)->lp_advertising & ADVERTISED_##_mode) 396 397#define XGBE_LM_COPY(_dphy, _dname, _sphy, _sname) \ 398 ((_dphy)->_dname = (_sphy)->_sname) 399 400struct xgbe_prv_data; 401 402struct xgbe_packet_data { 403 struct mbuf *m; 404 405 unsigned int attributes; 406 407 unsigned int errors; 408 409 unsigned int rdesc_count; 410 unsigned int length; 411 412 unsigned int header_len; 413 unsigned int tcp_header_len; 414 unsigned int tcp_payload_len; 415 unsigned short mss; 416 417 unsigned short vlan_ctag; 418 419 uint64_t rx_tstamp; 420 421 unsigned int tx_packets; 422 unsigned int tx_bytes; 423 424 uint32_t rss_hash; 425 uint32_t rss_hash_type; 426}; 427 428/* Common Rx and Tx descriptor mapping */ 429struct xgbe_ring_desc { 430 __le32 desc0; 431 __le32 desc1; 432 __le32 desc2; 433 __le32 desc3; 434}; 435 436/* Tx-related ring data */ 437struct xgbe_tx_ring_data { 438 unsigned int packets; /* BQL packet count */ 439 unsigned int bytes; /* BQL byte count */ 440}; 441 442/* Rx-related ring data */ 443struct xgbe_rx_ring_data { 444 unsigned short hdr_len; /* Length of received header */ 445 unsigned short len; /* Length of received packet */ 446}; 447 448/* Structure used to hold information related to the descriptor 449 * and the packet associated with the descriptor (always use 450 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 451 */ 452struct xgbe_ring_data { 453 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 454 bus_addr_t rdata_paddr; 455 456 struct xgbe_tx_ring_data tx; /* Tx-related data */ 457 struct xgbe_rx_ring_data rx; /* Rx-related data */ 458 459 460 /* Incomplete receive save location. If the budget is exhausted 461 * or the last descriptor (last normal descriptor or a following 462 * context descriptor) has not been DMA'd yet the current state 463 * of the receive processing needs to be saved. 464 */ 465 unsigned int state_saved; 466 struct { 467 struct mbuf *m; 468 unsigned int len; 469 unsigned int error; 470 } state; 471 472}; 473 474struct xgbe_ring { 475 /* Ring lock - used just for TX rings at the moment */ 476 spinlock_t lock; 477 478 /* Per packet related information */ 479 struct xgbe_packet_data packet_data; 480 481 /* Virtual/DMA addresses and count of allocated descriptor memory */ 482 struct xgbe_ring_desc *rdesc; 483 bus_addr_t rdesc_paddr; 484 unsigned int rdesc_count; 485 486 /* Array of descriptor data corresponding the descriptor memory 487 * (always use the XGBE_GET_DESC_DATA macro to access this data) 488 */ 489 struct xgbe_ring_data *rdata; 490 491 /* Ring index values 492 * cur - Tx: index of descriptor to be used for current transfer 493 * Rx: index of descriptor to check for packet availability 494 * dirty - Tx: index of descriptor to check for transfer complete 495 * Rx: index of descriptor to check for buffer reallocation 496 */ 497 unsigned int cur; 498 unsigned int dirty; 499 500 /* Coalesce frame count used for interrupt bit setting */ 501 unsigned int coalesce_count; 502 503 union { 504 struct { 505 unsigned int queue_stopped; 506 unsigned int xmit_more; 507 unsigned short cur_mss; 508 unsigned short cur_vlan_ctag; 509 } tx; 510 }; 511 512 uint16_t prev_pidx; 513 uint8_t prev_count; 514 515} __aligned(CACHE_LINE_SIZE); 516 517/* Structure used to describe the descriptor rings associated with 518 * a DMA channel. 519 */ 520struct xgbe_channel { 521 char name[16]; 522 523 /* Address of private data area for device */ 524 struct xgbe_prv_data *pdata; 525 526 /* Queue index and base address of queue's DMA registers */ 527 unsigned int queue_index; 528 bus_space_tag_t dma_tag; 529 bus_space_handle_t dma_handle; 530 int dma_irq_rid; 531 532 /* Per channel interrupt irq number */ 533 struct resource *dma_irq_res; 534 void *dma_irq_tag; 535 536 /* Per channel interrupt enablement tracker */ 537 unsigned int curr_ier; 538 unsigned int saved_ier; 539 540 struct xgbe_ring *tx_ring; 541 struct xgbe_ring *rx_ring; 542} __aligned(CACHE_LINE_SIZE); 543 544enum xgbe_state { 545 XGBE_DOWN, 546 XGBE_LINK_INIT, 547 XGBE_LINK_ERR, 548 XGBE_STOPPED, 549}; 550 551enum xgbe_int { 552 XGMAC_INT_DMA_CH_SR_TI, 553 XGMAC_INT_DMA_CH_SR_TPS, 554 XGMAC_INT_DMA_CH_SR_TBU, 555 XGMAC_INT_DMA_CH_SR_RI, 556 XGMAC_INT_DMA_CH_SR_RBU, 557 XGMAC_INT_DMA_CH_SR_RPS, 558 XGMAC_INT_DMA_CH_SR_TI_RI, 559 XGMAC_INT_DMA_CH_SR_FBE, 560 XGMAC_INT_DMA_ALL, 561}; 562 563enum xgbe_int_state { 564 XGMAC_INT_STATE_SAVE, 565 XGMAC_INT_STATE_RESTORE, 566}; 567 568enum xgbe_ecc_sec { 569 XGBE_ECC_SEC_TX, 570 XGBE_ECC_SEC_RX, 571 XGBE_ECC_SEC_DESC, 572}; 573 574enum xgbe_speed { 575 XGBE_SPEED_1000 = 0, 576 XGBE_SPEED_2500, 577 XGBE_SPEED_10000, 578 XGBE_SPEEDS, 579}; 580 581enum xgbe_xpcs_access { 582 XGBE_XPCS_ACCESS_V1 = 0, 583 XGBE_XPCS_ACCESS_V2, 584}; 585 586enum xgbe_an_mode { 587 XGBE_AN_MODE_CL73 = 0, 588 XGBE_AN_MODE_CL73_REDRV, 589 XGBE_AN_MODE_CL37, 590 XGBE_AN_MODE_CL37_SGMII, 591 XGBE_AN_MODE_NONE, 592}; 593 594enum xgbe_an { 595 XGBE_AN_READY = 0, 596 XGBE_AN_PAGE_RECEIVED, 597 XGBE_AN_INCOMPAT_LINK, 598 XGBE_AN_COMPLETE, 599 XGBE_AN_NO_LINK, 600 XGBE_AN_ERROR, 601}; 602 603enum xgbe_rx { 604 XGBE_RX_BPA = 0, 605 XGBE_RX_XNP, 606 XGBE_RX_COMPLETE, 607 XGBE_RX_ERROR, 608}; 609 610enum xgbe_mode { 611 XGBE_MODE_KR = 0, 612 XGBE_MODE_KX, 613 XGBE_MODE_KX_1000, 614 XGBE_MODE_KX_2500, 615 XGBE_MODE_X, 616 XGBE_MODE_SGMII_100, 617 XGBE_MODE_SGMII_1000, 618 XGBE_MODE_SFI, 619 XGBE_MODE_UNKNOWN, 620}; 621 622enum xgbe_speedset { 623 XGBE_SPEEDSET_1000_10000 = 0, 624 XGBE_SPEEDSET_2500_10000, 625}; 626 627enum xgbe_mdio_mode { 628 XGBE_MDIO_MODE_NONE = 0, 629 XGBE_MDIO_MODE_CL22, 630 XGBE_MDIO_MODE_CL45, 631}; 632 633struct xgbe_phy { 634 uint32_t supported; 635 uint32_t advertising; 636 uint32_t lp_advertising; 637 638 int address; 639 640 int autoneg; 641 int speed; 642 int duplex; 643 644 int link; 645 646 int pause_autoneg; 647 int tx_pause; 648 int rx_pause; 649 650 int pause; 651 int asym_pause; 652}; 653 654enum xgbe_i2c_cmd { 655 XGBE_I2C_CMD_READ = 0, 656 XGBE_I2C_CMD_WRITE, 657}; 658 659struct xgbe_i2c_op { 660 enum xgbe_i2c_cmd cmd; 661 662 unsigned int target; 663 664 void *buf; 665 unsigned int len; 666}; 667 668struct xgbe_i2c_op_state { 669 struct xgbe_i2c_op *op; 670 671 unsigned int tx_len; 672 unsigned char *tx_buf; 673 674 unsigned int rx_len; 675 unsigned char *rx_buf; 676 677 unsigned int tx_abort_source; 678 679 int ret; 680}; 681 682struct xgbe_i2c { 683 unsigned int started; 684 unsigned int max_speed_mode; 685 unsigned int rx_fifo_size; 686 unsigned int tx_fifo_size; 687 688 struct xgbe_i2c_op_state op_state; 689}; 690 691struct xgbe_mmc_stats { 692 /* Tx Stats */ 693 uint64_t txoctetcount_gb; 694 uint64_t txframecount_gb; 695 uint64_t txbroadcastframes_g; 696 uint64_t txmulticastframes_g; 697 uint64_t tx64octets_gb; 698 uint64_t tx65to127octets_gb; 699 uint64_t tx128to255octets_gb; 700 uint64_t tx256to511octets_gb; 701 uint64_t tx512to1023octets_gb; 702 uint64_t tx1024tomaxoctets_gb; 703 uint64_t txunicastframes_gb; 704 uint64_t txmulticastframes_gb; 705 uint64_t txbroadcastframes_gb; 706 uint64_t txunderflowerror; 707 uint64_t txoctetcount_g; 708 uint64_t txframecount_g; 709 uint64_t txpauseframes; 710 uint64_t txvlanframes_g; 711 712 /* Rx Stats */ 713 uint64_t rxframecount_gb; 714 uint64_t rxoctetcount_gb; 715 uint64_t rxoctetcount_g; 716 uint64_t rxbroadcastframes_g; 717 uint64_t rxmulticastframes_g; 718 uint64_t rxcrcerror; 719 uint64_t rxrunterror; 720 uint64_t rxjabbererror; 721 uint64_t rxundersize_g; 722 uint64_t rxoversize_g; 723 uint64_t rx64octets_gb; 724 uint64_t rx65to127octets_gb; 725 uint64_t rx128to255octets_gb; 726 uint64_t rx256to511octets_gb; 727 uint64_t rx512to1023octets_gb; 728 uint64_t rx1024tomaxoctets_gb; 729 uint64_t rxunicastframes_g; 730 uint64_t rxlengtherror; 731 uint64_t rxoutofrangetype; 732 uint64_t rxpauseframes; 733 uint64_t rxfifooverflow; 734 uint64_t rxvlanframes_gb; 735 uint64_t rxwatchdogerror; 736}; 737 738struct xgbe_ext_stats { 739 uint64_t tx_tso_packets; 740 uint64_t rx_split_header_packets; 741 uint64_t rx_buffer_unavailable; 742 743 uint64_t txq_packets[XGBE_MAX_DMA_CHANNELS]; 744 uint64_t txq_bytes[XGBE_MAX_DMA_CHANNELS]; 745 uint64_t rxq_packets[XGBE_MAX_DMA_CHANNELS]; 746 uint64_t rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 747 748 uint64_t tx_vxlan_packets; 749 uint64_t rx_vxlan_packets; 750 uint64_t rx_csum_errors; 751 uint64_t rx_vxlan_csum_errors; 752}; 753 754struct xgbe_hw_if { 755 int (*tx_complete)(struct xgbe_ring_desc *); 756 757 int (*set_mac_address)(struct xgbe_prv_data *, uint8_t *addr); 758 int (*config_rx_mode)(struct xgbe_prv_data *); 759 760 int (*enable_rx_csum)(struct xgbe_prv_data *); 761 int (*disable_rx_csum)(struct xgbe_prv_data *); 762 763 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 764 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 765 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 766 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 767 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 768 769 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 770 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 771 int (*set_speed)(struct xgbe_prv_data *, int); 772 773 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 774 enum xgbe_mdio_mode); 775 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); 776 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, uint16_t); 777 778 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 779 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 780 781 void (*enable_tx)(struct xgbe_prv_data *); 782 void (*disable_tx)(struct xgbe_prv_data *); 783 void (*enable_rx)(struct xgbe_prv_data *); 784 void (*disable_rx)(struct xgbe_prv_data *); 785 786 void (*powerup_tx)(struct xgbe_prv_data *); 787 void (*powerdown_tx)(struct xgbe_prv_data *); 788 void (*powerup_rx)(struct xgbe_prv_data *); 789 void (*powerdown_rx)(struct xgbe_prv_data *); 790 791 int (*init)(struct xgbe_prv_data *); 792 int (*exit)(struct xgbe_prv_data *); 793 794 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 795 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 796 int (*dev_read)(struct xgbe_channel *); 797 void (*tx_desc_init)(struct xgbe_channel *); 798 void (*rx_desc_init)(struct xgbe_channel *); 799 void (*tx_desc_reset)(struct xgbe_ring_data *); 800 int (*is_last_desc)(struct xgbe_ring_desc *); 801 int (*is_context_desc)(struct xgbe_ring_desc *); 802 803 /* For FLOW ctrl */ 804 int (*config_tx_flow_control)(struct xgbe_prv_data *); 805 int (*config_rx_flow_control)(struct xgbe_prv_data *); 806 807 /* For RX coalescing */ 808 int (*config_rx_coalesce)(struct xgbe_prv_data *); 809 int (*config_tx_coalesce)(struct xgbe_prv_data *); 810 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 811 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 812 813 /* For RX and TX threshold config */ 814 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 815 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 816 817 /* For RX and TX Store and Forward Mode config */ 818 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 819 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 820 821 /* For TX DMA Operate on Second Frame config */ 822 int (*config_osp_mode)(struct xgbe_prv_data *); 823 824 /* For MMC statistics */ 825 void (*rx_mmc_int)(struct xgbe_prv_data *); 826 void (*tx_mmc_int)(struct xgbe_prv_data *); 827 void (*read_mmc_stats)(struct xgbe_prv_data *); 828 829 /* For Receive Side Scaling */ 830 int (*enable_rss)(struct xgbe_prv_data *); 831 int (*disable_rss)(struct xgbe_prv_data *); 832 int (*set_rss_hash_key)(struct xgbe_prv_data *, const uint8_t *); 833 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const uint32_t *); 834}; 835 836/* This structure represents implementation specific routines for an 837 * implementation of a PHY. All routines are required unless noted below. 838 * Optional routines: 839 * an_pre, an_post 840 * kr_training_pre, kr_training_post 841 * module_info, module_eeprom 842 */ 843struct xgbe_phy_impl_if { 844 /* Perform Setup/teardown actions */ 845 int (*init)(struct xgbe_prv_data *); 846 void (*exit)(struct xgbe_prv_data *); 847 848 /* Perform start/stop specific actions */ 849 int (*reset)(struct xgbe_prv_data *); 850 int (*start)(struct xgbe_prv_data *); 851 void (*stop)(struct xgbe_prv_data *); 852 853 /* Return the link status */ 854 int (*link_status)(struct xgbe_prv_data *, int *); 855 856 /* Indicate if a particular speed is valid */ 857 bool (*valid_speed)(struct xgbe_prv_data *, int); 858 859 /* Check if the specified mode can/should be used */ 860 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 861 /* Switch the PHY into various modes */ 862 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 863 /* Retrieve mode needed for a specific speed */ 864 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 865 /* Retrieve new/next mode when trying to auto-negotiate */ 866 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 867 /* Retrieve current mode */ 868 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 869 /* Retrieve interface sub-type */ 870 void (*get_type)(struct xgbe_prv_data *, struct ifmediareq *); 871 872 /* Retrieve current auto-negotiation mode */ 873 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 874 875 /* Configure auto-negotiation settings */ 876 int (*an_config)(struct xgbe_prv_data *); 877 878 /* Set/override auto-negotiation advertisement settings */ 879 void (*an_advertising)(struct xgbe_prv_data *, 880 struct xgbe_phy *); 881 882 /* Process results of auto-negotiation */ 883 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 884 885 /* Pre/Post auto-negotiation support */ 886 void (*an_pre)(struct xgbe_prv_data *); 887 void (*an_post)(struct xgbe_prv_data *); 888 889 /* Pre/Post KR training enablement support */ 890 void (*kr_training_pre)(struct xgbe_prv_data *); 891 void (*kr_training_post)(struct xgbe_prv_data *); 892 893 /* SFP module related info */ 894 int (*module_info)(struct xgbe_prv_data *pdata); 895 int (*module_eeprom)(struct xgbe_prv_data *pdata); 896}; 897 898struct xgbe_phy_if { 899 /* For PHY setup/teardown */ 900 int (*phy_init)(struct xgbe_prv_data *); 901 void (*phy_exit)(struct xgbe_prv_data *); 902 903 /* For PHY support when setting device up/down */ 904 int (*phy_reset)(struct xgbe_prv_data *); 905 int (*phy_start)(struct xgbe_prv_data *); 906 void (*phy_stop)(struct xgbe_prv_data *); 907 908 /* For PHY support while device is up */ 909 void (*phy_status)(struct xgbe_prv_data *); 910 int (*phy_config_aneg)(struct xgbe_prv_data *); 911 912 /* For PHY settings validation */ 913 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 914 915 /* For single interrupt support */ 916 void (*an_isr)(struct xgbe_prv_data *); 917 918 /* PHY implementation specific services */ 919 struct xgbe_phy_impl_if phy_impl; 920}; 921 922struct xgbe_i2c_if { 923 /* For initial I2C setup */ 924 int (*i2c_init)(struct xgbe_prv_data *); 925 926 /* For I2C support when setting device up/down */ 927 int (*i2c_start)(struct xgbe_prv_data *); 928 void (*i2c_stop)(struct xgbe_prv_data *); 929 930 /* For performing I2C operations */ 931 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 932 933 /* For single interrupt support */ 934 void (*i2c_isr)(struct xgbe_prv_data *); 935}; 936 937struct xgbe_desc_if { 938 int (*alloc_ring_resources)(struct xgbe_prv_data *); 939 void (*free_ring_resources)(struct xgbe_prv_data *); 940 int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *); 941 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 942 struct xgbe_ring_data *); 943 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 944 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 945 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 946}; 947 948/* This structure contains flags that indicate what hardware features 949 * or configurations are present in the device. 950 */ 951struct xgbe_hw_features { 952 /* HW Version */ 953 unsigned int version; 954 955 /* HW Feature Register0 */ 956 unsigned int gmii; /* 1000 Mbps support */ 957 unsigned int vlhash; /* VLAN Hash Filter */ 958 unsigned int sma; /* SMA(MDIO) Interface */ 959 unsigned int rwk; /* PMT remote wake-up packet */ 960 unsigned int mgk; /* PMT magic packet */ 961 unsigned int mmc; /* RMON module */ 962 unsigned int aoe; /* ARP Offload */ 963 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 964 unsigned int eee; /* Energy Efficient Ethernet */ 965 unsigned int tx_coe; /* Tx Checksum Offload */ 966 unsigned int rx_coe; /* Rx Checksum Offload */ 967 unsigned int addn_mac; /* Additional MAC Addresses */ 968 unsigned int ts_src; /* Timestamp Source */ 969 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 970 unsigned int vxn; /* VXLAN/NVGRE */ 971 972 /* HW Feature Register1 */ 973 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 974 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 975 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 976 unsigned int dma_width; /* DMA width */ 977 unsigned int dcb; /* DCB Feature */ 978 unsigned int sph; /* Split Header Feature */ 979 unsigned int tso; /* TCP Segmentation Offload */ 980 unsigned int dma_debug; /* DMA Debug Registers */ 981 unsigned int rss; /* Receive Side Scaling */ 982 unsigned int tc_cnt; /* Number of Traffic Classes */ 983 unsigned int hash_table_size; /* Hash Table Size */ 984 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 985 986 /* HW Feature Register2 */ 987 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 988 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 989 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 990 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 991 unsigned int pps_out_num; /* Number of PPS outputs */ 992 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 993}; 994 995struct xgbe_version_data { 996 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 997 enum xgbe_xpcs_access xpcs_access; 998 unsigned int mmc_64bit; 999 unsigned int tx_max_fifo_size; 1000 unsigned int rx_max_fifo_size; 1001 unsigned int tx_tstamp_workaround; 1002 unsigned int ecc_support; 1003 unsigned int i2c_support; 1004 unsigned int irq_reissue_support; 1005 unsigned int tx_desc_prefetch; 1006 unsigned int rx_desc_prefetch; 1007 unsigned int an_cdr_workaround; 1008}; 1009 1010struct xgbe_prv_data { 1011 if_t netdev; 1012 1013 struct platform_device *pdev; 1014 struct acpi_device *adev; 1015 device_t dev; 1016 1017 /* Version related data */ 1018 struct xgbe_version_data *vdata; 1019 1020 /* ACPI or DT flag */ 1021 unsigned int use_acpi; 1022 1023 /* XGMAC/XPCS related mmio registers */ 1024 struct resource *xgmac_res; /* XGMAC CSRs */ 1025 struct resource *xpcs_res; /* XPCS MMD registers */ 1026 struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */ 1027 struct resource *sir0_res; /* SerDes integration registers (1/2) */ 1028 struct resource *sir1_res; /* SerDes integration registers (2/2) */ 1029 1030 /* Port property registers */ 1031 unsigned int pp0; 1032 unsigned int pp1; 1033 unsigned int pp2; 1034 unsigned int pp3; 1035 unsigned int pp4; 1036 1037 /* DMA tag */ 1038 bus_dma_tag_t dmat; 1039 1040 /* XPCS indirect addressing lock */ 1041 spinlock_t xpcs_lock; 1042 unsigned int xpcs_window_def_reg; 1043 unsigned int xpcs_window_sel_reg; 1044 unsigned int xpcs_window; 1045 unsigned int xpcs_window_size; 1046 unsigned int xpcs_window_mask; 1047 1048 /* RSS addressing mutex */ 1049 struct mtx rss_mutex; 1050 1051 /* Flags representing xgbe_state */ 1052 unsigned long dev_state; 1053 1054 /* ECC support */ 1055 unsigned long tx_sec_period; 1056 unsigned long tx_ded_period; 1057 unsigned long rx_sec_period; 1058 unsigned long rx_ded_period; 1059 unsigned long desc_sec_period; 1060 unsigned long desc_ded_period; 1061 1062 unsigned int tx_sec_count; 1063 unsigned int tx_ded_count; 1064 unsigned int rx_sec_count; 1065 unsigned int rx_ded_count; 1066 unsigned int desc_ded_count; 1067 unsigned int desc_sec_count; 1068 1069 struct if_irq dev_irq; 1070 1071 struct resource *dev_irq_res; 1072 struct resource *ecc_irq_res; 1073 struct resource *i2c_irq_res; 1074 struct resource *an_irq_res; 1075 1076 int ecc_rid; 1077 int i2c_rid; 1078 int an_rid; 1079 1080 void *dev_irq_tag; 1081 void *ecc_irq_tag; 1082 void *i2c_irq_tag; 1083 void *an_irq_tag; 1084 1085 struct resource *chan_irq_res[XGBE_MAX_DMA_CHANNELS]; 1086 1087 unsigned int per_channel_irq; 1088 unsigned int irq_count; 1089 unsigned int channel_irq_count; 1090 unsigned int channel_irq_mode; 1091 1092 char ecc_name[IFNAMSIZ + 32]; 1093 1094 unsigned int isr_as_tasklet; 1095 struct xgbe_hw_if hw_if; 1096 struct xgbe_phy_if phy_if; 1097 struct xgbe_desc_if desc_if; 1098 struct xgbe_i2c_if i2c_if; 1099 1100 /* AXI DMA settings */ 1101 unsigned int coherent; 1102 unsigned int arcr; 1103 unsigned int awcr; 1104 unsigned int awarcr; 1105 1106 /* Service routine support */ 1107 struct taskqueue *dev_workqueue; 1108 struct task service_work; 1109 struct callout service_timer; 1110 struct mtx timer_mutex; 1111 1112 /* Rings for Tx/Rx on a DMA channel */ 1113 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1114 unsigned int tx_max_channel_count; 1115 unsigned int rx_max_channel_count; 1116 unsigned int total_channel_count; 1117 unsigned int channel_count; 1118 unsigned int tx_ring_count; 1119 unsigned int tx_desc_count; 1120 unsigned int rx_ring_count; 1121 unsigned int rx_desc_count; 1122 1123 unsigned int new_tx_ring_count; 1124 unsigned int new_rx_ring_count; 1125 1126 unsigned int tx_max_q_count; 1127 unsigned int rx_max_q_count; 1128 unsigned int tx_q_count; 1129 unsigned int rx_q_count; 1130 1131 /* Tx/Rx common settings */ 1132 unsigned int blen; 1133 unsigned int pbl; 1134 unsigned int aal; 1135 unsigned int rd_osr_limit; 1136 unsigned int wr_osr_limit; 1137 1138 /* Tx settings */ 1139 unsigned int tx_sf_mode; 1140 unsigned int tx_threshold; 1141 unsigned int tx_osp_mode; 1142 unsigned int tx_max_fifo_size; 1143 1144 /* Rx settings */ 1145 unsigned int rx_sf_mode; 1146 unsigned int rx_threshold; 1147 unsigned int rx_max_fifo_size; 1148 1149 /* Tx coalescing settings */ 1150 unsigned int tx_usecs; 1151 unsigned int tx_frames; 1152 1153 /* Rx coalescing settings */ 1154 unsigned int rx_riwt; 1155 unsigned int rx_usecs; 1156 unsigned int rx_frames; 1157 1158 /* Current Rx buffer size */ 1159 unsigned int rx_buf_size; 1160 1161 /* Flow control settings */ 1162 unsigned int pause_autoneg; 1163 unsigned int tx_pause; 1164 unsigned int rx_pause; 1165 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1166 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1167 1168 /* Receive Side Scaling settings */ 1169 uint8_t rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1170 uint32_t rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1171 uint32_t rss_options; 1172 unsigned int enable_rss; 1173 1174 /* VXLAN settings */ 1175 unsigned int vxlan_port_set; 1176 unsigned int vxlan_offloads_set; 1177 unsigned int vxlan_force_disable; 1178 unsigned int vxlan_port_count; 1179 uint16_t vxlan_port; 1180 uint64_t vxlan_features; 1181 1182 /* Netdev related settings */ 1183 unsigned char mac_addr[ETH_ALEN]; 1184 uint64_t netdev_features; 1185 struct xgbe_mmc_stats mmc_stats; 1186 struct xgbe_ext_stats ext_stats; 1187 1188 /* Filtering support */ 1189 bitstr_t *active_vlans; 1190 unsigned int num_active_vlans; 1191 1192 /* Device clocks */ 1193 struct clk *sysclk; 1194 unsigned long sysclk_rate; 1195 struct clk *ptpclk; 1196 unsigned long ptpclk_rate; 1197 1198 /* DCB support */ 1199 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1200 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1201 1202 /* Hardware features of the device */ 1203 struct xgbe_hw_features hw_feat; 1204 1205 /* Device work structure */ 1206 struct task restart_work; 1207 struct task stopdev_work; 1208 1209 /* Keeps track of power mode */ 1210 unsigned int power_down; 1211 1212 /* Network interface message level setting */ 1213 uint32_t msg_enable; 1214 1215 /* Current PHY settings */ 1216 int phy_link; 1217 int phy_speed; 1218 1219 /* MDIO/PHY related settings */ 1220 unsigned int phy_started; 1221 void *phy_data; 1222 struct xgbe_phy phy; 1223 int mdio_mmd; 1224 unsigned long link_check; 1225 struct mtx mdio_mutex; 1226 unsigned int mdio_addr; 1227 1228 unsigned int kr_redrv; 1229 1230 char an_name[IFNAMSIZ + 32]; 1231 struct taskqueue *an_workqueue; 1232 1233 struct task an_irq_work; 1234 1235 unsigned int speed_set; 1236 1237 /* SerDes UEFI configurable settings. 1238 * Switching between modes/speeds requires new values for some 1239 * SerDes settings. The values can be supplied as device 1240 * properties in array format. The first array entry is for 1241 * 1GbE, second for 2.5GbE and third for 10GbE 1242 */ 1243 uint32_t serdes_blwc[XGBE_SPEEDS]; 1244 uint32_t serdes_cdr_rate[XGBE_SPEEDS]; 1245 uint32_t serdes_pq_skew[XGBE_SPEEDS]; 1246 uint32_t serdes_tx_amp[XGBE_SPEEDS]; 1247 uint32_t serdes_dfe_tap_cfg[XGBE_SPEEDS]; 1248 uint32_t serdes_dfe_tap_ena[XGBE_SPEEDS]; 1249 1250 /* Auto-negotiation state machine support */ 1251 unsigned int an_int; 1252 unsigned int an_status; 1253 struct sx an_mutex; 1254 enum xgbe_an an_result; 1255 enum xgbe_an an_state; 1256 enum xgbe_rx kr_state; 1257 enum xgbe_rx kx_state; 1258 struct task an_work; 1259 unsigned int an_again; 1260 unsigned int an_supported; 1261 unsigned int parallel_detect; 1262 unsigned int fec_ability; 1263 unsigned long an_start; 1264 enum xgbe_an_mode an_mode; 1265 1266 /* I2C support */ 1267 struct xgbe_i2c i2c; 1268 struct mtx i2c_mutex; 1269 bool i2c_complete; 1270 1271 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1272 unsigned int an_cdr_track_early; 1273 1274 uint64_t features; 1275 1276 device_t axgbe_miibus; 1277 unsigned int sysctl_xgmac_reg; 1278 unsigned int sysctl_xpcs_mmd; 1279 unsigned int sysctl_xpcs_reg; 1280 1281 unsigned int sysctl_xprop_reg; 1282 unsigned int sysctl_xi2c_reg; 1283 1284 bool sysctl_an_cdr_workaround; 1285 bool sysctl_an_cdr_track_early; 1286 1287 int pcie_bus; /* PCIe bus number */ 1288 int pcie_device; /* PCIe device/slot number */ 1289 int pcie_func; /* PCIe function number */ 1290 1291 void *sys_op; 1292 uint64_t use_adaptive_rx_coalesce; 1293 uint64_t use_adaptive_tx_coalesce; 1294 uint64_t rx_coalesce_usecs; 1295 1296 unsigned int debug_level; 1297 1298 /* 1299 * Toggles the split header feature. 1300 * This requires a complete restart. 1301 */ 1302 unsigned int sph_enable; 1303 unsigned int link_workaround; 1304}; 1305 1306struct axgbe_if_softc { 1307 struct xgbe_prv_data pdata; 1308 if_softc_ctx_t scctx; 1309 if_shared_ctx_t sctx; 1310 if_ctx_t ctx; 1311 if_t ifp; 1312 struct ifmedia *media; 1313 unsigned int link_status; 1314}; 1315 1316/* Function prototypes*/ 1317void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1318void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1319void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1320void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1321void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1322void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1323void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1324void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1325void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1326 1327int xgbe_calc_rx_buf_size(if_t netdev, unsigned int mtu); 1328 1329void axgbe_sysctl_init(struct xgbe_prv_data *pdata); 1330void axgbe_sysctl_exit(struct xgbe_prv_data *pdata); 1331 1332int xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, 1333 uint16_t val); 1334int xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg); 1335 1336void xgbe_dump_i2c_registers(struct xgbe_prv_data *); 1337 1338uint32_t bitrev32(uint32_t); 1339 1340/* For debug prints */ 1341#ifdef YDEBUG 1342#define DBGPR(x...) device_printf(pdata->dev, x) 1343#else 1344#define DBGPR(x...) do { } while (0) 1345#endif 1346 1347#ifdef YDEBUG_MDIO 1348#define DBGPR_MDIO(x...) device_printf(pdata->dev, x) 1349#else 1350#define DBGPR_MDIO(x...) do { } while (0) 1351#endif 1352 1353#define axgbe_printf(lvl, ...) do { \ 1354 if (lvl <= pdata->debug_level) \ 1355 device_printf(pdata->dev, __VA_ARGS__); \ 1356} while (0) 1357 1358#define axgbe_error(...) do { \ 1359 device_printf(pdata->dev, __VA_ARGS__); \ 1360} while (0) 1361 1362#endif /* __XGBE_H__ */ 1363