1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/param.h> 30#include <sys/module.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/ata.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/sema.h> 40#include <sys/taskqueue.h> 41#include <vm/uma.h> 42#include <machine/stdarg.h> 43#include <machine/resource.h> 44#include <machine/bus.h> 45#include <sys/rman.h> 46#include <dev/pci/pcivar.h> 47#include <dev/pci/pcireg.h> 48#include <dev/ata/ata-all.h> 49#include <dev/ata/ata-pci.h> 50#include <ata_if.h> 51 52/* local prototypes */ 53static int ata_promise_chipinit(device_t dev); 54static int ata_promise_ch_attach(device_t dev); 55static int ata_promise_status(device_t dev); 56static int ata_promise_dmastart(struct ata_request *request); 57static int ata_promise_dmastop(struct ata_request *request); 58static void ata_promise_dmareset(device_t dev); 59static int ata_promise_setmode(device_t dev, int target, int mode); 60static int ata_promise_tx2_ch_attach(device_t dev); 61static int ata_promise_tx2_status(device_t dev); 62static int ata_promise_mio_ch_attach(device_t dev); 63static int ata_promise_mio_ch_detach(device_t dev); 64static void ata_promise_mio_intr(void *data); 65static int ata_promise_mio_status(device_t dev); 66static int ata_promise_mio_command(struct ata_request *request); 67static void ata_promise_mio_reset(device_t dev); 68static int ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result); 69static int ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t result); 70static u_int32_t ata_promise_mio_softreset(device_t dev, int port); 71static void ata_promise_mio_dmainit(device_t dev); 72static void ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 73static int ata_promise_mio_setmode(device_t dev, int target, int mode); 74static int ata_promise_mio_getrev(device_t dev, int target); 75static void ata_promise_sx4_intr(void *data); 76static int ata_promise_sx4_command(struct ata_request *request); 77static int ata_promise_apkt(u_int8_t *bytep, struct ata_request *request); 78static void ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt); 79static void ata_promise_next_hpkt(struct ata_pci_controller *ctlr); 80 81/* misc defines */ 82#define PR_OLD 0 83#define PR_NEW 1 84#define PR_TX 2 85#define PR_MIO 3 86#define PR_TX4 0x01 87#define PR_SX4X 0x02 88#define PR_SX6K 0x04 89#define PR_PATA 0x08 90#define PR_CMBO 0x10 91#define PR_CMBO2 0x20 92#define PR_SATA 0x40 93#define PR_SATA2 0x80 94 95/* 96 * Promise chipset support functions 97 */ 98#define ATA_PDC_APKT_OFFSET 0x00000010 99#define ATA_PDC_HPKT_OFFSET 0x00000040 100#define ATA_PDC_ASG_OFFSET 0x00000080 101#define ATA_PDC_LSG_OFFSET 0x000000c0 102#define ATA_PDC_HSG_OFFSET 0x00000100 103#define ATA_PDC_CHN_OFFSET 0x00000400 104#define ATA_PDC_BUF_BASE 0x00400000 105#define ATA_PDC_BUF_OFFSET 0x00100000 106#define ATA_PDC_MAX_HPKT 8 107#define ATA_PDC_WRITE_REG 0x00 108#define ATA_PDC_WRITE_CTL 0x0e 109#define ATA_PDC_WRITE_END 0x08 110#define ATA_PDC_WAIT_NBUSY 0x10 111#define ATA_PDC_WAIT_READY 0x18 112#define ATA_PDC_1B 0x20 113#define ATA_PDC_2B 0x40 114 115struct host_packet { 116 u_int32_t addr; 117 TAILQ_ENTRY(host_packet) chain; 118}; 119 120struct ata_promise_sx4 { 121 struct mtx mtx; 122 TAILQ_HEAD(, host_packet) queue; 123 int busy; 124}; 125 126static int 127ata_promise_probe(device_t dev) 128{ 129 struct ata_pci_controller *ctlr = device_get_softc(dev); 130 const struct ata_chip_id *idx; 131 static const struct ata_chip_id ids[] = 132 {{ ATA_PDC20246, 0, PR_OLD, 0x00, ATA_UDMA2, "PDC20246" }, 133 { ATA_PDC20262, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20262" }, 134 { ATA_PDC20263, 0, PR_NEW, 0x00, ATA_UDMA4, "PDC20263" }, 135 { ATA_PDC20265, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20265" }, 136 { ATA_PDC20267, 0, PR_NEW, 0x00, ATA_UDMA5, "PDC20267" }, 137 { ATA_PDC20268, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20268" }, 138 { ATA_PDC20269, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20269" }, 139 { ATA_PDC20270, 0, PR_TX, PR_TX4, ATA_UDMA5, "PDC20270" }, 140 { ATA_PDC20271, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20271" }, 141 { ATA_PDC20275, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20275" }, 142 { ATA_PDC20276, 0, PR_TX, PR_SX6K, ATA_UDMA6, "PDC20276" }, 143 { ATA_PDC20277, 0, PR_TX, 0x00, ATA_UDMA6, "PDC20277" }, 144 { ATA_PDC20318, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20318" }, 145 { ATA_PDC20319, 0, PR_MIO, PR_SATA, ATA_SA150, "PDC20319" }, 146 { ATA_PDC20371, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20371" }, 147 { ATA_PDC20375, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20375" }, 148 { ATA_PDC20376, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20376" }, 149 { ATA_PDC20377, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20377" }, 150 { ATA_PDC20378, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20378" }, 151 { ATA_PDC20379, 0, PR_MIO, PR_CMBO, ATA_SA150, "PDC20379" }, 152 { ATA_PDC20571, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20571" }, 153 { ATA_PDC20575, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20575" }, 154 { ATA_PDC20579, 0, PR_MIO, PR_CMBO2, ATA_SA150, "PDC20579" }, 155 { ATA_PDC20771, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC20771" }, 156 { ATA_PDC40775, 0, PR_MIO, PR_CMBO2, ATA_SA300, "PDC40775" }, 157 { ATA_PDC20617, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20617" }, 158 { ATA_PDC20618, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20618" }, 159 { ATA_PDC20619, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20619" }, 160 { ATA_PDC20620, 0, PR_MIO, PR_PATA, ATA_UDMA6, "PDC20620" }, 161 { ATA_PDC20621, 0, PR_MIO, PR_SX4X, ATA_UDMA5, "PDC20621" }, 162 { ATA_PDC20622, 0, PR_MIO, PR_SX4X, ATA_SA150, "PDC20622" }, 163 { ATA_PDC40518, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40518" }, 164 { ATA_PDC40519, 0, PR_MIO, PR_SATA2, ATA_SA150, "PDC40519" }, 165 { ATA_PDC40718, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40718" }, 166 { ATA_PDC40719, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40719" }, 167 { ATA_PDC40779, 0, PR_MIO, PR_SATA2, ATA_SA300, "PDC40779" }, 168 { 0, 0, 0, 0, 0, 0}}; 169 const char *channel; 170 uintptr_t devid = 0; 171 172 if (pci_get_vendor(dev) != ATA_PROMISE_ID) 173 return ENXIO; 174 175 if (!(idx = ata_match_chip(dev, ids))) 176 return ENXIO; 177 178 /* if we are on a SuperTrak SX6000 dont attach */ 179 if ((idx->cfg2 & PR_SX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 180 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 181 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 182 devid == ATA_I960RM) 183 return ENXIO; 184 185 /* if we are on a FastTrak TX4, adjust the interrupt resource */ 186 channel = NULL; 187 if ((idx->cfg2 & PR_TX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE && 188 !BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)), 189 GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) && 190 ((devid == ATA_DEC_21150) || (devid == ATA_DEC_21150_1))) { 191 static rman_res_t start = 0, end = 0; 192 193 if (pci_get_slot(dev) == 1) { 194 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end); 195 channel = " (channel 0+1)"; 196 } 197 else if (pci_get_slot(dev) == 2 && start && end) { 198 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end); 199 channel = " (channel 2+3)"; 200 } 201 else { 202 start = end = 0; 203 } 204 } 205 device_set_descf(dev, "Promise %s%s %s controller", idx->text, 206 channel == NULL ? "" : channel, ata_mode2str(idx->max_dma)); 207 ctlr->chip = idx; 208 ctlr->chipinit = ata_promise_chipinit; 209 return (BUS_PROBE_LOW_PRIORITY); 210} 211 212static int 213ata_promise_chipinit(device_t dev) 214{ 215 struct ata_pci_controller *ctlr = device_get_softc(dev); 216 int stat_reg; 217 218 if (ata_setup_interrupt(dev, ata_generic_intr)) 219 return ENXIO; 220 221 switch (ctlr->chip->cfg1) { 222 case PR_NEW: 223 /* setup clocks */ 224 ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a); 225 /* FALLTHROUGH */ 226 227 case PR_OLD: 228 /* enable burst mode */ 229 ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01); 230 ctlr->ch_attach = ata_promise_ch_attach; 231 ctlr->ch_detach = ata_pci_ch_detach; 232 ctlr->setmode = ata_promise_setmode; 233 return 0; 234 235 case PR_TX: 236 ctlr->ch_attach = ata_promise_tx2_ch_attach; 237 ctlr->ch_detach = ata_pci_ch_detach; 238 ctlr->setmode = ata_promise_setmode; 239 return 0; 240 241 case PR_MIO: 242 ctlr->r_type1 = SYS_RES_MEMORY; 243 ctlr->r_rid1 = PCIR_BAR(4); 244 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1, 245 &ctlr->r_rid1, RF_ACTIVE))) 246 goto failnfree; 247 248 ctlr->r_type2 = SYS_RES_MEMORY; 249 ctlr->r_rid2 = PCIR_BAR(3); 250 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 251 &ctlr->r_rid2, RF_ACTIVE))) 252 goto failnfree; 253 254 if (ctlr->chip->cfg2 == PR_SX4X) { 255 struct ata_promise_sx4 *hpkt; 256 u_int32_t dimm = ATA_INL(ctlr->r_res2, 0x000c0080); 257 258 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 259 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 260 ata_promise_sx4_intr, ctlr, &ctlr->handle)) { 261 device_printf(dev, "unable to setup interrupt\n"); 262 goto failnfree; 263 } 264 265 /* print info about cache memory */ 266 device_printf(dev, "DIMM size %dMB @ 0x%08x%s\n", 267 (((dimm >> 16) & 0xff)-((dimm >> 24) & 0xff)+1) << 4, 268 ((dimm >> 24) & 0xff), 269 ATA_INL(ctlr->r_res2, 0x000c0088) & (1<<16) ? 270 " ECC enabled" : "" ); 271 272 /* adjust cache memory parameters */ 273 ATA_OUTL(ctlr->r_res2, 0x000c000c, 274 (ATA_INL(ctlr->r_res2, 0x000c000c) & 0xffff0000)); 275 276 /* setup host packet controls */ 277 hpkt = malloc(sizeof(struct ata_promise_sx4), 278 M_ATAPCI, M_NOWAIT | M_ZERO); 279 if (hpkt == NULL) { 280 device_printf(dev, "Cannot allocate HPKT\n"); 281 goto failnfree; 282 } 283 mtx_init(&hpkt->mtx, "ATA promise HPKT lock", NULL, MTX_DEF); 284 TAILQ_INIT(&hpkt->queue); 285 hpkt->busy = 0; 286 ctlr->chipset_data = hpkt; 287 ctlr->ch_attach = ata_promise_mio_ch_attach; 288 ctlr->ch_detach = ata_promise_mio_ch_detach; 289 ctlr->reset = ata_promise_mio_reset; 290 ctlr->setmode = ata_promise_setmode; 291 ctlr->channels = 4; 292 return 0; 293 } 294 295 /* mio type controllers need an interrupt intercept */ 296 if (bus_teardown_intr(dev, ctlr->r_irq, ctlr->handle) || 297 bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL, 298 ata_promise_mio_intr, ctlr, &ctlr->handle)) { 299 device_printf(dev, "unable to setup interrupt\n"); 300 goto failnfree; 301 } 302 303 switch (ctlr->chip->cfg2) { 304 case PR_PATA: 305 ctlr->channels = ((ATA_INL(ctlr->r_res2, 0x48) & 0x01) > 0) + 306 ((ATA_INL(ctlr->r_res2, 0x48) & 0x02) > 0) + 2; 307 goto sata150; 308 case PR_CMBO: 309 ctlr->channels = 3; 310 goto sata150; 311 case PR_SATA: 312 ctlr->channels = 4; 313sata150: 314 stat_reg = 0x6c; 315 break; 316 317 case PR_CMBO2: 318 ctlr->channels = 3; 319 goto sataii; 320 case PR_SATA2: 321 default: 322 ctlr->channels = 4; 323sataii: 324 stat_reg = 0x60; 325 break; 326 } 327 328 /* prime fake interrupt register */ 329 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 330 331 /* clear SATA status and unmask interrupts */ 332 ATA_OUTL(ctlr->r_res2, stat_reg, 0x000000ff); 333 334 /* enable "long burst length" on gen2 chips */ 335 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) 336 ATA_OUTL(ctlr->r_res2, 0x44, ATA_INL(ctlr->r_res2, 0x44) | 0x2000); 337 338 ctlr->ch_attach = ata_promise_mio_ch_attach; 339 ctlr->ch_detach = ata_promise_mio_ch_detach; 340 ctlr->reset = ata_promise_mio_reset; 341 ctlr->setmode = ata_promise_mio_setmode; 342 ctlr->getrev = ata_promise_mio_getrev; 343 344 return 0; 345 } 346 347failnfree: 348 if (ctlr->r_res2) 349 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 350 if (ctlr->r_res1) 351 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1, ctlr->r_res1); 352 return ENXIO; 353} 354 355static int 356ata_promise_ch_attach(device_t dev) 357{ 358 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 359 struct ata_channel *ch = device_get_softc(dev); 360 361 if (ata_pci_ch_attach(dev)) 362 return ENXIO; 363 364 if (ctlr->chip->cfg1 == PR_NEW) { 365 ch->dma.start = ata_promise_dmastart; 366 ch->dma.stop = ata_promise_dmastop; 367 ch->dma.reset = ata_promise_dmareset; 368 } 369 370 ch->hw.status = ata_promise_status; 371 ch->flags |= ATA_NO_ATAPI_DMA; 372 ch->flags |= ATA_CHECKS_CABLE; 373 return 0; 374} 375 376static int 377ata_promise_status(device_t dev) 378{ 379 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 380 struct ata_channel *ch = device_get_softc(dev); 381 382 if (ATA_INL(ctlr->r_res1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) { 383 return ata_pci_status(dev); 384 } 385 return 0; 386} 387 388static int 389ata_promise_dmastart(struct ata_request *request) 390{ 391 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 392 struct ata_channel *ch = device_get_softc(request->parent); 393 394 if (request->flags & ATA_R_48BIT) { 395 ATA_OUTB(ctlr->r_res1, 0x11, 396 ATA_INB(ctlr->r_res1, 0x11) | (ch->unit ? 0x08 : 0x02)); 397 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 398 ((request->flags & ATA_R_READ) ? 0x05000000 : 0x06000000) | 399 (request->bytecount >> 1)); 400 } 401 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) | 402 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 403 ATA_IDX_OUTL(ch, ATA_BMDTP_PORT, request->dma->sg_bus); 404 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 405 ((request->flags & ATA_R_READ) ? ATA_BMCMD_WRITE_READ : 0) | 406 ATA_BMCMD_START_STOP); 407 ch->dma.flags |= ATA_DMA_ACTIVE; 408 return 0; 409} 410 411static int 412ata_promise_dmastop(struct ata_request *request) 413{ 414 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 415 struct ata_channel *ch = device_get_softc(request->parent); 416 int error; 417 418 if (request->flags & ATA_R_48BIT) { 419 ATA_OUTB(ctlr->r_res1, 0x11, 420 ATA_INB(ctlr->r_res1, 0x11) & ~(ch->unit ? 0x08 : 0x02)); 421 ATA_OUTL(ctlr->r_res1, ch->unit ? 0x24 : 0x20, 0); 422 } 423 error = ATA_IDX_INB(ch, ATA_BMSTAT_PORT); 424 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 425 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 426 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 427 ch->dma.flags &= ~ATA_DMA_ACTIVE; 428 return error; 429} 430 431static void 432ata_promise_dmareset(device_t dev) 433{ 434 struct ata_channel *ch = device_get_softc(dev); 435 436 ATA_IDX_OUTB(ch, ATA_BMCMD_PORT, 437 ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 438 ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 439 ch->flags &= ~ATA_DMA_ACTIVE; 440} 441 442static int 443ata_promise_setmode(device_t dev, int target, int mode) 444{ 445 device_t parent = device_get_parent(dev); 446 struct ata_pci_controller *ctlr = device_get_softc(parent); 447 struct ata_channel *ch = device_get_softc(dev); 448 int devno = (ch->unit << 1) + target; 449 static const uint32_t timings[][2] = { 450 /* PR_OLD PR_NEW mode */ 451 { 0x004ff329, 0x004fff2f }, /* PIO 0 */ 452 { 0x004fec25, 0x004ff82a }, /* PIO 1 */ 453 { 0x004fe823, 0x004ff026 }, /* PIO 2 */ 454 { 0x004fe622, 0x004fec24 }, /* PIO 3 */ 455 { 0x004fe421, 0x004fe822 }, /* PIO 4 */ 456 { 0x004567f3, 0x004acef6 }, /* MWDMA 0 */ 457 { 0x004467f3, 0x0048cef6 }, /* MWDMA 1 */ 458 { 0x004367f3, 0x0046cef6 }, /* MWDMA 2 */ 459 { 0x004367f3, 0x0046cef6 }, /* UDMA 0 */ 460 { 0x004247f3, 0x00448ef6 }, /* UDMA 1 */ 461 { 0x004127f3, 0x00436ef6 }, /* UDMA 2 */ 462 { 0, 0x00424ef6 }, /* UDMA 3 */ 463 { 0, 0x004127f3 }, /* UDMA 4 */ 464 { 0, 0x004127f3 } /* UDMA 5 */ 465 }; 466 467 mode = min(mode, ctlr->chip->max_dma); 468 469 switch (ctlr->chip->cfg1) { 470 case PR_OLD: 471 case PR_NEW: 472 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 473 (pci_read_config(parent, 0x50, 2) & 474 (ch->unit ? 1 << 11 : 1 << 10))) { 475 ata_print_cable(dev, "controller"); 476 mode = ATA_UDMA2; 477 } 478 break; 479 480 case PR_TX: 481 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 482 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 483 ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x04) { 484 ata_print_cable(dev, "controller"); 485 mode = ATA_UDMA2; 486 } 487 break; 488 489 case PR_MIO: 490 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 491 (ATA_INL(ctlr->r_res2, 492 (ctlr->chip->cfg2 & PR_SX4X ? 0x000c0260 : 0x0260) + 493 (ch->unit << 7)) & 0x01000000)) { 494 ata_print_cable(dev, "controller"); 495 mode = ATA_UDMA2; 496 } 497 break; 498 } 499 500 if (ctlr->chip->cfg1 < PR_TX) 501 pci_write_config(parent, 0x60 + (devno << 2), 502 timings[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); 503 return (mode); 504} 505 506static int 507ata_promise_tx2_ch_attach(device_t dev) 508{ 509 struct ata_channel *ch = device_get_softc(dev); 510 511 if (ata_pci_ch_attach(dev)) 512 return ENXIO; 513 514 ch->hw.status = ata_promise_tx2_status; 515 ch->flags |= ATA_CHECKS_CABLE; 516 return 0; 517} 518 519static int 520ata_promise_tx2_status(device_t dev) 521{ 522 struct ata_channel *ch = device_get_softc(dev); 523 524 ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b); 525 if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) { 526 return ata_pci_status(dev); 527 } 528 return 0; 529} 530 531static int 532ata_promise_mio_ch_attach(device_t dev) 533{ 534 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 535 struct ata_channel *ch = device_get_softc(dev); 536 int offset = (ctlr->chip->cfg2 & PR_SX4X) ? 0x000c0000 : 0; 537 int i; 538 539 ata_promise_mio_dmainit(dev); 540 541 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 542 ch->r_io[i].res = ctlr->r_res2; 543 ch->r_io[i].offset = offset + 0x0200 + (i << 2) + (ch->unit << 7); 544 } 545 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 546 ch->r_io[ATA_CONTROL].offset = offset + 0x0238 + (ch->unit << 7); 547 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 548 ata_default_registers(dev); 549 if ((ctlr->chip->cfg2 & (PR_SATA | PR_SATA2)) || 550 ((ctlr->chip->cfg2 & (PR_CMBO | PR_CMBO2)) && ch->unit < 2)) { 551 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 552 ch->r_io[ATA_SSTATUS].offset = 0x400 + (ch->unit << 8); 553 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 554 ch->r_io[ATA_SERROR].offset = 0x404 + (ch->unit << 8); 555 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 556 ch->r_io[ATA_SCONTROL].offset = 0x408 + (ch->unit << 8); 557 ch->flags |= ATA_NO_SLAVE; 558 ch->flags |= ATA_SATA; 559 } 560 ch->flags |= ATA_USE_16BIT; 561 ch->flags |= ATA_CHECKS_CABLE; 562 563 ata_generic_hw(dev); 564 if (ctlr->chip->cfg2 & PR_SX4X) { 565 ch->hw.command = ata_promise_sx4_command; 566 } 567 else { 568 ch->hw.command = ata_promise_mio_command; 569 ch->hw.status = ata_promise_mio_status; 570 ch->hw.softreset = ata_promise_mio_softreset; 571 ch->hw.pm_read = ata_promise_mio_pm_read; 572 ch->hw.pm_write = ata_promise_mio_pm_write; 573 } 574 return 0; 575} 576 577static int 578ata_promise_mio_ch_detach(device_t dev) 579{ 580 581 ata_dmafini(dev); 582 return (0); 583} 584 585static void 586ata_promise_mio_intr(void *data) 587{ 588 struct ata_pci_controller *ctlr = data; 589 struct ata_channel *ch; 590 u_int32_t vector; 591 int unit; 592 593 /* 594 * since reading interrupt status register on early "mio" chips 595 * clears the status bits we cannot read it for each channel later on 596 * in the generic interrupt routine. 597 */ 598 vector = ATA_INL(ctlr->r_res2, 0x040); 599 ATA_OUTL(ctlr->r_res2, 0x040, vector); 600 ctlr->chipset_data = (void *)(uintptr_t)vector; 601 602 for (unit = 0; unit < ctlr->channels; unit++) { 603 if ((ch = ctlr->interrupt[unit].argument)) 604 ctlr->interrupt[unit].function(ch); 605 } 606 607 ctlr->chipset_data = (void *)(uintptr_t)0xffffffff; 608} 609 610static int 611ata_promise_mio_status(device_t dev) 612{ 613 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 614 struct ata_channel *ch = device_get_softc(dev); 615 u_int32_t stat_reg, vector, status; 616 617 switch (ctlr->chip->cfg2) { 618 case PR_PATA: 619 case PR_CMBO: 620 case PR_SATA: 621 stat_reg = 0x6c; 622 break; 623 case PR_CMBO2: 624 case PR_SATA2: 625 default: 626 stat_reg = 0x60; 627 break; 628 } 629 630 /* read and acknowledge interrupt */ 631 vector = (uint32_t)(uintptr_t)ctlr->chipset_data; 632 633 /* read and clear interface status */ 634 status = ATA_INL(ctlr->r_res2, stat_reg); 635 ATA_OUTL(ctlr->r_res2, stat_reg, status & (0x00000011 << ch->unit)); 636 637 /* check for and handle disconnect events */ 638 if (status & (0x00000001 << ch->unit)) { 639 if (bootverbose) 640 device_printf(dev, "DISCONNECT requested\n"); 641 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 642 } 643 644 /* check for and handle connect events */ 645 if (status & (0x00000010 << ch->unit)) { 646 if (bootverbose) 647 device_printf(dev, "CONNECT requested\n"); 648 taskqueue_enqueue(taskqueue_thread, &ch->conntask); 649 } 650 651 /* do we have any device action ? */ 652 return (vector & (1 << (ch->unit + 1))); 653} 654 655static int 656ata_promise_mio_command(struct ata_request *request) 657{ 658 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent)); 659 struct ata_channel *ch = device_get_softc(request->parent); 660 661 u_int32_t *wordp = (u_int32_t *)ch->dma.work; 662 663 ATA_OUTL(ctlr->r_res2, (ch->unit + 1) << 2, 0x00000001); 664 665 if ((ctlr->chip->cfg2 == PR_SATA2) || 666 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 667 /* set portmultiplier port */ 668 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), request->unit & 0x0f); 669 } 670 671 /* XXX SOS add ATAPI commands support later */ 672 switch (request->u.ata.command) { 673 default: 674 return ata_generic_command(request); 675 676 case ATA_READ_DMA: 677 case ATA_READ_DMA48: 678 wordp[0] = htole32(0x04 | ((ch->unit + 1) << 16) | (0x00 << 24)); 679 break; 680 681 case ATA_WRITE_DMA: 682 case ATA_WRITE_DMA48: 683 wordp[0] = htole32(0x00 | ((ch->unit + 1) << 16) | (0x00 << 24)); 684 break; 685 } 686 wordp[1] = htole32(request->dma->sg_bus); 687 wordp[2] = 0; 688 ata_promise_apkt((u_int8_t*)wordp, request); 689 690 ATA_OUTL(ctlr->r_res2, 0x0240 + (ch->unit << 7), ch->dma.work_bus); 691 return 0; 692} 693 694static void 695ata_promise_mio_reset(device_t dev) 696{ 697 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 698 struct ata_channel *ch = device_get_softc(dev); 699 struct ata_promise_sx4 *hpktp; 700 701 switch (ctlr->chip->cfg2) { 702 case PR_SX4X: 703 704 /* softreset channel ATA module */ 705 hpktp = ctlr->chipset_data; 706 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), ch->unit + 1); 707 ata_udelay(1000); 708 ATA_OUTL(ctlr->r_res2, 0xc0260 + (ch->unit << 7), 709 (ATA_INL(ctlr->r_res2, 0xc0260 + (ch->unit << 7)) & 710 ~0x00003f9f) | (ch->unit + 1)); 711 712 /* softreset HOST module */ /* XXX SOS what about other outstandings */ 713 mtx_lock(&hpktp->mtx); 714 ATA_OUTL(ctlr->r_res2, 0xc012c, 715 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f) | (1 << 11)); 716 DELAY(10); 717 ATA_OUTL(ctlr->r_res2, 0xc012c, 718 (ATA_INL(ctlr->r_res2, 0xc012c) & ~0x00000f9f)); 719 hpktp->busy = 0; 720 mtx_unlock(&hpktp->mtx); 721 ata_generic_reset(dev); 722 break; 723 724 case PR_PATA: 725 case PR_CMBO: 726 case PR_SATA: 727 if ((ctlr->chip->cfg2 == PR_SATA) || 728 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 729 /* mask plug/unplug intr */ 730 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00110000 << ch->unit)); 731 } 732 733 /* softreset channels ATA module */ 734 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 735 ata_udelay(10000); 736 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 737 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 738 ~0x00003f9f) | (ch->unit + 1)); 739 740 if ((ctlr->chip->cfg2 == PR_SATA) || 741 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2))) { 742 if (ata_sata_phy_reset(dev, -1, 1)) 743 ata_generic_reset(dev); 744 else 745 ch->devices = 0; 746 747 /* reset and enable plug/unplug intr */ 748 ATA_OUTL(ctlr->r_res2, 0x06c, (0x00000011 << ch->unit)); 749 } 750 else 751 ata_generic_reset(dev); 752 break; 753 754 case PR_CMBO2: 755 case PR_SATA2: 756 if ((ctlr->chip->cfg2 == PR_SATA2) || 757 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 758 /* set portmultiplier port */ 759 //ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 760 761 /* mask plug/unplug intr */ 762 ATA_OUTL(ctlr->r_res2, 0x060, (0x00110000 << ch->unit)); 763 } 764 765 /* softreset channels ATA module */ 766 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), (1 << 11)); 767 ata_udelay(10000); 768 ATA_OUTL(ctlr->r_res2, 0x0260 + (ch->unit << 7), 769 (ATA_INL(ctlr->r_res2, 0x0260 + (ch->unit << 7)) & 770 ~0x00003f9f) | (ch->unit + 1)); 771 772 if ((ctlr->chip->cfg2 == PR_SATA2) || 773 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) { 774 /* set PHY mode to "improved" */ 775 ATA_OUTL(ctlr->r_res2, 0x414 + (ch->unit << 8), 776 (ATA_INL(ctlr->r_res2, 0x414 + (ch->unit << 8)) & 777 ~0x00000003) | 0x00000001); 778 779 if (ata_sata_phy_reset(dev, -1, 1)) { 780 u_int32_t signature = ch->hw.softreset(dev, ATA_PM); 781 782 if (bootverbose) 783 device_printf(dev, "SIGNATURE: %08x\n", signature); 784 785 switch (signature >> 16) { 786 case 0x0000: 787 ch->devices = ATA_ATA_MASTER; 788 break; 789 case 0x9669: 790 ch->devices = ATA_PORTMULTIPLIER; 791 ata_pm_identify(dev); 792 break; 793 case 0xeb14: 794 ch->devices = ATA_ATAPI_MASTER; 795 break; 796 default: /* SOS XXX */ 797 if (bootverbose) 798 device_printf(dev, 799 "No signature, assuming disk device\n"); 800 ch->devices = ATA_ATA_MASTER; 801 } 802 if (bootverbose) 803 device_printf(dev, "promise_mio_reset devices=%08x\n", 804 ch->devices); 805 806 } else 807 ch->devices = 0; 808 809 /* reset and enable plug/unplug intr */ 810 ATA_OUTL(ctlr->r_res2, 0x060, (0x00000011 << ch->unit)); 811 812 ///* set portmultiplier port */ 813 ATA_OUTL(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x00); 814 } 815 else 816 ata_generic_reset(dev); 817 break; 818 } 819} 820 821static int 822ata_promise_mio_pm_read(device_t dev, int port, int reg, u_int32_t *result) 823{ 824 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 825 struct ata_channel *ch = device_get_softc(dev); 826 int timeout = 0; 827 828 if (port < 0) { 829 *result = ATA_IDX_INL(ch, reg); 830 return (0); 831 } 832 if (port < ATA_PM) { 833 switch (reg) { 834 case ATA_SSTATUS: 835 reg = 0; 836 break; 837 case ATA_SERROR: 838 reg = 1; 839 break; 840 case ATA_SCONTROL: 841 reg = 2; 842 break; 843 default: 844 return (EINVAL); 845 } 846 } 847 /* set portmultiplier port */ 848 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 849 850 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 851 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 852 853 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_READ_PM); 854 855 while (timeout < 1000000) { 856 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 857 if (!(status & ATA_S_BUSY)) 858 break; 859 timeout += 1000; 860 DELAY(1000); 861 } 862 if (timeout >= 1000000) 863 return ATA_E_ABORT; 864 865 *result = ATA_IDX_INB(ch, ATA_COUNT) | 866 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 867 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 868 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 869 return 0; 870} 871 872static int 873ata_promise_mio_pm_write(device_t dev, int port, int reg, u_int32_t value) 874{ 875 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 876 struct ata_channel *ch = device_get_softc(dev); 877 int timeout = 0; 878 879 if (port < 0) { 880 ATA_IDX_OUTL(ch, reg, value); 881 return (0); 882 } 883 if (port < ATA_PM) { 884 switch (reg) { 885 case ATA_SSTATUS: 886 reg = 0; 887 break; 888 case ATA_SERROR: 889 reg = 1; 890 break; 891 case ATA_SCONTROL: 892 reg = 2; 893 break; 894 default: 895 return (EINVAL); 896 } 897 } 898 /* set portmultiplier port */ 899 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), 0x0f); 900 901 ATA_IDX_OUTB(ch, ATA_FEATURE, reg); 902 ATA_IDX_OUTB(ch, ATA_DRIVE, port); 903 ATA_IDX_OUTB(ch, ATA_COUNT, value & 0xff); 904 ATA_IDX_OUTB(ch, ATA_SECTOR, (value >> 8) & 0xff); 905 ATA_IDX_OUTB(ch, ATA_CYL_LSB, (value >> 16) & 0xff); 906 ATA_IDX_OUTB(ch, ATA_CYL_MSB, (value >> 24) & 0xff); 907 908 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_WRITE_PM); 909 910 while (timeout < 1000000) { 911 u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS); 912 if (!(status & ATA_S_BUSY)) 913 break; 914 timeout += 1000; 915 DELAY(1000); 916 } 917 if (timeout >= 1000000) 918 return ATA_E_ABORT; 919 920 return ATA_IDX_INB(ch, ATA_ERROR); 921} 922 923/* must be called with ATA channel locked and state_mtx held */ 924static u_int32_t 925ata_promise_mio_softreset(device_t dev, int port) 926{ 927 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 928 struct ata_channel *ch = device_get_softc(dev); 929 int timeout; 930 931 /* set portmultiplier port */ 932 ATA_OUTB(ctlr->r_res2, 0x4e8 + (ch->unit << 8), port & 0x0f); 933 934 /* softreset device on this channel */ 935 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER)); 936 DELAY(10); 937 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET); 938 ata_udelay(10000); 939 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS); 940 ata_udelay(150000); 941 ATA_IDX_INB(ch, ATA_ERROR); 942 943 /* wait for BUSY to go inactive */ 944 for (timeout = 0; timeout < 100; timeout++) { 945 u_int8_t /* err, */ stat; 946 947 /* err = */ ATA_IDX_INB(ch, ATA_ERROR); 948 stat = ATA_IDX_INB(ch, ATA_STATUS); 949 950 //if (stat == err && timeout > (stat & ATA_S_BUSY ? 100 : 10)) 951 //break; 952 953 if (!(stat & ATA_S_BUSY)) { 954 //if ((err & 0x7f) == ATA_E_ILI) { 955 return ATA_IDX_INB(ch, ATA_COUNT) | 956 (ATA_IDX_INB(ch, ATA_SECTOR) << 8) | 957 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 16) | 958 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 24); 959 //} 960 //else if (stat & 0x0f) { 961 //stat |= ATA_S_BUSY; 962 //} 963 } 964 965 if (!(stat & ATA_S_BUSY) || (stat == 0xff && timeout > 10)) 966 break; 967 ata_udelay(100000); 968 } 969 return -1; 970} 971 972static void 973ata_promise_mio_dmainit(device_t dev) 974{ 975 struct ata_channel *ch = device_get_softc(dev); 976 977 /* note start and stop are not used here */ 978 ch->dma.setprd = ata_promise_mio_setprd; 979 ch->dma.max_iosize = 65536; 980 ata_dmainit(dev); 981} 982 983#define MAXLASTSGSIZE (32 * sizeof(u_int32_t)) 984static void 985ata_promise_mio_setprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 986{ 987 struct ata_dmasetprd_args *args = xsc; 988 struct ata_dma_prdentry *prd = args->dmatab; 989 int i; 990 991 if ((args->error = error)) 992 return; 993 994 for (i = 0; i < nsegs; i++) { 995 prd[i].addr = htole32(segs[i].ds_addr); 996 prd[i].count = htole32(segs[i].ds_len); 997 } 998 if (segs[i - 1].ds_len > MAXLASTSGSIZE) { 999 //printf("split last SG element of %u\n", segs[i - 1].ds_len); 1000 prd[i - 1].count = htole32(segs[i - 1].ds_len - MAXLASTSGSIZE); 1001 prd[i].count = htole32(MAXLASTSGSIZE); 1002 prd[i].addr = htole32(segs[i - 1].ds_addr + 1003 (segs[i - 1].ds_len - MAXLASTSGSIZE)); 1004 nsegs++; 1005 i++; 1006 } 1007 prd[i - 1].count |= htole32(ATA_DMA_EOT); 1008 KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n")); 1009 args->nsegs = nsegs; 1010} 1011 1012static int 1013ata_promise_mio_setmode(device_t dev, int target, int mode) 1014{ 1015 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1016 struct ata_channel *ch = device_get_softc(dev); 1017 1018 if ( (ctlr->chip->cfg2 == PR_SATA) || 1019 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1020 (ctlr->chip->cfg2 == PR_SATA2) || 1021 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1022 mode = ata_sata_setmode(dev, target, mode); 1023 else 1024 mode = ata_promise_setmode(dev, target, mode); 1025 return (mode); 1026} 1027 1028static int 1029ata_promise_mio_getrev(device_t dev, int target) 1030{ 1031 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 1032 struct ata_channel *ch = device_get_softc(dev); 1033 1034 if ( (ctlr->chip->cfg2 == PR_SATA) || 1035 ((ctlr->chip->cfg2 == PR_CMBO) && (ch->unit < 2)) || 1036 (ctlr->chip->cfg2 == PR_SATA2) || 1037 ((ctlr->chip->cfg2 == PR_CMBO2) && (ch->unit < 2))) 1038 return (ata_sata_getrev(dev, target)); 1039 else 1040 return (0); 1041} 1042 1043static void 1044ata_promise_sx4_intr(void *data) 1045{ 1046 struct ata_pci_controller *ctlr = data; 1047 struct ata_channel *ch; 1048 u_int32_t vector = ATA_INL(ctlr->r_res2, 0x000c0480); 1049 int unit; 1050 1051 for (unit = 0; unit < ctlr->channels; unit++) { 1052 if (vector & (1 << (unit + 1))) 1053 if ((ch = ctlr->interrupt[unit].argument)) 1054 ctlr->interrupt[unit].function(ch); 1055 if (vector & (1 << (unit + 5))) 1056 if ((ch = ctlr->interrupt[unit].argument)) 1057 ata_promise_queue_hpkt(ctlr, 1058 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1059 ATA_PDC_HPKT_OFFSET)); 1060 if (vector & (1 << (unit + 9))) { 1061 ata_promise_next_hpkt(ctlr); 1062 if ((ch = ctlr->interrupt[unit].argument)) 1063 ctlr->interrupt[unit].function(ch); 1064 } 1065 if (vector & (1 << (unit + 13))) { 1066 ata_promise_next_hpkt(ctlr); 1067 if ((ch = ctlr->interrupt[unit].argument)) 1068 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1069 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + 1070 ATA_PDC_APKT_OFFSET)); 1071 } 1072 } 1073} 1074 1075static int 1076ata_promise_sx4_command(struct ata_request *request) 1077{ 1078 device_t gparent = device_get_parent(request->parent); 1079 struct ata_pci_controller *ctlr = device_get_softc(gparent); 1080 struct ata_channel *ch = device_get_softc(request->parent); 1081 struct ata_dma_prdentry *prd; 1082 caddr_t window = rman_get_virtual(ctlr->r_res1); 1083 u_int32_t *wordp; 1084 int i, idx; 1085 1086 /* XXX SOS add ATAPI commands support later */ 1087 switch (request->u.ata.command) { 1088 1089 default: 1090 return -1; 1091 1092 case ATA_ATA_IDENTIFY: 1093 case ATA_READ: 1094 case ATA_READ48: 1095 case ATA_READ_MUL: 1096 case ATA_READ_MUL48: 1097 case ATA_WRITE: 1098 case ATA_WRITE48: 1099 case ATA_WRITE_MUL: 1100 case ATA_WRITE_MUL48: 1101 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1102 return ata_generic_command(request); 1103 1104 case ATA_SETFEATURES: 1105 case ATA_FLUSHCACHE: 1106 case ATA_FLUSHCACHE48: 1107 case ATA_SLEEP: 1108 case ATA_SET_MULTI: 1109 wordp = (u_int32_t *) 1110 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1111 wordp[0] = htole32(0x08 | ((ch->unit + 1)<<16) | (0x00 << 24)); 1112 wordp[1] = 0; 1113 wordp[2] = 0; 1114 ata_promise_apkt((u_int8_t *)wordp, request); 1115 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1116 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit + 1) << 2), 0x00000001); 1117 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1118 htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_APKT_OFFSET)); 1119 return 0; 1120 1121 case ATA_READ_DMA: 1122 case ATA_READ_DMA48: 1123 case ATA_WRITE_DMA: 1124 case ATA_WRITE_DMA48: 1125 prd = request->dma->sg; 1126 wordp = (u_int32_t *) 1127 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HSG_OFFSET); 1128 i = idx = 0; 1129 do { 1130 wordp[idx++] = prd[i].addr; 1131 wordp[idx++] = prd[i].count; 1132 } while (!(prd[i++].count & ATA_DMA_EOT)); 1133 1134 wordp = (u_int32_t *) 1135 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_LSG_OFFSET); 1136 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1137 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1138 1139 wordp = (u_int32_t *) 1140 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_ASG_OFFSET); 1141 wordp[0] = htole32((ch->unit * ATA_PDC_BUF_OFFSET) + ATA_PDC_BUF_BASE); 1142 wordp[1] = htole32(request->bytecount | ATA_DMA_EOT); 1143 1144 wordp = (u_int32_t *) 1145 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET); 1146 if (request->flags & ATA_R_READ) 1147 wordp[0] = htole32(0x14 | ((ch->unit+9)<<16) | ((ch->unit+5)<<24)); 1148 if (request->flags & ATA_R_WRITE) 1149 wordp[0] = htole32(0x00 | ((ch->unit+13)<<16) | (0x00<<24)); 1150 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_HSG_OFFSET); 1151 wordp[2] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_LSG_OFFSET); 1152 wordp[3] = 0; 1153 1154 wordp = (u_int32_t *) 1155 (window + (ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET); 1156 if (request->flags & ATA_R_READ) 1157 wordp[0] = htole32(0x04 | ((ch->unit+5)<<16) | (0x00<<24)); 1158 if (request->flags & ATA_R_WRITE) 1159 wordp[0] = htole32(0x10 | ((ch->unit+1)<<16) | ((ch->unit+13)<<24)); 1160 wordp[1] = htole32((ch->unit * ATA_PDC_CHN_OFFSET)+ATA_PDC_ASG_OFFSET); 1161 wordp[2] = 0; 1162 ata_promise_apkt((u_int8_t *)wordp, request); 1163 ATA_OUTL(ctlr->r_res2, 0x000c0484, 0x00000001); 1164 1165 if (request->flags & ATA_R_READ) { 1166 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+5)<<2), 0x00000001); 1167 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+9)<<2), 0x00000001); 1168 ATA_OUTL(ctlr->r_res2, 0x000c0240 + (ch->unit << 7), 1169 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_APKT_OFFSET)); 1170 } 1171 if (request->flags & ATA_R_WRITE) { 1172 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+1)<<2), 0x00000001); 1173 ATA_OUTL(ctlr->r_res2, 0x000c0400 + ((ch->unit+13)<<2), 0x00000001); 1174 ata_promise_queue_hpkt(ctlr, 1175 htole32((ch->unit * ATA_PDC_CHN_OFFSET) + ATA_PDC_HPKT_OFFSET)); 1176 } 1177 return 0; 1178 } 1179} 1180 1181static int 1182ata_promise_apkt(u_int8_t *bytep, struct ata_request *request) 1183{ 1184 int i = 12; 1185 1186 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_PDC_WAIT_NBUSY|ATA_DRIVE; 1187 bytep[i++] = ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit); 1188 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_CTL; 1189 bytep[i++] = ATA_A_4BIT; 1190 1191 if (request->flags & ATA_R_48BIT) { 1192 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1193 bytep[i++] = request->u.ata.feature >> 8; 1194 bytep[i++] = request->u.ata.feature; 1195 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_COUNT; 1196 bytep[i++] = request->u.ata.count >> 8; 1197 bytep[i++] = request->u.ata.count; 1198 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1199 bytep[i++] = request->u.ata.lba >> 24; 1200 bytep[i++] = request->u.ata.lba; 1201 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1202 bytep[i++] = request->u.ata.lba >> 32; 1203 bytep[i++] = request->u.ata.lba >> 8; 1204 bytep[i++] = ATA_PDC_2B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1205 bytep[i++] = request->u.ata.lba >> 40; 1206 bytep[i++] = request->u.ata.lba >> 16; 1207 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1208 bytep[i++] = ATA_D_LBA | ATA_DEV(request->unit); 1209 } 1210 else { 1211 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_FEATURE; 1212 bytep[i++] = request->u.ata.feature; 1213 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_COUNT; 1214 bytep[i++] = request->u.ata.count; 1215 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_SECTOR; 1216 bytep[i++] = request->u.ata.lba; 1217 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_LSB; 1218 bytep[i++] = request->u.ata.lba >> 8; 1219 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_CYL_MSB; 1220 bytep[i++] = request->u.ata.lba >> 16; 1221 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_REG | ATA_DRIVE; 1222 bytep[i++] = ATA_D_LBA | ATA_D_IBM | ATA_DEV(request->unit) | 1223 ((request->u.ata.lba >> 24)&0xf); 1224 } 1225 bytep[i++] = ATA_PDC_1B | ATA_PDC_WRITE_END | ATA_COMMAND; 1226 bytep[i++] = request->u.ata.command; 1227 return i; 1228} 1229 1230static void 1231ata_promise_queue_hpkt(struct ata_pci_controller *ctlr, u_int32_t hpkt) 1232{ 1233 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1234 1235 mtx_lock(&hpktp->mtx); 1236 if (hpktp->busy) { 1237 struct host_packet *hp = 1238 malloc(sizeof(struct host_packet), M_TEMP, M_NOWAIT | M_ZERO); 1239 hp->addr = hpkt; 1240 TAILQ_INSERT_TAIL(&hpktp->queue, hp, chain); 1241 } 1242 else { 1243 hpktp->busy = 1; 1244 ATA_OUTL(ctlr->r_res2, 0x000c0100, hpkt); 1245 } 1246 mtx_unlock(&hpktp->mtx); 1247} 1248 1249static void 1250ata_promise_next_hpkt(struct ata_pci_controller *ctlr) 1251{ 1252 struct ata_promise_sx4 *hpktp = ctlr->chipset_data; 1253 struct host_packet *hp; 1254 1255 mtx_lock(&hpktp->mtx); 1256 if ((hp = TAILQ_FIRST(&hpktp->queue))) { 1257 TAILQ_REMOVE(&hpktp->queue, hp, chain); 1258 ATA_OUTL(ctlr->r_res2, 0x000c0100, hp->addr); 1259 free(hp, M_TEMP); 1260 } 1261 else 1262 hpktp->busy = 0; 1263 mtx_unlock(&hpktp->mtx); 1264} 1265 1266ATA_DECLARE_DRIVER(ata_promise); 1267