1/*- 2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include "opt_altera_msgdma.h" 32 33/* Altera mSGDMA registers. */ 34#define DMA_STATUS 0x00 35#define STATUS_RESETTING (1 << 6) 36#define DMA_CONTROL 0x04 37#define CONTROL_GIEM (1 << 4) /* Global Interrupt Enable Mask */ 38#define CONTROL_RESET (1 << 1) /* Reset Dispatcher */ 39 40/* Descriptor fields. */ 41#define CONTROL_GO (1 << 31) /* Commit all the descriptor info */ 42#define CONTROL_OWN (1 << 30) /* Owned by hardware (prefetcher-enabled only) */ 43#define CONTROL_EDE (1 << 24) /* Early done enable */ 44#define CONTROL_ERR_S 16 /* Transmit Error, Error IRQ Enable */ 45#define CONTROL_ERR_M (0xff << CONTROL_ERR_S) 46#define CONTROL_ET_IRQ_EN (1 << 15) /* Early Termination IRQ Enable */ 47#define CONTROL_TC_IRQ_EN (1 << 14) /* Transfer Complete IRQ Enable */ 48#define CONTROL_END_ON_EOP (1 << 12) /* End on EOP */ 49#define CONTROL_PARK_WR (1 << 11) /* Park Writes */ 50#define CONTROL_PARK_RD (1 << 10) /* Park Reads */ 51#define CONTROL_GEN_EOP (1 << 9) /* Generate EOP */ 52#define CONTROL_GEN_SOP (1 << 8) /* Generate SOP */ 53#define CONTROL_TX_CHANNEL_S 0 /* Transmit Channel */ 54#define CONTROL_TX_CHANNEL_M (0xff << CONTROL_TRANSMIT_CH_S) 55 56/* Prefetcher */ 57#define PF_CONTROL 0x00 58#define PF_CONTROL_GIEM (1 << 3) 59#define PF_CONTROL_RESET (1 << 2) 60#define PF_CONTROL_DESC_POLL_EN (1 << 1) 61#define PF_CONTROL_RUN (1 << 0) 62#define PF_NEXT_LO 0x04 63#define PF_NEXT_HI 0x08 64#define PF_POLL_FREQ 0x0C 65#define PF_STATUS 0x10 66#define PF_STATUS_IRQ (1 << 0) 67 68#define READ4(_sc, _reg) \ 69 le32toh(bus_space_read_4(_sc->bst, _sc->bsh, _reg)) 70#define WRITE4(_sc, _reg, _val) \ 71 bus_space_write_4(_sc->bst, _sc->bsh, _reg, htole32(_val)) 72 73#define READ4_DESC(_sc, _reg) \ 74 le32toh(bus_space_read_4(_sc->bst_d, _sc->bsh_d, _reg)) 75#define WRITE4_DESC(_sc, _reg, _val) \ 76 bus_space_write_4(_sc->bst_d, _sc->bsh_d, _reg, htole32(_val)) 77 78#if defined(ALTERA_MSGDMA_DESC_STD) 79 80/* Standard descriptor format with prefetcher disabled. */ 81struct msgdma_desc { 82 uint32_t read_lo; 83 uint32_t write_lo; 84 uint32_t length; 85 uint32_t control; 86}; 87 88#elif defined(ALTERA_MSGDMA_DESC_EXT) 89 90/* Extended descriptor format with prefetcher disabled. */ 91struct msgdma_desc { 92 uint32_t read_lo; 93 uint32_t write_lo; 94 uint32_t length; 95 uint8_t write_burst; 96 uint8_t read_burst; 97 uint16_t seq_num; 98 uint16_t write_stride; 99 uint16_t read_stride; 100 uint32_t read_hi; 101 uint32_t write_hi; 102 uint32_t control; 103}; 104 105#elif defined(ALTERA_MSGDMA_DESC_PF_STD) 106 107/* Standard descriptor format with prefetcher enabled. */ 108struct msgdma_desc { 109 uint32_t read_lo; 110 uint32_t write_lo; 111 uint32_t length; 112 uint32_t next; 113 uint32_t transferred; 114 uint32_t status; 115 uint32_t reserved; 116 uint32_t control; 117}; 118 119#elif defined(ALTERA_MSGDMA_DESC_PF_EXT) 120 121/* Extended descriptor format with prefetcher enabled. */ 122struct msgdma_desc { 123 uint32_t read_lo; 124 uint32_t write_lo; 125 uint32_t length; 126 uint32_t next; 127 uint32_t transferred; 128 uint32_t status; 129 uint32_t reserved; 130 uint8_t write_burst; 131 uint8_t read_burst; 132 uint16_t seq_num; 133 uint16_t write_stride; 134 uint16_t read_stride; 135 uint32_t read_hi; 136 uint32_t write_hi; 137 uint32_t next_hi; 138 uint32_t reserved1; 139 uint32_t reserved2; 140 uint32_t reserved3; 141 uint32_t control; 142}; 143 144#else 145 146#error "mSGDMA descriptor format (kernel option) is not set." 147 148#endif 149