1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 5 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* ATA register defines */ 31#define ATA_DATA 0 /* (RW) data */ 32 33#define ATA_FEATURE 1 /* (W) feature */ 34#define ATA_F_DMA 0x01 /* enable DMA */ 35#define ATA_F_OVL 0x02 /* enable overlap */ 36 37#define ATA_COUNT 2 /* (W) sector count */ 38 39#define ATA_SECTOR 3 /* (RW) sector # */ 40#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 41#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43#define ATA_D_LBA 0x40 /* use LBA addressing */ 44#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45 46#define ATA_COMMAND 7 /* (W) command */ 47 48#define ATA_ERROR 8 /* (R) error */ 49#define ATA_E_ILI 0x01 /* illegal length */ 50#define ATA_E_NM 0x02 /* no media */ 51#define ATA_E_ABORT 0x04 /* command aborted */ 52#define ATA_E_MCR 0x08 /* media change request */ 53#define ATA_E_IDNF 0x10 /* ID not found */ 54#define ATA_E_MC 0x20 /* media changed */ 55#define ATA_E_UNC 0x40 /* uncorrectable data */ 56#define ATA_E_ICRC 0x80 /* UDMA crc error */ 57#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58 59#define ATA_IREASON 9 /* (R) interrupt reason */ 60#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61#define ATA_I_IN 0x02 /* read (1) | write (0) */ 62#define ATA_I_RELEASE 0x04 /* released bus (1) */ 63#define ATA_I_TAGMASK 0xf8 /* tag mask */ 64 65#define ATA_STATUS 10 /* (R) status */ 66#define ATA_ALTSTAT 11 /* (R) alternate status */ 67#define ATA_S_ERROR 0x01 /* error */ 68#define ATA_S_INDEX 0x02 /* index */ 69#define ATA_S_CORR 0x04 /* data corrected */ 70#define ATA_S_DRQ 0x08 /* data request */ 71#define ATA_S_DSC 0x10 /* drive seek completed */ 72#define ATA_S_SERVICE 0x10 /* drive needs service */ 73#define ATA_S_DWF 0x20 /* drive write fault */ 74#define ATA_S_DMA 0x20 /* DMA ready */ 75#define ATA_S_READY 0x40 /* drive ready */ 76#define ATA_S_BUSY 0x80 /* busy */ 77 78#define ATA_CONTROL 12 /* (W) control */ 79#define ATA_A_IDS 0x02 /* disable interrupts */ 80#define ATA_A_RESET 0x04 /* RESET controller */ 81#define ATA_A_4BIT 0x08 /* 4 head bits */ 82#define ATA_A_HOB 0x80 /* High Order Byte enable */ 83 84/* SATA register defines */ 85#define ATA_SSTATUS 13 86#define ATA_SS_DET_MASK 0x0000000f 87#define ATA_SS_DET_NO_DEVICE 0x00000000 88#define ATA_SS_DET_DEV_PRESENT 0x00000001 89#define ATA_SS_DET_PHY_ONLINE 0x00000003 90#define ATA_SS_DET_PHY_OFFLINE 0x00000004 91 92#define ATA_SS_SPD_MASK 0x000000f0 93#define ATA_SS_SPD_NO_SPEED 0x00000000 94#define ATA_SS_SPD_GEN1 0x00000010 95#define ATA_SS_SPD_GEN2 0x00000020 96#define ATA_SS_SPD_GEN3 0x00000030 97 98#define ATA_SS_IPM_MASK 0x00000f00 99#define ATA_SS_IPM_NO_DEVICE 0x00000000 100#define ATA_SS_IPM_ACTIVE 0x00000100 101#define ATA_SS_IPM_PARTIAL 0x00000200 102#define ATA_SS_IPM_SLUMBER 0x00000600 103#define ATA_SS_IPM_DEVSLEEP 0x00000800 104 105#define ATA_SERROR 14 106#define ATA_SE_DATA_CORRECTED 0x00000001 107#define ATA_SE_COMM_CORRECTED 0x00000002 108#define ATA_SE_DATA_ERR 0x00000100 109#define ATA_SE_COMM_ERR 0x00000200 110#define ATA_SE_PROT_ERR 0x00000400 111#define ATA_SE_HOST_ERR 0x00000800 112#define ATA_SE_PHY_CHANGED 0x00010000 113#define ATA_SE_PHY_IERROR 0x00020000 114#define ATA_SE_COMM_WAKE 0x00040000 115#define ATA_SE_DECODE_ERR 0x00080000 116#define ATA_SE_PARITY_ERR 0x00100000 117#define ATA_SE_CRC_ERR 0x00200000 118#define ATA_SE_HANDSHAKE_ERR 0x00400000 119#define ATA_SE_LINKSEQ_ERR 0x00800000 120#define ATA_SE_TRANSPORT_ERR 0x01000000 121#define ATA_SE_UNKNOWN_FIS 0x02000000 122#define ATA_SE_EXCHANGED 0x04000000 123 124#define ATA_SCONTROL 15 125#define ATA_SC_DET_MASK 0x0000000f 126#define ATA_SC_DET_IDLE 0x00000000 127#define ATA_SC_DET_RESET 0x00000001 128#define ATA_SC_DET_DISABLE 0x00000004 129 130#define ATA_SC_SPD_MASK 0x000000f0 131#define ATA_SC_SPD_NO_SPEED 0x00000000 132#define ATA_SC_SPD_SPEED_GEN1 0x00000010 133#define ATA_SC_SPD_SPEED_GEN2 0x00000020 134#define ATA_SC_SPD_SPEED_GEN3 0x00000030 135 136#define ATA_SC_IPM_MASK 0x00000f00 137#define ATA_SC_IPM_NONE 0x00000000 138#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 139#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 140#define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 141 142#define ATA_SACTIVE 16 143 144#define AHCI_MAX_PORTS 32 145#define AHCI_MAX_SLOTS 32 146#define AHCI_MAX_IRQS 16 147 148/* SATA AHCI v1.0 register defines */ 149#define AHCI_CAP 0x00 150#define AHCI_CAP_NPMASK 0x0000001f 151#define AHCI_CAP_SXS 0x00000020 152#define AHCI_CAP_EMS 0x00000040 153#define AHCI_CAP_CCCS 0x00000080 154#define AHCI_CAP_NCS 0x00001F00 155#define AHCI_CAP_NCS_SHIFT 8 156#define AHCI_CAP_PSC 0x00002000 157#define AHCI_CAP_SSC 0x00004000 158#define AHCI_CAP_PMD 0x00008000 159#define AHCI_CAP_FBSS 0x00010000 160#define AHCI_CAP_SPM 0x00020000 161#define AHCI_CAP_SAM 0x00080000 162#define AHCI_CAP_ISS 0x00F00000 163#define AHCI_CAP_ISS_SHIFT 20 164#define AHCI_CAP_SCLO 0x01000000 165#define AHCI_CAP_SAL 0x02000000 166#define AHCI_CAP_SALP 0x04000000 167#define AHCI_CAP_SSS 0x08000000 168#define AHCI_CAP_SMPS 0x10000000 169#define AHCI_CAP_SSNTF 0x20000000 170#define AHCI_CAP_SNCQ 0x40000000 171#define AHCI_CAP_64BIT 0x80000000 172 173#define AHCI_GHC 0x04 174#define AHCI_GHC_AE 0x80000000 175#define AHCI_GHC_MRSM 0x00000004 176#define AHCI_GHC_IE 0x00000002 177#define AHCI_GHC_HR 0x00000001 178 179#define AHCI_IS 0x08 180#define AHCI_PI 0x0c 181#define AHCI_VS 0x10 182 183#define AHCI_CCCC 0x14 184#define AHCI_CCCC_TV_MASK 0xffff0000 185#define AHCI_CCCC_TV_SHIFT 16 186#define AHCI_CCCC_CC_MASK 0x0000ff00 187#define AHCI_CCCC_CC_SHIFT 8 188#define AHCI_CCCC_INT_MASK 0x000000f8 189#define AHCI_CCCC_INT_SHIFT 3 190#define AHCI_CCCC_EN 0x00000001 191#define AHCI_CCCP 0x18 192 193#define AHCI_EM_LOC 0x1C 194#define AHCI_EM_CTL 0x20 195#define AHCI_EM_MR 0x00000001 196#define AHCI_EM_TM 0x00000100 197#define AHCI_EM_RST 0x00000200 198#define AHCI_EM_LED 0x00010000 199#define AHCI_EM_SAFTE 0x00020000 200#define AHCI_EM_SES2 0x00040000 201#define AHCI_EM_SGPIO 0x00080000 202#define AHCI_EM_SMB 0x01000000 203#define AHCI_EM_XMT 0x02000000 204#define AHCI_EM_ALHD 0x04000000 205#define AHCI_EM_PM 0x08000000 206 207#define AHCI_CAP2 0x24 208#define AHCI_CAP2_BOH 0x00000001 209#define AHCI_CAP2_NVMP 0x00000002 210#define AHCI_CAP2_APST 0x00000004 211#define AHCI_CAP2_SDS 0x00000008 212#define AHCI_CAP2_SADM 0x00000010 213#define AHCI_CAP2_DESO 0x00000020 214 215#define AHCI_BOHC 0x28 216#define AHCI_BOHC_BOS 0x00000001 217#define AHCI_BOHC_OOS 0x00000002 218#define AHCI_BOHC_SOOE 0x00000004 219#define AHCI_BOHC_OOC 0x00000008 220#define AHCI_BOHC_BB 0x00000010 221 222#define AHCI_VSCAP 0xa4 223#define AHCI_OFFSET 0x100 224#define AHCI_STEP 0x80 225 226#define AHCI_P_CLB 0x00 227#define AHCI_P_CLBU 0x04 228#define AHCI_P_FB 0x08 229#define AHCI_P_FBU 0x0c 230#define AHCI_P_IS 0x10 231#define AHCI_P_IE 0x14 232#define AHCI_P_IX_DHR 0x00000001 233#define AHCI_P_IX_PS 0x00000002 234#define AHCI_P_IX_DS 0x00000004 235#define AHCI_P_IX_SDB 0x00000008 236#define AHCI_P_IX_UF 0x00000010 237#define AHCI_P_IX_DP 0x00000020 238#define AHCI_P_IX_PC 0x00000040 239#define AHCI_P_IX_MP 0x00000080 240 241#define AHCI_P_IX_PRC 0x00400000 242#define AHCI_P_IX_IPM 0x00800000 243#define AHCI_P_IX_OF 0x01000000 244#define AHCI_P_IX_INF 0x04000000 245#define AHCI_P_IX_IF 0x08000000 246#define AHCI_P_IX_HBD 0x10000000 247#define AHCI_P_IX_HBF 0x20000000 248#define AHCI_P_IX_TFE 0x40000000 249#define AHCI_P_IX_CPD 0x80000000 250 251#define AHCI_P_CMD 0x18 252#define AHCI_P_CMD_ST 0x00000001 253#define AHCI_P_CMD_SUD 0x00000002 254#define AHCI_P_CMD_POD 0x00000004 255#define AHCI_P_CMD_CLO 0x00000008 256#define AHCI_P_CMD_FRE 0x00000010 257#define AHCI_P_CMD_CCS_MASK 0x00001f00 258#define AHCI_P_CMD_CCS_SHIFT 8 259#define AHCI_P_CMD_ISS 0x00002000 260#define AHCI_P_CMD_FR 0x00004000 261#define AHCI_P_CMD_CR 0x00008000 262#define AHCI_P_CMD_CPS 0x00010000 263#define AHCI_P_CMD_PMA 0x00020000 264#define AHCI_P_CMD_HPCP 0x00040000 265#define AHCI_P_CMD_MPSP 0x00080000 266#define AHCI_P_CMD_CPD 0x00100000 267#define AHCI_P_CMD_ESP 0x00200000 268#define AHCI_P_CMD_FBSCP 0x00400000 269#define AHCI_P_CMD_APSTE 0x00800000 270#define AHCI_P_CMD_ATAPI 0x01000000 271#define AHCI_P_CMD_DLAE 0x02000000 272#define AHCI_P_CMD_ALPE 0x04000000 273#define AHCI_P_CMD_ASP 0x08000000 274#define AHCI_P_CMD_ICC_MASK 0xf0000000 275#define AHCI_P_CMD_NOOP 0x00000000 276#define AHCI_P_CMD_ACTIVE 0x10000000 277#define AHCI_P_CMD_PARTIAL 0x20000000 278#define AHCI_P_CMD_SLUMBER 0x60000000 279#define AHCI_P_CMD_DEVSLEEP 0x80000000 280 281#define AHCI_P_TFD 0x20 282#define AHCI_P_SIG 0x24 283#define AHCI_P_SSTS 0x28 284#define AHCI_P_SCTL 0x2c 285#define AHCI_P_SERR 0x30 286#define AHCI_P_SACT 0x34 287#define AHCI_P_CI 0x38 288#define AHCI_P_SNTF 0x3C 289#define AHCI_P_FBS 0x40 290#define AHCI_P_FBS_EN 0x00000001 291#define AHCI_P_FBS_DEC 0x00000002 292#define AHCI_P_FBS_SDE 0x00000004 293#define AHCI_P_FBS_DEV 0x00000f00 294#define AHCI_P_FBS_DEV_SHIFT 8 295#define AHCI_P_FBS_ADO 0x0000f000 296#define AHCI_P_FBS_ADO_SHIFT 12 297#define AHCI_P_FBS_DWE 0x000f0000 298#define AHCI_P_FBS_DWE_SHIFT 16 299#define AHCI_P_DEVSLP 0x44 300#define AHCI_P_DEVSLP_ADSE 0x00000001 301#define AHCI_P_DEVSLP_DSP 0x00000002 302#define AHCI_P_DEVSLP_DETO 0x000003fc 303#define AHCI_P_DEVSLP_DETO_SHIFT 2 304#define AHCI_P_DEVSLP_MDAT 0x00007c00 305#define AHCI_P_DEVSLP_MDAT_SHIFT 10 306#define AHCI_P_DEVSLP_DITO 0x01ff8000 307#define AHCI_P_DEVSLP_DITO_SHIFT 15 308#define AHCI_P_DEVSLP_DM 0x0e000000 309#define AHCI_P_DEVSLP_DM_SHIFT 25 310 311/* Pessimistic prognosis on number of required S/G entries */ 312#define AHCI_SG_ENTRIES MIN(roundup(btoc(maxphys) + 1, 8), 65528) 313/* Command list. 32 commands. First, 1Kbyte aligned. */ 314#define AHCI_CL_OFFSET 0 315#define AHCI_CL_SIZE 32 316/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 317#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 318#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 319/* Total main work area. */ 320#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 321 322/* ivars value fields */ 323#define AHCI_REMAPPED_UNIT (1 << 31) /* NVMe remapped device. */ 324#define AHCI_EM_UNIT (1 << 30) /* Enclosure Mgmt device. */ 325#define AHCI_UNIT 0xff /* Channel number. */ 326 327struct ahci_dma_prd { 328 u_int64_t dba; 329 u_int32_t reserved; 330 u_int32_t dbc; /* 0 based */ 331#define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 332#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 333#define AHCI_PRD_IPC (1U << 31) 334} __packed; 335 336struct ahci_cmd_tab { 337 u_int8_t cfis[64]; 338 u_int8_t acmd[32]; 339 u_int8_t reserved[32]; 340 struct ahci_dma_prd prd_tab[]; 341} __packed; 342 343struct ahci_cmd_list { 344 u_int16_t cmd_flags; 345#define AHCI_CMD_ATAPI 0x0020 346#define AHCI_CMD_WRITE 0x0040 347#define AHCI_CMD_PREFETCH 0x0080 348#define AHCI_CMD_RESET 0x0100 349#define AHCI_CMD_BIST 0x0200 350#define AHCI_CMD_CLR_BUSY 0x0400 351 352 u_int16_t prd_length; /* PRD entries */ 353 u_int32_t bytecount; 354 u_int64_t cmd_table_phys; /* 128byte aligned */ 355} __packed; 356 357/* misc defines */ 358#define ATA_IRQ_RID 0 359#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 360 361struct ata_dmaslot { 362 bus_dmamap_t data_map; /* data DMA map */ 363 int nsegs; /* Number of segs loaded */ 364}; 365 366/* structure holding DMA related information */ 367struct ata_dma { 368 bus_dma_tag_t work_tag; /* workspace DMA tag */ 369 bus_dmamap_t work_map; /* workspace DMA map */ 370 uint8_t *work; /* workspace */ 371 bus_addr_t work_bus; /* bus address of work */ 372 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 373 bus_dmamap_t rfis_map; /* RFIS list DMA map */ 374 uint8_t *rfis; /* FIS receive area */ 375 bus_addr_t rfis_bus; /* bus address of rfis */ 376 bus_dma_tag_t data_tag; /* data DMA tag */ 377}; 378 379enum ahci_slot_states { 380 AHCI_SLOT_EMPTY, 381 AHCI_SLOT_LOADING, 382 AHCI_SLOT_RUNNING, 383 AHCI_SLOT_EXECUTING 384}; 385 386struct ahci_slot { 387 struct ahci_channel *ch; /* Channel */ 388 u_int8_t slot; /* Number of this slot */ 389 enum ahci_slot_states state; /* Slot state */ 390 u_int ct_offset; /* cmd_tab offset */ 391 union ccb *ccb; /* CCB occupying slot */ 392 struct ata_dmaslot dma; /* DMA data of this slot */ 393 struct callout timeout; /* Execution timeout */ 394}; 395 396struct ahci_device { 397 int revision; 398 int mode; 399 u_int bytecount; 400 u_int atapi; 401 u_int tags; 402 u_int caps; 403}; 404 405struct ahci_led { 406 device_t dev; /* Device handle */ 407 struct cdev *led; 408 uint8_t num; /* Number of this led */ 409 uint8_t state; /* State of this led */ 410}; 411 412#define AHCI_NUM_LEDS 3 413 414/* structure describing an ATA channel */ 415struct ahci_channel { 416 device_t dev; /* Device handle */ 417 int unit; /* Physical channel */ 418 struct resource *r_mem; /* Memory of this channel */ 419 struct resource *r_irq; /* Interrupt of this channel */ 420 void *ih; /* Interrupt handle */ 421 struct ata_dma dma; /* DMA data */ 422 struct cam_sim *sim; 423 struct cam_path *path; 424 uint32_t caps; /* Controller capabilities */ 425 uint32_t caps2; /* Controller capabilities */ 426 uint32_t chcaps; /* Channel capabilities */ 427 uint32_t chscaps; /* Channel sleep capabilities */ 428 uint16_t vendorid; /* Vendor ID from the bus */ 429 uint16_t deviceid; /* Device ID from the bus */ 430 uint16_t subvendorid; /* Subvendor ID from the bus */ 431 uint16_t subdeviceid; /* Subdevice ID from the bus */ 432 int quirks; 433 int numslots; /* Number of present slots */ 434 int pm_level; /* power management level */ 435 int devices; /* What is present */ 436 int pm_present; /* PM presence reported */ 437 int fbs_enabled; /* FIS-based switching enabled */ 438 439 void (*start)(struct ahci_channel *); 440 441 union ccb *hold[AHCI_MAX_SLOTS]; 442 struct ahci_slot slot[AHCI_MAX_SLOTS]; 443 uint32_t oslots; /* Occupied slots */ 444 uint32_t rslots; /* Running slots */ 445 uint32_t aslots; /* Slots with atomic commands */ 446 uint32_t eslots; /* Slots in error */ 447 uint32_t toslots; /* Slots in timeout */ 448 int lastslot; /* Last used slot */ 449 int taggedtarget; /* Last tagged target */ 450 int numrslots; /* Number of running slots */ 451 int numrslotspd[16];/* Number of running slots per dev */ 452 int numtslots; /* Number of tagged slots */ 453 int numtslotspd[16];/* Number of tagged slots per dev */ 454 int numhslots; /* Number of held slots */ 455 int recoverycmd; /* Our READ LOG active */ 456 int fatalerr; /* Fatal error happened */ 457 int resetting; /* Hard-reset in progress. */ 458 int resetpolldiv; /* Hard-reset poll divider. */ 459 int listening; /* SUD bit is cleared. */ 460 int wrongccs; /* CCS field in CMD was wrong */ 461 union ccb *frozen; /* Frozen command */ 462 struct callout pm_timer; /* Power management events */ 463 struct callout reset_timer; /* Hard-reset timeout */ 464 465 struct ahci_device user[16]; /* User-specified settings */ 466 struct ahci_device curr[16]; /* Current settings */ 467 468 struct mtx_padalign mtx; /* state lock */ 469 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */ 470 int batch; /* doneq is in use */ 471 472 int disablephy; /* keep PHY disabled */ 473}; 474 475struct ahci_enclosure { 476 device_t dev; /* Device handle */ 477 struct resource *r_memc; /* Control register */ 478 struct resource *r_memt; /* Transmit buffer */ 479 struct resource *r_memr; /* Receive buffer */ 480 struct cam_sim *sim; 481 struct cam_path *path; 482 struct mtx mtx; /* state lock */ 483 struct ahci_led leds[AHCI_MAX_PORTS * 3]; 484 uint32_t capsem; /* Controller capabilities */ 485 uint8_t status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */ 486 int quirks; 487 int channels; 488 uint32_t ichannels; 489}; 490 491/* structure describing a AHCI controller */ 492struct ahci_controller { 493 device_t dev; 494 bus_dma_tag_t dma_tag; 495 int r_rid; 496 int r_msix_tab_rid; 497 int r_msix_pba_rid; 498 uint16_t vendorid; /* Vendor ID from the bus */ 499 uint16_t deviceid; /* Device ID from the bus */ 500 uint16_t subvendorid; /* Subvendor ID from the bus */ 501 uint16_t subdeviceid; /* Subdevice ID from the bus */ 502 struct resource *r_mem; 503 struct resource *r_msix_table; 504 struct resource *r_msix_pba; 505 struct rman sc_iomem; 506 struct ahci_controller_irq { 507 struct ahci_controller *ctlr; 508 struct resource *r_irq; 509 void *handle; 510 int r_irq_rid; 511 int mode; 512#define AHCI_IRQ_MODE_ALL 0 513#define AHCI_IRQ_MODE_AFTER 1 514#define AHCI_IRQ_MODE_ONE 2 515 } irqs[AHCI_MAX_IRQS]; 516 uint32_t caps; /* Controller capabilities */ 517 uint32_t caps2; /* Controller capabilities */ 518 uint32_t capsem; /* Controller capabilities */ 519 uint32_t emloc; /* EM buffer location */ 520 int quirks; 521 int numirqs; 522 int channels; 523 uint32_t ichannels; 524 int ccc; /* CCC timeout */ 525 int cccv; /* CCC vector */ 526 int direct; /* Direct command completion */ 527 int msi; /* MSI interupts */ 528 int remapped_devices; /* Remapped NVMe devices */ 529 uint32_t remap_offset; 530 uint32_t remap_size; 531 struct { 532 void (*function)(void *); 533 void *argument; 534 } interrupt[AHCI_MAX_PORTS]; 535 void (*ch_start)(struct ahci_channel *); 536 int dma_coherent; /* DMA is cache-coherent */ 537 struct mtx ch_mtx; /* Lock for attached channels */ 538 struct ahci_channel *ch[AHCI_MAX_PORTS]; /* Attached channels */ 539}; 540 541enum ahci_err_type { 542 AHCI_ERR_NONE, /* No error */ 543 AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 544 AHCI_ERR_INNOCENT, /* Innocent victim. */ 545 AHCI_ERR_TFE, /* Task File Error. */ 546 AHCI_ERR_SATA, /* SATA error. */ 547 AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 548 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 549 * until READ LOG executed to reveal error. */ 550}; 551 552/* macros to hide busspace uglyness */ 553#define ATA_INB(res, offset) \ 554 bus_read_1((res), (offset)) 555#define ATA_INW(res, offset) \ 556 bus_read_2((res), (offset)) 557#define ATA_INL(res, offset) \ 558 bus_read_4((res), (offset)) 559#define ATA_INSW(res, offset, addr, count) \ 560 bus_read_multi_2((res), (offset), (addr), (count)) 561#define ATA_INSW_STRM(res, offset, addr, count) \ 562 bus_read_multi_stream_2((res), (offset), (addr), (count)) 563#define ATA_INSL(res, offset, addr, count) \ 564 bus_read_multi_4((res), (offset), (addr), (count)) 565#define ATA_INSL_STRM(res, offset, addr, count) \ 566 bus_read_multi_stream_4((res), (offset), (addr), (count)) 567#define ATA_OUTB(res, offset, value) \ 568 bus_write_1((res), (offset), (value)) 569#define ATA_OUTW(res, offset, value) \ 570 bus_write_2((res), (offset), (value)) 571#define ATA_OUTL(res, offset, value) \ 572 bus_write_4((res), (offset), (value)) 573#define ATA_OUTSW(res, offset, addr, count) \ 574 bus_write_multi_2((res), (offset), (addr), (count)) 575#define ATA_OUTSW_STRM(res, offset, addr, count) \ 576 bus_write_multi_stream_2((res), (offset), (addr), (count)) 577#define ATA_OUTSL(res, offset, addr, count) \ 578 bus_write_multi_4((res), (offset), (addr), (count)) 579#define ATA_OUTSL_STRM(res, offset, addr, count) \ 580 bus_write_multi_stream_4((res), (offset), (addr), (count)) 581 582/* 583 * On some platforms, we must ensure proper interdevice write ordering. 584 * The AHCI interrupt status register must be updated in HW before 585 * registers in interrupt controller. 586 * Unfortunately, only way how we can do it is readback. 587 * 588 * Currently, only ARM is known to have this issue. 589 */ 590#if defined(__arm__) 591#define ATA_RBL(res, offset) \ 592 bus_read_4((res), (offset)) 593#else 594#define ATA_RBL(res, offset) 595#endif 596 597#define AHCI_Q_NOFORCE 0x00000001 598#define AHCI_Q_NOPMP 0x00000002 599#define AHCI_Q_NONCQ 0x00000004 600#define AHCI_Q_1CH 0x00000008 601#define AHCI_Q_2CH 0x00000010 602#define AHCI_Q_4CH 0x00000020 603#define AHCI_Q_EDGEIS 0x00000040 604#define AHCI_Q_SATA2 0x00000080 605#define AHCI_Q_NOBSYRES 0x00000100 606#define AHCI_Q_NOAA 0x00000200 607#define AHCI_Q_NOCOUNT 0x00000400 608#define AHCI_Q_ALTSIG 0x00000800 609#define AHCI_Q_NOMSI 0x00001000 610#define AHCI_Q_ATI_PMP_BUG 0x00002000 611#define AHCI_Q_MAXIO_64K 0x00004000 612#define AHCI_Q_SATA1_UNIT0 0x00008000 /* need better method for this */ 613#define AHCI_Q_ABAR0 0x00010000 614#define AHCI_Q_1MSI 0x00020000 615#define AHCI_Q_FORCE_PI 0x00040000 616#define AHCI_Q_RESTORE_CAP 0x00080000 617#define AHCI_Q_NOMSIX 0x00100000 618#define AHCI_Q_MRVL_SR_DEL 0x00200000 619#define AHCI_Q_NOCCS 0x00400000 620#define AHCI_Q_NOAUX 0x00800000 621#define AHCI_Q_IOMMU_BUSWIDE 0x01000000 622#define AHCI_Q_SLOWDEV 0x02000000 623 624#define AHCI_Q_BIT_STRING \ 625 "\020" \ 626 "\001NOFORCE" \ 627 "\002NOPMP" \ 628 "\003NONCQ" \ 629 "\0041CH" \ 630 "\0052CH" \ 631 "\0064CH" \ 632 "\007EDGEIS" \ 633 "\010SATA2" \ 634 "\011NOBSYRES" \ 635 "\012NOAA" \ 636 "\013NOCOUNT" \ 637 "\014ALTSIG" \ 638 "\015NOMSI" \ 639 "\016ATI_PMP_BUG" \ 640 "\017MAXIO_64K" \ 641 "\020SATA1_UNIT0" \ 642 "\021ABAR0" \ 643 "\0221MSI" \ 644 "\023FORCE_PI" \ 645 "\024RESTORE_CAP" \ 646 "\025NOMSIX" \ 647 "\026MRVL_SR_DEL" \ 648 "\027NOCCS" \ 649 "\030NOAUX" \ 650 "\031IOMMU_BUSWIDE" \ 651 "\032SLOWDEV" 652 653int ahci_attach(device_t dev); 654int ahci_detach(device_t dev); 655int ahci_setup_interrupt(device_t dev); 656int ahci_print_child(device_t dev, device_t child); 657struct resource *ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 658 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); 659int ahci_release_resource(device_t dev, device_t child, struct resource *r); 660int ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 661 int flags, driver_filter_t *filter, driver_intr_t *function, 662 void *argument, void **cookiep); 663int ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 664 void *cookie); 665int ahci_child_location(device_t dev, device_t child, struct sbuf *sb); 666bus_dma_tag_t ahci_get_dma_tag(device_t dev, device_t child); 667int ahci_ctlr_reset(device_t dev); 668int ahci_ctlr_setup(device_t dev); 669void ahci_free_mem(device_t dev); 670 671/* Functions to allow AHCI EM to access other channels. */ 672void ahci_attached(device_t dev, struct ahci_channel *ch); 673void ahci_detached(device_t dev, struct ahci_channel *ch); 674struct ahci_channel * ahci_getch(device_t dev, int n); 675void ahci_putch(struct ahci_channel *ch); 676