1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include "rockchip-pinconf.dtsi"
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	auddsm {
15		/omit-if-no-ref/
16		auddsm_pins: auddsm-pins {
17			rockchip,pins =
18				/* auddsm_ln */
19				<3 RK_PA1 4 &pcfg_pull_none>,
20				/* auddsm_lp */
21				<3 RK_PA2 4 &pcfg_pull_none>,
22				/* auddsm_rn */
23				<3 RK_PA3 4 &pcfg_pull_none>,
24				/* auddsm_rp */
25				<3 RK_PA4 4 &pcfg_pull_none>;
26		};
27	};
28
29	bt1120 {
30		/omit-if-no-ref/
31		bt1120_pins: bt1120-pins {
32			rockchip,pins =
33				/* bt1120_clkout */
34				<4 RK_PB0 2 &pcfg_pull_none>,
35				/* bt1120_d0 */
36				<4 RK_PA0 2 &pcfg_pull_none>,
37				/* bt1120_d1 */
38				<4 RK_PA1 2 &pcfg_pull_none>,
39				/* bt1120_d2 */
40				<4 RK_PA2 2 &pcfg_pull_none>,
41				/* bt1120_d3 */
42				<4 RK_PA3 2 &pcfg_pull_none>,
43				/* bt1120_d4 */
44				<4 RK_PA4 2 &pcfg_pull_none>,
45				/* bt1120_d5 */
46				<4 RK_PA5 2 &pcfg_pull_none>,
47				/* bt1120_d6 */
48				<4 RK_PA6 2 &pcfg_pull_none>,
49				/* bt1120_d7 */
50				<4 RK_PA7 2 &pcfg_pull_none>,
51				/* bt1120_d8 */
52				<4 RK_PB2 2 &pcfg_pull_none>,
53				/* bt1120_d9 */
54				<4 RK_PB3 2 &pcfg_pull_none>,
55				/* bt1120_d10 */
56				<4 RK_PB4 2 &pcfg_pull_none>,
57				/* bt1120_d11 */
58				<4 RK_PB5 2 &pcfg_pull_none>,
59				/* bt1120_d12 */
60				<4 RK_PB6 2 &pcfg_pull_none>,
61				/* bt1120_d13 */
62				<4 RK_PB7 2 &pcfg_pull_none>,
63				/* bt1120_d14 */
64				<4 RK_PC0 2 &pcfg_pull_none>,
65				/* bt1120_d15 */
66				<4 RK_PC1 2 &pcfg_pull_none>;
67		};
68	};
69
70	can0 {
71		/omit-if-no-ref/
72		can0m0_pins: can0m0-pins {
73			rockchip,pins =
74				/* can0_rx_m0 */
75				<0 RK_PC0 11 &pcfg_pull_none>,
76				/* can0_tx_m0 */
77				<0 RK_PB7 11 &pcfg_pull_none>;
78		};
79
80		/omit-if-no-ref/
81		can0m1_pins: can0m1-pins {
82			rockchip,pins =
83				/* can0_rx_m1 */
84				<4 RK_PD5 9 &pcfg_pull_none>,
85				/* can0_tx_m1 */
86				<4 RK_PD4 9 &pcfg_pull_none>;
87		};
88	};
89
90	can1 {
91		/omit-if-no-ref/
92		can1m0_pins: can1m0-pins {
93			rockchip,pins =
94				/* can1_rx_m0 */
95				<3 RK_PB5 9 &pcfg_pull_none>,
96				/* can1_tx_m0 */
97				<3 RK_PB6 9 &pcfg_pull_none>;
98		};
99
100		/omit-if-no-ref/
101		can1m1_pins: can1m1-pins {
102			rockchip,pins =
103				/* can1_rx_m1 */
104				<4 RK_PB2 12 &pcfg_pull_none>,
105				/* can1_tx_m1 */
106				<4 RK_PB3 12 &pcfg_pull_none>;
107		};
108	};
109
110	can2 {
111		/omit-if-no-ref/
112		can2m0_pins: can2m0-pins {
113			rockchip,pins =
114				/* can2_rx_m0 */
115				<3 RK_PC4 9 &pcfg_pull_none>,
116				/* can2_tx_m0 */
117				<3 RK_PC5 9 &pcfg_pull_none>;
118		};
119
120		/omit-if-no-ref/
121		can2m1_pins: can2m1-pins {
122			rockchip,pins =
123				/* can2_rx_m1 */
124				<0 RK_PD4 10 &pcfg_pull_none>,
125				/* can2_tx_m1 */
126				<0 RK_PD5 10 &pcfg_pull_none>;
127		};
128	};
129
130	cif {
131		/omit-if-no-ref/
132		cif_clk: cif-clk {
133			rockchip,pins =
134				/* cif_clkout */
135				<4 RK_PB4 1 &pcfg_pull_none>;
136		};
137
138		/omit-if-no-ref/
139		cif_dvp_clk: cif-dvp-clk {
140			rockchip,pins =
141				/* cif_clkin */
142				<4 RK_PB0 1 &pcfg_pull_none>,
143				/* cif_href */
144				<4 RK_PB2 1 &pcfg_pull_none>,
145				/* cif_vsync */
146				<4 RK_PB3 1 &pcfg_pull_none>;
147		};
148
149		/omit-if-no-ref/
150		cif_dvp_bus16: cif-dvp-bus16 {
151			rockchip,pins =
152				/* cif_d8 */
153				<3 RK_PC4 1 &pcfg_pull_none>,
154				/* cif_d9 */
155				<3 RK_PC5 1 &pcfg_pull_none>,
156				/* cif_d10 */
157				<3 RK_PC6 1 &pcfg_pull_none>,
158				/* cif_d11 */
159				<3 RK_PC7 1 &pcfg_pull_none>,
160				/* cif_d12 */
161				<3 RK_PD0 1 &pcfg_pull_none>,
162				/* cif_d13 */
163				<3 RK_PD1 1 &pcfg_pull_none>,
164				/* cif_d14 */
165				<3 RK_PD2 1 &pcfg_pull_none>,
166				/* cif_d15 */
167				<3 RK_PD3 1 &pcfg_pull_none>;
168		};
169
170		/omit-if-no-ref/
171		cif_dvp_bus8: cif-dvp-bus8 {
172			rockchip,pins =
173				/* cif_d0 */
174				<4 RK_PA0 1 &pcfg_pull_none>,
175				/* cif_d1 */
176				<4 RK_PA1 1 &pcfg_pull_none>,
177				/* cif_d2 */
178				<4 RK_PA2 1 &pcfg_pull_none>,
179				/* cif_d3 */
180				<4 RK_PA3 1 &pcfg_pull_none>,
181				/* cif_d4 */
182				<4 RK_PA4 1 &pcfg_pull_none>,
183				/* cif_d5 */
184				<4 RK_PA5 1 &pcfg_pull_none>,
185				/* cif_d6 */
186				<4 RK_PA6 1 &pcfg_pull_none>,
187				/* cif_d7 */
188				<4 RK_PA7 1 &pcfg_pull_none>;
189		};
190	};
191
192	clk32k {
193		/omit-if-no-ref/
194		clk32k_in: clk32k-in {
195			rockchip,pins =
196				/* clk32k_in */
197				<0 RK_PB2 1 &pcfg_pull_none>;
198		};
199
200		/omit-if-no-ref/
201		clk32k_out0: clk32k-out0 {
202			rockchip,pins =
203				/* clk32k_out0 */
204				<0 RK_PB2 2 &pcfg_pull_none>;
205		};
206	};
207
208	cpu {
209		/omit-if-no-ref/
210		cpu_pins: cpu-pins {
211			rockchip,pins =
212				/* cpu_big0_avs */
213				<0 RK_PD1 2 &pcfg_pull_none>,
214				/* cpu_big1_avs */
215				<0 RK_PD5 2 &pcfg_pull_none>;
216		};
217	};
218
219	ddrphych0 {
220		/omit-if-no-ref/
221		ddrphych0_pins: ddrphych0-pins {
222			rockchip,pins =
223				/* ddrphych0_dtb0 */
224				<4 RK_PA0 7 &pcfg_pull_none>,
225				/* ddrphych0_dtb1 */
226				<4 RK_PA1 7 &pcfg_pull_none>,
227				/* ddrphych0_dtb2 */
228				<4 RK_PA2 7 &pcfg_pull_none>,
229				/* ddrphych0_dtb3 */
230				<4 RK_PA3 7 &pcfg_pull_none>;
231		};
232	};
233
234	ddrphych1 {
235		/omit-if-no-ref/
236		ddrphych1_pins: ddrphych1-pins {
237			rockchip,pins =
238				/* ddrphych1_dtb0 */
239				<4 RK_PA4 7 &pcfg_pull_none>,
240				/* ddrphych1_dtb1 */
241				<4 RK_PA5 7 &pcfg_pull_none>,
242				/* ddrphych1_dtb2 */
243				<4 RK_PA6 7 &pcfg_pull_none>,
244				/* ddrphych1_dtb3 */
245				<4 RK_PA7 7 &pcfg_pull_none>;
246		};
247	};
248
249	ddrphych2 {
250		/omit-if-no-ref/
251		ddrphych2_pins: ddrphych2-pins {
252			rockchip,pins =
253				/* ddrphych2_dtb0 */
254				<4 RK_PB0 7 &pcfg_pull_none>,
255				/* ddrphych2_dtb1 */
256				<4 RK_PB1 7 &pcfg_pull_none>,
257				/* ddrphych2_dtb2 */
258				<4 RK_PB2 7 &pcfg_pull_none>,
259				/* ddrphych2_dtb3 */
260				<4 RK_PB3 7 &pcfg_pull_none>;
261		};
262	};
263
264	ddrphych3 {
265		/omit-if-no-ref/
266		ddrphych3_pins: ddrphych3-pins {
267			rockchip,pins =
268				/* ddrphych3_dtb0 */
269				<4 RK_PB4 7 &pcfg_pull_none>,
270				/* ddrphych3_dtb1 */
271				<4 RK_PB5 7 &pcfg_pull_none>,
272				/* ddrphych3_dtb2 */
273				<4 RK_PB6 7 &pcfg_pull_none>,
274				/* ddrphych3_dtb3 */
275				<4 RK_PB7 7 &pcfg_pull_none>;
276		};
277	};
278
279	dp0 {
280		/omit-if-no-ref/
281		dp0m0_pins: dp0m0-pins {
282			rockchip,pins =
283				/* dp0_hpdin_m0 */
284				<4 RK_PB4 5 &pcfg_pull_none>;
285		};
286
287		/omit-if-no-ref/
288		dp0m1_pins: dp0m1-pins {
289			rockchip,pins =
290				/* dp0_hpdin_m1 */
291				<0 RK_PC4 10 &pcfg_pull_none>;
292		};
293
294		/omit-if-no-ref/
295		dp0m2_pins: dp0m2-pins {
296			rockchip,pins =
297				/* dp0_hpdin_m2 */
298				<1 RK_PA0 5 &pcfg_pull_none>;
299		};
300	};
301
302	dp1 {
303		/omit-if-no-ref/
304		dp1m0_pins: dp1m0-pins {
305			rockchip,pins =
306				/* dp1_hpdin_m0 */
307				<3 RK_PD5 5 &pcfg_pull_none>;
308		};
309
310		/omit-if-no-ref/
311		dp1m1_pins: dp1m1-pins {
312			rockchip,pins =
313				/* dp1_hpdin_m1 */
314				<0 RK_PC5 10 &pcfg_pull_none>;
315		};
316
317		/omit-if-no-ref/
318		dp1m2_pins: dp1m2-pins {
319			rockchip,pins =
320				/* dp1_hpdin_m2 */
321				<1 RK_PA1 5 &pcfg_pull_none>;
322		};
323	};
324
325	emmc {
326		/omit-if-no-ref/
327		emmc_rstnout: emmc-rstnout {
328			rockchip,pins =
329				/* emmc_rstn */
330				<2 RK_PA3 1 &pcfg_pull_none>;
331		};
332
333		/omit-if-no-ref/
334		emmc_bus8: emmc-bus8 {
335			rockchip,pins =
336				/* emmc_d0 */
337				<2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
338				/* emmc_d1 */
339				<2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
340				/* emmc_d2 */
341				<2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
342				/* emmc_d3 */
343				<2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
344				/* emmc_d4 */
345				<2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
346				/* emmc_d5 */
347				<2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
348				/* emmc_d6 */
349				<2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
350				/* emmc_d7 */
351				<2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
352		};
353
354		/omit-if-no-ref/
355		emmc_clk: emmc-clk {
356			rockchip,pins =
357				/* emmc_clkout */
358				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
359		};
360
361		/omit-if-no-ref/
362		emmc_cmd: emmc-cmd {
363			rockchip,pins =
364				/* emmc_cmd */
365				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
366		};
367
368		/omit-if-no-ref/
369		emmc_data_strobe: emmc-data-strobe {
370			rockchip,pins =
371				/* emmc_data_strobe */
372				<2 RK_PA2 1 &pcfg_pull_down>;
373		};
374	};
375
376	eth1 {
377		/omit-if-no-ref/
378		eth1_pins: eth1-pins {
379			rockchip,pins =
380				/* eth1_refclko_25m */
381				<3 RK_PA6 1 &pcfg_pull_none>;
382		};
383	};
384
385	fspi {
386		/omit-if-no-ref/
387		fspim0_pins: fspim0-pins {
388			rockchip,pins =
389				/* fspi_clk_m0 */
390				<2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
391				/* fspi_cs0n_m0 */
392				<2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
393				/* fspi_d0_m0 */
394				<2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
395				/* fspi_d1_m0 */
396				<2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
397				/* fspi_d2_m0 */
398				<2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
399				/* fspi_d3_m0 */
400				<2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
401		};
402
403		/omit-if-no-ref/
404		fspim0_cs1: fspim0-cs1 {
405			rockchip,pins =
406				/* fspi_cs1n_m0 */
407				<2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
408		};
409
410		/omit-if-no-ref/
411		fspim2_pins: fspim2-pins {
412			rockchip,pins =
413				/* fspi_clk_m2 */
414				<3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
415				/* fspi_cs0n_m2 */
416				<3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
417				/* fspi_d0_m2 */
418				<3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
419				/* fspi_d1_m2 */
420				<3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
421				/* fspi_d2_m2 */
422				<3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
423				/* fspi_d3_m2 */
424				<3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
425		};
426
427		/omit-if-no-ref/
428		fspim2_cs1: fspim2-cs1 {
429			rockchip,pins =
430				/* fspi_cs1n_m2 */
431				<3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
432		};
433	};
434
435	gmac1 {
436		/omit-if-no-ref/
437		gmac1_miim: gmac1-miim {
438			rockchip,pins =
439				/* gmac1_mdc */
440				<3 RK_PC2 1 &pcfg_pull_none>,
441				/* gmac1_mdio */
442				<3 RK_PC3 1 &pcfg_pull_none>;
443		};
444
445		/omit-if-no-ref/
446		gmac1_clkinout: gmac1-clkinout {
447			rockchip,pins =
448				/* gmac1_mclkinout */
449				<3 RK_PB6 1 &pcfg_pull_none>;
450		};
451
452		/omit-if-no-ref/
453		gmac1_rx_bus2: gmac1-rx-bus2 {
454			rockchip,pins =
455				/* gmac1_rxd0 */
456				<3 RK_PA7 1 &pcfg_pull_none>,
457				/* gmac1_rxd1 */
458				<3 RK_PB0 1 &pcfg_pull_none>,
459				/* gmac1_rxdv_crs */
460				<3 RK_PB1 1 &pcfg_pull_none>;
461		};
462
463		/omit-if-no-ref/
464		gmac1_tx_bus2: gmac1-tx-bus2 {
465			rockchip,pins =
466				/* gmac1_txd0 */
467				<3 RK_PB3 1 &pcfg_pull_none>,
468				/* gmac1_txd1 */
469				<3 RK_PB4 1 &pcfg_pull_none>,
470				/* gmac1_txen */
471				<3 RK_PB5 1 &pcfg_pull_none>;
472		};
473
474		/omit-if-no-ref/
475		gmac1_rgmii_clk: gmac1-rgmii-clk {
476			rockchip,pins =
477				/* gmac1_rxclk */
478				<3 RK_PA5 1 &pcfg_pull_none>,
479				/* gmac1_txclk */
480				<3 RK_PA4 1 &pcfg_pull_none>;
481		};
482
483		/omit-if-no-ref/
484		gmac1_rgmii_bus: gmac1-rgmii-bus {
485			rockchip,pins =
486				/* gmac1_rxd2 */
487				<3 RK_PA2 1 &pcfg_pull_none>,
488				/* gmac1_rxd3 */
489				<3 RK_PA3 1 &pcfg_pull_none>,
490				/* gmac1_txd2 */
491				<3 RK_PA0 1 &pcfg_pull_none>,
492				/* gmac1_txd3 */
493				<3 RK_PA1 1 &pcfg_pull_none>;
494		};
495
496		/omit-if-no-ref/
497		gmac1_ppsclk: gmac1-ppsclk {
498			rockchip,pins =
499				/* gmac1_ppsclk */
500				<3 RK_PC1 1 &pcfg_pull_none>;
501		};
502
503		/omit-if-no-ref/
504		gmac1_ppstrig: gmac1-ppstrig {
505			rockchip,pins =
506				/* gmac1_ppstrig */
507				<3 RK_PC0 1 &pcfg_pull_none>;
508		};
509
510		/omit-if-no-ref/
511		gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
512			rockchip,pins =
513				/* gmac1_ptp_ref_clk */
514				<3 RK_PB7 1 &pcfg_pull_none>;
515		};
516
517		/omit-if-no-ref/
518		gmac1_txer: gmac1-txer {
519			rockchip,pins =
520				/* gmac1_txer */
521				<3 RK_PB2 1 &pcfg_pull_none>;
522		};
523	};
524
525	gpu {
526		/omit-if-no-ref/
527		gpu_pins: gpu-pins {
528			rockchip,pins =
529				/* gpu_avs */
530				<0 RK_PC5 2 &pcfg_pull_none>;
531		};
532	};
533
534	hdmi {
535		/omit-if-no-ref/
536		hdmim0_rx_cec: hdmim0-rx-cec {
537			rockchip,pins =
538				/* hdmim0_rx_cec */
539				<4 RK_PB5 5 &pcfg_pull_none>;
540		};
541
542		/omit-if-no-ref/
543		hdmim0_rx_hpdin: hdmim0-rx-hpdin {
544			rockchip,pins =
545				/* hdmim0_rx_hpdin */
546				<4 RK_PB6 5 &pcfg_pull_none>;
547		};
548
549		/omit-if-no-ref/
550		hdmim0_rx_scl: hdmim0-rx-scl {
551			rockchip,pins =
552				/* hdmim0_rx_scl */
553				<0 RK_PD2 11 &pcfg_pull_none>;
554		};
555
556		/omit-if-no-ref/
557		hdmim0_rx_sda: hdmim0-rx-sda {
558			rockchip,pins =
559				/* hdmim0_rx_sda */
560				<0 RK_PD1 11 &pcfg_pull_none>;
561		};
562
563		/omit-if-no-ref/
564		hdmim0_tx0_cec: hdmim0-tx0-cec {
565			rockchip,pins =
566				/* hdmim0_tx0_cec */
567				<4 RK_PC1 5 &pcfg_pull_none>;
568		};
569
570		/omit-if-no-ref/
571		hdmim0_tx0_hpd: hdmim0-tx0-hpd {
572			rockchip,pins =
573				/* hdmim0_tx0_hpd */
574				<1 RK_PA5 5 &pcfg_pull_none>;
575		};
576
577		/omit-if-no-ref/
578		hdmim0_tx0_scl: hdmim0-tx0-scl {
579			rockchip,pins =
580				/* hdmim0_tx0_scl */
581				<4 RK_PB7 5 &pcfg_pull_none>;
582		};
583
584		/omit-if-no-ref/
585		hdmim0_tx0_sda: hdmim0-tx0-sda {
586			rockchip,pins =
587				/* hdmim0_tx0_sda */
588				<4 RK_PC0 5 &pcfg_pull_none>;
589		};
590
591		/omit-if-no-ref/
592		hdmim0_tx1_hpd: hdmim0-tx1-hpd {
593			rockchip,pins =
594				/* hdmim0_tx1_hpd */
595				<1 RK_PA6 5 &pcfg_pull_none>;
596		};
597		/omit-if-no-ref/
598		hdmim1_rx_cec: hdmim1-rx-cec {
599			rockchip,pins =
600				/* hdmim1_rx_cec */
601				<3 RK_PD1 5 &pcfg_pull_none>;
602		};
603
604		/omit-if-no-ref/
605		hdmim1_rx_hpdin: hdmim1-rx-hpdin {
606			rockchip,pins =
607				/* hdmim1_rx_hpdin */
608				<3 RK_PD4 5 &pcfg_pull_none>;
609		};
610
611		/omit-if-no-ref/
612		hdmim1_rx_scl: hdmim1-rx-scl {
613			rockchip,pins =
614				/* hdmim1_rx_scl */
615				<3 RK_PD2 5 &pcfg_pull_none>;
616		};
617
618		/omit-if-no-ref/
619		hdmim1_rx_sda: hdmim1-rx-sda {
620			rockchip,pins =
621				/* hdmim1_rx_sda */
622				<3 RK_PD3 5 &pcfg_pull_none>;
623		};
624
625		/omit-if-no-ref/
626		hdmim1_tx0_cec: hdmim1-tx0-cec {
627			rockchip,pins =
628				/* hdmim1_tx0_cec */
629				<0 RK_PD1 13 &pcfg_pull_none>;
630		};
631
632		/omit-if-no-ref/
633		hdmim1_tx0_hpd: hdmim1-tx0-hpd {
634			rockchip,pins =
635				/* hdmim1_tx0_hpd */
636				<3 RK_PD4 3 &pcfg_pull_none>;
637		};
638
639		/omit-if-no-ref/
640		hdmim1_tx0_scl: hdmim1-tx0-scl {
641			rockchip,pins =
642				/* hdmim1_tx0_scl */
643				<0 RK_PD5 11 &pcfg_pull_none>;
644		};
645
646		/omit-if-no-ref/
647		hdmim1_tx0_sda: hdmim1-tx0-sda {
648			rockchip,pins =
649				/* hdmim1_tx0_sda */
650				<0 RK_PD4 11 &pcfg_pull_none>;
651		};
652
653		/omit-if-no-ref/
654		hdmim1_tx1_cec: hdmim1-tx1-cec {
655			rockchip,pins =
656				/* hdmim1_tx1_cec */
657				<0 RK_PD2 13 &pcfg_pull_none>;
658		};
659
660		/omit-if-no-ref/
661		hdmim1_tx1_hpd: hdmim1-tx1-hpd {
662			rockchip,pins =
663				/* hdmim1_tx1_hpd */
664				<3 RK_PB7 5 &pcfg_pull_none>;
665		};
666
667		/omit-if-no-ref/
668		hdmim1_tx1_scl: hdmim1-tx1-scl {
669			rockchip,pins =
670				/* hdmim1_tx1_scl */
671				<3 RK_PC6 5 &pcfg_pull_none>;
672		};
673
674		/omit-if-no-ref/
675		hdmim1_tx1_sda: hdmim1-tx1-sda {
676			rockchip,pins =
677				/* hdmim1_tx1_sda */
678				<3 RK_PC5 5 &pcfg_pull_none>;
679		};
680		/omit-if-no-ref/
681		hdmim2_rx_cec: hdmim2-rx-cec {
682			rockchip,pins =
683				/* hdmim2_rx_cec */
684				<1 RK_PB7 5 &pcfg_pull_none>;
685		};
686
687		/omit-if-no-ref/
688		hdmim2_rx_hpdin: hdmim2-rx-hpdin {
689			rockchip,pins =
690				/* hdmim2_rx_hpdin */
691				<1 RK_PB6 5 &pcfg_pull_none>;
692		};
693
694		/omit-if-no-ref/
695		hdmim2_rx_scl: hdmim2-rx-scl {
696			rockchip,pins =
697				/* hdmim2_rx_scl */
698				<1 RK_PD6 5 &pcfg_pull_none>;
699		};
700
701		/omit-if-no-ref/
702		hdmim2_rx_sda: hdmim2-rx-sda {
703			rockchip,pins =
704				/* hdmim2_rx_sda */
705				<1 RK_PD7 5 &pcfg_pull_none>;
706		};
707
708		/omit-if-no-ref/
709		hdmim2_tx0_scl: hdmim2-tx0-scl {
710			rockchip,pins =
711				/* hdmim2_tx0_scl */
712				<3 RK_PC7 5 &pcfg_pull_none>;
713		};
714
715		/omit-if-no-ref/
716		hdmim2_tx0_sda: hdmim2-tx0-sda {
717			rockchip,pins =
718				/* hdmim2_tx0_sda */
719				<3 RK_PD0 5 &pcfg_pull_none>;
720		};
721
722		/omit-if-no-ref/
723		hdmim2_tx1_cec: hdmim2-tx1-cec {
724			rockchip,pins =
725				/* hdmim2_tx1_cec */
726				<3 RK_PC4 5 &pcfg_pull_none>;
727		};
728
729		/omit-if-no-ref/
730		hdmim2_tx1_scl: hdmim2-tx1-scl {
731			rockchip,pins =
732				/* hdmim2_tx1_scl */
733				<1 RK_PA4 5 &pcfg_pull_none>;
734		};
735
736		/omit-if-no-ref/
737		hdmim2_tx1_sda: hdmim2-tx1-sda {
738			rockchip,pins =
739				/* hdmim2_tx1_sda */
740				<1 RK_PA3 5 &pcfg_pull_none>;
741		};
742
743		/omit-if-no-ref/
744		hdmi_debug0: hdmi-debug0 {
745			rockchip,pins =
746				/* hdmi_debug0 */
747				<1 RK_PA7 7 &pcfg_pull_none>;
748		};
749
750		/omit-if-no-ref/
751		hdmi_debug1: hdmi-debug1 {
752			rockchip,pins =
753				/* hdmi_debug1 */
754				<1 RK_PB0 7 &pcfg_pull_none>;
755		};
756
757		/omit-if-no-ref/
758		hdmi_debug2: hdmi-debug2 {
759			rockchip,pins =
760				/* hdmi_debug2 */
761				<1 RK_PB1 7 &pcfg_pull_none>;
762		};
763
764		/omit-if-no-ref/
765		hdmi_debug3: hdmi-debug3 {
766			rockchip,pins =
767				/* hdmi_debug3 */
768				<1 RK_PB2 7 &pcfg_pull_none>;
769		};
770
771		/omit-if-no-ref/
772		hdmi_debug4: hdmi-debug4 {
773			rockchip,pins =
774				/* hdmi_debug4 */
775				<1 RK_PB3 7 &pcfg_pull_none>;
776		};
777
778		/omit-if-no-ref/
779		hdmi_debug5: hdmi-debug5 {
780			rockchip,pins =
781				/* hdmi_debug5 */
782				<1 RK_PB4 7 &pcfg_pull_none>;
783		};
784
785		/omit-if-no-ref/
786		hdmi_debug6: hdmi-debug6 {
787			rockchip,pins =
788				/* hdmi_debug6 */
789				<1 RK_PA0 7 &pcfg_pull_none>;
790		};
791	};
792
793	i2c0 {
794		/omit-if-no-ref/
795		i2c0m0_xfer: i2c0m0-xfer {
796			rockchip,pins =
797				/* i2c0_scl_m0 */
798				<0 RK_PB3 2 &pcfg_pull_none_smt>,
799				/* i2c0_sda_m0 */
800				<0 RK_PA6 2 &pcfg_pull_none_smt>;
801		};
802
803		/omit-if-no-ref/
804		i2c0m2_xfer: i2c0m2-xfer {
805			rockchip,pins =
806				/* i2c0_scl_m2 */
807				<0 RK_PD1 3 &pcfg_pull_none_smt>,
808				/* i2c0_sda_m2 */
809				<0 RK_PD2 3 &pcfg_pull_none_smt>;
810		};
811	};
812
813	i2c1 {
814		/omit-if-no-ref/
815		i2c1m0_xfer: i2c1m0-xfer {
816			rockchip,pins =
817				/* i2c1_scl_m0 */
818				<0 RK_PB5 9 &pcfg_pull_none_smt>,
819				/* i2c1_sda_m0 */
820				<0 RK_PB6 9 &pcfg_pull_none_smt>;
821		};
822
823		/omit-if-no-ref/
824		i2c1m1_xfer: i2c1m1-xfer {
825			rockchip,pins =
826				/* i2c1_scl_m1 */
827				<0 RK_PB0 2 &pcfg_pull_none_smt>,
828				/* i2c1_sda_m1 */
829				<0 RK_PB1 2 &pcfg_pull_none_smt>;
830		};
831
832		/omit-if-no-ref/
833		i2c1m2_xfer: i2c1m2-xfer {
834			rockchip,pins =
835				/* i2c1_scl_m2 */
836				<0 RK_PD4 9 &pcfg_pull_none_smt>,
837				/* i2c1_sda_m2 */
838				<0 RK_PD5 9 &pcfg_pull_none_smt>;
839		};
840
841		/omit-if-no-ref/
842		i2c1m3_xfer: i2c1m3-xfer {
843			rockchip,pins =
844				/* i2c1_scl_m3 */
845				<2 RK_PD4 9 &pcfg_pull_none_smt>,
846				/* i2c1_sda_m3 */
847				<2 RK_PD5 9 &pcfg_pull_none_smt>;
848		};
849
850		/omit-if-no-ref/
851		i2c1m4_xfer: i2c1m4-xfer {
852			rockchip,pins =
853				/* i2c1_scl_m4 */
854				<1 RK_PD2 9 &pcfg_pull_none_smt>,
855				/* i2c1_sda_m4 */
856				<1 RK_PD3 9 &pcfg_pull_none_smt>;
857		};
858	};
859
860	i2c2 {
861		/omit-if-no-ref/
862		i2c2m0_xfer: i2c2m0-xfer {
863			rockchip,pins =
864				/* i2c2_scl_m0 */
865				<0 RK_PB7 9 &pcfg_pull_none_smt>,
866				/* i2c2_sda_m0 */
867				<0 RK_PC0 9 &pcfg_pull_none_smt>;
868		};
869
870		/omit-if-no-ref/
871		i2c2m2_xfer: i2c2m2-xfer {
872			rockchip,pins =
873				/* i2c2_scl_m2 */
874				<2 RK_PA3 9 &pcfg_pull_none_smt>,
875				/* i2c2_sda_m2 */
876				<2 RK_PA2 9 &pcfg_pull_none_smt>;
877		};
878
879		/omit-if-no-ref/
880		i2c2m3_xfer: i2c2m3-xfer {
881			rockchip,pins =
882				/* i2c2_scl_m3 */
883				<1 RK_PC5 9 &pcfg_pull_none_smt>,
884				/* i2c2_sda_m3 */
885				<1 RK_PC4 9 &pcfg_pull_none_smt>;
886		};
887
888		/omit-if-no-ref/
889		i2c2m4_xfer: i2c2m4-xfer {
890			rockchip,pins =
891				/* i2c2_scl_m4 */
892				<1 RK_PA1 9 &pcfg_pull_none_smt>,
893				/* i2c2_sda_m4 */
894				<1 RK_PA0 9 &pcfg_pull_none_smt>;
895		};
896	};
897
898	i2c3 {
899		/omit-if-no-ref/
900		i2c3m0_xfer: i2c3m0-xfer {
901			rockchip,pins =
902				/* i2c3_scl_m0 */
903				<1 RK_PC1 9 &pcfg_pull_none_smt>,
904				/* i2c3_sda_m0 */
905				<1 RK_PC0 9 &pcfg_pull_none_smt>;
906		};
907
908		/omit-if-no-ref/
909		i2c3m1_xfer: i2c3m1-xfer {
910			rockchip,pins =
911				/* i2c3_scl_m1 */
912				<3 RK_PB7 9 &pcfg_pull_none_smt>,
913				/* i2c3_sda_m1 */
914				<3 RK_PC0 9 &pcfg_pull_none_smt>;
915		};
916
917		/omit-if-no-ref/
918		i2c3m2_xfer: i2c3m2-xfer {
919			rockchip,pins =
920				/* i2c3_scl_m2 */
921				<4 RK_PA4 9 &pcfg_pull_none_smt>,
922				/* i2c3_sda_m2 */
923				<4 RK_PA5 9 &pcfg_pull_none_smt>;
924		};
925
926		/omit-if-no-ref/
927		i2c3m4_xfer: i2c3m4-xfer {
928			rockchip,pins =
929				/* i2c3_scl_m4 */
930				<4 RK_PD0 9 &pcfg_pull_none_smt>,
931				/* i2c3_sda_m4 */
932				<4 RK_PD1 9 &pcfg_pull_none_smt>;
933		};
934	};
935
936	i2c4 {
937		/omit-if-no-ref/
938		i2c4m0_xfer: i2c4m0-xfer {
939			rockchip,pins =
940				/* i2c4_scl_m0 */
941				<3 RK_PA6 9 &pcfg_pull_none_smt>,
942				/* i2c4_sda_m0 */
943				<3 RK_PA5 9 &pcfg_pull_none_smt>;
944		};
945
946		/omit-if-no-ref/
947		i2c4m2_xfer: i2c4m2-xfer {
948			rockchip,pins =
949				/* i2c4_scl_m2 */
950				<0 RK_PC5 9 &pcfg_pull_none_smt>,
951				/* i2c4_sda_m2 */
952				<0 RK_PC4 9 &pcfg_pull_none_smt>;
953		};
954
955		/omit-if-no-ref/
956		i2c4m3_xfer: i2c4m3-xfer {
957			rockchip,pins =
958				/* i2c4_scl_m3 */
959				<1 RK_PA3 9 &pcfg_pull_none_smt>,
960				/* i2c4_sda_m3 */
961				<1 RK_PA2 9 &pcfg_pull_none_smt>;
962		};
963
964		/omit-if-no-ref/
965		i2c4m4_xfer: i2c4m4-xfer {
966			rockchip,pins =
967				/* i2c4_scl_m4 */
968				<1 RK_PC7 9 &pcfg_pull_none_smt>,
969				/* i2c4_sda_m4 */
970				<1 RK_PC6 9 &pcfg_pull_none_smt>;
971		};
972	};
973
974	i2c5 {
975		/omit-if-no-ref/
976		i2c5m0_xfer: i2c5m0-xfer {
977			rockchip,pins =
978				/* i2c5_scl_m0 */
979				<3 RK_PC7 9 &pcfg_pull_none_smt>,
980				/* i2c5_sda_m0 */
981				<3 RK_PD0 9 &pcfg_pull_none_smt>;
982		};
983
984		/omit-if-no-ref/
985		i2c5m1_xfer: i2c5m1-xfer {
986			rockchip,pins =
987				/* i2c5_scl_m1 */
988				<4 RK_PB6 9 &pcfg_pull_none_smt>,
989				/* i2c5_sda_m1 */
990				<4 RK_PB7 9 &pcfg_pull_none_smt>;
991		};
992
993		/omit-if-no-ref/
994		i2c5m2_xfer: i2c5m2-xfer {
995			rockchip,pins =
996				/* i2c5_scl_m2 */
997				<4 RK_PA6 9 &pcfg_pull_none_smt>,
998				/* i2c5_sda_m2 */
999				<4 RK_PA7 9 &pcfg_pull_none_smt>;
1000		};
1001
1002		/omit-if-no-ref/
1003		i2c5m3_xfer: i2c5m3-xfer {
1004			rockchip,pins =
1005				/* i2c5_scl_m3 */
1006				<1 RK_PB6 9 &pcfg_pull_none_smt>,
1007				/* i2c5_sda_m3 */
1008				<1 RK_PB7 9 &pcfg_pull_none_smt>;
1009		};
1010	};
1011
1012	i2c6 {
1013		/omit-if-no-ref/
1014		i2c6m0_xfer: i2c6m0-xfer {
1015			rockchip,pins =
1016				/* i2c6_scl_m0 */
1017				<0 RK_PD0 9 &pcfg_pull_none_smt>,
1018				/* i2c6_sda_m0 */
1019				<0 RK_PC7 9 &pcfg_pull_none_smt>;
1020		};
1021
1022		/omit-if-no-ref/
1023		i2c6m1_xfer: i2c6m1-xfer {
1024			rockchip,pins =
1025				/* i2c6_scl_m1 */
1026				<1 RK_PC3 9 &pcfg_pull_none_smt>,
1027				/* i2c6_sda_m1 */
1028				<1 RK_PC2 9 &pcfg_pull_none_smt>;
1029		};
1030
1031		/omit-if-no-ref/
1032		i2c6m3_xfer: i2c6m3-xfer {
1033			rockchip,pins =
1034				/* i2c6_scl_m3 */
1035				<4 RK_PB1 9 &pcfg_pull_none_smt>,
1036				/* i2c6_sda_m3 */
1037				<4 RK_PB0 9 &pcfg_pull_none_smt>;
1038		};
1039
1040		/omit-if-no-ref/
1041		i2c6m4_xfer: i2c6m4-xfer {
1042			rockchip,pins =
1043				/* i2c6_scl_m4 */
1044				<3 RK_PA1 9 &pcfg_pull_none_smt>,
1045				/* i2c6_sda_m4 */
1046				<3 RK_PA0 9 &pcfg_pull_none_smt>;
1047		};
1048	};
1049
1050	i2c7 {
1051		/omit-if-no-ref/
1052		i2c7m0_xfer: i2c7m0-xfer {
1053			rockchip,pins =
1054				/* i2c7_scl_m0 */
1055				<1 RK_PD0 9 &pcfg_pull_none_smt>,
1056				/* i2c7_sda_m0 */
1057				<1 RK_PD1 9 &pcfg_pull_none_smt>;
1058		};
1059
1060		/omit-if-no-ref/
1061		i2c7m2_xfer: i2c7m2-xfer {
1062			rockchip,pins =
1063				/* i2c7_scl_m2 */
1064				<3 RK_PD2 9 &pcfg_pull_none_smt>,
1065				/* i2c7_sda_m2 */
1066				<3 RK_PD3 9 &pcfg_pull_none_smt>;
1067		};
1068
1069		/omit-if-no-ref/
1070		i2c7m3_xfer: i2c7m3-xfer {
1071			rockchip,pins =
1072				/* i2c7_scl_m3 */
1073				<4 RK_PB2 9 &pcfg_pull_none_smt>,
1074				/* i2c7_sda_m3 */
1075				<4 RK_PB3 9 &pcfg_pull_none_smt>;
1076		};
1077	};
1078
1079	i2c8 {
1080		/omit-if-no-ref/
1081		i2c8m0_xfer: i2c8m0-xfer {
1082			rockchip,pins =
1083				/* i2c8_scl_m0 */
1084				<4 RK_PD2 9 &pcfg_pull_none_smt>,
1085				/* i2c8_sda_m0 */
1086				<4 RK_PD3 9 &pcfg_pull_none_smt>;
1087		};
1088
1089		/omit-if-no-ref/
1090		i2c8m2_xfer: i2c8m2-xfer {
1091			rockchip,pins =
1092				/* i2c8_scl_m2 */
1093				<1 RK_PD6 9 &pcfg_pull_none_smt>,
1094				/* i2c8_sda_m2 */
1095				<1 RK_PD7 9 &pcfg_pull_none_smt>;
1096		};
1097
1098		/omit-if-no-ref/
1099		i2c8m3_xfer: i2c8m3-xfer {
1100			rockchip,pins =
1101				/* i2c8_scl_m3 */
1102				<4 RK_PC0 9 &pcfg_pull_none_smt>,
1103				/* i2c8_sda_m3 */
1104				<4 RK_PC1 9 &pcfg_pull_none_smt>;
1105		};
1106
1107		/omit-if-no-ref/
1108		i2c8m4_xfer: i2c8m4-xfer {
1109			rockchip,pins =
1110				/* i2c8_scl_m4 */
1111				<3 RK_PC2 9 &pcfg_pull_none_smt>,
1112				/* i2c8_sda_m4 */
1113				<3 RK_PC3 9 &pcfg_pull_none_smt>;
1114		};
1115	};
1116
1117	i2s0 {
1118		/omit-if-no-ref/
1119		i2s0_lrck: i2s0-lrck {
1120			rockchip,pins =
1121				/* i2s0_lrck */
1122				<1 RK_PC5 1 &pcfg_pull_none>;
1123		};
1124
1125		/omit-if-no-ref/
1126		i2s0_mclk: i2s0-mclk {
1127			rockchip,pins =
1128				/* i2s0_mclk */
1129				<1 RK_PC2 1 &pcfg_pull_none>;
1130		};
1131
1132		/omit-if-no-ref/
1133		i2s0_sclk: i2s0-sclk {
1134			rockchip,pins =
1135				/* i2s0_sclk */
1136				<1 RK_PC3 1 &pcfg_pull_none>;
1137		};
1138
1139		/omit-if-no-ref/
1140		i2s0_sdi0: i2s0-sdi0 {
1141			rockchip,pins =
1142				/* i2s0_sdi0 */
1143				<1 RK_PD4 2 &pcfg_pull_none>;
1144		};
1145
1146		/omit-if-no-ref/
1147		i2s0_sdi1: i2s0-sdi1 {
1148			rockchip,pins =
1149				/* i2s0_sdi1 */
1150				<1 RK_PD3 2 &pcfg_pull_none>;
1151		};
1152
1153		/omit-if-no-ref/
1154		i2s0_sdi2: i2s0-sdi2 {
1155			rockchip,pins =
1156				/* i2s0_sdi2 */
1157				<1 RK_PD2 2 &pcfg_pull_none>;
1158		};
1159
1160		/omit-if-no-ref/
1161		i2s0_sdi3: i2s0-sdi3 {
1162			rockchip,pins =
1163				/* i2s0_sdi3 */
1164				<1 RK_PD1 2 &pcfg_pull_none>;
1165		};
1166
1167		/omit-if-no-ref/
1168		i2s0_sdo0: i2s0-sdo0 {
1169			rockchip,pins =
1170				/* i2s0_sdo0 */
1171				<1 RK_PC7 1 &pcfg_pull_none>;
1172		};
1173
1174		/omit-if-no-ref/
1175		i2s0_sdo1: i2s0-sdo1 {
1176			rockchip,pins =
1177				/* i2s0_sdo1 */
1178				<1 RK_PD0 1 &pcfg_pull_none>;
1179		};
1180
1181		/omit-if-no-ref/
1182		i2s0_sdo2: i2s0-sdo2 {
1183			rockchip,pins =
1184				/* i2s0_sdo2 */
1185				<1 RK_PD1 1 &pcfg_pull_none>;
1186		};
1187
1188		/omit-if-no-ref/
1189		i2s0_sdo3: i2s0-sdo3 {
1190			rockchip,pins =
1191				/* i2s0_sdo3 */
1192				<1 RK_PD2 1 &pcfg_pull_none>;
1193		};
1194	};
1195
1196	i2s1 {
1197		/omit-if-no-ref/
1198		i2s1m0_lrck: i2s1m0-lrck {
1199			rockchip,pins =
1200				/* i2s1m0_lrck */
1201				<4 RK_PA2 3 &pcfg_pull_none>;
1202		};
1203
1204		/omit-if-no-ref/
1205		i2s1m0_mclk: i2s1m0-mclk {
1206			rockchip,pins =
1207				/* i2s1m0_mclk */
1208				<4 RK_PA0 3 &pcfg_pull_none>;
1209		};
1210
1211		/omit-if-no-ref/
1212		i2s1m0_sclk: i2s1m0-sclk {
1213			rockchip,pins =
1214				/* i2s1m0_sclk */
1215				<4 RK_PA1 3 &pcfg_pull_none>;
1216		};
1217
1218		/omit-if-no-ref/
1219		i2s1m0_sdi0: i2s1m0-sdi0 {
1220			rockchip,pins =
1221				/* i2s1m0_sdi0 */
1222				<4 RK_PA5 3 &pcfg_pull_none>;
1223		};
1224
1225		/omit-if-no-ref/
1226		i2s1m0_sdi1: i2s1m0-sdi1 {
1227			rockchip,pins =
1228				/* i2s1m0_sdi1 */
1229				<4 RK_PA6 3 &pcfg_pull_none>;
1230		};
1231
1232		/omit-if-no-ref/
1233		i2s1m0_sdi2: i2s1m0-sdi2 {
1234			rockchip,pins =
1235				/* i2s1m0_sdi2 */
1236				<4 RK_PA7 3 &pcfg_pull_none>;
1237		};
1238
1239		/omit-if-no-ref/
1240		i2s1m0_sdi3: i2s1m0-sdi3 {
1241			rockchip,pins =
1242				/* i2s1m0_sdi3 */
1243				<4 RK_PB0 3 &pcfg_pull_none>;
1244		};
1245
1246		/omit-if-no-ref/
1247		i2s1m0_sdo0: i2s1m0-sdo0 {
1248			rockchip,pins =
1249				/* i2s1m0_sdo0 */
1250				<4 RK_PB1 3 &pcfg_pull_none>;
1251		};
1252
1253		/omit-if-no-ref/
1254		i2s1m0_sdo1: i2s1m0-sdo1 {
1255			rockchip,pins =
1256				/* i2s1m0_sdo1 */
1257				<4 RK_PB2 3 &pcfg_pull_none>;
1258		};
1259
1260		/omit-if-no-ref/
1261		i2s1m0_sdo2: i2s1m0-sdo2 {
1262			rockchip,pins =
1263				/* i2s1m0_sdo2 */
1264				<4 RK_PB3 3 &pcfg_pull_none>;
1265		};
1266
1267		/omit-if-no-ref/
1268		i2s1m0_sdo3: i2s1m0-sdo3 {
1269			rockchip,pins =
1270				/* i2s1m0_sdo3 */
1271				<4 RK_PB4 3 &pcfg_pull_none>;
1272		};
1273		/omit-if-no-ref/
1274		i2s1m1_lrck: i2s1m1-lrck {
1275			rockchip,pins =
1276				/* i2s1m1_lrck */
1277				<0 RK_PB7 1 &pcfg_pull_none>;
1278		};
1279
1280		/omit-if-no-ref/
1281		i2s1m1_mclk: i2s1m1-mclk {
1282			rockchip,pins =
1283				/* i2s1m1_mclk */
1284				<0 RK_PB5 1 &pcfg_pull_none>;
1285		};
1286
1287		/omit-if-no-ref/
1288		i2s1m1_sclk: i2s1m1-sclk {
1289			rockchip,pins =
1290				/* i2s1m1_sclk */
1291				<0 RK_PB6 1 &pcfg_pull_none>;
1292		};
1293
1294		/omit-if-no-ref/
1295		i2s1m1_sdi0: i2s1m1-sdi0 {
1296			rockchip,pins =
1297				/* i2s1m1_sdi0 */
1298				<0 RK_PC5 1 &pcfg_pull_none>;
1299		};
1300
1301		/omit-if-no-ref/
1302		i2s1m1_sdi1: i2s1m1-sdi1 {
1303			rockchip,pins =
1304				/* i2s1m1_sdi1 */
1305				<0 RK_PC6 1 &pcfg_pull_none>;
1306		};
1307
1308		/omit-if-no-ref/
1309		i2s1m1_sdi2: i2s1m1-sdi2 {
1310			rockchip,pins =
1311				/* i2s1m1_sdi2 */
1312				<0 RK_PC7 1 &pcfg_pull_none>;
1313		};
1314
1315		/omit-if-no-ref/
1316		i2s1m1_sdi3: i2s1m1-sdi3 {
1317			rockchip,pins =
1318				/* i2s1m1_sdi3 */
1319				<0 RK_PD0 1 &pcfg_pull_none>;
1320		};
1321
1322		/omit-if-no-ref/
1323		i2s1m1_sdo0: i2s1m1-sdo0 {
1324			rockchip,pins =
1325				/* i2s1m1_sdo0 */
1326				<0 RK_PD1 1 &pcfg_pull_none>;
1327		};
1328
1329		/omit-if-no-ref/
1330		i2s1m1_sdo1: i2s1m1-sdo1 {
1331			rockchip,pins =
1332				/* i2s1m1_sdo1 */
1333				<0 RK_PD2 1 &pcfg_pull_none>;
1334		};
1335
1336		/omit-if-no-ref/
1337		i2s1m1_sdo2: i2s1m1-sdo2 {
1338			rockchip,pins =
1339				/* i2s1m1_sdo2 */
1340				<0 RK_PD4 1 &pcfg_pull_none>;
1341		};
1342
1343		/omit-if-no-ref/
1344		i2s1m1_sdo3: i2s1m1-sdo3 {
1345			rockchip,pins =
1346				/* i2s1m1_sdo3 */
1347				<0 RK_PD5 1 &pcfg_pull_none>;
1348		};
1349	};
1350
1351	i2s2 {
1352		/omit-if-no-ref/
1353		i2s2m0_lrck: i2s2m0-lrck {
1354			rockchip,pins =
1355				/* i2s2m0_lrck */
1356				<2 RK_PC0 2 &pcfg_pull_none>;
1357		};
1358
1359		/omit-if-no-ref/
1360		i2s2m0_mclk: i2s2m0-mclk {
1361			rockchip,pins =
1362				/* i2s2m0_mclk */
1363				<2 RK_PB6 2 &pcfg_pull_none>;
1364		};
1365
1366		/omit-if-no-ref/
1367		i2s2m0_sclk: i2s2m0-sclk {
1368			rockchip,pins =
1369				/* i2s2m0_sclk */
1370				<2 RK_PB7 2 &pcfg_pull_none>;
1371		};
1372
1373		/omit-if-no-ref/
1374		i2s2m0_sdi: i2s2m0-sdi {
1375			rockchip,pins =
1376				/* i2s2m0_sdi */
1377				<2 RK_PC3 2 &pcfg_pull_none>;
1378		};
1379
1380		/omit-if-no-ref/
1381		i2s2m0_sdo: i2s2m0-sdo {
1382			rockchip,pins =
1383				/* i2s2m0_sdo */
1384				<4 RK_PC3 2 &pcfg_pull_none>;
1385		};
1386
1387		/omit-if-no-ref/
1388		i2s2m1_lrck: i2s2m1-lrck {
1389			rockchip,pins =
1390				/* i2s2m1_lrck */
1391				<3 RK_PB6 3 &pcfg_pull_none>;
1392		};
1393
1394		/omit-if-no-ref/
1395		i2s2m1_mclk: i2s2m1-mclk {
1396			rockchip,pins =
1397				/* i2s2m1_mclk */
1398				<3 RK_PB4 3 &pcfg_pull_none>;
1399		};
1400
1401		/omit-if-no-ref/
1402		i2s2m1_sclk: i2s2m1-sclk {
1403			rockchip,pins =
1404				/* i2s2m1_sclk */
1405				<3 RK_PB5 3 &pcfg_pull_none>;
1406		};
1407
1408		/omit-if-no-ref/
1409		i2s2m1_sdi: i2s2m1-sdi {
1410			rockchip,pins =
1411				/* i2s2m1_sdi */
1412				<3 RK_PB2 3 &pcfg_pull_none>;
1413		};
1414
1415		/omit-if-no-ref/
1416		i2s2m1_sdo: i2s2m1-sdo {
1417			rockchip,pins =
1418				/* i2s2m1_sdo */
1419				<3 RK_PB3 3 &pcfg_pull_none>;
1420		};
1421	};
1422
1423	i2s3 {
1424		/omit-if-no-ref/
1425		i2s3_lrck: i2s3-lrck {
1426			rockchip,pins =
1427				/* i2s3_lrck */
1428				<3 RK_PA2 3 &pcfg_pull_none>;
1429		};
1430
1431		/omit-if-no-ref/
1432		i2s3_mclk: i2s3-mclk {
1433			rockchip,pins =
1434				/* i2s3_mclk */
1435				<3 RK_PA0 3 &pcfg_pull_none>;
1436		};
1437
1438		/omit-if-no-ref/
1439		i2s3_sclk: i2s3-sclk {
1440			rockchip,pins =
1441				/* i2s3_sclk */
1442				<3 RK_PA1 3 &pcfg_pull_none>;
1443		};
1444
1445		/omit-if-no-ref/
1446		i2s3_sdi: i2s3-sdi {
1447			rockchip,pins =
1448				/* i2s3_sdi */
1449				<3 RK_PA4 3 &pcfg_pull_none>;
1450		};
1451
1452		/omit-if-no-ref/
1453		i2s3_sdo: i2s3-sdo {
1454			rockchip,pins =
1455				/* i2s3_sdo */
1456				<3 RK_PA3 3 &pcfg_pull_none>;
1457		};
1458	};
1459
1460	jtag {
1461		/omit-if-no-ref/
1462		jtagm0_pins: jtagm0-pins {
1463			rockchip,pins =
1464				/* jtag_tck_m0 */
1465				<4 RK_PD2 5 &pcfg_pull_none>,
1466				/* jtag_tms_m0 */
1467				<4 RK_PD3 5 &pcfg_pull_none>;
1468		};
1469
1470		/omit-if-no-ref/
1471		jtagm1_pins: jtagm1-pins {
1472			rockchip,pins =
1473				/* jtag_tck_m1 */
1474				<4 RK_PD0 5 &pcfg_pull_none>,
1475				/* jtag_tms_m1 */
1476				<4 RK_PD1 5 &pcfg_pull_none>;
1477		};
1478
1479		/omit-if-no-ref/
1480		jtagm2_pins: jtagm2-pins {
1481			rockchip,pins =
1482				/* jtag_tck_m2 */
1483				<0 RK_PB5 2 &pcfg_pull_none>,
1484				/* jtag_tms_m2 */
1485				<0 RK_PB6 2 &pcfg_pull_none>;
1486		};
1487	};
1488
1489	litcpu {
1490		/omit-if-no-ref/
1491		litcpu_pins: litcpu-pins {
1492			rockchip,pins =
1493				/* litcpu_avs */
1494				<0 RK_PD3 1 &pcfg_pull_none>;
1495		};
1496	};
1497
1498	mcu {
1499		/omit-if-no-ref/
1500		mcum0_pins: mcum0-pins {
1501			rockchip,pins =
1502				/* mcu_jtag_tck_m0 */
1503				<4 RK_PD4 5 &pcfg_pull_none>,
1504				/* mcu_jtag_tms_m0 */
1505				<4 RK_PD5 5 &pcfg_pull_none>;
1506		};
1507
1508		/omit-if-no-ref/
1509		mcum1_pins: mcum1-pins {
1510			rockchip,pins =
1511				/* mcu_jtag_tck_m1 */
1512				<3 RK_PD4 6 &pcfg_pull_none>,
1513				/* mcu_jtag_tms_m1 */
1514				<3 RK_PD5 6 &pcfg_pull_none>;
1515		};
1516	};
1517
1518	mipi {
1519		/omit-if-no-ref/
1520		mipim0_camera0_clk: mipim0-camera0-clk {
1521			rockchip,pins =
1522				/* mipim0_camera0_clk */
1523				<4 RK_PB1 1 &pcfg_pull_none>;
1524		};
1525
1526		/omit-if-no-ref/
1527		mipim0_camera1_clk: mipim0-camera1-clk {
1528			rockchip,pins =
1529				/* mipim0_camera1_clk */
1530				<1 RK_PB6 2 &pcfg_pull_none>;
1531		};
1532
1533		/omit-if-no-ref/
1534		mipim0_camera2_clk: mipim0-camera2-clk {
1535			rockchip,pins =
1536				/* mipim0_camera2_clk */
1537				<1 RK_PB7 2 &pcfg_pull_none>;
1538		};
1539
1540		/omit-if-no-ref/
1541		mipim0_camera3_clk: mipim0-camera3-clk {
1542			rockchip,pins =
1543				/* mipim0_camera3_clk */
1544				<1 RK_PD6 2 &pcfg_pull_none>;
1545		};
1546
1547		/omit-if-no-ref/
1548		mipim0_camera4_clk: mipim0-camera4-clk {
1549			rockchip,pins =
1550				/* mipim0_camera4_clk */
1551				<1 RK_PD7 2 &pcfg_pull_none>;
1552		};
1553
1554		/omit-if-no-ref/
1555		mipim1_camera0_clk: mipim1-camera0-clk {
1556			rockchip,pins =
1557				/* mipim1_camera0_clk */
1558				<3 RK_PA5 4 &pcfg_pull_none>;
1559		};
1560
1561		/omit-if-no-ref/
1562		mipim1_camera1_clk: mipim1-camera1-clk {
1563			rockchip,pins =
1564				/* mipim1_camera1_clk */
1565				<3 RK_PA6 4 &pcfg_pull_none>;
1566		};
1567
1568		/omit-if-no-ref/
1569		mipim1_camera2_clk: mipim1-camera2-clk {
1570			rockchip,pins =
1571				/* mipim1_camera2_clk */
1572				<3 RK_PA7 4 &pcfg_pull_none>;
1573		};
1574
1575		/omit-if-no-ref/
1576		mipim1_camera3_clk: mipim1-camera3-clk {
1577			rockchip,pins =
1578				/* mipim1_camera3_clk */
1579				<3 RK_PB0 4 &pcfg_pull_none>;
1580		};
1581
1582		/omit-if-no-ref/
1583		mipim1_camera4_clk: mipim1-camera4-clk {
1584			rockchip,pins =
1585				/* mipim1_camera4_clk */
1586				<3 RK_PB1 4 &pcfg_pull_none>;
1587		};
1588
1589		/omit-if-no-ref/
1590		mipi_te0: mipi-te0 {
1591			rockchip,pins =
1592				/* mipi_te0 */
1593				<3 RK_PC2 2 &pcfg_pull_none>;
1594		};
1595
1596		/omit-if-no-ref/
1597		mipi_te1: mipi-te1 {
1598			rockchip,pins =
1599				/* mipi_te1 */
1600				<3 RK_PC3 2 &pcfg_pull_none>;
1601		};
1602	};
1603
1604	npu {
1605		/omit-if-no-ref/
1606		npu_pins: npu-pins {
1607			rockchip,pins =
1608				/* npu_avs */
1609				<0 RK_PC6 2 &pcfg_pull_none>;
1610		};
1611	};
1612
1613	pcie20x1 {
1614		/omit-if-no-ref/
1615		pcie20x1m0_pins: pcie20x1m0-pins {
1616			rockchip,pins =
1617				/* pcie20x1_2_clkreqn_m0 */
1618				<3 RK_PC7 4 &pcfg_pull_none>,
1619				/* pcie20x1_2_perstn_m0 */
1620				<3 RK_PD1 4 &pcfg_pull_none>,
1621				/* pcie20x1_2_waken_m0 */
1622				<3 RK_PD0 4 &pcfg_pull_none>;
1623		};
1624
1625		/omit-if-no-ref/
1626		pcie20x1m1_pins: pcie20x1m1-pins {
1627			rockchip,pins =
1628				/* pcie20x1_2_clkreqn_m1 */
1629				<4 RK_PB7 4 &pcfg_pull_none>,
1630				/* pcie20x1_2_perstn_m1 */
1631				<4 RK_PC1 4 &pcfg_pull_none>,
1632				/* pcie20x1_2_waken_m1 */
1633				<4 RK_PC0 4 &pcfg_pull_none>;
1634		};
1635
1636		/omit-if-no-ref/
1637		pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
1638			rockchip,pins =
1639				/* pcie20x1_2_button_rstn */
1640				<4 RK_PB3 4 &pcfg_pull_none>;
1641		};
1642	};
1643
1644	pcie30phy {
1645		/omit-if-no-ref/
1646		pcie30phy_pins: pcie30phy-pins {
1647			rockchip,pins =
1648				/* pcie30phy_dtb0 */
1649				<1 RK_PC4 4 &pcfg_pull_none>,
1650				/* pcie30phy_dtb1 */
1651				<1 RK_PD1 4 &pcfg_pull_none>;
1652		};
1653	};
1654
1655	pcie30x1 {
1656		/omit-if-no-ref/
1657		pcie30x1m0_pins: pcie30x1m0-pins {
1658			rockchip,pins =
1659				/* pcie30x1_0_clkreqn_m0 */
1660				<0 RK_PC0 12 &pcfg_pull_none>,
1661				/* pcie30x1_0_perstn_m0 */
1662				<0 RK_PC5 12 &pcfg_pull_none>,
1663				/* pcie30x1_0_waken_m0 */
1664				<0 RK_PC4 12 &pcfg_pull_none>,
1665				/* pcie30x1_1_clkreqn_m0 */
1666				<0 RK_PB5 12 &pcfg_pull_none>,
1667				/* pcie30x1_1_perstn_m0 */
1668				<0 RK_PB7 12 &pcfg_pull_none>,
1669				/* pcie30x1_1_waken_m0 */
1670				<0 RK_PB6 12 &pcfg_pull_none>;
1671		};
1672
1673		/omit-if-no-ref/
1674		pcie30x1m1_pins: pcie30x1m1-pins {
1675			rockchip,pins =
1676				/* pcie30x1_0_clkreqn_m1 */
1677				<4 RK_PA3 4 &pcfg_pull_none>,
1678				/* pcie30x1_0_perstn_m1 */
1679				<4 RK_PA5 4 &pcfg_pull_none>,
1680				/* pcie30x1_0_waken_m1 */
1681				<4 RK_PA4 4 &pcfg_pull_none>,
1682				/* pcie30x1_1_clkreqn_m1 */
1683				<4 RK_PA0 4 &pcfg_pull_none>,
1684				/* pcie30x1_1_perstn_m1 */
1685				<4 RK_PA2 4 &pcfg_pull_none>,
1686				/* pcie30x1_1_waken_m1 */
1687				<4 RK_PA1 4 &pcfg_pull_none>;
1688		};
1689
1690		/omit-if-no-ref/
1691		pcie30x1m2_pins: pcie30x1m2-pins {
1692			rockchip,pins =
1693				/* pcie30x1_0_clkreqn_m2 */
1694				<1 RK_PB5 4 &pcfg_pull_none>,
1695				/* pcie30x1_0_perstn_m2 */
1696				<1 RK_PB4 4 &pcfg_pull_none>,
1697				/* pcie30x1_0_waken_m2 */
1698				<1 RK_PB3 4 &pcfg_pull_none>,
1699				/* pcie30x1_1_clkreqn_m2 */
1700				<1 RK_PA0 4 &pcfg_pull_none>,
1701				/* pcie30x1_1_perstn_m2 */
1702				<1 RK_PA7 4 &pcfg_pull_none>,
1703				/* pcie30x1_1_waken_m2 */
1704				<1 RK_PA1 4 &pcfg_pull_none>;
1705		};
1706
1707		/omit-if-no-ref/
1708		pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
1709			rockchip,pins =
1710				/* pcie30x1_0_button_rstn */
1711				<4 RK_PB1 4 &pcfg_pull_none>;
1712		};
1713
1714		/omit-if-no-ref/
1715		pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
1716			rockchip,pins =
1717				/* pcie30x1_1_button_rstn */
1718				<4 RK_PB2 4 &pcfg_pull_none>;
1719		};
1720	};
1721
1722	pcie30x2 {
1723		/omit-if-no-ref/
1724		pcie30x2m0_pins: pcie30x2m0-pins {
1725			rockchip,pins =
1726				/* pcie30x2_clkreqn_m0 */
1727				<0 RK_PD1 12 &pcfg_pull_none>,
1728				/* pcie30x2_perstn_m0 */
1729				<0 RK_PD4 12 &pcfg_pull_none>,
1730				/* pcie30x2_waken_m0 */
1731				<0 RK_PD2 12 &pcfg_pull_none>;
1732		};
1733
1734		/omit-if-no-ref/
1735		pcie30x2m1_pins: pcie30x2m1-pins {
1736			rockchip,pins =
1737				/* pcie30x2_clkreqn_m1 */
1738				<4 RK_PA6 4 &pcfg_pull_none>,
1739				/* pcie30x2_perstn_m1 */
1740				<4 RK_PB0 4 &pcfg_pull_none>,
1741				/* pcie30x2_waken_m1 */
1742				<4 RK_PA7 4 &pcfg_pull_none>;
1743		};
1744
1745		/omit-if-no-ref/
1746		pcie30x2m2_pins: pcie30x2m2-pins {
1747			rockchip,pins =
1748				/* pcie30x2_clkreqn_m2 */
1749				<3 RK_PD2 4 &pcfg_pull_none>,
1750				/* pcie30x2_perstn_m2 */
1751				<3 RK_PD4 4 &pcfg_pull_none>,
1752				/* pcie30x2_waken_m2 */
1753				<3 RK_PD3 4 &pcfg_pull_none>;
1754		};
1755
1756		/omit-if-no-ref/
1757		pcie30x2m3_pins: pcie30x2m3-pins {
1758			rockchip,pins =
1759				/* pcie30x2_clkreqn_m3 */
1760				<1 RK_PD7 4 &pcfg_pull_none>,
1761				/* pcie30x2_perstn_m3 */
1762				<1 RK_PB7 4 &pcfg_pull_none>,
1763				/* pcie30x2_waken_m3 */
1764				<1 RK_PB6 4 &pcfg_pull_none>;
1765		};
1766
1767		/omit-if-no-ref/
1768		pcie30x2_button_rstn: pcie30x2-button-rstn {
1769			rockchip,pins =
1770				/* pcie30x2_button_rstn */
1771				<3 RK_PC1 4 &pcfg_pull_none>;
1772		};
1773	};
1774
1775	pcie30x4 {
1776		/omit-if-no-ref/
1777		pcie30x4m0_pins: pcie30x4m0-pins {
1778			rockchip,pins =
1779				/* pcie30x4_clkreqn_m0 */
1780				<0 RK_PC6 12 &pcfg_pull_none>,
1781				/* pcie30x4_perstn_m0 */
1782				<0 RK_PD0 12 &pcfg_pull_none>,
1783				/* pcie30x4_waken_m0 */
1784				<0 RK_PC7 12 &pcfg_pull_none>;
1785		};
1786
1787		/omit-if-no-ref/
1788		pcie30x4m1_pins: pcie30x4m1-pins {
1789			rockchip,pins =
1790				/* pcie30x4_clkreqn_m1 */
1791				<4 RK_PB4 4 &pcfg_pull_none>,
1792				/* pcie30x4_perstn_m1 */
1793				<4 RK_PB6 4 &pcfg_pull_none>,
1794				/* pcie30x4_waken_m1 */
1795				<4 RK_PB5 4 &pcfg_pull_none>;
1796		};
1797
1798		/omit-if-no-ref/
1799		pcie30x4m2_pins: pcie30x4m2-pins {
1800			rockchip,pins =
1801				/* pcie30x4_clkreqn_m2 */
1802				<3 RK_PC4 4 &pcfg_pull_none>,
1803				/* pcie30x4_perstn_m2 */
1804				<3 RK_PC6 4 &pcfg_pull_none>,
1805				/* pcie30x4_waken_m2 */
1806				<3 RK_PC5 4 &pcfg_pull_none>;
1807		};
1808
1809		/omit-if-no-ref/
1810		pcie30x4m3_pins: pcie30x4m3-pins {
1811			rockchip,pins =
1812				/* pcie30x4_clkreqn_m3 */
1813				<1 RK_PB0 4 &pcfg_pull_none>,
1814				/* pcie30x4_perstn_m3 */
1815				<1 RK_PB2 4 &pcfg_pull_none>,
1816				/* pcie30x4_waken_m3 */
1817				<1 RK_PB1 4 &pcfg_pull_none>;
1818		};
1819
1820		/omit-if-no-ref/
1821		pcie30x4_button_rstn: pcie30x4-button-rstn {
1822			rockchip,pins =
1823				/* pcie30x4_button_rstn */
1824				<3 RK_PD5 4 &pcfg_pull_none>;
1825		};
1826	};
1827
1828	pdm0 {
1829		/omit-if-no-ref/
1830		pdm0m0_clk: pdm0m0-clk {
1831			rockchip,pins =
1832				/* pdm0_clk0_m0 */
1833				<1 RK_PC6 3 &pcfg_pull_none>;
1834		};
1835
1836		/omit-if-no-ref/
1837		pdm0m0_clk1: pdm0m0-clk1 {
1838			rockchip,pins =
1839				/* pdm0m0_clk1 */
1840				<1 RK_PC4 3 &pcfg_pull_none>;
1841		};
1842
1843		/omit-if-no-ref/
1844		pdm0m0_sdi0: pdm0m0-sdi0 {
1845			rockchip,pins =
1846				/* pdm0m0_sdi0 */
1847				<1 RK_PD5 3 &pcfg_pull_none>;
1848		};
1849
1850		/omit-if-no-ref/
1851		pdm0m0_sdi1: pdm0m0-sdi1 {
1852			rockchip,pins =
1853				/* pdm0m0_sdi1 */
1854				<1 RK_PD1 3 &pcfg_pull_none>;
1855		};
1856
1857		/omit-if-no-ref/
1858		pdm0m0_sdi2: pdm0m0-sdi2 {
1859			rockchip,pins =
1860				/* pdm0m0_sdi2 */
1861				<1 RK_PD2 3 &pcfg_pull_none>;
1862		};
1863
1864		/omit-if-no-ref/
1865		pdm0m0_sdi3: pdm0m0-sdi3 {
1866			rockchip,pins =
1867				/* pdm0m0_sdi3 */
1868				<1 RK_PD3 3 &pcfg_pull_none>;
1869		};
1870		/omit-if-no-ref/
1871		pdm0m1_clk: pdm0m1-clk {
1872			rockchip,pins =
1873				/* pdm0_clk0_m1 */
1874				<0 RK_PC0 2 &pcfg_pull_none>;
1875		};
1876
1877		/omit-if-no-ref/
1878		pdm0m1_clk1: pdm0m1-clk1 {
1879			rockchip,pins =
1880				/* pdm0m1_clk1 */
1881				<0 RK_PC4 2 &pcfg_pull_none>;
1882		};
1883
1884		/omit-if-no-ref/
1885		pdm0m1_sdi0: pdm0m1-sdi0 {
1886			rockchip,pins =
1887				/* pdm0m1_sdi0 */
1888				<0 RK_PC7 2 &pcfg_pull_none>;
1889		};
1890
1891		/omit-if-no-ref/
1892		pdm0m1_sdi1: pdm0m1-sdi1 {
1893			rockchip,pins =
1894				/* pdm0m1_sdi1 */
1895				<0 RK_PD0 2 &pcfg_pull_none>;
1896		};
1897
1898		/omit-if-no-ref/
1899		pdm0m1_sdi2: pdm0m1-sdi2 {
1900			rockchip,pins =
1901				/* pdm0m1_sdi2 */
1902				<0 RK_PD4 2 &pcfg_pull_none>;
1903		};
1904
1905		/omit-if-no-ref/
1906		pdm0m1_sdi3: pdm0m1-sdi3 {
1907			rockchip,pins =
1908				/* pdm0m1_sdi3 */
1909				<0 RK_PD6 2 &pcfg_pull_none>;
1910		};
1911	};
1912
1913	pdm1 {
1914		/omit-if-no-ref/
1915		pdm1m0_clk: pdm1m0-clk {
1916			rockchip,pins =
1917				/* pdm1_clk0_m0 */
1918				<4 RK_PD5 2 &pcfg_pull_none>;
1919		};
1920
1921		/omit-if-no-ref/
1922		pdm1m0_clk1: pdm1m0-clk1 {
1923			rockchip,pins =
1924				/* pdm1m0_clk1 */
1925				<4 RK_PD4 2 &pcfg_pull_none>;
1926		};
1927
1928		/omit-if-no-ref/
1929		pdm1m0_sdi0: pdm1m0-sdi0 {
1930			rockchip,pins =
1931				/* pdm1m0_sdi0 */
1932				<4 RK_PD3 2 &pcfg_pull_none>;
1933		};
1934
1935		/omit-if-no-ref/
1936		pdm1m0_sdi1: pdm1m0-sdi1 {
1937			rockchip,pins =
1938				/* pdm1m0_sdi1 */
1939				<4 RK_PD2 2 &pcfg_pull_none>;
1940		};
1941
1942		/omit-if-no-ref/
1943		pdm1m0_sdi2: pdm1m0-sdi2 {
1944			rockchip,pins =
1945				/* pdm1m0_sdi2 */
1946				<4 RK_PD1 2 &pcfg_pull_none>;
1947		};
1948
1949		/omit-if-no-ref/
1950		pdm1m0_sdi3: pdm1m0-sdi3 {
1951			rockchip,pins =
1952				/* pdm1m0_sdi3 */
1953				<4 RK_PD0 2 &pcfg_pull_none>;
1954		};
1955		/omit-if-no-ref/
1956		pdm1m1_clk: pdm1m1-clk {
1957			rockchip,pins =
1958				/* pdm1_clk0_m1 */
1959				<1 RK_PB4 2 &pcfg_pull_none>;
1960		};
1961
1962		/omit-if-no-ref/
1963		pdm1m1_clk1: pdm1m1-clk1 {
1964			rockchip,pins =
1965				/* pdm1m1_clk1 */
1966				<1 RK_PB3 2 &pcfg_pull_none>;
1967		};
1968
1969		/omit-if-no-ref/
1970		pdm1m1_sdi0: pdm1m1-sdi0 {
1971			rockchip,pins =
1972				/* pdm1m1_sdi0 */
1973				<1 RK_PA7 2 &pcfg_pull_none>;
1974		};
1975
1976		/omit-if-no-ref/
1977		pdm1m1_sdi1: pdm1m1-sdi1 {
1978			rockchip,pins =
1979				/* pdm1m1_sdi1 */
1980				<1 RK_PB0 2 &pcfg_pull_none>;
1981		};
1982
1983		/omit-if-no-ref/
1984		pdm1m1_sdi2: pdm1m1-sdi2 {
1985			rockchip,pins =
1986				/* pdm1m1_sdi2 */
1987				<1 RK_PB1 2 &pcfg_pull_none>;
1988		};
1989
1990		/omit-if-no-ref/
1991		pdm1m1_sdi3: pdm1m1-sdi3 {
1992			rockchip,pins =
1993				/* pdm1m1_sdi3 */
1994				<1 RK_PB2 2 &pcfg_pull_none>;
1995		};
1996	};
1997
1998	pmic {
1999		/omit-if-no-ref/
2000		pmic_pins: pmic-pins {
2001			rockchip,pins =
2002				/* pmic_int_l */
2003				<0 RK_PA7 0 &pcfg_pull_up>,
2004				/* pmic_sleep1 */
2005				<0 RK_PA2 1 &pcfg_pull_none>,
2006				/* pmic_sleep2 */
2007				<0 RK_PA3 1 &pcfg_pull_none>,
2008				/* pmic_sleep3 */
2009				<0 RK_PC1 1 &pcfg_pull_none>,
2010				/* pmic_sleep4 */
2011				<0 RK_PC2 1 &pcfg_pull_none>,
2012				/* pmic_sleep5 */
2013				<0 RK_PC3 1 &pcfg_pull_none>,
2014				/* pmic_sleep6 */
2015				<0 RK_PD6 1 &pcfg_pull_none>;
2016		};
2017	};
2018
2019	pmu {
2020		/omit-if-no-ref/
2021		pmu_pins: pmu-pins {
2022			rockchip,pins =
2023				/* pmu_debug */
2024				<0 RK_PA5 3 &pcfg_pull_none>;
2025		};
2026	};
2027
2028	pwm0 {
2029		/omit-if-no-ref/
2030		pwm0m0_pins: pwm0m0-pins {
2031			rockchip,pins =
2032				/* pwm0_m0 */
2033				<0 RK_PB7 3 &pcfg_pull_none>;
2034		};
2035
2036		/omit-if-no-ref/
2037		pwm0m1_pins: pwm0m1-pins {
2038			rockchip,pins =
2039				/* pwm0_m1 */
2040				<1 RK_PD2 11 &pcfg_pull_none>;
2041		};
2042
2043		/omit-if-no-ref/
2044		pwm0m2_pins: pwm0m2-pins {
2045			rockchip,pins =
2046				/* pwm0_m2 */
2047				<1 RK_PA2 11 &pcfg_pull_none>;
2048		};
2049	};
2050
2051	pwm1 {
2052		/omit-if-no-ref/
2053		pwm1m0_pins: pwm1m0-pins {
2054			rockchip,pins =
2055				/* pwm1_m0 */
2056				<0 RK_PC0 3 &pcfg_pull_none>;
2057		};
2058
2059		/omit-if-no-ref/
2060		pwm1m1_pins: pwm1m1-pins {
2061			rockchip,pins =
2062				/* pwm1_m1 */
2063				<1 RK_PD3 11 &pcfg_pull_none>;
2064		};
2065
2066		/omit-if-no-ref/
2067		pwm1m2_pins: pwm1m2-pins {
2068			rockchip,pins =
2069				/* pwm1_m2 */
2070				<1 RK_PA3 11 &pcfg_pull_none>;
2071		};
2072	};
2073
2074	pwm2 {
2075		/omit-if-no-ref/
2076		pwm2m0_pins: pwm2m0-pins {
2077			rockchip,pins =
2078				/* pwm2_m0 */
2079				<0 RK_PC4 3 &pcfg_pull_none>;
2080		};
2081
2082		/omit-if-no-ref/
2083		pwm2m1_pins: pwm2m1-pins {
2084			rockchip,pins =
2085				/* pwm2_m1 */
2086				<3 RK_PB1 11 &pcfg_pull_none>;
2087		};
2088	};
2089
2090	pwm3 {
2091		/omit-if-no-ref/
2092		pwm3m0_pins: pwm3m0-pins {
2093			rockchip,pins =
2094				/* pwm3_ir_m0 */
2095				<0 RK_PD4 3 &pcfg_pull_none>;
2096		};
2097
2098		/omit-if-no-ref/
2099		pwm3m1_pins: pwm3m1-pins {
2100			rockchip,pins =
2101				/* pwm3_ir_m1 */
2102				<3 RK_PB2 11 &pcfg_pull_none>;
2103		};
2104
2105		/omit-if-no-ref/
2106		pwm3m2_pins: pwm3m2-pins {
2107			rockchip,pins =
2108				/* pwm3_ir_m2 */
2109				<1 RK_PC2 11 &pcfg_pull_none>;
2110		};
2111
2112		/omit-if-no-ref/
2113		pwm3m3_pins: pwm3m3-pins {
2114			rockchip,pins =
2115				/* pwm3_ir_m3 */
2116				<1 RK_PA7 11 &pcfg_pull_none>;
2117		};
2118	};
2119
2120	pwm4 {
2121		/omit-if-no-ref/
2122		pwm4m0_pins: pwm4m0-pins {
2123			rockchip,pins =
2124				/* pwm4_m0 */
2125				<0 RK_PC5 11 &pcfg_pull_none>;
2126		};
2127	};
2128
2129	pwm5 {
2130		/omit-if-no-ref/
2131		pwm5m0_pins: pwm5m0-pins {
2132			rockchip,pins =
2133				/* pwm5_m0 */
2134				<0 RK_PB1 3 &pcfg_pull_none>;
2135		};
2136
2137		/omit-if-no-ref/
2138		pwm5m1_pins: pwm5m1-pins {
2139			rockchip,pins =
2140				/* pwm5_m1 */
2141				<0 RK_PC6 11 &pcfg_pull_none>;
2142		};
2143	};
2144
2145	pwm6 {
2146		/omit-if-no-ref/
2147		pwm6m0_pins: pwm6m0-pins {
2148			rockchip,pins =
2149				/* pwm6_m0 */
2150				<0 RK_PC7 11 &pcfg_pull_none>;
2151		};
2152
2153		/omit-if-no-ref/
2154		pwm6m1_pins: pwm6m1-pins {
2155			rockchip,pins =
2156				/* pwm6_m1 */
2157				<4 RK_PC1 11 &pcfg_pull_none>;
2158		};
2159	};
2160
2161	pwm7 {
2162		/omit-if-no-ref/
2163		pwm7m0_pins: pwm7m0-pins {
2164			rockchip,pins =
2165				/* pwm7_ir_m0 */
2166				<0 RK_PD0 11 &pcfg_pull_none>;
2167		};
2168
2169		/omit-if-no-ref/
2170		pwm7m1_pins: pwm7m1-pins {
2171			rockchip,pins =
2172				/* pwm7_ir_m1 */
2173				<4 RK_PD4 11 &pcfg_pull_none>;
2174		};
2175
2176		/omit-if-no-ref/
2177		pwm7m2_pins: pwm7m2-pins {
2178			rockchip,pins =
2179				/* pwm7_ir_m2 */
2180				<1 RK_PC3 11 &pcfg_pull_none>;
2181		};
2182	};
2183
2184	pwm8 {
2185		/omit-if-no-ref/
2186		pwm8m0_pins: pwm8m0-pins {
2187			rockchip,pins =
2188				/* pwm8_m0 */
2189				<3 RK_PA7 11 &pcfg_pull_none>;
2190		};
2191
2192		/omit-if-no-ref/
2193		pwm8m1_pins: pwm8m1-pins {
2194			rockchip,pins =
2195				/* pwm8_m1 */
2196				<4 RK_PD0 11 &pcfg_pull_none>;
2197		};
2198
2199		/omit-if-no-ref/
2200		pwm8m2_pins: pwm8m2-pins {
2201			rockchip,pins =
2202				/* pwm8_m2 */
2203				<3 RK_PD0 11 &pcfg_pull_none>;
2204		};
2205	};
2206
2207	pwm9 {
2208		/omit-if-no-ref/
2209		pwm9m0_pins: pwm9m0-pins {
2210			rockchip,pins =
2211				/* pwm9_m0 */
2212				<3 RK_PB0 11 &pcfg_pull_none>;
2213		};
2214
2215		/omit-if-no-ref/
2216		pwm9m1_pins: pwm9m1-pins {
2217			rockchip,pins =
2218				/* pwm9_m1 */
2219				<4 RK_PD1 11 &pcfg_pull_none>;
2220		};
2221
2222		/omit-if-no-ref/
2223		pwm9m2_pins: pwm9m2-pins {
2224			rockchip,pins =
2225				/* pwm9_m2 */
2226				<3 RK_PD1 11 &pcfg_pull_none>;
2227		};
2228	};
2229
2230	pwm10 {
2231		/omit-if-no-ref/
2232		pwm10m0_pins: pwm10m0-pins {
2233			rockchip,pins =
2234				/* pwm10_m0 */
2235				<3 RK_PA0 11 &pcfg_pull_none>;
2236		};
2237
2238		/omit-if-no-ref/
2239		pwm10m1_pins: pwm10m1-pins {
2240			rockchip,pins =
2241				/* pwm10_m1 */
2242				<4 RK_PD3 11 &pcfg_pull_none>;
2243		};
2244
2245		/omit-if-no-ref/
2246		pwm10m2_pins: pwm10m2-pins {
2247			rockchip,pins =
2248				/* pwm10_m2 */
2249				<3 RK_PD3 11 &pcfg_pull_none>;
2250		};
2251	};
2252
2253	pwm11 {
2254		/omit-if-no-ref/
2255		pwm11m0_pins: pwm11m0-pins {
2256			rockchip,pins =
2257				/* pwm11_ir_m0 */
2258				<3 RK_PA1 11 &pcfg_pull_none>;
2259		};
2260
2261		/omit-if-no-ref/
2262		pwm11m1_pins: pwm11m1-pins {
2263			rockchip,pins =
2264				/* pwm11_ir_m1 */
2265				<4 RK_PB4 11 &pcfg_pull_none>;
2266		};
2267
2268		/omit-if-no-ref/
2269		pwm11m2_pins: pwm11m2-pins {
2270			rockchip,pins =
2271				/* pwm11_ir_m2 */
2272				<1 RK_PC4 11 &pcfg_pull_none>;
2273		};
2274
2275		/omit-if-no-ref/
2276		pwm11m3_pins: pwm11m3-pins {
2277			rockchip,pins =
2278				/* pwm11_ir_m3 */
2279				<3 RK_PD5 11 &pcfg_pull_none>;
2280		};
2281	};
2282
2283	pwm12 {
2284		/omit-if-no-ref/
2285		pwm12m0_pins: pwm12m0-pins {
2286			rockchip,pins =
2287				/* pwm12_m0 */
2288				<3 RK_PB5 11 &pcfg_pull_none>;
2289		};
2290
2291		/omit-if-no-ref/
2292		pwm12m1_pins: pwm12m1-pins {
2293			rockchip,pins =
2294				/* pwm12_m1 */
2295				<4 RK_PB5 11 &pcfg_pull_none>;
2296		};
2297	};
2298
2299	pwm13 {
2300		/omit-if-no-ref/
2301		pwm13m0_pins: pwm13m0-pins {
2302			rockchip,pins =
2303				/* pwm13_m0 */
2304				<3 RK_PB6 11 &pcfg_pull_none>;
2305		};
2306
2307		/omit-if-no-ref/
2308		pwm13m1_pins: pwm13m1-pins {
2309			rockchip,pins =
2310				/* pwm13_m1 */
2311				<4 RK_PB6 11 &pcfg_pull_none>;
2312		};
2313
2314		/omit-if-no-ref/
2315		pwm13m2_pins: pwm13m2-pins {
2316			rockchip,pins =
2317				/* pwm13_m2 */
2318				<1 RK_PB7 11 &pcfg_pull_none>;
2319		};
2320	};
2321
2322	pwm14 {
2323		/omit-if-no-ref/
2324		pwm14m0_pins: pwm14m0-pins {
2325			rockchip,pins =
2326				/* pwm14_m0 */
2327				<3 RK_PC2 11 &pcfg_pull_none>;
2328		};
2329
2330		/omit-if-no-ref/
2331		pwm14m1_pins: pwm14m1-pins {
2332			rockchip,pins =
2333				/* pwm14_m1 */
2334				<4 RK_PB2 11 &pcfg_pull_none>;
2335		};
2336
2337		/omit-if-no-ref/
2338		pwm14m2_pins: pwm14m2-pins {
2339			rockchip,pins =
2340				/* pwm14_m2 */
2341				<1 RK_PD6 11 &pcfg_pull_none>;
2342		};
2343	};
2344
2345	pwm15 {
2346		/omit-if-no-ref/
2347		pwm15m0_pins: pwm15m0-pins {
2348			rockchip,pins =
2349				/* pwm15_ir_m0 */
2350				<3 RK_PC3 11 &pcfg_pull_none>;
2351		};
2352
2353		/omit-if-no-ref/
2354		pwm15m1_pins: pwm15m1-pins {
2355			rockchip,pins =
2356				/* pwm15_ir_m1 */
2357				<4 RK_PB3 11 &pcfg_pull_none>;
2358		};
2359
2360		/omit-if-no-ref/
2361		pwm15m2_pins: pwm15m2-pins {
2362			rockchip,pins =
2363				/* pwm15_ir_m2 */
2364				<1 RK_PC6 11 &pcfg_pull_none>;
2365		};
2366
2367		/omit-if-no-ref/
2368		pwm15m3_pins: pwm15m3-pins {
2369			rockchip,pins =
2370				/* pwm15_ir_m3 */
2371				<1 RK_PD7 11 &pcfg_pull_none>;
2372		};
2373	};
2374
2375	refclk {
2376		/omit-if-no-ref/
2377		refclk_pins: refclk-pins {
2378			rockchip,pins =
2379				/* refclk_out */
2380				<0 RK_PA0 1 &pcfg_pull_none>;
2381		};
2382	};
2383
2384	sata {
2385		/omit-if-no-ref/
2386		sata_pins: sata-pins {
2387			rockchip,pins =
2388				/* sata_cp_pod */
2389				<0 RK_PC6 13 &pcfg_pull_none>,
2390				/* sata_cpdet */
2391				<0 RK_PD4 13 &pcfg_pull_none>,
2392				/* sata_mp_switch */
2393				<0 RK_PD5 13 &pcfg_pull_none>;
2394		};
2395	};
2396
2397	sata0 {
2398		/omit-if-no-ref/
2399		sata0m0_pins: sata0m0-pins {
2400			rockchip,pins =
2401				/* sata0_act_led_m0 */
2402				<4 RK_PB6 6 &pcfg_pull_none>;
2403		};
2404
2405		/omit-if-no-ref/
2406		sata0m1_pins: sata0m1-pins {
2407			rockchip,pins =
2408				/* sata0_act_led_m1 */
2409				<1 RK_PB3 6 &pcfg_pull_none>;
2410		};
2411	};
2412
2413	sata1 {
2414		/omit-if-no-ref/
2415		sata1m0_pins: sata1m0-pins {
2416			rockchip,pins =
2417				/* sata1_act_led_m0 */
2418				<4 RK_PB5 6 &pcfg_pull_none>;
2419		};
2420
2421		/omit-if-no-ref/
2422		sata1m1_pins: sata1m1-pins {
2423			rockchip,pins =
2424				/* sata1_act_led_m1 */
2425				<1 RK_PA1 6 &pcfg_pull_none>;
2426		};
2427	};
2428
2429	sata2 {
2430		/omit-if-no-ref/
2431		sata2m0_pins: sata2m0-pins {
2432			rockchip,pins =
2433				/* sata2_act_led_m0 */
2434				<4 RK_PB1 6 &pcfg_pull_none>;
2435		};
2436
2437		/omit-if-no-ref/
2438		sata2m1_pins: sata2m1-pins {
2439			rockchip,pins =
2440				/* sata2_act_led_m1 */
2441				<1 RK_PB7 6 &pcfg_pull_none>;
2442		};
2443	};
2444
2445	sdio {
2446		/omit-if-no-ref/
2447		sdiom1_pins: sdiom1-pins {
2448			rockchip,pins =
2449				/* sdio_clk_m1 */
2450				<3 RK_PA5 2 &pcfg_pull_none>,
2451				/* sdio_cmd_m1 */
2452				<3 RK_PA4 2 &pcfg_pull_none>,
2453				/* sdio_d0_m1 */
2454				<3 RK_PA0 2 &pcfg_pull_none>,
2455				/* sdio_d1_m1 */
2456				<3 RK_PA1 2 &pcfg_pull_none>,
2457				/* sdio_d2_m1 */
2458				<3 RK_PA2 2 &pcfg_pull_none>,
2459				/* sdio_d3_m1 */
2460				<3 RK_PA3 2 &pcfg_pull_none>;
2461		};
2462	};
2463
2464	sdmmc {
2465		/omit-if-no-ref/
2466		sdmmc_bus4: sdmmc-bus4 {
2467			rockchip,pins =
2468				/* sdmmc_d0 */
2469				<4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
2470				/* sdmmc_d1 */
2471				<4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
2472				/* sdmmc_d2 */
2473				<4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
2474				/* sdmmc_d3 */
2475				<4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
2476		};
2477
2478		/omit-if-no-ref/
2479		sdmmc_clk: sdmmc-clk {
2480			rockchip,pins =
2481				/* sdmmc_clk */
2482				<4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
2483		};
2484
2485		/omit-if-no-ref/
2486		sdmmc_cmd: sdmmc-cmd {
2487			rockchip,pins =
2488				/* sdmmc_cmd */
2489				<4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
2490		};
2491
2492		/omit-if-no-ref/
2493		sdmmc_det: sdmmc-det {
2494			rockchip,pins =
2495				/* sdmmc_det */
2496				<0 RK_PA4 1 &pcfg_pull_up>;
2497		};
2498
2499		/omit-if-no-ref/
2500		sdmmc_pwren: sdmmc-pwren {
2501			rockchip,pins =
2502				/* sdmmc_pwren */
2503				<0 RK_PA5 2 &pcfg_pull_none>;
2504		};
2505	};
2506
2507	spdif0 {
2508		/omit-if-no-ref/
2509		spdif0m0_tx: spdif0m0-tx {
2510			rockchip,pins =
2511				/* spdif0m0_tx */
2512				<1 RK_PB6 3 &pcfg_pull_none>;
2513		};
2514
2515		/omit-if-no-ref/
2516		spdif0m1_tx: spdif0m1-tx {
2517			rockchip,pins =
2518				/* spdif0m1_tx */
2519				<4 RK_PB4 6 &pcfg_pull_none>;
2520		};
2521	};
2522
2523	spdif1 {
2524		/omit-if-no-ref/
2525		spdif1m0_tx: spdif1m0-tx {
2526			rockchip,pins =
2527				/* spdif1m0_tx */
2528				<1 RK_PB7 3 &pcfg_pull_none>;
2529		};
2530
2531		/omit-if-no-ref/
2532		spdif1m1_tx: spdif1m1-tx {
2533			rockchip,pins =
2534				/* spdif1m1_tx */
2535				<4 RK_PB1 2 &pcfg_pull_none>;
2536		};
2537
2538		/omit-if-no-ref/
2539		spdif1m2_tx: spdif1m2-tx {
2540			rockchip,pins =
2541				/* spdif1m2_tx */
2542				<4 RK_PC1 3 &pcfg_pull_none>;
2543		};
2544	};
2545
2546	spi0 {
2547		/omit-if-no-ref/
2548		spi0m0_pins: spi0m0-pins {
2549			rockchip,pins =
2550				/* spi0_clk_m0 */
2551				<0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
2552				/* spi0_miso_m0 */
2553				<0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
2554				/* spi0_mosi_m0 */
2555				<0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
2556		};
2557
2558		/omit-if-no-ref/
2559		spi0m0_cs0: spi0m0-cs0 {
2560			rockchip,pins =
2561				/* spi0_cs0_m0 */
2562				<0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
2563		};
2564
2565		/omit-if-no-ref/
2566		spi0m0_cs1: spi0m0-cs1 {
2567			rockchip,pins =
2568				/* spi0_cs1_m0 */
2569				<0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
2570		};
2571		/omit-if-no-ref/
2572		spi0m1_pins: spi0m1-pins {
2573			rockchip,pins =
2574				/* spi0_clk_m1 */
2575				<4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2576				/* spi0_miso_m1 */
2577				<4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2578				/* spi0_mosi_m1 */
2579				<4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2580		};
2581
2582		/omit-if-no-ref/
2583		spi0m1_cs0: spi0m1-cs0 {
2584			rockchip,pins =
2585				/* spi0_cs0_m1 */
2586				<4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
2587		};
2588
2589		/omit-if-no-ref/
2590		spi0m1_cs1: spi0m1-cs1 {
2591			rockchip,pins =
2592				/* spi0_cs1_m1 */
2593				<4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
2594		};
2595		/omit-if-no-ref/
2596		spi0m2_pins: spi0m2-pins {
2597			rockchip,pins =
2598				/* spi0_clk_m2 */
2599				<1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
2600				/* spi0_miso_m2 */
2601				<1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
2602				/* spi0_mosi_m2 */
2603				<1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
2604		};
2605
2606		/omit-if-no-ref/
2607		spi0m2_cs0: spi0m2-cs0 {
2608			rockchip,pins =
2609				/* spi0_cs0_m2 */
2610				<1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
2611		};
2612
2613		/omit-if-no-ref/
2614		spi0m2_cs1: spi0m2-cs1 {
2615			rockchip,pins =
2616				/* spi0_cs1_m2 */
2617				<1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
2618		};
2619		/omit-if-no-ref/
2620		spi0m3_pins: spi0m3-pins {
2621			rockchip,pins =
2622				/* spi0_clk_m3 */
2623				<3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
2624				/* spi0_miso_m3 */
2625				<3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
2626				/* spi0_mosi_m3 */
2627				<3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
2628		};
2629
2630		/omit-if-no-ref/
2631		spi0m3_cs0: spi0m3-cs0 {
2632			rockchip,pins =
2633				/* spi0_cs0_m3 */
2634				<3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
2635		};
2636
2637		/omit-if-no-ref/
2638		spi0m3_cs1: spi0m3-cs1 {
2639			rockchip,pins =
2640				/* spi0_cs1_m3 */
2641				<3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2642		};
2643	};
2644
2645	spi1 {
2646		/omit-if-no-ref/
2647		spi1m1_pins: spi1m1-pins {
2648			rockchip,pins =
2649				/* spi1_clk_m1 */
2650				<3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
2651				/* spi1_miso_m1 */
2652				<3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
2653				/* spi1_mosi_m1 */
2654				<3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
2655		};
2656
2657		/omit-if-no-ref/
2658		spi1m1_cs0: spi1m1-cs0 {
2659			rockchip,pins =
2660				/* spi1_cs0_m1 */
2661				<3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
2662		};
2663
2664		/omit-if-no-ref/
2665		spi1m1_cs1: spi1m1-cs1 {
2666			rockchip,pins =
2667				/* spi1_cs1_m1 */
2668				<3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
2669		};
2670
2671		/omit-if-no-ref/
2672		spi1m2_pins: spi1m2-pins {
2673			rockchip,pins =
2674				/* spi1_clk_m2 */
2675				<1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
2676				/* spi1_miso_m2 */
2677				<1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2678				/* spi1_mosi_m2 */
2679				<1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
2680		};
2681
2682		/omit-if-no-ref/
2683		spi1m2_cs0: spi1m2-cs0 {
2684			rockchip,pins =
2685				/* spi1_cs0_m2 */
2686				<1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
2687		};
2688
2689		/omit-if-no-ref/
2690		spi1m2_cs1: spi1m2-cs1 {
2691			rockchip,pins =
2692				/* spi1_cs1_m2 */
2693				<1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2694		};
2695	};
2696
2697	spi2 {
2698		/omit-if-no-ref/
2699		spi2m0_pins: spi2m0-pins {
2700			rockchip,pins =
2701				/* spi2_clk_m0 */
2702				<1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
2703				/* spi2_miso_m0 */
2704				<1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
2705				/* spi2_mosi_m0 */
2706				<1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
2707		};
2708
2709		/omit-if-no-ref/
2710		spi2m0_cs0: spi2m0-cs0 {
2711			rockchip,pins =
2712				/* spi2_cs0_m0 */
2713				<1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
2714		};
2715
2716		/omit-if-no-ref/
2717		spi2m0_cs1: spi2m0-cs1 {
2718			rockchip,pins =
2719				/* spi2_cs1_m0 */
2720				<1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
2721		};
2722
2723		/omit-if-no-ref/
2724		spi2m1_pins: spi2m1-pins {
2725			rockchip,pins =
2726				/* spi2_clk_m1 */
2727				<4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
2728				/* spi2_miso_m1 */
2729				<4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
2730				/* spi2_mosi_m1 */
2731				<4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
2732		};
2733
2734		/omit-if-no-ref/
2735		spi2m1_cs0: spi2m1-cs0 {
2736			rockchip,pins =
2737				/* spi2_cs0_m1 */
2738				<4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
2739		};
2740
2741		/omit-if-no-ref/
2742		spi2m1_cs1: spi2m1-cs1 {
2743			rockchip,pins =
2744				/* spi2_cs1_m1 */
2745				<4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
2746		};
2747
2748		/omit-if-no-ref/
2749		spi2m2_pins: spi2m2-pins {
2750			rockchip,pins =
2751				/* spi2_clk_m2 */
2752				<0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
2753				/* spi2_miso_m2 */
2754				<0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
2755				/* spi2_mosi_m2 */
2756				<0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
2757		};
2758
2759		/omit-if-no-ref/
2760		spi2m2_cs0: spi2m2-cs0 {
2761			rockchip,pins =
2762				/* spi2_cs0_m2 */
2763				<0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
2764		};
2765
2766		/omit-if-no-ref/
2767		spi2m2_cs1: spi2m2-cs1 {
2768			rockchip,pins =
2769				/* spi2_cs1_m2 */
2770				<0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
2771		};
2772	};
2773
2774	spi3 {
2775		/omit-if-no-ref/
2776		spi3m1_pins: spi3m1-pins {
2777			rockchip,pins =
2778				/* spi3_clk_m1 */
2779				<4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
2780				/* spi3_miso_m1 */
2781				<4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
2782				/* spi3_mosi_m1 */
2783				<4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
2784		};
2785
2786		/omit-if-no-ref/
2787		spi3m1_cs0: spi3m1-cs0 {
2788			rockchip,pins =
2789				/* spi3_cs0_m1 */
2790				<4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
2791		};
2792
2793		/omit-if-no-ref/
2794		spi3m1_cs1: spi3m1-cs1 {
2795			rockchip,pins =
2796				/* spi3_cs1_m1 */
2797				<4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
2798		};
2799
2800		/omit-if-no-ref/
2801		spi3m2_pins: spi3m2-pins {
2802			rockchip,pins =
2803				/* spi3_clk_m2 */
2804				<0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
2805				/* spi3_miso_m2 */
2806				<0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2807				/* spi3_mosi_m2 */
2808				<0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
2809		};
2810
2811		/omit-if-no-ref/
2812		spi3m2_cs0: spi3m2-cs0 {
2813			rockchip,pins =
2814				/* spi3_cs0_m2 */
2815				<0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
2816		};
2817
2818		/omit-if-no-ref/
2819		spi3m2_cs1: spi3m2-cs1 {
2820			rockchip,pins =
2821				/* spi3_cs1_m2 */
2822				<0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
2823		};
2824
2825		/omit-if-no-ref/
2826		spi3m3_pins: spi3m3-pins {
2827			rockchip,pins =
2828				/* spi3_clk_m3 */
2829				<3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
2830				/* spi3_miso_m3 */
2831				<3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
2832				/* spi3_mosi_m3 */
2833				<3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
2834		};
2835
2836		/omit-if-no-ref/
2837		spi3m3_cs0: spi3m3-cs0 {
2838			rockchip,pins =
2839				/* spi3_cs0_m3 */
2840				<3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
2841		};
2842
2843		/omit-if-no-ref/
2844		spi3m3_cs1: spi3m3-cs1 {
2845			rockchip,pins =
2846				/* spi3_cs1_m3 */
2847				<3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
2848		};
2849	};
2850
2851	spi4 {
2852		/omit-if-no-ref/
2853		spi4m0_pins: spi4m0-pins {
2854			rockchip,pins =
2855				/* spi4_clk_m0 */
2856				<1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
2857				/* spi4_miso_m0 */
2858				<1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
2859				/* spi4_mosi_m0 */
2860				<1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
2861		};
2862
2863		/omit-if-no-ref/
2864		spi4m0_cs0: spi4m0-cs0 {
2865			rockchip,pins =
2866				/* spi4_cs0_m0 */
2867				<1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
2868		};
2869
2870		/omit-if-no-ref/
2871		spi4m0_cs1: spi4m0-cs1 {
2872			rockchip,pins =
2873				/* spi4_cs1_m0 */
2874				<1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
2875		};
2876
2877		/omit-if-no-ref/
2878		spi4m1_pins: spi4m1-pins {
2879			rockchip,pins =
2880				/* spi4_clk_m1 */
2881				<3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2882				/* spi4_miso_m1 */
2883				<3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2884				/* spi4_mosi_m1 */
2885				<3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2886		};
2887
2888		/omit-if-no-ref/
2889		spi4m1_cs0: spi4m1-cs0 {
2890			rockchip,pins =
2891				/* spi4_cs0_m1 */
2892				<3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
2893		};
2894
2895		/omit-if-no-ref/
2896		spi4m1_cs1: spi4m1-cs1 {
2897			rockchip,pins =
2898				/* spi4_cs1_m1 */
2899				<3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
2900		};
2901
2902		/omit-if-no-ref/
2903		spi4m2_pins: spi4m2-pins {
2904			rockchip,pins =
2905				/* spi4_clk_m2 */
2906				<1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
2907				/* spi4_miso_m2 */
2908				<1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
2909				/* spi4_mosi_m2 */
2910				<1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
2911		};
2912
2913		/omit-if-no-ref/
2914		spi4m2_cs0: spi4m2-cs0 {
2915			rockchip,pins =
2916				/* spi4_cs0_m2 */
2917				<1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
2918		};
2919	};
2920
2921	tsadc {
2922		/omit-if-no-ref/
2923		tsadcm1_shut: tsadcm1-shut {
2924			rockchip,pins =
2925				/* tsadcm1_shut */
2926				<0 RK_PA2 2 &pcfg_pull_none>;
2927		};
2928
2929		/omit-if-no-ref/
2930		tsadc_shut: tsadc-shut {
2931			rockchip,pins =
2932				/* tsadc_shut */
2933				<0 RK_PA1 2 &pcfg_pull_none>;
2934		};
2935
2936		/omit-if-no-ref/
2937		tsadc_shut_org: tsadc-shut-org {
2938			rockchip,pins =
2939				/* tsadc_shut_org */
2940				<0 RK_PA1 1 &pcfg_pull_none>;
2941		};
2942	};
2943
2944	uart0 {
2945		/omit-if-no-ref/
2946		uart0m0_xfer: uart0m0-xfer {
2947			rockchip,pins =
2948				/* uart0_rx_m0 */
2949				<0 RK_PC4 4 &pcfg_pull_up>,
2950				/* uart0_tx_m0 */
2951				<0 RK_PC5 4 &pcfg_pull_up>;
2952		};
2953
2954		/omit-if-no-ref/
2955		uart0m1_xfer: uart0m1-xfer {
2956			rockchip,pins =
2957				/* uart0_rx_m1 */
2958				<0 RK_PB0 4 &pcfg_pull_up>,
2959				/* uart0_tx_m1 */
2960				<0 RK_PB1 4 &pcfg_pull_up>;
2961		};
2962
2963		/omit-if-no-ref/
2964		uart0m2_xfer: uart0m2-xfer {
2965			rockchip,pins =
2966				/* uart0_rx_m2 */
2967				<4 RK_PA4 10 &pcfg_pull_up>,
2968				/* uart0_tx_m2 */
2969				<4 RK_PA3 10 &pcfg_pull_up>;
2970		};
2971
2972		/omit-if-no-ref/
2973		uart0_ctsn: uart0-ctsn {
2974			rockchip,pins =
2975				/* uart0_ctsn */
2976				<0 RK_PD1 4 &pcfg_pull_none>;
2977		};
2978
2979		/omit-if-no-ref/
2980		uart0_rtsn: uart0-rtsn {
2981			rockchip,pins =
2982				/* uart0_rtsn */
2983				<0 RK_PC6 4 &pcfg_pull_none>;
2984		};
2985	};
2986
2987	uart1 {
2988		/omit-if-no-ref/
2989		uart1m1_xfer: uart1m1-xfer {
2990			rockchip,pins =
2991				/* uart1_rx_m1 */
2992				<1 RK_PB7 10 &pcfg_pull_up>,
2993				/* uart1_tx_m1 */
2994				<1 RK_PB6 10 &pcfg_pull_up>;
2995		};
2996
2997		/omit-if-no-ref/
2998		uart1m1_ctsn: uart1m1-ctsn {
2999			rockchip,pins =
3000				/* uart1m1_ctsn */
3001				<1 RK_PD7 10 &pcfg_pull_none>;
3002		};
3003
3004		/omit-if-no-ref/
3005		uart1m1_rtsn: uart1m1-rtsn {
3006			rockchip,pins =
3007				/* uart1m1_rtsn */
3008				<1 RK_PD6 10 &pcfg_pull_none>;
3009		};
3010
3011		/omit-if-no-ref/
3012		uart1m2_xfer: uart1m2-xfer {
3013			rockchip,pins =
3014				/* uart1_rx_m2 */
3015				<0 RK_PD2 10 &pcfg_pull_up>,
3016				/* uart1_tx_m2 */
3017				<0 RK_PD1 10 &pcfg_pull_up>;
3018		};
3019
3020		/omit-if-no-ref/
3021		uart1m2_ctsn: uart1m2-ctsn {
3022			rockchip,pins =
3023				/* uart1m2_ctsn */
3024				<0 RK_PD0 10 &pcfg_pull_none>;
3025		};
3026
3027		/omit-if-no-ref/
3028		uart1m2_rtsn: uart1m2-rtsn {
3029			rockchip,pins =
3030				/* uart1m2_rtsn */
3031				<0 RK_PC7 10 &pcfg_pull_none>;
3032		};
3033	};
3034
3035	uart2 {
3036		/omit-if-no-ref/
3037		uart2m0_xfer: uart2m0-xfer {
3038			rockchip,pins =
3039				/* uart2_rx_m0 */
3040				<0 RK_PB6 10 &pcfg_pull_up>,
3041				/* uart2_tx_m0 */
3042				<0 RK_PB5 10 &pcfg_pull_up>;
3043		};
3044
3045		/omit-if-no-ref/
3046		uart2m1_xfer: uart2m1-xfer {
3047			rockchip,pins =
3048				/* uart2_rx_m1 */
3049				<4 RK_PD1 10 &pcfg_pull_up>,
3050				/* uart2_tx_m1 */
3051				<4 RK_PD0 10 &pcfg_pull_up>;
3052		};
3053
3054		/omit-if-no-ref/
3055		uart2m2_xfer: uart2m2-xfer {
3056			rockchip,pins =
3057				/* uart2_rx_m2 */
3058				<3 RK_PB2 10 &pcfg_pull_up>,
3059				/* uart2_tx_m2 */
3060				<3 RK_PB1 10 &pcfg_pull_up>;
3061		};
3062
3063		/omit-if-no-ref/
3064		uart2_ctsn: uart2-ctsn {
3065			rockchip,pins =
3066				/* uart2_ctsn */
3067				<3 RK_PB4 10 &pcfg_pull_none>;
3068		};
3069
3070		/omit-if-no-ref/
3071		uart2_rtsn: uart2-rtsn {
3072			rockchip,pins =
3073				/* uart2_rtsn */
3074				<3 RK_PB3 10 &pcfg_pull_none>;
3075		};
3076	};
3077
3078	uart3 {
3079		/omit-if-no-ref/
3080		uart3m0_xfer: uart3m0-xfer {
3081			rockchip,pins =
3082				/* uart3_rx_m0 */
3083				<1 RK_PC0 10 &pcfg_pull_up>,
3084				/* uart3_tx_m0 */
3085				<1 RK_PC1 10 &pcfg_pull_up>;
3086		};
3087
3088		/omit-if-no-ref/
3089		uart3m1_xfer: uart3m1-xfer {
3090			rockchip,pins =
3091				/* uart3_rx_m1 */
3092				<3 RK_PB6 10 &pcfg_pull_up>,
3093				/* uart3_tx_m1 */
3094				<3 RK_PB5 10 &pcfg_pull_up>;
3095		};
3096
3097		/omit-if-no-ref/
3098		uart3m2_xfer: uart3m2-xfer {
3099			rockchip,pins =
3100				/* uart3_rx_m2 */
3101				<4 RK_PA6 10 &pcfg_pull_up>,
3102				/* uart3_tx_m2 */
3103				<4 RK_PA5 10 &pcfg_pull_up>;
3104		};
3105
3106		/omit-if-no-ref/
3107		uart3_ctsn: uart3-ctsn {
3108			rockchip,pins =
3109				/* uart3_ctsn */
3110				<1 RK_PC3 10 &pcfg_pull_none>;
3111		};
3112
3113		/omit-if-no-ref/
3114		uart3_rtsn: uart3-rtsn {
3115			rockchip,pins =
3116				/* uart3_rtsn */
3117				<1 RK_PC2 10 &pcfg_pull_none>;
3118		};
3119	};
3120
3121	uart4 {
3122		/omit-if-no-ref/
3123		uart4m0_xfer: uart4m0-xfer {
3124			rockchip,pins =
3125				/* uart4_rx_m0 */
3126				<1 RK_PD3 10 &pcfg_pull_up>,
3127				/* uart4_tx_m0 */
3128				<1 RK_PD2 10 &pcfg_pull_up>;
3129		};
3130
3131		/omit-if-no-ref/
3132		uart4m1_xfer: uart4m1-xfer {
3133			rockchip,pins =
3134				/* uart4_rx_m1 */
3135				<3 RK_PD0 10 &pcfg_pull_up>,
3136				/* uart4_tx_m1 */
3137				<3 RK_PD1 10 &pcfg_pull_up>;
3138		};
3139
3140		/omit-if-no-ref/
3141		uart4m2_xfer: uart4m2-xfer {
3142			rockchip,pins =
3143				/* uart4_rx_m2 */
3144				<1 RK_PB2 10 &pcfg_pull_up>,
3145				/* uart4_tx_m2 */
3146				<1 RK_PB3 10 &pcfg_pull_up>;
3147		};
3148
3149		/omit-if-no-ref/
3150		uart4_ctsn: uart4-ctsn {
3151			rockchip,pins =
3152				/* uart4_ctsn */
3153				<1 RK_PC7 10 &pcfg_pull_none>;
3154		};
3155
3156		/omit-if-no-ref/
3157		uart4_rtsn: uart4-rtsn {
3158			rockchip,pins =
3159				/* uart4_rtsn */
3160				<1 RK_PC5 10 &pcfg_pull_none>;
3161		};
3162	};
3163
3164	uart5 {
3165		/omit-if-no-ref/
3166		uart5m0_xfer: uart5m0-xfer {
3167			rockchip,pins =
3168				/* uart5_rx_m0 */
3169				<4 RK_PD4 10 &pcfg_pull_up>,
3170				/* uart5_tx_m0 */
3171				<4 RK_PD5 10 &pcfg_pull_up>;
3172		};
3173
3174		/omit-if-no-ref/
3175		uart5m0_ctsn: uart5m0-ctsn {
3176			rockchip,pins =
3177				/* uart5m0_ctsn */
3178				<4 RK_PD2 10 &pcfg_pull_none>;
3179		};
3180
3181		/omit-if-no-ref/
3182		uart5m0_rtsn: uart5m0-rtsn {
3183			rockchip,pins =
3184				/* uart5m0_rtsn */
3185				<4 RK_PD3 10 &pcfg_pull_none>;
3186		};
3187
3188		/omit-if-no-ref/
3189		uart5m1_xfer: uart5m1-xfer {
3190			rockchip,pins =
3191				/* uart5_rx_m1 */
3192				<3 RK_PC5 10 &pcfg_pull_up>,
3193				/* uart5_tx_m1 */
3194				<3 RK_PC4 10 &pcfg_pull_up>;
3195		};
3196
3197		/omit-if-no-ref/
3198		uart5m1_ctsn: uart5m1-ctsn {
3199			rockchip,pins =
3200				/* uart5m1_ctsn */
3201				<2 RK_PA2 10 &pcfg_pull_none>;
3202		};
3203
3204		/omit-if-no-ref/
3205		uart5m1_rtsn: uart5m1-rtsn {
3206			rockchip,pins =
3207				/* uart5m1_rtsn */
3208				<2 RK_PA3 10 &pcfg_pull_none>;
3209		};
3210
3211		/omit-if-no-ref/
3212		uart5m2_xfer: uart5m2-xfer {
3213			rockchip,pins =
3214				/* uart5_rx_m2 */
3215				<2 RK_PD4 10 &pcfg_pull_up>,
3216				/* uart5_tx_m2 */
3217				<2 RK_PD5 10 &pcfg_pull_up>;
3218		};
3219	};
3220
3221	uart6 {
3222		/omit-if-no-ref/
3223		uart6m1_xfer: uart6m1-xfer {
3224			rockchip,pins =
3225				/* uart6_rx_m1 */
3226				<1 RK_PA0 10 &pcfg_pull_up>,
3227				/* uart6_tx_m1 */
3228				<1 RK_PA1 10 &pcfg_pull_up>;
3229		};
3230
3231		/omit-if-no-ref/
3232		uart6m1_ctsn: uart6m1-ctsn {
3233			rockchip,pins =
3234				/* uart6m1_ctsn */
3235				<1 RK_PA3 10 &pcfg_pull_none>;
3236		};
3237
3238		/omit-if-no-ref/
3239		uart6m1_rtsn: uart6m1-rtsn {
3240			rockchip,pins =
3241				/* uart6m1_rtsn */
3242				<1 RK_PA2 10 &pcfg_pull_none>;
3243		};
3244
3245		/omit-if-no-ref/
3246		uart6m2_xfer: uart6m2-xfer {
3247			rockchip,pins =
3248				/* uart6_rx_m2 */
3249				<1 RK_PD1 10 &pcfg_pull_up>,
3250				/* uart6_tx_m2 */
3251				<1 RK_PD0 10 &pcfg_pull_up>;
3252		};
3253	};
3254
3255	uart7 {
3256		/omit-if-no-ref/
3257		uart7m1_xfer: uart7m1-xfer {
3258			rockchip,pins =
3259				/* uart7_rx_m1 */
3260				<3 RK_PC1 10 &pcfg_pull_up>,
3261				/* uart7_tx_m1 */
3262				<3 RK_PC0 10 &pcfg_pull_up>;
3263		};
3264
3265		/omit-if-no-ref/
3266		uart7m1_ctsn: uart7m1-ctsn {
3267			rockchip,pins =
3268				/* uart7m1_ctsn */
3269				<3 RK_PC3 10 &pcfg_pull_none>;
3270		};
3271
3272		/omit-if-no-ref/
3273		uart7m1_rtsn: uart7m1-rtsn {
3274			rockchip,pins =
3275				/* uart7m1_rtsn */
3276				<3 RK_PC2 10 &pcfg_pull_none>;
3277		};
3278
3279		/omit-if-no-ref/
3280		uart7m2_xfer: uart7m2-xfer {
3281			rockchip,pins =
3282				/* uart7_rx_m2 */
3283				<1 RK_PB4 10 &pcfg_pull_up>,
3284				/* uart7_tx_m2 */
3285				<1 RK_PB5 10 &pcfg_pull_up>;
3286		};
3287	};
3288
3289	uart8 {
3290		/omit-if-no-ref/
3291		uart8m0_xfer: uart8m0-xfer {
3292			rockchip,pins =
3293				/* uart8_rx_m0 */
3294				<4 RK_PB1 10 &pcfg_pull_up>,
3295				/* uart8_tx_m0 */
3296				<4 RK_PB0 10 &pcfg_pull_up>;
3297		};
3298
3299		/omit-if-no-ref/
3300		uart8m0_ctsn: uart8m0-ctsn {
3301			rockchip,pins =
3302				/* uart8m0_ctsn */
3303				<4 RK_PB3 10 &pcfg_pull_none>;
3304		};
3305
3306		/omit-if-no-ref/
3307		uart8m0_rtsn: uart8m0-rtsn {
3308			rockchip,pins =
3309				/* uart8m0_rtsn */
3310				<4 RK_PB2 10 &pcfg_pull_none>;
3311		};
3312
3313		/omit-if-no-ref/
3314		uart8m1_xfer: uart8m1-xfer {
3315			rockchip,pins =
3316				/* uart8_rx_m1 */
3317				<3 RK_PA3 10 &pcfg_pull_up>,
3318				/* uart8_tx_m1 */
3319				<3 RK_PA2 10 &pcfg_pull_up>;
3320		};
3321
3322		/omit-if-no-ref/
3323		uart8m1_ctsn: uart8m1-ctsn {
3324			rockchip,pins =
3325				/* uart8m1_ctsn */
3326				<3 RK_PA5 10 &pcfg_pull_none>;
3327		};
3328
3329		/omit-if-no-ref/
3330		uart8m1_rtsn: uart8m1-rtsn {
3331			rockchip,pins =
3332				/* uart8m1_rtsn */
3333				<3 RK_PA4 10 &pcfg_pull_none>;
3334		};
3335
3336		/omit-if-no-ref/
3337		uart8_xfer: uart8-xfer {
3338			rockchip,pins =
3339				/* uart8_rx_ */
3340				<4 RK_PB1 10 &pcfg_pull_up>;
3341		};
3342	};
3343
3344	uart9 {
3345		/omit-if-no-ref/
3346		uart9m0_xfer: uart9m0-xfer {
3347			rockchip,pins =
3348				/* uart9_rx_m0 */
3349				<2 RK_PC4 10 &pcfg_pull_up>,
3350				/* uart9_tx_m0 */
3351				<2 RK_PC2 10 &pcfg_pull_up>;
3352		};
3353
3354		/omit-if-no-ref/
3355		uart9m1_xfer: uart9m1-xfer {
3356			rockchip,pins =
3357				/* uart9_rx_m1 */
3358				<4 RK_PB5 10 &pcfg_pull_up>,
3359				/* uart9_tx_m1 */
3360				<4 RK_PB4 10 &pcfg_pull_up>;
3361		};
3362
3363		/omit-if-no-ref/
3364		uart9m1_ctsn: uart9m1-ctsn {
3365			rockchip,pins =
3366				/* uart9m1_ctsn */
3367				<4 RK_PA1 10 &pcfg_pull_none>;
3368		};
3369
3370		/omit-if-no-ref/
3371		uart9m1_rtsn: uart9m1-rtsn {
3372			rockchip,pins =
3373				/* uart9m1_rtsn */
3374				<4 RK_PA0 10 &pcfg_pull_none>;
3375		};
3376
3377		/omit-if-no-ref/
3378		uart9m2_xfer: uart9m2-xfer {
3379			rockchip,pins =
3380				/* uart9_rx_m2 */
3381				<3 RK_PD4 10 &pcfg_pull_up>,
3382				/* uart9_tx_m2 */
3383				<3 RK_PD5 10 &pcfg_pull_up>;
3384		};
3385
3386		/omit-if-no-ref/
3387		uart9m2_ctsn: uart9m2-ctsn {
3388			rockchip,pins =
3389				/* uart9m2_ctsn */
3390				<3 RK_PD3 10 &pcfg_pull_none>;
3391		};
3392
3393		/omit-if-no-ref/
3394		uart9m2_rtsn: uart9m2-rtsn {
3395			rockchip,pins =
3396				/* uart9m2_rtsn */
3397				<3 RK_PD2 10 &pcfg_pull_none>;
3398		};
3399	};
3400
3401	vop {
3402		/omit-if-no-ref/
3403		vop_pins: vop-pins {
3404			rockchip,pins =
3405				/* vop_post_empty */
3406				<1 RK_PA2 1 &pcfg_pull_none>;
3407		};
3408	};
3409};
3410
3411/*
3412 * This part is edited handly.
3413 */
3414&pinctrl {
3415	bt656 {
3416		/omit-if-no-ref/
3417		bt656_pins: bt656-pins {
3418			rockchip,pins =
3419				/* bt1120_clkout */
3420				<4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
3421				/* bt1120_d0 */
3422				<4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
3423				/* bt1120_d1 */
3424				<4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
3425				/* bt1120_d2 */
3426				<4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
3427				/* bt1120_d3 */
3428				<4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
3429				/* bt1120_d4 */
3430				<4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
3431				/* bt1120_d5 */
3432				<4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
3433				/* bt1120_d6 */
3434				<4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
3435				/* bt1120_d7 */
3436				<4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
3437		};
3438	};
3439
3440	gpio-func {
3441		/omit-if-no-ref/
3442		tsadc_gpio_func: tsadc-gpio-func {
3443			rockchip,pins =
3444				<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
3445		};
3446	};
3447};
3448