1/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2/* 3 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H 7#define _DT_BINDINGS_CLK_QCOM_GCC_QDU1000_H 8 9/* GCC clocks */ 10#define GCC_GPLL0 0 11#define GCC_GPLL0_OUT_EVEN 1 12#define GCC_GPLL1 2 13#define GCC_GPLL2 3 14#define GCC_GPLL2_OUT_EVEN 4 15#define GCC_GPLL3 5 16#define GCC_GPLL4 6 17#define GCC_GPLL5 7 18#define GCC_GPLL5_OUT_EVEN 8 19#define GCC_GPLL6 9 20#define GCC_GPLL7 10 21#define GCC_GPLL8 11 22#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12 23#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13 24#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14 25#define GCC_BOOT_ROM_AHB_CLK 15 26#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16 27#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 28#define GCC_DDRSS_ECPRI_DMA_CLK 18 29#define GCC_ECPRI_AHB_CLK 19 30#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20 31#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21 32#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22 33#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23 34#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24 35#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25 36#define GCC_ECPRI_XO_CLK 26 37#define GCC_ETH_DBG_SNOC_AXI_CLK 27 38#define GCC_GEMNOC_PCIE_QX_CLK 28 39#define GCC_GP1_CLK 29 40#define GCC_GP1_CLK_SRC 30 41#define GCC_GP2_CLK 31 42#define GCC_GP2_CLK_SRC 32 43#define GCC_GP3_CLK 33 44#define GCC_GP3_CLK_SRC 34 45#define GCC_PCIE_0_AUX_CLK 35 46#define GCC_PCIE_0_AUX_CLK_SRC 36 47#define GCC_PCIE_0_CFG_AHB_CLK 37 48#define GCC_PCIE_0_CLKREF_EN 38 49#define GCC_PCIE_0_MSTR_AXI_CLK 39 50#define GCC_PCIE_0_PHY_AUX_CLK 40 51#define GCC_PCIE_0_PHY_RCHNG_CLK 41 52#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 53#define GCC_PCIE_0_PIPE_CLK 43 54#define GCC_PCIE_0_SLV_AXI_CLK 44 55#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 56#define GCC_PDM2_CLK 46 57#define GCC_PDM2_CLK_SRC 47 58#define GCC_PDM_AHB_CLK 48 59#define GCC_PDM_XO4_CLK 49 60#define GCC_QMIP_ANOC_PCIE_CLK 50 61#define GCC_QMIP_ECPRI_DMA0_CLK 51 62#define GCC_QMIP_ECPRI_DMA1_CLK 52 63#define GCC_QMIP_ECPRI_GSI_CLK 53 64#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54 65#define GCC_QUPV3_WRAP0_CORE_CLK 55 66#define GCC_QUPV3_WRAP0_S0_CLK 56 67#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57 68#define GCC_QUPV3_WRAP0_S1_CLK 58 69#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59 70#define GCC_QUPV3_WRAP0_S2_CLK 60 71#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61 72#define GCC_QUPV3_WRAP0_S3_CLK 62 73#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63 74#define GCC_QUPV3_WRAP0_S4_CLK 64 75#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65 76#define GCC_QUPV3_WRAP0_S5_CLK 66 77#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67 78#define GCC_QUPV3_WRAP0_S6_CLK 68 79#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69 80#define GCC_QUPV3_WRAP0_S7_CLK 70 81#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71 82#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72 83#define GCC_QUPV3_WRAP1_CORE_CLK 73 84#define GCC_QUPV3_WRAP1_S0_CLK 74 85#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75 86#define GCC_QUPV3_WRAP1_S1_CLK 76 87#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77 88#define GCC_QUPV3_WRAP1_S2_CLK 78 89#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79 90#define GCC_QUPV3_WRAP1_S3_CLK 80 91#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81 92#define GCC_QUPV3_WRAP1_S4_CLK 82 93#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83 94#define GCC_QUPV3_WRAP1_S5_CLK 84 95#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85 96#define GCC_QUPV3_WRAP1_S6_CLK 86 97#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87 98#define GCC_QUPV3_WRAP1_S7_CLK 88 99#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89 100#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90 101#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91 102#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92 103#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93 104#define GCC_SDCC5_AHB_CLK 94 105#define GCC_SDCC5_APPS_CLK 95 106#define GCC_SDCC5_APPS_CLK_SRC 96 107#define GCC_SDCC5_ICE_CORE_CLK 97 108#define GCC_SDCC5_ICE_CORE_CLK_SRC 98 109#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99 110#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100 111#define GCC_SNOC_CNOC_PCIE_QX_CLK 101 112#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102 113#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103 114#define GCC_TSC_CFG_AHB_CLK 104 115#define GCC_TSC_CLK_SRC 105 116#define GCC_TSC_CNTR_CLK 106 117#define GCC_TSC_ETU_CLK 107 118#define GCC_USB2_CLKREF_EN 108 119#define GCC_USB30_PRIM_MASTER_CLK 109 120#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 121#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 122#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 123#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113 124#define GCC_USB30_PRIM_SLEEP_CLK 114 125#define GCC_USB3_PRIM_PHY_AUX_CLK 115 126#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 127#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 128#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 129#define GCC_SM_BUS_AHB_CLK 119 130#define GCC_SM_BUS_XO_CLK 120 131#define GCC_SM_BUS_XO_CLK_SRC 121 132#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122 133#define GCC_ETH_100G_C2C_HM_APB_CLK 123 134#define GCC_ETH_100G_FH_HM_APB_0_CLK 124 135#define GCC_ETH_100G_FH_HM_APB_1_CLK 125 136#define GCC_ETH_100G_FH_HM_APB_2_CLK 126 137#define GCC_ETH_DBG_C2C_HM_APB_CLK 127 138#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 139#define GCC_PCIE_0_PIPE_CLK_SRC 129 140#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 141#define GCC_GPLL1_OUT_EVEN 131 142#define GCC_DDRSS_ECPRI_GSI_CLK 132 143 144/* GCC resets */ 145#define GCC_ECPRI_CC_BCR 0 146#define GCC_ECPRI_SS_BCR 1 147#define GCC_ETH_WRAPPER_BCR 2 148#define GCC_PCIE_0_BCR 3 149#define GCC_PCIE_0_LINK_DOWN_BCR 4 150#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 151#define GCC_PCIE_0_PHY_BCR 6 152#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 153#define GCC_PCIE_PHY_CFG_AHB_BCR 8 154#define GCC_PCIE_PHY_COM_BCR 9 155#define GCC_PDM_BCR 10 156#define GCC_QUPV3_WRAPPER_0_BCR 11 157#define GCC_QUPV3_WRAPPER_1_BCR 12 158#define GCC_QUSB2PHY_PRIM_BCR 13 159#define GCC_QUSB2PHY_SEC_BCR 14 160#define GCC_SDCC5_BCR 15 161#define GCC_TCSR_PCIE_BCR 16 162#define GCC_TSC_BCR 17 163#define GCC_USB30_PRIM_BCR 18 164#define GCC_USB3_DP_PHY_PRIM_BCR 19 165#define GCC_USB3_DP_PHY_SEC_BCR 20 166#define GCC_USB3_PHY_PRIM_BCR 21 167#define GCC_USB3_PHY_SEC_BCR 22 168#define GCC_USB3PHY_PHY_PRIM_BCR 23 169#define GCC_USB3PHY_PHY_SEC_BCR 24 170#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25 171 172/* GCC power domains */ 173#define PCIE_0_GDSC 0 174#define PCIE_0_PHY_GDSC 1 175#define USB30_PRIM_GDSC 2 176 177#endif 178