1275970Scy/* SPDX-License-Identifier: GPL-2.0 */ 2275970Scy/* 3275970Scy * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4275970Scy */ 5275970Scy 6275970Scy#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H 7275970Scy#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H 8275970Scy 9275970Scy/* DISP_CC clock registers */ 10275970Scy#define DISP_CC_MDSS_AHB_CLK 0 11275970Scy#define DISP_CC_MDSS_AHB_CLK_SRC 1 12275970Scy#define DISP_CC_MDSS_BYTE0_CLK 2 13275970Scy#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 14275970Scy#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 15275970Scy#define DISP_CC_MDSS_BYTE0_INTF_CLK 5 16275970Scy#define DISP_CC_MDSS_BYTE1_CLK 6 17275970Scy#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 18275970Scy#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 19275970Scy#define DISP_CC_MDSS_BYTE1_INTF_CLK 9 20275970Scy#define DISP_CC_MDSS_DP_AUX1_CLK 10 21275970Scy#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 22275970Scy#define DISP_CC_MDSS_DP_AUX_CLK 12 23275970Scy#define DISP_CC_MDSS_DP_AUX_CLK_SRC 13 24275970Scy#define DISP_CC_MDSS_DP_LINK1_CLK 14 25275970Scy#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 26275970Scy#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 27275970Scy#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 28275970Scy#define DISP_CC_MDSS_DP_LINK_CLK 18 29275970Scy#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 30275970Scy#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 31275970Scy#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 32275970Scy#define DISP_CC_MDSS_DP_PIXEL1_CLK 22 33275970Scy#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 34275970Scy#define DISP_CC_MDSS_DP_PIXEL2_CLK 24 35275970Scy#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 36275970Scy#define DISP_CC_MDSS_DP_PIXEL_CLK 26 37275970Scy#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 38275970Scy#define DISP_CC_MDSS_ESC0_CLK 28 39275970Scy#define DISP_CC_MDSS_ESC0_CLK_SRC 29 40275970Scy#define DISP_CC_MDSS_ESC1_CLK 30 41275970Scy#define DISP_CC_MDSS_ESC1_CLK_SRC 31 42275970Scy#define DISP_CC_MDSS_MDP_CLK 32 43275970Scy#define DISP_CC_MDSS_MDP_CLK_SRC 33 44275970Scy#define DISP_CC_MDSS_MDP_LUT_CLK 34 45275970Scy#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35 46275970Scy#define DISP_CC_MDSS_PCLK0_CLK 36 47275970Scy#define DISP_CC_MDSS_PCLK0_CLK_SRC 37 48275970Scy#define DISP_CC_MDSS_PCLK1_CLK 38 49275970Scy#define DISP_CC_MDSS_PCLK1_CLK_SRC 39 50275970Scy#define DISP_CC_MDSS_ROT_CLK 40 51275970Scy#define DISP_CC_MDSS_ROT_CLK_SRC 41 52275970Scy#define DISP_CC_MDSS_RSCC_AHB_CLK 42 53275970Scy#define DISP_CC_MDSS_RSCC_VSYNC_CLK 43 54275970Scy#define DISP_CC_MDSS_VSYNC_CLK 44 55275970Scy#define DISP_CC_MDSS_VSYNC_CLK_SRC 45 56275970Scy#define DISP_CC_PLL0 46 57275970Scy#define DISP_CC_PLL1 47 58275970Scy#define DISP_CC_MDSS_EDP_AUX_CLK 48 59275970Scy#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 49 60275970Scy#define DISP_CC_MDSS_EDP_GTC_CLK 50 61275970Scy#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 51 62275970Scy#define DISP_CC_MDSS_EDP_LINK_CLK 52 63275970Scy#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 53 64275970Scy#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54 65275970Scy#define DISP_CC_MDSS_EDP_PIXEL_CLK 55 66275970Scy#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56 67275970Scy#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 57 68275970Scy 69275970Scy/* DISP_CC Reset */ 70275970Scy#define DISP_CC_MDSS_CORE_BCR 0 71275970Scy#define DISP_CC_MDSS_RSCC_BCR 1 72275970Scy 73275970Scy/* DISP_CC GDSCR */ 74275970Scy#define MDSS_GDSC 0 75275970Scy 76275970Scy#endif 77275970Scy