1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5#ifndef __RTW89_REG_H__ 6#define __RTW89_REG_H__ 7 8#define R_AX_SYS_WL_EFUSE_CTRL 0x000A 9#define B_AX_AUTOLOAD_SUS BIT(5) 10 11#define R_AX_SYS_ISO_CTRL 0x0000 12#define B_AX_PWC_EV2EF_MASK GENMASK(15, 14) 13#define B_AX_PWC_EV2EF_B15 BIT(15) 14#define B_AX_PWC_EV2EF_B14 BIT(14) 15#define B_AX_ISO_EB2CORE BIT(8) 16 17#define R_AX_SYS_FUNC_EN 0x0002 18#define B_AX_FEN_BB_GLB_RSTN BIT(1) 19#define B_AX_FEN_BBRSTB BIT(0) 20 21#define R_AX_SYS_PW_CTRL 0x0004 22#define B_AX_SOP_ASWRM BIT(31) 23#define B_AX_SOP_PWMM_DSWR BIT(29) 24#define B_AX_XTAL_OFF_A_DIE BIT(22) 25#define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18) 26#define B_AX_RDY_SYSPWR BIT(17) 27#define B_AX_EN_WLON BIT(16) 28#define B_AX_APDM_HPDN BIT(15) 29#define B_AX_PSUS_OFF_CAPC_EN BIT(14) 30#define B_AX_AFSM_PCIE_SUS_EN BIT(12) 31#define B_AX_AFSM_WLSUS_EN BIT(11) 32#define B_AX_APFM_SWLPS BIT(10) 33#define B_AX_APFM_OFFMAC BIT(9) 34#define B_AX_APFN_ONMAC BIT(8) 35 36#define R_AX_SYS_CLK_CTRL 0x0008 37#define B_AX_CPU_CLK_EN BIT(14) 38 39#define R_AX_SYS_SWR_CTRL1 0x0010 40#define B_AX_SYM_CTRL_SPS_PWMFREQ BIT(10) 41 42#define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018 43#define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6) 44#define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5) 45 46#define R_AX_RSV_CTRL 0x001C 47#define B_AX_R_DIS_PRST BIT(6) 48#define B_AX_WLOCK_1C_BIT6 BIT(5) 49 50#define R_AX_AFE_LDO_CTRL 0x0020 51#define B_AX_AON_OFF_PC_EN BIT(23) 52 53#define R_AX_EFUSE_CTRL_1 0x0038 54#define B_AX_EF_PGPD_MASK GENMASK(30, 28) 55#define B_AX_EF_RDT BIT(27) 56#define B_AX_EF_VDDQST_MASK GENMASK(26, 24) 57#define B_AX_EF_PGTS_MASK GENMASK(23, 20) 58#define B_AX_EF_PD_DIS BIT(11) 59#define B_AX_EF_POR BIT(10) 60#define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8) 61 62#define R_AX_EFUSE_CTRL 0x0030 63#define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30) 64#define B_AX_EF_RDY BIT(29) 65#define B_AX_EF_COMP_RESULT BIT(28) 66#define B_AX_EF_ADDR_MASK GENMASK(26, 16) 67#define B_AX_EF_DATA_MASK GENMASK(15, 0) 68 69#define R_AX_EFUSE_CTRL_1_V1 0x0038 70#define B_AX_EF_ENT BIT(31) 71#define B_AX_EF_BURST BIT(19) 72#define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16) 73#define B_AX_EF_TROW_EN BIT(15) 74#define B_AX_EF_ERR_FLAG BIT(14) 75#define B_AX_EF_DSB_EN BIT(11) 76#define B_AX_PCIE_CALIB_EN_V1 BIT(12) 77#define B_AX_WDT_WAKE_PCIE_EN BIT(10) 78#define B_AX_WDT_WAKE_USB_EN BIT(9) 79 80#define R_AX_GPIO_MUXCFG 0x0040 81#define B_AX_BOOT_MODE BIT(19) 82#define B_AX_WL_EECS_EXT_32K_SEL BIT(18) 83#define B_AX_WL_SEC_BONDING_OPT_STS BIT(17) 84#define B_AX_SECSIC_SEL BIT(16) 85#define B_AX_ENHTP BIT(14) 86#define B_AX_BT_AOD_GPIO3 BIT(13) 87#define B_AX_ENSIC BIT(12) 88#define B_AX_SIC_SWRST BIT(11) 89#define B_AX_PO_WIFI_PTA_PINS BIT(10) 90#define B_AX_PO_BT_PTA_PINS BIT(9) 91#define B_AX_ENUARTTX BIT(8) 92#define B_AX_BTMODE_MASK GENMASK(7, 6) 93#define MAC_AX_BT_MODE_0_3 0 94#define MAC_AX_BT_MODE_2 2 95#define MAC_AX_RTK_MODE 0 96#define MAC_AX_CSR_MODE 1 97#define B_AX_ENBT BIT(5) 98#define B_AX_EROM_EN BIT(4) 99#define B_AX_ENUARTRX BIT(2) 100#define B_AX_GPIOSEL_MASK GENMASK(1, 0) 101 102#define R_AX_DBG_CTRL 0x0058 103#define B_AX_DBG_SEL1_4BIT GENMASK(31, 30) 104#define B_AX_DBG_SEL1_16BIT BIT(27) 105#define B_AX_DBG_SEL1 GENMASK(23, 16) 106#define B_AX_DBG_SEL0_4BIT GENMASK(15, 14) 107#define B_AX_DBG_SEL0_16BIT BIT(11) 108#define B_AX_DBG_SEL0 GENMASK(7, 0) 109 110#define R_AX_SYS_SDIO_CTRL 0x0070 111#define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15) 112#define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14) 113#define B_AX_PCIE_FORCE_PWR_NGAT BIT(13) 114#define B_AX_PCIE_CALIB_EN_V1 BIT(12) 115#define B_AX_PCIE_AUXCLK_GATE BIT(11) 116#define B_AX_LTE_MUX_CTRL_PATH BIT(26) 117 118#define R_AX_HCI_OPT_CTRL 0x0074 119#define BIT_WAKE_CTRL BIT(5) 120 121#define R_AX_HCI_BG_CTRL 0x0078 122#define B_AX_IBX_EN_VALUE BIT(15) 123#define B_AX_IB_EN_VALUE BIT(14) 124#define B_AX_FORCED_IB_EN BIT(4) 125#define B_AX_EN_REGBG BIT(3) 126#define B_AX_R_AX_BG_LPF BIT(2) 127#define B_AX_R_AX_BG GENMASK(1, 0) 128 129#define R_AX_HCI_LDO_CTRL 0x007A 130#define B_AX_R_AX_VADJ_MASK GENMASK(3, 0) 131 132#define R_AX_PLATFORM_ENABLE 0x0088 133#define B_AX_AXIDMA_EN BIT(3) 134#define B_AX_APB_WRAP_EN BIT(2) 135#define B_AX_WCPU_EN BIT(1) 136#define B_AX_PLATFORM_EN BIT(0) 137 138#define R_AX_WLLPS_CTRL 0x0090 139#define B_AX_LPSOP_ASWRM BIT(17) 140#define B_AX_LPSOP_DSWRM BIT(9) 141#define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1) 142#define SW_LPS_OPTION 0x0001A0B2 143 144#define R_AX_SCOREBOARD 0x00AC 145#define B_AX_TOGGLE BIT(31) 146#define B_MAC_AX_SB_FW_MASK GENMASK(30, 24) 147#define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0) 148#define B_MAC_AX_BTGS1_NOTIFY BIT(0) 149#define MAC_AX_NOTIFY_TP_MAJOR 0x81 150#define MAC_AX_NOTIFY_PWR_MAJOR 0x80 151 152#define R_AX_DBG_PORT_SEL 0x00C0 153#define B_AX_DEBUG_ST_MASK GENMASK(31, 0) 154 155#define R_AX_PMC_DBG_CTRL2 0x00CC 156#define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2) 157 158#define R_AX_PCIE_MIO_INTF 0x00E4 159#define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16) 160#define B_AX_PCIE_MIO_BYIOREG BIT(13) 161#define B_AX_PCIE_MIO_RE BIT(12) 162#define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8) 163#define MIO_WRITE_BYTE_ALL 0xF 164#define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0) 165#define MIO_ADDR_PAGE_MASK GENMASK(12, 8) 166 167#define R_AX_PCIE_MIO_INTD 0x00E8 168#define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0) 169 170#define R_AX_SYS_CFG1 0x00F0 171#define B_AX_CHIP_VER_MASK GENMASK(15, 12) 172 173#define R_AX_SYS_STATUS1 0x00F4 174#define B_AX_SEL_0XC0_MASK GENMASK(17, 16) 175#define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3) 176#define MAC_AX_HCI_SEL_SDIO_UART 0 177#define MAC_AX_HCI_SEL_MULTI_USB 1 178#define MAC_AX_HCI_SEL_PCIE_UART 2 179#define MAC_AX_HCI_SEL_PCIE_USB 3 180#define MAC_AX_HCI_SEL_MULTI_SDIO 4 181 182#define R_AX_HALT_H2C_CTRL 0x0160 183#define R_AX_HALT_H2C 0x0168 184#define B_AX_HALT_H2C_TRIGGER BIT(0) 185#define R_AX_HALT_C2H_CTRL 0x0164 186#define R_AX_HALT_C2H 0x016C 187 188#define R_AX_WCPU_FW_CTRL 0x01E0 189#define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5) 190#define B_AX_FWDL_PATH_RDY BIT(2) 191#define B_AX_H2C_PATH_RDY BIT(1) 192#define B_AX_WCPU_FWDL_EN BIT(0) 193 194#define R_AX_RPWM 0x01E4 195#define R_AX_PCIE_HRPWM 0x10C0 196#define PS_RPWM_TOGGLE BIT(15) 197#define PS_RPWM_ACK BIT(14) 198#define PS_RPWM_SEQ_NUM GENMASK(13, 12) 199#define PS_RPWM_NOTIFY_WAKE BIT(8) 200#define PS_RPWM_STATE 0x7 201#define RPWM_SEQ_NUM_MAX 3 202#define PS_CPWM_SEQ_NUM GENMASK(13, 12) 203#define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8) 204#define PS_CPWM_STATE GENMASK(2, 0) 205#define CPWM_SEQ_NUM_MAX 3 206 207#define R_AX_BOOT_REASON 0x01E6 208#define B_AX_BOOT_REASON_MASK GENMASK(2, 0) 209 210#define R_AX_LDM 0x01E8 211#define B_AX_EN_32K BIT(31) 212 213#define R_AX_UDM0 0x01F0 214#define R_AX_UDM1 0x01F4 215#define B_AX_UDM1_MASK GENMASK(31, 16) 216#define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12) 217#define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8) 218#define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4) 219#define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0) 220#define R_AX_UDM2 0x01F8 221#define R_AX_UDM3 0x01FC 222 223#define R_AX_SPS_DIG_ON_CTRL0 0x0200 224#define B_AX_VREFPFM_L_MASK GENMASK(25, 22) 225#define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17) 226#define B_AX_OCP_L1_MASK GENMASK(15, 13) 227#define B_AX_VOL_L1_MASK GENMASK(3, 0) 228 229#define R_AX_SPSLDO_ON_CTRL1 0x0204 230#define B_AX_FPWMDELAY BIT(3) 231 232#define R_AX_LDO_AON_CTRL0 0x0218 233#define B_AX_PD_REGU_L BIT(16) 234 235#define R_AX_SPSANA_ON_CTRL1 0x0224 236 237#define R_AX_WLAN_XTAL_SI_CTRL 0x0270 238#define B_AX_WL_XTAL_SI_CMD_POLL BIT(31) 239#define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30) 240#define B_AX_WL_XTAL_GNT BIT(29) 241#define B_AX_BT_XTAL_GNT BIT(28) 242#define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24) 243#define XTAL_SI_NORMAL_WRITE 0x00 244#define XTAL_SI_NORMAL_READ 0x01 245#define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16) 246#define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8) 247#define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0) 248 249#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274 250#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0) 251 252#define R_AX_XTAL_ON_CTRL0 0x0280 253#define B_AX_XTAL_SC_LPS BIT(31) 254#define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17) 255#define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10) 256#define B_AX_XTAL_SC_MASK GENMASK(6, 0) 257 258#define R_AX_XTAL_ON_CTRL3 0x028C 259#define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24) 260#define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16) 261#define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8) 262#define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0) 263 264#define R_AX_GPIO0_7_FUNC_SEL 0x02D0 265 266#define R_AX_EECS_EESK_FUNC_SEL 0x02D8 267#define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4) 268 269#define R_AX_GPIO16_23_FUNC_SEL 0x02D8 270#define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4) 271#define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0) 272 273#define R_AX_LED1_FUNC_SEL 0x02DC 274#define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24) 275#define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1 276 277#define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 278#define B_AX_LED1_PULL_LOW_EN BIT(18) 279#define B_AX_EESK_PULL_LOW_EN BIT(17) 280#define B_AX_EECS_PULL_LOW_EN BIT(16) 281 282#define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 283#define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19) 284#define B_AX_GPIO10_PULL_LOW_EN BIT(10) 285 286#define R_AX_WLRF_CTRL 0x02F0 287#define B_AX_AFC_AFEDIG BIT(17) 288#define B_AX_WLRF1_CTRL_7 BIT(15) 289#define B_AX_WLRF1_CTRL_1 BIT(9) 290#define B_AX_WLRF_CTRL_7 BIT(7) 291#define B_AX_WLRF_CTRL_1 BIT(1) 292 293#define R_AX_IC_PWR_STATE 0x03F0 294#define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16) 295#define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8) 296#define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6) 297#define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4) 298#define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2) 299#define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0) 300 301#define R_AX_SPS_DIG_OFF_CTRL0 0x0400 302#define B_AX_C3_L1_MASK GENMASK(5, 4) 303#define B_AX_C1_L1_MASK GENMASK(1, 0) 304 305#define R_AX_AFE_OFF_CTRL1 0x0444 306#define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24) 307#define B_AX_S1_LDO2PWRCUT_F BIT(23) 308#define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21) 309 310#define R_AX_SEC_CTRL 0x0C00 311#define B_AX_SEC_IDMEM_SIZE_CONFIG_MASK GENMASK(17, 16) 312 313#define R_AX_FILTER_MODEL_ADDR 0x0C04 314 315#define R_AX_HAXI_INIT_CFG1 0x1000 316#define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28) 317#define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24) 318#define B_AX_DMA_MODE_MASK GENMASK(19, 18) 319#define DMA_MOD_PCIE_1B 0x0 320#define DMA_MOD_PCIE_4B 0x1 321#define DMA_MOD_USB 0x2 322#define DMA_MOD_SDIO 0x3 323#define B_AX_STOP_AXI_MST BIT(17) 324#define B_AX_HAXI_RST_KEEP_REG BIT(16) 325#define B_AX_RXHCI_EN_V1 BIT(15) 326#define B_AX_RXBD_MODE_V1 BIT(14) 327#define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8) 328#define B_AX_TXHCI_EN_V1 BIT(7) 329#define B_AX_FLUSH_AXI_MST BIT(4) 330#define B_AX_RST_BDRAM BIT(3) 331#define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0) 332 333#define R_AX_HAXI_DMA_STOP1 0x1010 334#define B_AX_STOP_WPDMA BIT(19) 335#define B_AX_STOP_CH12 BIT(18) 336#define B_AX_STOP_CH9 BIT(17) 337#define B_AX_STOP_CH8 BIT(16) 338#define B_AX_STOP_ACH7 BIT(15) 339#define B_AX_STOP_ACH6 BIT(14) 340#define B_AX_STOP_ACH5 BIT(13) 341#define B_AX_STOP_ACH4 BIT(12) 342#define B_AX_STOP_ACH3 BIT(11) 343#define B_AX_STOP_ACH2 BIT(10) 344#define B_AX_STOP_ACH1 BIT(9) 345#define B_AX_STOP_ACH0 BIT(8) 346 347#define R_AX_HAXI_DMA_BUSY1 0x101C 348#define B_AX_HAXIIO_BUSY BIT(20) 349#define B_AX_WPDMA_BUSY BIT(19) 350#define B_AX_CH12_BUSY BIT(18) 351#define B_AX_CH9_BUSY BIT(17) 352#define B_AX_CH8_BUSY BIT(16) 353#define B_AX_ACH7_BUSY BIT(15) 354#define B_AX_ACH6_BUSY BIT(14) 355#define B_AX_ACH5_BUSY BIT(13) 356#define B_AX_ACH4_BUSY BIT(12) 357#define B_AX_ACH3_BUSY BIT(11) 358#define B_AX_ACH2_BUSY BIT(10) 359#define B_AX_ACH1_BUSY BIT(9) 360#define B_AX_ACH0_BUSY BIT(8) 361 362#define R_AX_PCIE_DBG_CTRL 0x11C0 363#define B_AX_DBG_DUMMY_MASK GENMASK(23, 16) 364#define B_AX_PCIE_DBG_SEL_MASK GENMASK(15, 13) 365#define B_AX_MRD_TIMEOUT_EN BIT(10) 366#define B_AX_ASFF_FULL_NO_STK BIT(1) 367#define B_AX_EN_STUCK_DBG BIT(0) 368 369#define R_AX_HAXI_DMA_STOP2 0x11C0 370#define B_AX_STOP_CH11 BIT(1) 371#define B_AX_STOP_CH10 BIT(0) 372 373#define R_AX_HAXI_DMA_BUSY2 0x11C8 374#define B_AX_CH11_BUSY BIT(1) 375#define B_AX_CH10_BUSY BIT(0) 376 377#define R_AX_HAXI_DMA_BUSY3 0x1208 378#define B_AX_RPQ_BUSY BIT(1) 379#define B_AX_RXQ_BUSY BIT(0) 380 381#define R_AX_LTR_DEC_CTRL 0x1600 382#define B_AX_LTR_IDX_DRV_VLD BIT(16) 383#define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14) 384#define B_AX_LTR_IDX_FW_VLD BIT(13) 385#define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11) 386#define B_AX_LTR_IDX_HW_VLD BIT(10) 387#define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8) 388#define B_AX_LTR_REQ_DRV BIT(7) 389#define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5) 390#define PCIE_LTR_IDX_IDLE 3 391#define B_AX_LTR_DRV_DEC_EN BIT(4) 392#define B_AX_LTR_FW_DEC_EN BIT(3) 393#define B_AX_LTR_HW_DEC_EN BIT(2) 394#define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0) 395#define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN) 396 397#define R_AX_LTR_LATENCY_IDX0 0x1604 398#define R_AX_LTR_LATENCY_IDX1 0x1608 399#define R_AX_LTR_LATENCY_IDX2 0x160C 400#define R_AX_LTR_LATENCY_IDX3 0x1610 401 402#define R_AX_HCI_FC_CTRL_V1 0x1700 403#define R_AX_CH_PAGE_CTRL_V1 0x1704 404 405#define R_AX_ACH0_PAGE_CTRL_V1 0x1710 406#define R_AX_ACH1_PAGE_CTRL_V1 0x1714 407#define R_AX_ACH2_PAGE_CTRL_V1 0x1718 408#define R_AX_ACH3_PAGE_CTRL_V1 0x171C 409#define R_AX_ACH4_PAGE_CTRL_V1 0x1720 410#define R_AX_ACH5_PAGE_CTRL_V1 0x1724 411#define R_AX_ACH6_PAGE_CTRL_V1 0x1728 412#define R_AX_ACH7_PAGE_CTRL_V1 0x172C 413#define R_AX_CH8_PAGE_CTRL_V1 0x1730 414#define R_AX_CH9_PAGE_CTRL_V1 0x1734 415#define R_AX_CH10_PAGE_CTRL_V1 0x1738 416#define R_AX_CH11_PAGE_CTRL_V1 0x173C 417 418#define R_AX_ACH0_PAGE_INFO_V1 0x1750 419#define R_AX_ACH1_PAGE_INFO_V1 0x1754 420#define R_AX_ACH2_PAGE_INFO_V1 0x1758 421#define R_AX_ACH3_PAGE_INFO_V1 0x175C 422#define R_AX_ACH4_PAGE_INFO_V1 0x1760 423#define R_AX_ACH5_PAGE_INFO_V1 0x1764 424#define R_AX_ACH6_PAGE_INFO_V1 0x1768 425#define R_AX_ACH7_PAGE_INFO_V1 0x176C 426#define R_AX_CH8_PAGE_INFO_V1 0x1770 427#define R_AX_CH9_PAGE_INFO_V1 0x1774 428#define R_AX_CH10_PAGE_INFO_V1 0x1778 429#define R_AX_CH11_PAGE_INFO_V1 0x177C 430#define R_AX_CH12_PAGE_INFO_V1 0x1780 431 432#define R_AX_PUB_PAGE_INFO3_V1 0x178C 433#define R_AX_PUB_PAGE_CTRL1_V1 0x1790 434#define R_AX_PUB_PAGE_CTRL2_V1 0x1794 435#define R_AX_PUB_PAGE_INFO1_V1 0x1798 436#define R_AX_PUB_PAGE_INFO2_V1 0x179C 437#define R_AX_WP_PAGE_CTRL1_V1 0x17A0 438#define R_AX_WP_PAGE_CTRL2_V1 0x17A4 439#define R_AX_WP_PAGE_INFO1_V1 0x17A8 440 441#define R_AX_H2CREG_DATA0_V1 0x7140 442#define R_AX_H2CREG_DATA1_V1 0x7144 443#define R_AX_H2CREG_DATA2_V1 0x7148 444#define R_AX_H2CREG_DATA3_V1 0x714C 445#define R_AX_C2HREG_DATA0_V1 0x7150 446#define R_AX_C2HREG_DATA1_V1 0x7154 447#define R_AX_C2HREG_DATA2_V1 0x7158 448#define R_AX_C2HREG_DATA3_V1 0x715C 449#define R_AX_H2CREG_CTRL_V1 0x7160 450#define R_AX_C2HREG_CTRL_V1 0x7164 451 452#define R_AX_HCI_FUNC_EN_V1 0x7880 453 454#define R_AX_PHYREG_SET 0x8040 455#define PHYREG_SET_ALL_CYCLE 0x8 456#define PHYREG_SET_XYN_CYCLE 0xE 457 458#define R_AX_HD0IMR 0x8110 459#define B_AX_WDT_PTFM_INT_EN BIT(5) 460#define B_AX_CPWM_INT_EN BIT(2) 461#define B_AX_GT3_INT_EN BIT(1) 462#define B_AX_C2H_INT_EN BIT(0) 463#define R_AX_HD0ISR 0x8114 464#define B_AX_C2H_INT BIT(0) 465 466#define R_AX_H2CREG_DATA0 0x8140 467#define R_AX_H2CREG_DATA1 0x8144 468#define R_AX_H2CREG_DATA2 0x8148 469#define R_AX_H2CREG_DATA3 0x814C 470#define R_AX_C2HREG_DATA0 0x8150 471#define R_AX_C2HREG_DATA1 0x8154 472#define R_AX_C2HREG_DATA2 0x8158 473#define R_AX_C2HREG_DATA3 0x815C 474#define R_AX_H2CREG_CTRL 0x8160 475#define B_AX_H2CREG_TRIGGER BIT(0) 476#define R_AX_C2HREG_CTRL 0x8164 477#define B_AX_C2HREG_TRIGGER BIT(0) 478#define R_AX_CPWM 0x8170 479 480#define R_AX_HCI_FUNC_EN 0x8380 481#define B_AX_HCI_RXDMA_EN BIT(1) 482#define B_AX_HCI_TXDMA_EN BIT(0) 483 484#define R_AX_BOOT_DBG 0x83F0 485 486#define R_AX_DMAC_FUNC_EN 0x8400 487#define B_AX_DMAC_CRPRT BIT(31) 488#define B_AX_MAC_FUNC_EN BIT(30) 489#define B_AX_DMAC_FUNC_EN BIT(29) 490#define B_AX_MPDU_PROC_EN BIT(28) 491#define B_AX_WD_RLS_EN BIT(27) 492#define B_AX_DLE_WDE_EN BIT(26) 493#define B_AX_TXPKT_CTRL_EN BIT(25) 494#define B_AX_STA_SCH_EN BIT(24) 495#define B_AX_DLE_PLE_EN BIT(23) 496#define B_AX_PKT_BUF_EN BIT(22) 497#define B_AX_DMAC_TBL_EN BIT(21) 498#define B_AX_PKT_IN_EN BIT(20) 499#define B_AX_DLE_CPUIO_EN BIT(19) 500#define B_AX_DISPATCHER_EN BIT(18) 501#define B_AX_BBRPT_EN BIT(17) 502#define B_AX_MAC_SEC_EN BIT(16) 503#define B_AX_DMACREG_GCKEN BIT(15) 504#define B_AX_MAC_UN_EN BIT(15) 505#define B_AX_H_AXIDMA_EN BIT(14) 506 507#define R_AX_DMAC_CLK_EN 0x8404 508#define B_AX_WD_RLS_CLK_EN BIT(27) 509#define B_AX_DLE_WDE_CLK_EN BIT(26) 510#define B_AX_TXPKT_CTRL_CLK_EN BIT(25) 511#define B_AX_STA_SCH_CLK_EN BIT(24) 512#define B_AX_DLE_PLE_CLK_EN BIT(23) 513#define B_AX_PKT_IN_CLK_EN BIT(20) 514#define B_AX_DLE_CPUIO_CLK_EN BIT(19) 515#define B_AX_DISPATCHER_CLK_EN BIT(18) 516#define B_AX_BBRPT_CLK_EN BIT(17) 517#define B_AX_MAC_SEC_CLK_EN BIT(16) 518#define B_AX_AXIDMA_CLK_EN BIT(9) 519 520#define PCI_LTR_IDLE_TIMER_1US 0 521#define PCI_LTR_IDLE_TIMER_10US 1 522#define PCI_LTR_IDLE_TIMER_100US 2 523#define PCI_LTR_IDLE_TIMER_200US 3 524#define PCI_LTR_IDLE_TIMER_400US 4 525#define PCI_LTR_IDLE_TIMER_800US 5 526#define PCI_LTR_IDLE_TIMER_1_6MS 6 527#define PCI_LTR_IDLE_TIMER_3_2MS 7 528#define PCI_LTR_IDLE_TIMER_R_ERR 0xFD 529#define PCI_LTR_IDLE_TIMER_DEF 0xFE 530#define PCI_LTR_IDLE_TIMER_IGNORE 0xFF 531 532#define PCI_LTR_SPC_10US 0 533#define PCI_LTR_SPC_100US 1 534#define PCI_LTR_SPC_500US 2 535#define PCI_LTR_SPC_1MS 3 536#define PCI_LTR_SPC_R_ERR 0xFD 537#define PCI_LTR_SPC_DEF 0xFE 538#define PCI_LTR_SPC_IGNORE 0xFF 539 540#define R_AX_LTR_CTRL_0 0x8410 541#define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12) 542#define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) 543#define B_AX_LTR_WD_NOEMP_CHK BIT(6) 544#define B_AX_APP_LTR_ACT BIT(5) 545#define B_AX_APP_LTR_IDLE BIT(4) 546#define B_AX_LTR_EN BIT(1) 547#define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1) 548#define B_AX_LTR_HW_EN BIT(0) 549 550#define R_AX_LTR_CTRL_1 0x8414 551#define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16) 552#define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0) 553 554#define R_AX_LTR_IDLE_LATENCY 0x8418 555 556#define R_AX_LTR_ACTIVE_LATENCY 0x841C 557 558#define R_AX_SER_DBG_INFO 0x8424 559#define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28) 560 561#define R_AX_DLE_EMPTY0 0x8430 562#define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) 563#define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) 564#define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) 565#define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23) 566#define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) 567#define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) 568#define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) 569#define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) 570#define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) 571#define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) 572#define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16) 573#define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) 574#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) 575#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) 576#define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7) 577#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) 578#define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) 579#define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) 580#define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) 581#define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) 582 583#define R_AX_DLE_EMPTY1 0x8434 584#define B_AX_PLE_EMPTY_QTA_DMAC_WDRLS BIT(20) 585#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_BBRPT BIT(19) 586#define B_AX_PLE_EMPTY_QTA_CMAC1_DMA_RX BIT(18) 587#define B_AX_PLE_EMPTY_QTA_CMAC0_DMA_RX BIT(17) 588#define B_AX_PLE_EMPTY_QTA_DMAC_C2H BIT(16) 589#define B_AX_PLE_EMPTY_QUE_DMAC_PLRLS BIT(5) 590#define B_AX_PLE_EMPTY_QUE_DMAC_CPUIO BIT(4) 591#define B_AX_PLE_EMPTY_QUE_DMAC_SEC_RX BIT(3) 592#define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_RX BIT(2) 593#define B_AX_PLE_EMPTY_QUE_DMAC_HDP BIT(1) 594#define B_AX_WDE_EMPTY_QUE_DMAC_WDRLS BIT(0) 595 596#define R_AX_DMAC_ERR_IMR 0x8520 597#define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10) 598#define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9) 599#define B_AX_DISPATCH_ERR_INT_EN BIT(8) 600#define B_AX_PKTIN_ERR_INT_EN BIT(7) 601#define B_AX_PLE_DLE_ERR_INT_EN BIT(6) 602#define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5) 603#define B_AX_WDE_DLE_ERR_INT_EN BIT(4) 604#define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3) 605#define B_AX_MPDU_ERR_INT_EN BIT(2) 606#define B_AX_WSEC_ERR_INT_EN BIT(1) 607#define B_AX_WDRLS_ERR_INT_EN BIT(0) 608#define DMAC_ERR_IMR_EN GENMASK(31, 0) 609#define DMAC_ERR_IMR_DIS 0 610 611#define R_AX_DMAC_ERR_ISR 0x8524 612#define B_AX_HAXIDMA_ERR_FLAG BIT(14) 613#define B_AX_PAXIDMA_ERR_FLAG BIT(13) 614#define B_AX_HCI_BUF_ERR_FLAG BIT(12) 615#define B_AX_BBRPT_ERR_FLAG BIT(11) 616#define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) 617#define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) 618#define B_AX_DISPATCH_ERR_FLAG BIT(8) 619#define B_AX_PKTIN_ERR_FLAG BIT(7) 620#define B_AX_PLE_DLE_ERR_FLAG BIT(6) 621#define B_AX_TXPKTCTRL_ERR_FLAG BIT(5) 622#define B_AX_WDE_DLE_ERR_FLAG BIT(4) 623#define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3) 624#define B_AX_MPDU_ERR_FLAG BIT(2) 625#define B_AX_WSEC_ERR_FLAG BIT(1) 626#define B_AX_WDRLS_ERR_FLAG BIT(0) 627 628#define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800 629#define B_AX_PL_PAGE_128B_SEL BIT(9) 630#define B_AX_WD_PAGE_64B_SEL BIT(8) 631#define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804 632#define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808 633#define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C 634#define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810 635#define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0) 636 637#define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850 638#define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31) 639#define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30) 640#define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29) 641#define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) 642#define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27) 643#define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26) 644#define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25) 645#define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24) 646#define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21) 647#define B_AX_HDT_RES_ERR_INT_EN BIT(20) 648#define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19) 649#define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18) 650#define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17) 651#define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16) 652#define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15) 653#define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14) 654#define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13) 655#define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12) 656#define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11) 657#define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10) 658#define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9) 659#define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8) 660#define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7) 661#define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6) 662#define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5) 663#define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4) 664#define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3) 665#define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2) 666#define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1) 667#define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0) 668#define B_AX_HOST_DISP_IMR_CLR (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \ 669 B_AX_HDT_CHANNEL_ID_ERR_INT_EN | \ 670 B_AX_HDT_PKT_FAIL_DBG_INT_EN | \ 671 B_AX_HDT_PERMU_OVERFLOW_INT_EN | \ 672 B_AX_HDT_PERMU_UNDERFLOW_INT_EN | \ 673 B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \ 674 B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \ 675 B_AX_HDT_OFFSET_UNMATCH_INT_EN | \ 676 B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \ 677 B_AX_HDT_WD_CHK_ERR_INT_EN | \ 678 B_AX_HDT_PRE_COST_ERR_INT_EN | \ 679 B_AX_HDT_TXPKTSIZE_ERR_INT_EN | \ 680 B_AX_HDT_TCP_CHK_ERR_INT_EN | \ 681 B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | \ 682 B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | \ 683 B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | \ 684 B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | \ 685 B_AX_HDT_FLOW_CTRL_ERR_INT_EN | \ 686 B_AX_HDT_NULLPKT_ERR_INT_EN | \ 687 B_AX_HDT_BURST_NUM_ERR_INT_EN | \ 688 B_AX_HDT_RXAGG_CFG_ERR_INT_EN | \ 689 B_AX_HDT_SHIFT_EN_ERR_INT_EN | \ 690 B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \ 691 B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \ 692 B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | \ 693 B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | \ 694 B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \ 695 B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN) 696#define B_AX_HOST_DISP_IMR_SET (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \ 697 B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \ 698 B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \ 699 B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \ 700 B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \ 701 B_AX_HDT_DMA_PROCESS_ERR_INT_EN) 702 703#define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31) 704#define B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30) 705#define B_AX_HR_CHKSUM_FSM_ERR_INT_EN BIT(29) 706#define B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) 707#define B_AX_HR_DMA_PROCESS_ERR_INT_EN BIT(27) 708#define B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26) 709#define B_AX_HR_SHIFT_EN_ERR_INT_EN BIT(25) 710#define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24) 711#define B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN BIT(23) 712#define B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22) 713#define B_AX_HT_ILL_CH_ERR_INT_EN BIT(20) 714#define B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18) 715#define B_AX_HT_WD_LEN_OVER_ERR_INT_EN BIT(17) 716#define B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16) 717#define B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15) 718#define B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14) 719#define B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13) 720#define B_AX_HT_CHKSUM_FSM_ERR_INT_EN BIT(12) 721#define B_AX_HT_TXPKTSIZE_ERR_INT_EN BIT(11) 722#define B_AX_HT_PRE_SUB_ERR_INT_EN BIT(10) 723#define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9) 724#define B_AX_HT_CHANNEL_DMA_ERR_INT_EN BIT(8) 725#define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7) 726#define B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) 727#define B_AX_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5) 728#define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) 729#define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) 730#define B_AX_HT_PKT_FAIL_ERR_INT_EN BIT(2) 731#define B_AX_HT_CH_ID_ERR_INT_EN BIT(1) 732#define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0) 733#define B_AX_HOST_DISP_IMR_CLR_V1 (B_AX_HT_EP_CH_DIFF_ERR_INT_EN | \ 734 B_AX_HT_CH_ID_ERR_INT_EN | \ 735 B_AX_HT_PKT_FAIL_ERR_INT_EN | \ 736 B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ 737 B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ 738 B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \ 739 B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \ 740 B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN | \ 741 B_AX_HT_CHANNEL_DMA_ERR_INT_EN | \ 742 B_AX_HT_WD_CHKSUM_ERR_INT_EN | \ 743 B_AX_HT_PRE_SUB_ERR_INT_EN | \ 744 B_AX_HT_TXPKTSIZE_ERR_INT_EN | \ 745 B_AX_HT_CHKSUM_FSM_ERR_INT_EN | \ 746 B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN | \ 747 B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN | \ 748 B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ 749 B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ 750 B_AX_HT_WD_LEN_OVER_ERR_INT_EN | \ 751 B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN | \ 752 B_AX_HT_ILL_CH_ERR_INT_EN | \ 753 B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN | \ 754 B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN | \ 755 B_AX_HR_AGG_CFG_ERR_INT_EN | \ 756 B_AX_HR_SHIFT_EN_ERR_INT_EN | \ 757 B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 758 B_AX_HR_DMA_PROCESS_ERR_INT_EN | \ 759 B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN | \ 760 B_AX_HR_CHKSUM_FSM_ERR_INT_EN | \ 761 B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN | \ 762 B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN) 763#define B_AX_HOST_DISP_IMR_SET_V1 (B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \ 764 B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \ 765 B_AX_HT_ILL_CH_ERR_INT_EN | \ 766 B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 767 B_AX_HR_DMA_PROCESS_ERR_INT_EN) 768 769#define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854 770#define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31) 771#define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30) 772#define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29) 773#define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) 774#define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27) 775#define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26) 776#define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25) 777#define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24) 778#define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20) 779#define B_AX_CPU_RESP_ERR_INT_EN BIT(19) 780#define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18) 781#define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17) 782#define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16) 783#define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15) 784#define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14) 785#define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13) 786#define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12) 787#define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11) 788#define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10) 789#define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9) 790#define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8) 791#define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) 792#define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6) 793#define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5) 794#define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4) 795#define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3) 796#define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2) 797#define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1) 798#define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0) 799#define B_AX_CPU_DISP_IMR_CLR (B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | \ 800 B_AX_CPU_PKT_FAIL_DBG_INT_EN | \ 801 B_AX_CPU_CHANNEL_ID_ERR_INT_EN | \ 802 B_AX_CPU_PERMU_OVERFLOW_INT_EN | \ 803 B_AX_CPU_PERMU_UNDERFLOW_INT_EN | \ 804 B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \ 805 B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \ 806 B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | \ 807 B_AX_CPU_OFFSET_UNMATCH_INT_EN | \ 808 B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | \ 809 B_AX_CPU_WD_CHK_ERR_INT_EN | \ 810 B_AX_CPU_PRE_COST_ERR_INT_EN | \ 811 B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | \ 812 B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | \ 813 B_AX_CPU_F2P_QSEL_ERR_INT_EN | \ 814 B_AX_CPU_F2P_SEQ_ERR_INT_EN | \ 815 B_AX_CPU_FLOW_CTRL_ERR_INT_EN | \ 816 B_AX_CPU_NULLPKT_ERR_INT_EN | \ 817 B_AX_CPU_BURST_NUM_ERR_INT_EN | \ 818 B_AX_CPU_RXAGG_CFG_ERR_INT_EN | \ 819 B_AX_CPU_SHIFT_EN_ERR_INT_EN | \ 820 B_AX_CPU_TOTAL_LEN_ERR_INT_EN | \ 821 B_AX_CPU_DMA_PROCESS_ERR_INT_EN | \ 822 B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | \ 823 B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | \ 824 B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | \ 825 B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN) 826#define B_AX_CPU_DISP_IMR_SET (B_AX_CPU_PKT_FAIL_DBG_INT_EN | \ 827 B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \ 828 B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \ 829 B_AX_CPU_TOTAL_LEN_ERR_INT_EN) 830 831#define B_AX_CR_PLD_LEN_ERR_INT_EN BIT(30) 832#define B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29) 833#define B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28) 834#define B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27) 835#define B_AX_CR_DMA_PROCESS_ERR_INT_EN BIT(26) 836#define B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25) 837#define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24) 838#define B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22) 839#define B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21) 840#define B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20) 841#define B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19) 842#define B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17) 843#define B_AX_CT_WD_LEN_OVER_ERR_INT_EN BIT(16) 844#define B_AX_CT_F2P_SEQ_ERR_INT_EN BIT(15) 845#define B_AX_CT_F2P_QSEL_ERR_INT_EN BIT(14) 846#define B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13) 847#define B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12) 848#define B_AX_CT_PRE_SUB_ERR_INT_EN BIT(11) 849#define B_AX_CT_WD_CHKSUM_ERR_INT_EN BIT(10) 850#define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9) 851#define B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8) 852#define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) 853#define B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) 854#define B_AX_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5) 855#define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) 856#define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) 857#define B_AX_CT_CH_ID_ERR_INT_EN BIT(2) 858#define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0) 859#define B_AX_CPU_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \ 860 B_AX_CT_CH_ID_ERR_INT_EN | \ 861 B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ 862 B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ 863 B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \ 864 B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \ 865 B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN | \ 866 B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN | \ 867 B_AX_CT_CHANNEL_DMA_ERR_INT_EN | \ 868 B_AX_CT_WD_CHKSUM_ERR_INT_EN | \ 869 B_AX_CT_PRE_SUB_ERR_INT_EN | \ 870 B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ 871 B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ 872 B_AX_CT_F2P_QSEL_ERR_INT_EN | \ 873 B_AX_CT_F2P_SEQ_ERR_INT_EN | \ 874 B_AX_CT_WD_LEN_OVER_ERR_INT_EN | \ 875 B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \ 876 B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN | \ 877 B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN | \ 878 B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN | \ 879 B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN | \ 880 B_AX_CR_SHIFT_EN_ERR_INT_EN | \ 881 B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 882 B_AX_CR_DMA_PROCESS_ERR_INT_EN | \ 883 B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN | \ 884 B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \ 885 B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN | \ 886 B_AX_CR_PLD_LEN_ERR_INT_EN) 887#define B_AX_CPU_DISP_IMR_SET_V1 (B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \ 888 B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \ 889 B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 890 B_AX_CR_DMA_PROCESS_ERR_INT_EN | \ 891 B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \ 892 B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN) 893 894#define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858 895#define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29) 896#define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28) 897#define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27) 898#define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26) 899#define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25) 900#define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24) 901#define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17) 902#define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16) 903#define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12) 904#define B_AX_PLE_RESP_ERR_INT_EN BIT(11) 905#define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10) 906#define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9) 907#define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8) 908#define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4) 909#define B_AX_WDE_RESP_ERR_INT_EN BIT(3) 910#define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2) 911#define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1) 912#define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0) 913#define B_AX_OTHER_DISP_IMR_CLR (B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | \ 914 B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | \ 915 B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | \ 916 B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | \ 917 B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | \ 918 B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | \ 919 B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \ 920 B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \ 921 B_AX_PLE_OUTPUT_ERR_INT_EN | \ 922 B_AX_PLE_RESP_ERR_INT_EN | \ 923 B_AX_PLE_BURST_NUM_ERR_INT_EN | \ 924 B_AX_PLE_NULL_PKT_ERR_INT_EN | \ 925 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \ 926 B_AX_WDE_OUTPUT_ERR_INT_EN | \ 927 B_AX_WDE_RESP_ERR_INT_EN | \ 928 B_AX_WDE_BURST_NUM_ERR_INT_EN | \ 929 B_AX_WDE_NULL_PKT_ERR_INT_EN | \ 930 B_AX_WDE_FLOW_CTRL_ERR_INT_EN) 931 932#define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31) 933#define B_AX_REUSE_EN_ERR_INT_EN BIT(30) 934#define B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29) 935#define B_AX_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28) 936#define B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27) 937#define B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26) 938#define B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25) 939#define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24) 940#define B_AX_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23) 941#define B_AX_REUSE_PKT_CNT_ERR_INT_EN BIT(22) 942#define B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21) 943#define B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20) 944#define B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19) 945#define B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18) 946#define B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17) 947#define B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16) 948#define B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15) 949#define B_AX_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14) 950#define B_AX_PLE_RESPOSE_ERR_INT_EN BIT(11) 951#define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7) 952#define B_AX_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6) 953#define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3) 954#define B_AX_OTHER_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \ 955 B_AX_WDE_FLOW_CTRL_ERR_INT_EN | \ 956 B_AX_WDE_NULL_PKT_ERR_INT_EN | \ 957 B_AX_WDE_BURST_NUM_ERR_INT_EN | \ 958 B_AX_WDE_RESPONSE_ERR_INT_EN | \ 959 B_AX_WDE_OUTPUT_ERR_INT_EN | \ 960 B_AX_HDR_RX_TIMEOUT_ERR_INT_EN | \ 961 B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN | \ 962 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \ 963 B_AX_PLE_NULL_PKT_ERR_INT_EN | \ 964 B_AX_PLE_BURST_NUM_ERR_INT_EN | \ 965 B_AX_PLE_RESPOSE_ERR_INT_EN | \ 966 B_AX_PLE_OUTPUT_ERR_INT_EN | \ 967 B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \ 968 B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \ 969 B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN | \ 970 B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN | \ 971 B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \ 972 B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \ 973 B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \ 974 B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \ 975 B_AX_REUSE_PKT_CNT_ERR_INT_EN | \ 976 B_AX_REUSE_SIZE_ZERO_ERR_INT_EN | \ 977 B_AX_STF_CMD_OVERFLOW_ERR_INT_EN | \ 978 B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN | \ 979 B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN | \ 980 B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN | \ 981 B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \ 982 B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN | \ 983 B_AX_REUSE_EN_ERR_INT_EN | \ 984 B_AX_REUSE_SIZE_ERR_INT_EN) 985#define B_AX_OTHER_DISP_IMR_SET_V1 (B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \ 986 B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \ 987 B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \ 988 B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \ 989 B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \ 990 B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \ 991 B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \ 992 B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN) 993 994#define R_AX_DISPATCHER_DBG_PORT 0x8860 995#define B_AX_DISPATCHER_DBG_SEL_MASK GENMASK(11, 8) 996#define B_AX_DISPATCHER_INTN_SEL_MASK GENMASK(7, 4) 997#define B_AX_DISPATCHER_CH_SEL_MASK GENMASK(3, 0) 998 999#define R_AX_RX_FUNCTION_STOP 0x8920 1000#define B_AX_HDR_RX_STOP BIT(0) 1001 1002#define R_AX_HCI_FC_CTRL 0x8A00 1003#define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10) 1004#define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8) 1005#define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6) 1006#define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4) 1007#define B_AX_HCI_FC_CH12_EN BIT(3) 1008#define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1) 1009#define B_AX_HCI_FC_EN BIT(0) 1010 1011#define R_AX_CH_PAGE_CTRL 0x8A04 1012#define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16) 1013#define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0) 1014 1015#define B_AX_MAX_PG_MASK GENMASK(28, 16) 1016#define B_AX_MIN_PG_MASK GENMASK(12, 0) 1017#define B_AX_GRP BIT(31) 1018#define R_AX_ACH0_PAGE_CTRL 0x8A10 1019#define R_AX_ACH1_PAGE_CTRL 0x8A14 1020#define R_AX_ACH2_PAGE_CTRL 0x8A18 1021#define R_AX_ACH3_PAGE_CTRL 0x8A1C 1022#define R_AX_ACH4_PAGE_CTRL 0x8A20 1023#define R_AX_ACH5_PAGE_CTRL 0x8A24 1024#define R_AX_ACH6_PAGE_CTRL 0x8A28 1025#define R_AX_ACH7_PAGE_CTRL 0x8A2C 1026#define R_AX_CH8_PAGE_CTRL 0x8A30 1027#define R_AX_CH9_PAGE_CTRL 0x8A34 1028#define R_AX_CH10_PAGE_CTRL 0x8A38 1029#define R_AX_CH11_PAGE_CTRL 0x8A3C 1030 1031#define B_AX_AVAL_PG_MASK GENMASK(27, 16) 1032#define B_AX_USE_PG_MASK GENMASK(12, 0) 1033#define R_AX_ACH0_PAGE_INFO 0x8A50 1034#define R_AX_ACH1_PAGE_INFO 0x8A54 1035#define R_AX_ACH2_PAGE_INFO 0x8A58 1036#define R_AX_ACH3_PAGE_INFO 0x8A5C 1037#define R_AX_ACH4_PAGE_INFO 0x8A60 1038#define R_AX_ACH5_PAGE_INFO 0x8A64 1039#define R_AX_ACH6_PAGE_INFO 0x8A68 1040#define R_AX_ACH7_PAGE_INFO 0x8A6C 1041#define R_AX_CH8_PAGE_INFO 0x8A70 1042#define R_AX_CH9_PAGE_INFO 0x8A74 1043#define R_AX_CH10_PAGE_INFO 0x8A78 1044#define R_AX_CH11_PAGE_INFO 0x8A7C 1045#define R_AX_CH12_PAGE_INFO 0x8A80 1046 1047#define R_AX_PUB_PAGE_INFO3 0x8A8C 1048#define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16) 1049#define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0) 1050 1051#define R_AX_PUB_PAGE_CTRL1 0x8A90 1052#define B_AX_PUBPG_G1_MASK GENMASK(28, 16) 1053#define B_AX_PUBPG_G0_MASK GENMASK(12, 0) 1054 1055#define R_AX_PUB_PAGE_CTRL2 0x8A94 1056#define B_AX_PUBPG_ALL_MASK GENMASK(12, 0) 1057 1058#define R_AX_PUB_PAGE_INFO1 0x8A98 1059#define B_AX_G1_USE_PG_MASK GENMASK(28, 16) 1060#define B_AX_G0_USE_PG_MASK GENMASK(12, 0) 1061 1062#define R_AX_PUB_PAGE_INFO2 0x8A9C 1063#define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0) 1064 1065#define R_AX_WP_PAGE_CTRL1 0x8AA0 1066#define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16) 1067#define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0) 1068 1069#define R_AX_WP_PAGE_CTRL2 0x8AA4 1070#define B_AX_WP_THRD_MASK GENMASK(12, 0) 1071 1072#define R_AX_WP_PAGE_INFO1 0x8AA8 1073#define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16) 1074 1075#define R_AX_WDE_PKTBUF_CFG 0x8C08 1076#define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8) 1077#define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0) 1078#define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) 1079 1080#define R_AX_WDE_ERRFLAG_MSG 0x8C30 1081#define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0) 1082 1083#define R_AX_WDE_ERR_FLAG_CFG_NUM1 0x8C34 1084#define B_AX_WDE_ERR_FLAG_NUM1_VLD BIT(31) 1085#define B_AX_WDE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24) 1086#define B_AX_WDE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16) 1087#define B_AX_WDE_DATCHN_FRZTMR_MODE BIT(2) 1088#define B_AX_WDE_QUEMGN_FRZTMR_MODE BIT(1) 1089#define B_AX_WDE_BUFMGN_FRZTMR_MODE BIT(0) 1090 1091#define R_AX_WDE_ERR_IMR 0x8C38 1092#define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) 1093#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) 1094#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) 1095#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) 1096#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) 1097#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) 1098#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) 1099#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) 1100#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) 1101#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) 1102#define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13) 1103#define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12) 1104#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) 1105#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6) 1106#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5) 1107#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) 1108#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3) 1109#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) 1110#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) 1111#define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0) 1112#define B_AX_WDE_IMR_CLR (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1113 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1114 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1115 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \ 1116 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1117 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \ 1118 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \ 1119 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ 1120 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1121 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1122 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1123 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1124 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1125 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1126 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1127 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1128 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1129 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1130 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN) 1131#define B_AX_WDE_IMR_SET (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1132 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1133 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1134 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \ 1135 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1136 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \ 1137 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \ 1138 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ 1139 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1140 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1141 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1142 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1143 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1144 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1145 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1146 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1147 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1148 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1149 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN) 1150 1151#define B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) 1152#define B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28) 1153#define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) 1154#define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) 1155#define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) 1156#define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) 1157#define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) 1158#define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) 1159#define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) 1160#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) 1161#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) 1162#define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) 1163#define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) 1164#define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) 1165#define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) 1166#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) 1167#define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) 1168#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) 1169#define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) 1170#define B_AX_WDE_BUFREQ_SIZELMT_INT_EN BIT(2) 1171#define B_AX_WDE_BUFREQ_SIZE0_INT_EN BIT(1) 1172#define B_AX_WDE_IMR_CLR_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1173 B_AX_WDE_BUFREQ_SIZE0_INT_EN | \ 1174 B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \ 1175 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1176 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1177 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1178 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1179 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1180 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1181 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1182 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1183 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1184 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1185 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1186 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1187 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1188 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1189 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1190 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1191 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1192 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \ 1193 B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \ 1194 B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \ 1195 B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN) 1196#define B_AX_WDE_IMR_SET_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1197 B_AX_WDE_BUFREQ_SIZE0_INT_EN | \ 1198 B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \ 1199 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1200 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1201 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1202 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1203 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1204 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1205 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1206 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1207 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1208 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1209 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1210 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1211 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1212 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1213 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1214 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1215 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1216 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \ 1217 B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \ 1218 B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \ 1219 B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN) 1220 1221#define R_AX_WDE_ERR_ISR 0x8C3C 1222#define B_AX_WDE_DATCHN_RRDY_ERR BIT(27) 1223#define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26) 1224#define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25) 1225#define B_AX_WDE_DATCHN_ARBT_ERR BIT(24) 1226#define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19) 1227#define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18) 1228#define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17) 1229#define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16) 1230#define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15) 1231#define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14) 1232#define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13) 1233#define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12) 1234#define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7) 1235#define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6) 1236#define B_AX_WDE_GETNPG_STRPG_ERR BIT(5) 1237#define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4) 1238#define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3) 1239#define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2) 1240#define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1) 1241#define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0) 1242 1243#define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16) 1244#define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0) 1245#define R_AX_WDE_QTA0_CFG 0x8C40 1246#define R_AX_WDE_QTA1_CFG 0x8C44 1247#define R_AX_WDE_QTA2_CFG 0x8C48 1248#define R_AX_WDE_QTA3_CFG 0x8C4C 1249#define R_AX_WDE_QTA4_CFG 0x8C50 1250 1251#define B_AX_DLE_PUB_PGNUM GENMASK(12, 0) 1252#define B_AX_DLE_FREE_HEADPG GENMASK(11, 0) 1253#define B_AX_DLE_FREE_TAILPG GENMASK(27, 16) 1254#define B_AX_DLE_USE_PGNUM GENMASK(27, 16) 1255#define B_AX_DLE_RSV_PGNUM GENMASK(11, 0) 1256#define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0) 1257 1258#define R_AX_WDE_INI_STATUS 0x8D00 1259#define B_AX_WDE_Q_MGN_INI_RDY BIT(1) 1260#define B_AX_WDE_BUF_MGN_INI_RDY BIT(0) 1261#define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY) 1262#define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10 1263#define B_AX_WDE_DFI_ACTIVE BIT(31) 1264#define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16) 1265#define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0) 1266#define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14 1267#define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0) 1268 1269#define R_AX_PLE_PKTBUF_CFG 0x9008 1270#define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8) 1271#define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0) 1272#define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16) 1273 1274#define R_AX_PLE_DBGERR_LOCKEN 0x9020 1275#define B_AX_PLE_LOCKEN_DLEPIF07 BIT(7) 1276#define B_AX_PLE_LOCKEN_DLEPIF06 BIT(6) 1277#define B_AX_PLE_LOCKEN_DLEPIF05 BIT(5) 1278#define B_AX_PLE_LOCKEN_DLEPIF04 BIT(4) 1279#define B_AX_PLE_LOCKEN_DLEPIF03 BIT(3) 1280#define B_AX_PLE_LOCKEN_DLEPIF02 BIT(2) 1281#define B_AX_PLE_LOCKEN_DLEPIF01 BIT(1) 1282#define B_AX_PLE_LOCKEN_DLEPIF00 BIT(0) 1283 1284#define R_AX_PLE_DBGERR_STS 0x9024 1285#define B_AX_PLE_LOCKON_DLEPIF07 BIT(7) 1286#define B_AX_PLE_LOCKON_DLEPIF06 BIT(6) 1287#define B_AX_PLE_LOCKON_DLEPIF05 BIT(5) 1288#define B_AX_PLE_LOCKON_DLEPIF04 BIT(4) 1289#define B_AX_PLE_LOCKON_DLEPIF03 BIT(3) 1290#define B_AX_PLE_LOCKON_DLEPIF02 BIT(2) 1291#define B_AX_PLE_LOCKON_DLEPIF01 BIT(1) 1292#define B_AX_PLE_LOCKON_DLEPIF00 BIT(0) 1293 1294#define R_AX_PLE_ERR_FLAG_CFG_NUM1 0x9034 1295#define B_AX_PLE_ERR_FLAG_NUM1_VLD BIT(31) 1296#define B_AX_PLE_ERR_FLAG_NUM1_MSTIDX_MASK GENMASK(27, 24) 1297#define B_AX_PLE_ERR_FLAG_NUM1_ISRIDX_MASK GENMASK(20, 16) 1298#define B_AX_PLE_DATCHN_FRZTMR_MODE BIT(2) 1299#define B_AX_PLE_QUEMGN_FRZTMR_MODE BIT(1) 1300#define B_AX_PLE_BUFMGN_FRZTMR_MODE BIT(0) 1301 1302#define R_AX_PLE_ERRFLAG_MSG 0x9030 1303#define B_AX_PLE_ERR_FLAG_MSG_MASK GENMASK(31, 0) 1304#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) 1305#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28) 1306#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) 1307#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) 1308#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) 1309#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) 1310#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) 1311#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) 1312#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) 1313#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2) 1314#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1) 1315#define B_AX_PLE_DATCHN_CAMREQ_ERR BIT(29) 1316#define B_AX_PLE_DATCHN_ADRERR_ERR BIT(28) 1317#define B_AX_PLE_BUFMGN_FRZTO_ERR_V1 BIT(9) 1318#define B_AX_PLE_GETNPG_PGOFST_ERR_V1 BIT(8) 1319#define B_AX_PLE_GETNPG_STRPG_ERR_V1 BIT(7) 1320#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_V1 BIT(6) 1321#define B_AX_PLE_BUFRTN_SIZE_ERR_V1 BIT(5) 1322#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_V1 BIT(4) 1323#define B_AX_PLE_BUFREQ_UNAVAL_ERR_V1 BIT(3) 1324#define B_AX_PLE_BUFREQ_SIZELMT_ERR BIT(2) 1325#define B_AX_PLE_BUFREQ_SIZE0_ERR BIT(1) 1326 1327#define R_AX_PLE_ERR_IMR 0x9038 1328#define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27) 1329#define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26) 1330#define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25) 1331#define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24) 1332#define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) 1333#define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18) 1334#define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17) 1335#define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) 1336#define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) 1337#define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14) 1338#define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13) 1339#define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12) 1340#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) 1341#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6) 1342#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5) 1343#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) 1344#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3) 1345#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) 1346#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) 1347#define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0) 1348#define B_AX_PLE_IMR_CLR (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1349 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1350 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1351 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \ 1352 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1353 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | \ 1354 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \ 1355 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ 1356 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1357 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1358 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1359 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1360 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1361 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1362 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1363 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1364 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1365 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1366 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN) 1367#define B_AX_PLE_IMR_SET (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1368 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1369 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1370 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \ 1371 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1372 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \ 1373 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ 1374 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1375 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1376 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1377 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1378 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1379 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1380 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1381 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1382 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1383 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1384 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN) 1385 1386#define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) 1387#define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28) 1388#define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) 1389#define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) 1390#define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) 1391#define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) 1392#define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) 1393#define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) 1394#define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) 1395#define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2) 1396#define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1) 1397#define B_AX_PLE_IMR_CLR_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1398 B_AX_PLE_BUFREQ_SIZE0_INT_EN | \ 1399 B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \ 1400 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1401 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1402 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1403 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1404 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1405 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1406 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1407 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1408 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1409 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1410 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1411 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1412 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1413 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1414 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1415 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1416 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1417 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \ 1418 B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \ 1419 B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \ 1420 B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN) 1421#define B_AX_PLE_IMR_SET_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1422 B_AX_PLE_BUFREQ_SIZE0_INT_EN | \ 1423 B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \ 1424 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1425 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1426 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1427 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1428 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1429 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1430 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1431 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1432 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1433 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1434 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1435 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1436 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1437 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1438 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1439 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1440 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1441 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \ 1442 B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \ 1443 B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \ 1444 B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN) 1445 1446#define R_AX_PLE_ERR_FLAG_ISR 0x903C 1447#define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16) 1448#define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0) 1449#define R_AX_PLE_QTA0_CFG 0x9040 1450#define R_AX_PLE_QTA1_CFG 0x9044 1451#define R_AX_PLE_QTA2_CFG 0x9048 1452#define R_AX_PLE_QTA3_CFG 0x904C 1453#define R_AX_PLE_QTA4_CFG 0x9050 1454#define R_AX_PLE_QTA5_CFG 0x9054 1455#define R_AX_PLE_QTA6_CFG 0x9058 1456#define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16) 1457#define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0) 1458#define R_AX_PLE_QTA7_CFG 0x905C 1459#define R_AX_PLE_QTA8_CFG 0x9060 1460#define R_AX_PLE_QTA9_CFG 0x9064 1461#define R_AX_PLE_QTA10_CFG 0x9068 1462#define R_AX_PLE_QTA11_CFG 0x906C 1463 1464#define R_AX_PLE_INI_STATUS 0x9100 1465#define B_AX_PLE_Q_MGN_INI_RDY BIT(1) 1466#define B_AX_PLE_BUF_MGN_INI_RDY BIT(0) 1467#define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY) 1468#define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110 1469#define B_AX_PLE_DFI_ACTIVE BIT(31) 1470#define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) 1471#define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0) 1472#define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114 1473#define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0) 1474 1475#define R_AX_WDRLS_CFG 0x9408 1476#define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8) 1477#define B_AX_WDRLS_MODE_MASK GENMASK(1, 0) 1478 1479#define R_AX_RLSRPT0_CFG0 0x9410 1480#define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24) 1481#define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16) 1482#define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8) 1483#define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0) 1484 1485#define R_AX_RLSRPT0_CFG1 0x9414 1486#define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16) 1487#define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0) 1488 1489#define R_AX_WDRLS_ERR_IMR 0x9430 1490#define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) 1491#define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) 1492#define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) 1493#define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) 1494#define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) 1495#define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) 1496#define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) 1497#define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) 1498#define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) 1499#define B_AX_WDRLS_IMR_EN_CLR (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ 1500 B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ 1501 B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ 1502 B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ 1503 B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ 1504 B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ 1505 B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ 1506 B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ 1507 B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) 1508#define B_AX_WDRLS_IMR_SET (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ 1509 B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ 1510 B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ 1511 B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ 1512 B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ 1513 B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ 1514 B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ 1515 B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) 1516#define B_AX_WDRLS_IMR_SET_V1 (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ 1517 B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ 1518 B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ 1519 B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ 1520 B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ 1521 B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ 1522 B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ 1523 B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ 1524 B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) 1525 1526#define R_AX_WDRLS_ERR_ISR 0x9434 1527 1528#define R_AX_BBRPT_COM_ERR_IMR 0x9608 1529#define B_AX_BBRPT_COM_HANG_EN BIT(1) 1530#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) 1531 1532#define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C 1533#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16) 1534#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) 1535 1536#define R_AX_BBRPT_COM_ERR_ISR 0x960C 1537#define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_V1 BIT(0) 1538 1539#define R_AX_BBRPT_CHINFO_ERR_ISR 0x962C 1540#define B_AX_BBPRT_CHIF_TO_ERR_V1 BIT(7) 1541#define B_AX_BBPRT_CHIF_NULL_ERR_V1 BIT(6) 1542#define B_AX_BBPRT_CHIF_LEFT2_ERR_V1 BIT(5) 1543#define B_AX_BBPRT_CHIF_LEFT1_ERR_V1 BIT(4) 1544#define B_AX_BBPRT_CHIF_HDRL_ERR_V1 BIT(3) 1545#define B_AX_BBPRT_CHIF_BOVF_ERR_V1 BIT(2) 1546#define B_AX_BBPRT_CHIF_OVF_ERR_V1 BIT(1) 1547#define B_AX_BBPRT_CHIF_BB_TO_ERR_V1 BIT(0) 1548 1549#define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628 1550#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) 1551#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) 1552#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) 1553#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) 1554#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) 1555#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) 1556#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) 1557#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) 1558#define R_AX_BBRPT_CHINFO_IMR_SET_V1 (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \ 1559 B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \ 1560 B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \ 1561 B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \ 1562 B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \ 1563 B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \ 1564 B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \ 1565 B_AX_BBPRT_CHIF_TO_ERR_INT_EN) 1566 1567#define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C 1568#define B_AX_BBPRT_CHIF_TO_ERR BIT(23) 1569#define B_AX_BBPRT_CHIF_NULL_ERR BIT(22) 1570#define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21) 1571#define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20) 1572#define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19) 1573#define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18) 1574#define B_AX_BBPRT_CHIF_OVF_ERR BIT(17) 1575#define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16) 1576#define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) 1577#define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) 1578#define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) 1579#define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) 1580#define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) 1581#define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) 1582#define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) 1583#define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) 1584#define B_AX_BBRPT_CHINFO_IMR_CLR (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \ 1585 B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \ 1586 B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \ 1587 B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \ 1588 B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \ 1589 B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \ 1590 B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \ 1591 B_AX_BBPRT_CHIF_TO_ERR_INT_EN) 1592 1593#define R_AX_BBRPT_DFS_ERR_IMR 0x9638 1594#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) 1595 1596#define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C 1597#define B_AX_BBRPT_DFS_TO_ERR BIT(16) 1598#define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) 1599 1600#define R_AX_BBRPT_DFS_ERR_ISR 0x963C 1601#define B_AX_BBRPT_DFS_TO_ERR_V1 BIT(0) 1602 1603#define R_AX_LA_ERRFLAG 0x966C 1604#define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16) 1605#define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0) 1606 1607#define R_AX_WD_BUF_REQ 0x9800 1608#define R_AX_PL_BUF_REQ 0x9820 1609#define B_AX_WD_BUF_REQ_EXEC BIT(31) 1610#define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16) 1611#define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0) 1612 1613#define R_AX_WD_BUF_STATUS 0x9804 1614#define R_AX_PL_BUF_STATUS 0x9824 1615#define B_AX_WD_BUF_STAT_DONE BIT(31) 1616#define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0) 1617#define S_WD_BUF_STAT_PKTID_INVALID GENMASK(11, 0) 1618 1619#define R_AX_WD_CPUQ_OP_0 0x9810 1620#define R_AX_PL_CPUQ_OP_0 0x9830 1621#define B_AX_WD_CPUQ_OP_EXEC BIT(31) 1622#define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) 1623#define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16) 1624#define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) 1625 1626#define R_AX_WD_CPUQ_OP_1 0x9814 1627#define R_AX_PL_CPUQ_OP_1 0x9834 1628#define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22) 1629#define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16) 1630#define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6) 1631#define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0) 1632 1633#define R_AX_WD_CPUQ_OP_2 0x9818 1634#define R_AX_PL_CPUQ_OP_2 0x9838 1635#define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) 1636#define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) 1637 1638#define R_AX_WD_CPUQ_OP_STATUS 0x981C 1639#define R_AX_PL_CPUQ_OP_STATUS 0x983C 1640#define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31) 1641#define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0) 1642 1643#define R_AX_CPUIO_ERR_IMR 0x9840 1644#define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12) 1645#define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8) 1646#define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4) 1647#define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0) 1648#define B_AX_CPUIO_IMR_CLR (B_AX_WDEBUF_OP_ERR_INT_EN | \ 1649 B_AX_WDEQUE_OP_ERR_INT_EN | \ 1650 B_AX_PLEBUF_OP_ERR_INT_EN | \ 1651 B_AX_PLEQUE_OP_ERR_INT_EN) 1652#define B_AX_CPUIO_IMR_SET (B_AX_WDEBUF_OP_ERR_INT_EN | \ 1653 B_AX_WDEQUE_OP_ERR_INT_EN | \ 1654 B_AX_PLEBUF_OP_ERR_INT_EN | \ 1655 B_AX_PLEQUE_OP_ERR_INT_EN) 1656 1657#define R_AX_CPUIO_ERR_ISR 0x9844 1658 1659#define R_AX_SEC_ERR_IMR_ISR 0x991C 1660 1661#define R_AX_PKTIN_SETTING 0x9A00 1662#define B_AX_WD_ADDR_INFO_LENGTH BIT(1) 1663 1664#define R_AX_PKTIN_ERR_IMR 0x9A20 1665#define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0) 1666 1667#define R_AX_PKTIN_ERR_ISR 0x9A24 1668 1669#define R_AX_MPDU_TX_ERR_ISR 0x9BF0 1670#define R_AX_MPDU_TX_ERR_IMR 0x9BF4 1671#define B_AX_TX_KSRCH_ERR_EN BIT(9) 1672#define B_AX_TX_NW_TYPE_ERR_EN BIT(8) 1673#define B_AX_TX_LLC_PRE_ERR_EN BIT(7) 1674#define B_AX_TX_ETH_TYPE_ERR_EN BIT(6) 1675#define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5) 1676#define B_AX_TX_OFFSET_ERR_INT_EN BIT(4) 1677#define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3) 1678#define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2) 1679#define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1) 1680#define B_AX_MPDU_TX_IMR_SET_V1 (B_AX_TX_GET_ERRPKTID_INT_EN | \ 1681 B_AX_TX_NXT_ERRPKTID_INT_EN | \ 1682 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | \ 1683 B_AX_TX_HDR3_SIZE_ERR_INT_EN | \ 1684 B_AX_TX_ETH_TYPE_ERR_EN | \ 1685 B_AX_TX_NW_TYPE_ERR_EN | \ 1686 B_AX_TX_KSRCH_ERR_EN) 1687 1688#define R_AX_MPDU_PROC 0x9C00 1689#define B_AX_A_ICV_ERR BIT(1) 1690#define B_AX_APPEND_FCS BIT(0) 1691 1692#define R_AX_ACTION_FWD0 0x9C04 1693#define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95 1694 1695#define R_AX_ACTION_FWD1 0x9C08 1696 1697#define R_AX_TF_FWD 0x9C14 1698#define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55 1699 1700#define R_AX_HW_RPT_FWD 0x9C18 1701#define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0) 1702#define RTW89_PRPT_DEST_HOST 1 1703#define RTW89_PRPT_DEST_WLCPU 2 1704 1705#define R_AX_CUT_AMSDU_CTRL 0x9C40 1706#define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0 1707 1708#define R_AX_WOW_CTRL 0x9C50 1709#define B_AX_WOW_WOWEN BIT(1) 1710 1711#define R_AX_MPDU_RX_ERR_ISR 0x9CF0 1712#define R_AX_MPDU_RX_ERR_IMR 0x9CF4 1713#define B_AX_RPT_ERR_INT_EN BIT(3) 1714#define B_AX_MHDRLEN_ERR_INT_EN BIT(1) 1715#define B_AX_GETPKTID_ERR_INT_EN BIT(0) 1716#define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN 1717 1718#define R_AX_SEC_ENG_CTRL 0x9D00 1719#define B_AX_SEC_DBG_PORT_FIELD_MASK GENMASK(19, 16) 1720#define B_AX_TX_PARTIAL_MODE BIT(11) 1721#define B_AX_CLK_EN_CGCMP BIT(10) 1722#define B_AX_CLK_EN_WAPI BIT(9) 1723#define B_AX_CLK_EN_WEP_TKIP BIT(8) 1724#define B_AX_BMC_MGNT_DEC BIT(5) 1725#define B_AX_UC_MGNT_DEC BIT(4) 1726#define B_AX_MC_DEC BIT(3) 1727#define B_AX_BC_DEC BIT(2) 1728#define B_AX_SEC_RX_DEC BIT(1) 1729#define B_AX_SEC_TX_ENC BIT(0) 1730 1731#define R_AX_SEC_MPDU_PROC 0x9D04 1732#define B_AX_APPEND_ICV BIT(1) 1733#define B_AX_APPEND_MIC BIT(0) 1734 1735#define R_AX_SEC_CAM_ACCESS 0x9D10 1736#define R_AX_SEC_CAM_RDATA 0x9D14 1737#define R_AX_SEC_CAM_WDATA 0x9D18 1738 1739#define R_AX_SEC_DEBUG 0x9D1C 1740#define B_AX_IMR_ERROR BIT(3) 1741 1742#define R_AX_SEC_DEBUG1 0x9D1C 1743#define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30) 1744#define AX_TX_TO_VAL 0x2 1745 1746#define R_AX_SEC_TX_DEBUG 0x9D20 1747#define R_AX_SEC_RX_DEBUG 0x9D24 1748#define R_AX_SEC_TRX_PKT_CNT 0x9D28 1749 1750#define R_AX_SEC_DEBUG2 0x9D28 1751#define B_AX_DBG_READ_SH 2 1752#define B_AX_DBG_READ_MSK 0x3fffffff 1753 1754#define R_AX_SEC_TRX_BLK_CNT 0x9D2C 1755 1756#define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C 1757#define B_AX_RX_HANG_IMR BIT(1) 1758#define B_AX_TX_HANG_IMR BIT(0) 1759 1760#define R_AX_SEC_ERROR_FLAG 0x9D30 1761#define B_AX_RX_HANG_ERROR_V1 BIT(1) 1762#define B_AX_TX_HANG_ERROR_V1 BIT(0) 1763 1764#define R_AX_SS_CTRL 0x9E10 1765#define B_AX_SS_INIT_DONE_1 BIT(31) 1766#define B_AX_SS_WARM_INIT_FLG BIT(29) 1767#define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28) 1768#define B_AX_SS_EN BIT(0) 1769 1770#define R_AX_SS2FINFO_PATH 0x9E50 1771#define B_AX_SS_UL_REL BIT(31) 1772#define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24) 1773#define B_AX_SS_REL_PORT_MASK GENMASK(18, 16) 1774#define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8) 1775#define SS2F_PATH_WLCPU 0x0A 1776#define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0) 1777 1778#define R_AX_SS_MACID_PAUSE_0 0x9EB0 1779#define B_AX_SS_MACID31_0_PAUSE_SH 0 1780#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0) 1781 1782#define R_AX_SS_MACID_PAUSE_1 0x9EB4 1783#define B_AX_SS_MACID63_32_PAUSE_SH 0 1784#define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0) 1785 1786#define R_AX_SS_MACID_PAUSE_2 0x9EB8 1787#define B_AX_SS_MACID95_64_PAUSE_SH 0 1788#define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0) 1789 1790#define R_AX_SS_MACID_PAUSE_3 0x9EBC 1791#define B_AX_SS_MACID127_96_PAUSE_SH 0 1792#define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0) 1793 1794#define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0 1795#define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2) 1796#define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1) 1797#define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0) 1798#define B_AX_STA_SCHEDULER_IMR_SET (B_AX_SEARCH_HANG_TIMEOUT_INT_EN | \ 1799 B_AX_RPT_HANG_TIMEOUT_INT_EN | \ 1800 B_AX_PLE_B_PKTID_ERR_INT_EN) 1801 1802#define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4 1803 1804#define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C 1805#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25) 1806#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24) 1807#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19) 1808#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18) 1809#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17) 1810#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16) 1811#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) 1812#define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8) 1813#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) 1814#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) 1815#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) 1816#define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0) 1817#define B_AX_TXPKTCTL_IMR_B0_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1818 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ 1819 B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \ 1820 B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \ 1821 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ 1822 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) 1823#define B_AX_TXPKTCTL_IMR_B1_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1824 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ 1825 B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \ 1826 B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \ 1827 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ 1828 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) 1829#define B_AX_TXPKTCTL_IMR_B0_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1830 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN) 1831#define B_AX_TXPKTCTL_IMR_B1_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1832 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ 1833 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ 1834 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) 1835 1836#define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C 1837#define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) 1838#define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) 1839#define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) 1840#define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) 1841 1842#define R_AX_DBG_FUN_INTF_CTL 0x9F30 1843#define B_AX_DFI_ACTIVE BIT(31) 1844#define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16) 1845#define B_AX_DFI_ADDR_MASK GENMASK(15, 0) 1846#define R_AX_DBG_FUN_INTF_DATA 0x9F34 1847#define B_AX_DFI_DATA_MASK GENMASK(31, 0) 1848 1849#define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48 1850#define B_AX_B0_PRELD_FEN BIT(31) 1851#define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16) 1852#define PRELD_B0_ENT_NUM 10 1853#define PRELD_AMSDU_SIZE 52 1854#define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) 1855#define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) 1856 1857#define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C 1858#define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) 1859#define PRELD_NEXT_WND 1 1860#define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) 1861 1862#define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78 1863#define B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(21) 1864#define B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(20) 1865#define B_AX_B0_IMR_ERR_MPDUIF_DATAERR BIT(18) 1866#define B_AX_B0_IMR_ERR_MPDUINFO_RECFG BIT(16) 1867#define B_AX_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11) 1868#define B_AX_B0_IMR_ERR_CMDPSR_FRZTO BIT(10) 1869#define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9) 1870#define B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8) 1871#define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3) 1872#define B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD BIT(2) 1873#define B_AX_B0_IMR_ERR_USRCTL_NOINIT BIT(1) 1874#define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0) 1875#define B_AX_TXPKTCTL_IMR_B0_CLR_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \ 1876 B_AX_B0_IMR_ERR_USRCTL_NOINIT | \ 1877 B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD | \ 1878 B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN | \ 1879 B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \ 1880 B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \ 1881 B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \ 1882 B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \ 1883 B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \ 1884 B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \ 1885 B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ 1886 B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG) 1887#define B_AX_TXPKTCTL_IMR_B0_SET_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \ 1888 B_AX_B0_IMR_ERR_USRCTL_NOINIT | \ 1889 B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \ 1890 B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \ 1891 B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \ 1892 B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \ 1893 B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \ 1894 B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \ 1895 B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ 1896 B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG) 1897 1898#define R_AX_TXPKTCTL_B0_ERRFLAG_ISR 0x9F7C 1899#define B_AX_B0_ISR_ERR_PRELD_EVT3 BIT(23) 1900#define B_AX_B0_ISR_ERR_PRELD_EVT2 BIT(22) 1901#define B_AX_B0_ISR_ERR_PRELD_ENTNUMCFG BIT(21) 1902#define B_AX_B0_ISR_ERR_PRELD_RLSPKTSZERR BIT(20) 1903#define B_AX_B0_ISR_ERR_MPDUIF_ERR1 BIT(19) 1904#define B_AX_B0_ISR_ERR_MPDUIF_DATAERR BIT(18) 1905#define B_AX_B0_ISR_ERR_MPDUINFO_ERR1 BIT(17) 1906#define B_AX_B0_ISR_ERR_MPDUINFO_RECFG BIT(16) 1907#define B_AX_B0_ISR_ERR_CMDPSR_TBLSZ BIT(11) 1908#define B_AX_B0_ISR_ERR_CMDPSR_FRZTO BIT(10) 1909#define B_AX_B0_ISR_ERR_CMDPSR_CMDTYPE BIT(9) 1910#define B_AX_B0_ISR_ERR_CMDPSR_1STCMDERR BIT(8) 1911#define B_AX_B0_ISR_ERR_USRCTL_EVT7 BIT(7) 1912#define B_AX_B0_ISR_ERR_USRCTL_EVT6 BIT(6) 1913#define B_AX_B0_ISR_ERR_USRCTL_EVT5 BIT(5) 1914#define B_AX_B0_ISR_ERR_USRCTL_EVT4 BIT(4) 1915#define B_AX_B0_ISR_ERR_USRCTL_RLSBMPLEN BIT(3) 1916#define B_AX_B0_ISR_ERR_USRCTL_RDNRLSCMD BIT(2) 1917#define B_AX_B0_ISR_ERR_USRCTL_NOINIT BIT(1) 1918#define B_AX_B0_ISR_ERR_USRCTL_REINIT BIT(0) 1919 1920#define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88 1921#define B_AX_B1_PRELD_FEN BIT(31) 1922#define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16) 1923#define PRELD_B1_ENT_NUM 4 1924#define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) 1925#define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) 1926 1927#define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C 1928#define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) 1929#define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) 1930 1931#define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8 1932#define B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(21) 1933#define B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(20) 1934#define B_AX_B1_IMR_ERR_MPDUIF_DATAERR BIT(18) 1935#define B_AX_B1_IMR_ERR_MPDUINFO_RECFG BIT(16) 1936#define B_AX_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11) 1937#define B_AX_B1_IMR_ERR_CMDPSR_FRZTO BIT(10) 1938#define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9) 1939#define B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8) 1940#define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3) 1941#define B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD BIT(2) 1942#define B_AX_B1_IMR_ERR_USRCTL_NOINIT BIT(1) 1943#define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0) 1944#define B_AX_TXPKTCTL_IMR_B1_CLR_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \ 1945 B_AX_B1_IMR_ERR_USRCTL_NOINIT | \ 1946 B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD | \ 1947 B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN | \ 1948 B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \ 1949 B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \ 1950 B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \ 1951 B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \ 1952 B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \ 1953 B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \ 1954 B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ 1955 B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG) 1956#define B_AX_TXPKTCTL_IMR_B1_SET_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \ 1957 B_AX_B1_IMR_ERR_USRCTL_NOINIT | \ 1958 B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \ 1959 B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \ 1960 B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \ 1961 B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \ 1962 B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \ 1963 B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \ 1964 B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ 1965 B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG) 1966 1967#define R_AX_TXPKTCTL_B1_ERRFLAG_ISR 0x9FBC 1968#define B_AX_B1_ISR_ERR_PRELD_EVT3 BIT(23) 1969#define B_AX_B1_ISR_ERR_PRELD_EVT2 BIT(22) 1970#define B_AX_B1_ISR_ERR_PRELD_ENTNUMCFG BIT(21) 1971#define B_AX_B1_ISR_ERR_PRELD_RLSPKTSZERR BIT(20) 1972#define B_AX_B1_ISR_ERR_MPDUIF_ERR1 BIT(19) 1973#define B_AX_B1_ISR_ERR_MPDUIF_DATAERR BIT(18) 1974#define B_AX_B1_ISR_ERR_MPDUINFO_ERR1 BIT(17) 1975#define B_AX_B1_ISR_ERR_MPDUINFO_RECFG BIT(16) 1976#define B_AX_B1_ISR_ERR_CMDPSR_TBLSZ BIT(11) 1977#define B_AX_B1_ISR_ERR_CMDPSR_FRZTO BIT(10) 1978#define B_AX_B1_ISR_ERR_CMDPSR_CMDTYPE BIT(9) 1979#define B_AX_B1_ISR_ERR_CMDPSR_1STCMDERR BIT(8) 1980#define B_AX_B1_ISR_ERR_USRCTL_EVT7 BIT(7) 1981#define B_AX_B1_ISR_ERR_USRCTL_EVT6 BIT(6) 1982#define B_AX_B1_ISR_ERR_USRCTL_EVT5 BIT(5) 1983#define B_AX_B1_ISR_ERR_USRCTL_EVT4 BIT(4) 1984#define B_AX_B1_ISR_ERR_USRCTL_RLSBMPLEN BIT(3) 1985#define B_AX_B1_ISR_ERR_USRCTL_RDNRLSCMD BIT(2) 1986#define B_AX_B1_ISR_ERR_USRCTL_NOINIT BIT(1) 1987#define B_AX_B1_ISR_ERR_USRCTL_REINIT BIT(0) 1988 1989#define R_AX_AFE_CTRL1 0x0024 1990 1991#define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4) 1992#define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3) 1993#define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2) 1994#define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1) 1995#define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0) 1996 1997#define R_AX_SYS_ISO_CTRL_EXTEND 0x0080 1998#define B_AX_CMAC1_FEN BIT(30) 1999#define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17) 2000#define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16) 2001#define B_AX_R_SYM_ISO_CMAC12PP BIT(5) 2002 2003#define R_AX_CMAC_REG_START 0xC000 2004 2005#define R_AX_CMAC_FUNC_EN 0xC000 2006#define R_AX_CMAC_FUNC_EN_C1 0xE000 2007#define B_AX_CMAC_CRPRT BIT(31) 2008#define B_AX_CMAC_EN BIT(30) 2009#define B_AX_CMAC_TXEN BIT(29) 2010#define B_AX_CMAC_RXEN BIT(28) 2011#define B_AX_FORCE_CMACREG_GCKEN BIT(15) 2012#define B_AX_PHYINTF_EN BIT(5) 2013#define B_AX_CMAC_DMA_EN BIT(4) 2014#define B_AX_PTCLTOP_EN BIT(3) 2015#define B_AX_SCHEDULER_EN BIT(2) 2016#define B_AX_TMAC_EN BIT(1) 2017#define B_AX_RMAC_EN BIT(0) 2018 2019#define R_AX_CK_EN 0xC004 2020#define R_AX_CK_EN_C1 0xE004 2021#define B_AX_CMAC_ALLCKEN GENMASK(31, 0) 2022#define B_AX_CMAC_CKEN BIT(30) 2023#define B_AX_PHYINTF_CKEN BIT(5) 2024#define B_AX_CMAC_DMA_CKEN BIT(4) 2025#define B_AX_PTCLTOP_CKEN BIT(3) 2026#define B_AX_SCHEDULER_CKEN BIT(2) 2027#define B_AX_TMAC_CKEN BIT(1) 2028#define B_AX_RMAC_CKEN BIT(0) 2029 2030#define R_AX_WMAC_RFMOD 0xC010 2031#define R_AX_WMAC_RFMOD_C1 0xE010 2032#define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0) 2033#define AX_WMAC_RFMOD_20M 0 2034#define AX_WMAC_RFMOD_40M 1 2035#define AX_WMAC_RFMOD_80M 2 2036#define AX_WMAC_RFMOD_160M 3 2037 2038#define R_AX_GID_POSITION0 0xC070 2039#define R_AX_GID_POSITION0_C1 0xE070 2040#define R_AX_GID_POSITION1 0xC074 2041#define R_AX_GID_POSITION1_C1 0xE074 2042#define R_AX_GID_POSITION2 0xC078 2043#define R_AX_GID_POSITION2_C1 0xE078 2044#define R_AX_GID_POSITION3 0xC07C 2045#define R_AX_GID_POSITION3_C1 0xE07C 2046#define R_AX_GID_POSITION_EN0 0xC080 2047#define R_AX_GID_POSITION_EN0_C1 0xE080 2048#define R_AX_GID_POSITION_EN1 0xC084 2049#define R_AX_GID_POSITION_EN1_C1 0xE084 2050 2051#define R_AX_TX_SUB_CARRIER_VALUE 0xC088 2052#define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088 2053#define B_AX_TXSC_80M_MASK GENMASK(11, 8) 2054#define B_AX_TXSC_40M_MASK GENMASK(7, 4) 2055#define B_AX_TXSC_20M_MASK GENMASK(3, 0) 2056 2057#define R_AX_PTCL_RRSR1 0xC090 2058#define R_AX_PTCL_RRSR1_C1 0xE090 2059#define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8) 2060#define RRSR_OFDM_CCK_EN 3 2061#define B_AX_RSC_MASK GENMASK(7, 6) 2062#define B_AX_RRSR_CCK_MASK GENMASK(3, 0) 2063 2064#define R_AX_CMAC_ERR_IMR 0xC160 2065#define R_AX_CMAC_ERR_IMR_C1 0xE160 2066#define B_AX_WMAC_TX_ERR_IND_EN BIT(7) 2067#define B_AX_WMAC_RX_ERR_IND_EN BIT(6) 2068#define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5) 2069#define B_AX_PHYINTF_ERR_IND_EN BIT(4) 2070#define B_AX_DMA_TOP_ERR_IND_EN BIT(3) 2071#define B_AX_PTCL_TOP_ERR_IND_EN BIT(1) 2072#define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0) 2073#define CMAC0_ERR_IMR_EN GENMASK(31, 0) 2074#define CMAC1_ERR_IMR_EN GENMASK(31, 0) 2075#define CMAC0_ERR_IMR_DIS 0 2076#define CMAC1_ERR_IMR_DIS 0 2077 2078#define R_AX_CMAC_ERR_ISR 0xC164 2079#define R_AX_CMAC_ERR_ISR_C1 0xE164 2080#define B_AX_WMAC_TX_ERR_IND BIT(7) 2081#define B_AX_WMAC_RX_ERR_IND BIT(6) 2082#define B_AX_TXPWR_CTRL_ERR_IND BIT(5) 2083#define B_AX_PHYINTF_ERR_IND BIT(4) 2084#define B_AX_DMA_TOP_ERR_IND BIT(3) 2085#define B_AX_PTCL_TOP_ERR_IND BIT(1) 2086#define B_AX_SCHEDULE_TOP_ERR_IND BIT(0) 2087 2088#define R_AX_PORT0_TSF_SYNC 0xC2A0 2089#define R_AX_PORT0_TSF_SYNC_C1 0xE2A0 2090#define R_AX_PORT1_TSF_SYNC 0xC2A4 2091#define R_AX_PORT1_TSF_SYNC_C1 0xE2A4 2092#define R_AX_PORT2_TSF_SYNC 0xC2A8 2093#define R_AX_PORT2_TSF_SYNC_C1 0xE2A8 2094#define R_AX_PORT3_TSF_SYNC 0xC2AC 2095#define R_AX_PORT3_TSF_SYNC_C1 0xE2AC 2096#define R_AX_PORT4_TSF_SYNC 0xC2B0 2097#define R_AX_PORT4_TSF_SYNC_C1 0xE2B0 2098#define B_AX_SYNC_NOW BIT(30) 2099#define B_AX_SYNC_ONCE BIT(29) 2100#define B_AX_SYNC_AUTO BIT(28) 2101#define B_AX_SYNC_PORT_SRC GENMASK(26, 24) 2102#define B_AX_SYNC_PORT_OFFSET_SIGN BIT(18) 2103#define B_AX_SYNC_PORT_OFFSET_VAL GENMASK(17, 0) 2104 2105#define R_AX_MACID_SLEEP_0 0xC2C0 2106#define R_AX_MACID_SLEEP_0_C1 0xE2C0 2107#define B_AX_MACID31_0_SLEEP_SH 0 2108#define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0) 2109 2110#define R_AX_MACID_SLEEP_1 0xC2C4 2111#define R_AX_MACID_SLEEP_1_C1 0xE2C4 2112#define B_AX_MACID63_32_SLEEP_SH 0 2113#define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0) 2114 2115#define R_AX_MACID_SLEEP_2 0xC2C8 2116#define R_AX_MACID_SLEEP_2_C1 0xE2C8 2117#define B_AX_MACID95_64_SLEEP_SH 0 2118#define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0) 2119 2120#define R_AX_MACID_SLEEP_3 0xC2CC 2121#define R_AX_MACID_SLEEP_3_C1 0xE2CC 2122#define B_AX_MACID127_96_SLEEP_SH 0 2123#define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0) 2124 2125#define SCH_PREBKF_24US 0x18 2126#define R_AX_PREBKF_CFG_0 0xC338 2127#define R_AX_PREBKF_CFG_0_C1 0xE338 2128#define B_AX_PREBKF_TIME_MASK GENMASK(4, 0) 2129 2130#define R_AX_PREBKF_CFG_1 0xC33C 2131#define R_AX_PREBKF_CFG_1_C1 0xE33C 2132#define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24) 2133#define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16) 2134#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8) 2135#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0) 2136#define SIFS_MACTXEN_T1 0x47 2137#define SIFS_MACTXEN_T1_V1 0x41 2138 2139#define R_AX_CCA_CFG_0 0xC340 2140#define R_AX_CCA_CFG_0_C1 0xE340 2141#define B_AX_BTCCA_BRK_TXOP_EN BIT(9) 2142#define B_AX_BTCCA_EN BIT(5) 2143#define B_AX_EDCCA_EN BIT(4) 2144#define B_AX_SEC80_EN BIT(3) 2145#define B_AX_SEC40_EN BIT(2) 2146#define B_AX_SEC20_EN BIT(1) 2147#define B_AX_CCA_EN BIT(0) 2148 2149#define R_AX_CTN_TXEN 0xC348 2150#define R_AX_CTN_TXEN_C1 0xE348 2151#define B_AX_CTN_TXEN_TWT_1 BIT(15) 2152#define B_AX_CTN_TXEN_TWT_0 BIT(14) 2153#define B_AX_CTN_TXEN_ULQ BIT(13) 2154#define B_AX_CTN_TXEN_BCNQ BIT(12) 2155#define B_AX_CTN_TXEN_HGQ BIT(11) 2156#define B_AX_CTN_TXEN_CPUMGQ BIT(10) 2157#define B_AX_CTN_TXEN_MGQ1 BIT(9) 2158#define B_AX_CTN_TXEN_MGQ BIT(8) 2159#define B_AX_CTN_TXEN_VO_1 BIT(7) 2160#define B_AX_CTN_TXEN_VI_1 BIT(6) 2161#define B_AX_CTN_TXEN_BK_1 BIT(5) 2162#define B_AX_CTN_TXEN_BE_1 BIT(4) 2163#define B_AX_CTN_TXEN_VO_0 BIT(3) 2164#define B_AX_CTN_TXEN_VI_0 BIT(2) 2165#define B_AX_CTN_TXEN_BK_0 BIT(1) 2166#define B_AX_CTN_TXEN_BE_0 BIT(0) 2167#define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0) 2168 2169#define R_AX_MUEDCA_BE_PARAM_0 0xC350 2170#define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350 2171#define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16) 2172#define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8) 2173#define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0) 2174 2175#define R_AX_MUEDCA_BK_PARAM_0 0xC354 2176#define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354 2177#define R_AX_MUEDCA_VI_PARAM_0 0xC358 2178#define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358 2179#define R_AX_MUEDCA_VO_PARAM_0 0xC35C 2180#define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C 2181 2182#define R_AX_MUEDCA_EN 0xC370 2183#define R_AX_MUEDCA_EN_C1 0xE370 2184#define B_AX_MUEDCA_WMM_SEL BIT(8) 2185#define B_AX_SET_MUEDCATIMER_TF_0 BIT(4) 2186#define B_AX_MUEDCA_EN_0 BIT(0) 2187 2188#define R_AX_CCA_CONTROL 0xC390 2189#define R_AX_CCA_CONTROL_C1 0xE390 2190#define B_AX_TB_CHK_TX_NAV BIT(31) 2191#define B_AX_TB_CHK_BASIC_NAV BIT(30) 2192#define B_AX_TB_CHK_BTCCA BIT(29) 2193#define B_AX_TB_CHK_EDCCA BIT(28) 2194#define B_AX_TB_CHK_CCA_S80 BIT(27) 2195#define B_AX_TB_CHK_CCA_S40 BIT(26) 2196#define B_AX_TB_CHK_CCA_S20 BIT(25) 2197#define B_AX_TB_CHK_CCA_P20 BIT(24) 2198#define B_AX_SIFS_CHK_BTCCA BIT(21) 2199#define B_AX_SIFS_CHK_EDCCA BIT(20) 2200#define B_AX_SIFS_CHK_CCA_S80 BIT(19) 2201#define B_AX_SIFS_CHK_CCA_S40 BIT(18) 2202#define B_AX_SIFS_CHK_CCA_S20 BIT(17) 2203#define B_AX_SIFS_CHK_CCA_P20 BIT(16) 2204#define B_AX_CTN_CHK_TXNAV BIT(8) 2205#define B_AX_CTN_CHK_INTRA_NAV BIT(7) 2206#define B_AX_CTN_CHK_BASIC_NAV BIT(6) 2207#define B_AX_CTN_CHK_BTCCA BIT(5) 2208#define B_AX_CTN_CHK_EDCCA BIT(4) 2209#define B_AX_CTN_CHK_CCA_S80 BIT(3) 2210#define B_AX_CTN_CHK_CCA_S40 BIT(2) 2211#define B_AX_CTN_CHK_CCA_S20 BIT(1) 2212#define B_AX_CTN_CHK_CCA_P20 BIT(0) 2213 2214#define R_AX_CTN_DRV_TXEN 0xC398 2215#define R_AX_CTN_DRV_TXEN_C1 0xE398 2216#define B_AX_CTN_TXEN_TWT_3 BIT(17) 2217#define B_AX_CTN_TXEN_TWT_2 BIT(16) 2218#define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0) 2219 2220#define R_AX_SCHEDULE_ERR_IMR 0xC3E8 2221#define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8 2222#define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1) 2223 2224#define R_AX_SCHEDULE_ERR_ISR 0xC3EC 2225#define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC 2226 2227#define R_AX_SCH_DBG_SEL 0xC3F4 2228#define R_AX_SCH_DBG_SEL_C1 0xE3F4 2229#define B_AX_SCH_DBG_EN BIT(16) 2230#define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8) 2231#define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0) 2232 2233#define R_AX_SCH_DBG 0xC3F8 2234#define R_AX_SCH_DBG_C1 0xE3F8 2235#define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0) 2236 2237#define R_AX_SCH_EXT_CTRL 0xC3FC 2238#define R_AX_SCH_EXT_CTRL_C1 0xE3FC 2239#define B_AX_PORT_RST_TSF_ADV BIT(1) 2240 2241#define R_AX_PORT_CFG_P0 0xC400 2242#define R_AX_PORT_CFG_P1 0xC440 2243#define R_AX_PORT_CFG_P2 0xC480 2244#define R_AX_PORT_CFG_P3 0xC4C0 2245#define R_AX_PORT_CFG_P4 0xC500 2246#define B_AX_BRK_SETUP BIT(16) 2247#define B_AX_TBTT_UPD_SHIFT_SEL BIT(15) 2248#define B_AX_BCN_DROP_ALLOW BIT(14) 2249#define B_AX_TBTT_PROHIB_EN BIT(13) 2250#define B_AX_BCNTX_EN BIT(12) 2251#define B_AX_NET_TYPE_MASK GENMASK(11, 10) 2252#define B_AX_BCN_FORCETX_EN BIT(9) 2253#define B_AX_TXBCN_BTCCA_EN BIT(8) 2254#define B_AX_BCNERR_CNT_EN BIT(7) 2255#define B_AX_BCN_AGRES BIT(6) 2256#define B_AX_TSFTR_RST BIT(5) 2257#define B_AX_RX_BSSID_FIT_EN BIT(4) 2258#define B_AX_TSF_UDT_EN BIT(3) 2259#define B_AX_PORT_FUNC_EN BIT(2) 2260#define B_AX_TXBCN_RPT_EN BIT(1) 2261#define B_AX_RXBCN_RPT_EN BIT(0) 2262 2263#define R_AX_TBTT_PROHIB_P0 0xC404 2264#define R_AX_TBTT_PROHIB_P1 0xC444 2265#define R_AX_TBTT_PROHIB_P2 0xC484 2266#define R_AX_TBTT_PROHIB_P3 0xC4C4 2267#define R_AX_TBTT_PROHIB_P4 0xC504 2268#define B_AX_TBTT_HOLD_MASK GENMASK(27, 16) 2269#define B_AX_TBTT_SETUP_MASK GENMASK(7, 0) 2270 2271#define R_AX_BCN_AREA_P0 0xC408 2272#define R_AX_BCN_AREA_P1 0xC448 2273#define R_AX_BCN_AREA_P2 0xC488 2274#define R_AX_BCN_AREA_P3 0xC4C8 2275#define R_AX_BCN_AREA_P4 0xC508 2276#define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16) 2277#define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0) 2278 2279#define R_AX_BCNERLYINT_CFG_P0 0xC40C 2280#define R_AX_BCNERLYINT_CFG_P1 0xC44C 2281#define R_AX_BCNERLYINT_CFG_P2 0xC48C 2282#define R_AX_BCNERLYINT_CFG_P3 0xC4CC 2283#define R_AX_BCNERLYINT_CFG_P4 0xC50C 2284#define B_AX_BCNERLY_MASK GENMASK(11, 0) 2285 2286#define R_AX_TBTTERLYINT_CFG_P0 0xC40E 2287#define R_AX_TBTTERLYINT_CFG_P1 0xC44E 2288#define R_AX_TBTTERLYINT_CFG_P2 0xC48E 2289#define R_AX_TBTTERLYINT_CFG_P3 0xC4CE 2290#define R_AX_TBTTERLYINT_CFG_P4 0xC50E 2291#define B_AX_TBTTERLY_MASK GENMASK(11, 0) 2292 2293#define R_AX_TBTT_AGG_P0 0xC412 2294#define R_AX_TBTT_AGG_P1 0xC452 2295#define R_AX_TBTT_AGG_P2 0xC492 2296#define R_AX_TBTT_AGG_P3 0xC4D2 2297#define R_AX_TBTT_AGG_P4 0xC512 2298#define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8) 2299 2300#define R_AX_BCN_SPACE_CFG_P0 0xC414 2301#define R_AX_BCN_SPACE_CFG_P1 0xC454 2302#define R_AX_BCN_SPACE_CFG_P2 0xC494 2303#define R_AX_BCN_SPACE_CFG_P3 0xC4D4 2304#define R_AX_BCN_SPACE_CFG_P4 0xC514 2305#define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16) 2306#define B_AX_BCN_SPACE_MASK GENMASK(15, 0) 2307 2308#define R_AX_BCN_FORCETX_P0 0xC418 2309#define R_AX_BCN_FORCETX_P1 0xC458 2310#define R_AX_BCN_FORCETX_P2 0xC498 2311#define R_AX_BCN_FORCETX_P3 0xC4D8 2312#define R_AX_BCN_FORCETX_P4 0xC518 2313#define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16) 2314#define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0) 2315#define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0) 2316 2317#define R_AX_BCN_ERR_CNT_P0 0xC420 2318#define R_AX_BCN_ERR_CNT_P1 0xC460 2319#define R_AX_BCN_ERR_CNT_P2 0xC4A0 2320#define R_AX_BCN_ERR_CNT_P3 0xC4E0 2321#define R_AX_BCN_ERR_CNT_P4 0xC520 2322#define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24) 2323#define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16) 2324#define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0) 2325#define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0) 2326 2327#define R_AX_BCN_ERR_FLAG_P0 0xC424 2328#define R_AX_BCN_ERR_FLAG_P1 0xC464 2329#define R_AX_BCN_ERR_FLAG_P2 0xC4A4 2330#define R_AX_BCN_ERR_FLAG_P3 0xC4E4 2331#define R_AX_BCN_ERR_FLAG_P4 0xC524 2332#define B_AX_BCN_ERR_FLAG_OTHERS BIT(6) 2333#define B_AX_BCN_ERR_FLAG_MAC BIT(5) 2334#define B_AX_BCN_ERR_FLAG_TXON BIT(4) 2335#define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3) 2336#define B_AX_BCN_ERR_FLAG_INVALID BIT(2) 2337#define B_AX_BCN_ERR_FLAG_CMP BIT(1) 2338#define B_AX_BCN_ERR_FLAG_LOCK BIT(0) 2339 2340#define R_AX_DTIM_CTRL_P0 0xC426 2341#define R_AX_DTIM_CTRL_P1 0xC466 2342#define R_AX_DTIM_CTRL_P2 0xC4A6 2343#define R_AX_DTIM_CTRL_P3 0xC4E6 2344#define R_AX_DTIM_CTRL_P4 0xC526 2345#define B_AX_DTIM_NUM_MASK GENMASK(15, 8) 2346#define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0) 2347 2348#define R_AX_TBTT_SHIFT_P0 0xC428 2349#define R_AX_TBTT_SHIFT_P1 0xC468 2350#define R_AX_TBTT_SHIFT_P2 0xC4A8 2351#define R_AX_TBTT_SHIFT_P3 0xC4E8 2352#define R_AX_TBTT_SHIFT_P4 0xC528 2353#define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0) 2354#define B_AX_TBTT_SHIFT_OFST_SIGN BIT(11) 2355#define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0) 2356 2357#define R_AX_BCN_CNT_TMR_P0 0xC434 2358#define R_AX_BCN_CNT_TMR_P1 0xC474 2359#define R_AX_BCN_CNT_TMR_P2 0xC4B4 2360#define R_AX_BCN_CNT_TMR_P3 0xC4F4 2361#define R_AX_BCN_CNT_TMR_P4 0xC534 2362#define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0) 2363 2364#define R_AX_TSFTR_LOW_P0 0xC438 2365#define R_AX_TSFTR_LOW_P1 0xC478 2366#define R_AX_TSFTR_LOW_P2 0xC4B8 2367#define R_AX_TSFTR_LOW_P3 0xC4F8 2368#define R_AX_TSFTR_LOW_P4 0xC538 2369#define B_AX_TSFTR_LOW_MASK GENMASK(31, 0) 2370 2371#define R_AX_TSFTR_HIGH_P0 0xC43C 2372#define R_AX_TSFTR_HIGH_P1 0xC47C 2373#define R_AX_TSFTR_HIGH_P2 0xC4BC 2374#define R_AX_TSFTR_HIGH_P3 0xC4FC 2375#define R_AX_TSFTR_HIGH_P4 0xC53C 2376#define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0) 2377 2378#define R_AX_MBSSID_CTRL 0xC568 2379#define R_AX_MBSSID_CTRL_C1 0xE568 2380#define B_AX_P0MB_ALL_MASK GENMASK(23, 1) 2381#define B_AX_P0MB_NUM_MASK GENMASK(19, 16) 2382#define B_AX_P0MB15_EN BIT(15) 2383#define B_AX_P0MB14_EN BIT(14) 2384#define B_AX_P0MB13_EN BIT(13) 2385#define B_AX_P0MB12_EN BIT(12) 2386#define B_AX_P0MB11_EN BIT(11) 2387#define B_AX_P0MB10_EN BIT(10) 2388#define B_AX_P0MB9_EN BIT(9) 2389#define B_AX_P0MB8_EN BIT(8) 2390#define B_AX_P0MB7_EN BIT(7) 2391#define B_AX_P0MB6_EN BIT(6) 2392#define B_AX_P0MB5_EN BIT(5) 2393#define B_AX_P0MB4_EN BIT(4) 2394#define B_AX_P0MB3_EN BIT(3) 2395#define B_AX_P0MB2_EN BIT(2) 2396#define B_AX_P0MB1_EN BIT(1) 2397 2398#define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590 2399#define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590 2400#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0 2401#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0 2402 2403#define R_AX_PTCL_COMMON_SETTING_0 0xC600 2404#define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600 2405#define B_AX_PCIE_MODE_MASK GENMASK(15, 14) 2406#define B_AX_CPUMGQ_LIFETIME_EN BIT(8) 2407#define B_AX_MGQ_LIFETIME_EN BIT(7) 2408#define B_AX_LIFETIME_EN BIT(6) 2409#define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4) 2410#define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3) 2411#define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2) 2412#define B_AX_CMAC_TX_MODE_1 BIT(1) 2413#define B_AX_CMAC_TX_MODE_0 BIT(0) 2414 2415#define R_AX_AMPDU_AGG_LIMIT 0xC610 2416#define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24) 2417#define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) 2418#define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) 2419#define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0) 2420 2421#define R_AX_AGG_LEN_HT_0 0xC614 2422#define R_AX_AGG_LEN_HT_0_C1 0xE614 2423#define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) 2424#define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8) 2425#define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0) 2426 2427#define S_AX_CTS2S_TH_SEC_256B 1 2428#define R_AX_SIFS_SETTING 0xC624 2429#define R_AX_SIFS_SETTING_C1 0xE624 2430#define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) 2431#define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) 2432#define B_AX_HW_CTS2SELF_EN BIT(16) 2433#define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8 2434#define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) 2435#define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) 2436#define S_AX_CTS2S_TH_1K 4 2437 2438#define R_AX_TXRATE_CHK 0xC628 2439#define R_AX_TXRATE_CHK_C1 0xE628 2440#define B_AX_DEFT_RATE_MASK GENMASK(15, 7) 2441#define B_AX_BAND_MODE BIT(4) 2442#define B_AX_MAX_TXNSS_MASK GENMASK(3, 2) 2443#define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1) 2444#define B_AX_CHECK_CCK_EN BIT(0) 2445 2446#define R_AX_TXCNT 0xC62C 2447#define R_AX_TXCNT_C1 0xE62C 2448#define B_AX_ADD_TXCNT_BY BIT(31) 2449#define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24) 2450#define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16) 2451 2452#define R_AX_MBSSID_DROP_0 0xC63C 2453#define R_AX_MBSSID_DROP_0_C1 0xE63C 2454#define B_AX_GI_LTF_FB_SEL BIT(30) 2455#define B_AX_RATE_SEL_MASK GENMASK(29, 24) 2456#define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16) 2457#define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0) 2458 2459#define R_AX_PTCLRPT_FULL_HDL 0xC660 2460#define R_AX_PTCLRPT_FULL_HDL_C1 0xE660 2461#define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12) 2462#define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9) 2463#define B_AX_F2PCMD_RPT_EN BIT(8) 2464#define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6) 2465#define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4) 2466#define FWD_TO_WLCPU 1 2467#define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2) 2468#define B_AX_F2PCMDRPT_FULL_DROP BIT(1) 2469#define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0) 2470 2471#define R_AX_BT_PLT 0xC67C 2472#define R_AX_BT_PLT_C1 0xE67C 2473#define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) 2474#define B_AX_BT_PLT_RST BIT(9) 2475#define B_AX_PLT_EN BIT(8) 2476#define B_AX_RX_PLT_GNT_LTE_RX BIT(7) 2477#define B_AX_RX_PLT_GNT_BT_RX BIT(6) 2478#define B_AX_RX_PLT_GNT_BT_TX BIT(5) 2479#define B_AX_RX_PLT_GNT_WL BIT(4) 2480#define B_AX_TX_PLT_GNT_LTE_RX BIT(3) 2481#define B_AX_TX_PLT_GNT_BT_RX BIT(2) 2482#define B_AX_TX_PLT_GNT_BT_TX BIT(1) 2483#define B_AX_TX_PLT_GNT_WL BIT(0) 2484 2485#define R_AX_PTCL_BSS_COLOR_0 0xC6A0 2486#define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0 2487#define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24) 2488#define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16) 2489#define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8) 2490#define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0) 2491 2492#define R_AX_PTCL_BSS_COLOR_1 0xC6A4 2493#define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4 2494#define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0) 2495 2496#define R_AX_PTCL_IMR0 0xC6C0 2497#define R_AX_PTCL_IMR0_C1 0xE6C0 2498#define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31) 2499#define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30) 2500#define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29) 2501#define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28) 2502#define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27) 2503#define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26) 2504#define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25) 2505#define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24) 2506#define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23) 2507#define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15) 2508#define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14) 2509#define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12) 2510#define B_AX_Q_PKTID_ERR_INT_EN BIT(11) 2511#define B_AX_D_PKTID_ERR_INT_EN BIT(10) 2512#define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9) 2513#define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8) 2514#define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1) 2515#define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) 2516#define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0) 2517#define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \ 2518 B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \ 2519 B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \ 2520 B_AX_D_PKTID_ERR_INT_EN | \ 2521 B_AX_Q_PKTID_ERR_INT_EN | \ 2522 B_AX_BCNQ_ORDER_ERR_INT_EN | \ 2523 B_AX_TWTSP_QSEL_ERR_INT_EN | \ 2524 B_AX_F2PCMD_EMPTY_ERR_INT_EN | \ 2525 B_AX_TX_RECORD_PKTID_ERR_INT_EN | \ 2526 B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | \ 2527 B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | \ 2528 B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | \ 2529 B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | \ 2530 B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | \ 2531 B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | \ 2532 B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | \ 2533 B_AX_F2PCMD_PKTID_ERR_INT_EN) 2534#define B_AX_PTCL_IMR_SET (B_AX_FSM_TIMEOUT_ERR_INT_EN | \ 2535 B_AX_TX_RECORD_PKTID_ERR_INT_EN | \ 2536 B_AX_F2PCMD_USER_ALLC_ERR_INT_EN) 2537#define B_AX_PTCL_IMR_CLR_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \ 2538 B_AX_FSM_TIMEOUT_ERR_INT_EN) 2539#define B_AX_PTCL_IMR_SET_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \ 2540 B_AX_FSM_TIMEOUT_ERR_INT_EN) 2541 2542#define R_AX_PTCL_ISR0 0xC6C4 2543#define R_AX_PTCL_ISR0_C1 0xE6C4 2544 2545#define S_AX_PTCL_TO_2MS 0x3F 2546#define R_AX_PTCL_FSM_MON 0xC6E8 2547#define R_AX_PTCL_FSM_MON_C1 0xE6E8 2548#define B_AX_PTCL_TX_ARB_TO_MODE BIT(6) 2549#define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) 2550 2551#define R_AX_PTCL_TX_CTN_SEL 0xC6EC 2552#define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC 2553#define B_AX_PTCL_TX_ON_STAT BIT(7) 2554 2555#define R_AX_PTCL_DBG_INFO 0xC6F0 2556#define R_AX_PTCL_DBG_INFO_C1 0xE6F0 2557#define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0) 2558#define R_AX_PTCL_DBG 0xC6F4 2559#define R_AX_PTCL_DBG_C1 0xE6F4 2560#define B_AX_PTCL_DBG_EN BIT(8) 2561#define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0) 2562 2563#define R_AX_DLE_CTRL 0xC800 2564#define R_AX_DLE_CTRL_C1 0xE800 2565#define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23) 2566#define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15) 2567#define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14) 2568#define B_AX_DLE_IMR_CLR (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \ 2569 B_AX_RXDATA_FSM_HANG_ERROR_IMR | \ 2570 B_AX_NO_RESERVE_PAGE_ERR_IMR) 2571#define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \ 2572 B_AX_RXDATA_FSM_HANG_ERROR_IMR) 2573 2574#define R_AX_RX_ERR_FLAG 0xC800 2575#define R_AX_RX_ERR_FLAG_C1 0xE800 2576#define B_AX_RX_GET_NO_PAGE_ERR BIT(31) 2577#define B_AX_RX_GET_NULL_PKT_ERR BIT(30) 2578#define B_AX_RX_RU0_FSM_HANG_ERR BIT(29) 2579#define B_AX_RX_RU1_FSM_HANG_ERR BIT(28) 2580#define B_AX_RX_RU2_FSM_HANG_ERR BIT(27) 2581#define B_AX_RX_RU3_FSM_HANG_ERR BIT(26) 2582#define B_AX_RX_RU4_FSM_HANG_ERR BIT(25) 2583#define B_AX_RX_RU5_FSM_HANG_ERR BIT(24) 2584#define B_AX_RX_RU6_FSM_HANG_ERR BIT(23) 2585#define B_AX_RX_RU7_FSM_HANG_ERR BIT(22) 2586#define B_AX_RX_RXSTS_FSM_HANG_ERR BIT(21) 2587#define B_AX_RX_CSI_FSM_HANG_ERR BIT(20) 2588#define B_AX_RX_TXRPT_FSM_HANG_ERR BIT(19) 2589#define B_AX_RX_F2PCMD_FSM_HANG_ERR BIT(18) 2590#define B_AX_RX_RU0_ZERO_LEN_ERR BIT(17) 2591#define B_AX_RX_RU1_ZERO_LEN_ERR BIT(16) 2592#define B_AX_RX_RU2_ZERO_LEN_ERR BIT(15) 2593#define B_AX_RX_RU3_ZERO_LEN_ERR BIT(14) 2594#define B_AX_RX_RU4_ZERO_LEN_ERR BIT(13) 2595#define B_AX_RX_RU5_ZERO_LEN_ERR BIT(12) 2596#define B_AX_RX_RU6_ZERO_LEN_ERR BIT(11) 2597#define B_AX_RX_RU7_ZERO_LEN_ERR BIT(10) 2598#define B_AX_RX_RXSTS_ZERO_LEN_ERR BIT(9) 2599#define B_AX_RX_CSI_ZERO_LEN_ERR BIT(8) 2600#define B_AX_PLE_DATA_OPT_FSM_HANG BIT(7) 2601#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG BIT(6) 2602#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG BIT(5) 2603#define B_AX_PLE_WD_OPT_FSM_HANG BIT(4) 2604#define B_AX_PLE_ENQ_FSM_HANG BIT(3) 2605#define B_AX_RXDATA_ENQUE_ORDER_ERR BIT(2) 2606#define B_AX_RXSTS_ENQUE_ORDER_ERR BIT(1) 2607#define B_AX_RX_CSI_PKT_NUM_ERR BIT(0) 2608 2609#define R_AX_RXDMA_CTRL_0 0xC804 2610#define R_AX_RXDMA_CTRL_0_C1 0xE804 2611#define B_AX_RXDMA_DBGOUT_EN BIT(31) 2612#define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29) 2613#define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25) 2614#define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21) 2615#define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19) 2616#define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13) 2617#define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10) 2618#define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9) 2619#define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7) 2620#define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6) 2621#define B_AX_RXSTS_PTR_FULL_MODE BIT(5) 2622#define B_AX_CSI_PTR_FULL_MODE BIT(4) 2623#define B_AX_RU3_PTR_FULL_MODE BIT(3) 2624#define B_AX_RU2_PTR_FULL_MODE BIT(2) 2625#define B_AX_RU1_PTR_FULL_MODE BIT(1) 2626#define B_AX_RU0_PTR_FULL_MODE BIT(0) 2627#define RX_FULL_MODE (B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | \ 2628 B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \ 2629 B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE) 2630 2631#define R_AX_RX_CTRL0 0xC808 2632#define R_AX_RX_CTRL0_C1 0xE808 2633#define B_AX_DLE_CLOCK_FORCE_V1 BIT(31) 2634#define B_AX_TXDMA_CLOCK_FORCE_V1 BIT(30) 2635#define B_AX_RXDMA_CLOCK_FORCE_V1 BIT(29) 2636#define B_AX_RXDMA_DEFAULT_PAGE_V1_MASK GENMASK(28, 24) 2637#define B_AX_RXDMA_CSI_TGT_QUEID_MASK GENMASK(23, 18) 2638#define B_AX_RXDMA_CSI_TGT_PRID_MASK GENMASK(17, 15) 2639#define B_AX_RXDMA_DIS_CSI_RELEASE_V1 BIT(14) 2640#define B_AX_CSI_PTR_FULL_MODE_V1 BIT(13) 2641#define B_AX_RXDATA_PTR_FULL_MODE BIT(12) 2642#define B_AX_RXSTS_PTR_FULL_MODE_V1 BIT(11) 2643#define B_AX_TXRPT_FULL_RSV_DEPTH_V1_MASK GENMASK(10, 8) 2644#define B_AX_RXDATA_FULL_RSV_DEPTH_MASK GENMASK(7, 5) 2645#define B_AX_RXSTS_FULL_RSV_DEPTH_V1_MASK GENMASK(4, 2) 2646#define B_AX_ORDER_FIFO_MASK GENMASK(1, 0) 2647 2648#define R_AX_RX_CTRL1 0xC80C 2649#define R_AX_RX_CTRL1_C1 0xE80C 2650#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_EN BIT(31) 2651#define B_AX_RXDMA_TXRPT_QUEUE_ID_SW_V1_MASK GENMASK(30, 25) 2652#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_EN BIT(24) 2653#define B_AX_RXDMA_F2PCMD_QUEUE_ID_SW_V1_MASK GENMASK(23, 18) 2654#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_EN BIT(17) 2655#define B_AX_RXDMA_TXRPT_QUEUE_ID_TGT_SW_1_MASK GENMASK(16, 11) 2656#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_EN BIT(10) 2657#define B_AX_RXDMA_F2PCMD_QUEUE_ID_TGT_SW_1_MASK GENMASK(9, 4) 2658#define B_AX_ORDER_FIFO_OUT BIT(3) 2659#define B_AX_ORDER_FIFO_EMPTY BIT(2) 2660#define B_AX_DBG_SEL_MASK GENMASK(1, 0) 2661 2662#define R_AX_RX_CTRL2 0xC810 2663#define R_AX_RX_CTRL2_C1 0xE810 2664#define B_AX_DLE_WDE_STATE_V1_MASK GENMASK(31, 30) 2665#define B_AX_DLE_PLE_STATE_V1_MASK GENMASK(29, 28) 2666#define B_AX_DLE_REQ_BUF_STATE_MASK GENMASK(27, 26) 2667#define B_AX_DLE_ENQ_STATE_V1 BIT(25) 2668#define B_AX_RX_DBG_SEL_MASK GENMASK(24, 19) 2669#define B_AX_MACRX_CS_MASK GENMASK(18, 14) 2670#define B_AX_RXSTS_CS_MASK GENMASK(13, 9) 2671#define B_AX_ERR_INDICATOR BIT(5) 2672#define B_AX_TXRPT_CS_MASK GENMASK(4, 0) 2673 2674#define R_AX_RXDMA_PKT_INFO_0 0xC814 2675#define R_AX_RXDMA_PKT_INFO_1 0xC818 2676#define R_AX_RXDMA_PKT_INFO_2 0xC81C 2677 2678#define R_AX_RX_ERR_FLAG_IMR 0xC804 2679#define R_AX_RX_ERR_FLAG_IMR_C1 0xE804 2680#define B_AX_RX_GET_NULL_PKT_ERR_MSK BIT(30) 2681#define B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK BIT(29) 2682#define B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK BIT(28) 2683#define B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK BIT(27) 2684#define B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK BIT(26) 2685#define B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK BIT(25) 2686#define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24) 2687#define B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK BIT(23) 2688#define B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK BIT(22) 2689#define B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK BIT(21) 2690#define B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK BIT(20) 2691#define B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK BIT(19) 2692#define B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK BIT(18) 2693#define B_AX_RX_RU0_ZERO_LEN_ERR_MSK BIT(17) 2694#define B_AX_RX_RU1_ZERO_LEN_ERR_MSK BIT(16) 2695#define B_AX_RX_RU2_ZERO_LEN_ERR_MSK BIT(15) 2696#define B_AX_RX_RU3_ZERO_LEN_ERR_MSK BIT(14) 2697#define B_AX_RX_RU4_ZERO_LEN_ERR_MSK BIT(13) 2698#define B_AX_RX_RU5_ZERO_LEN_ERR_MSK BIT(12) 2699#define B_AX_RX_RU6_ZERO_LEN_ERR_MSK BIT(11) 2700#define B_AX_RX_RU7_ZERO_LEN_ERR_MSK BIT(10) 2701#define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9) 2702#define B_AX_RX_CSI_ZERO_LEN_ERR_MSK BIT(8) 2703#define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7) 2704#define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG_MSK BIT(6) 2705#define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG_MSK BIT(5) 2706#define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4) 2707#define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3) 2708#define B_AX_RXDATA_ENQUE_ORDER_ERR_MSK BIT(2) 2709#define B_AX_RXSTS_ENQUE_ORDER_ERR_MSK BIT(1) 2710#define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0) 2711#define B_AX_RX_ERR_IMR_CLR_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \ 2712 B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \ 2713 B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \ 2714 B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \ 2715 B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \ 2716 B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \ 2717 B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \ 2718 B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \ 2719 B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \ 2720 B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \ 2721 B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \ 2722 B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \ 2723 B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \ 2724 B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \ 2725 B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \ 2726 B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \ 2727 B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \ 2728 B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \ 2729 B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \ 2730 B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \ 2731 B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \ 2732 B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \ 2733 B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \ 2734 B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \ 2735 B_AX_RX_GET_NULL_PKT_ERR_MSK) 2736#define B_AX_RX_ERR_IMR_SET_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \ 2737 B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \ 2738 B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \ 2739 B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \ 2740 B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \ 2741 B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \ 2742 B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \ 2743 B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \ 2744 B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \ 2745 B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \ 2746 B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \ 2747 B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \ 2748 B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \ 2749 B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \ 2750 B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \ 2751 B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \ 2752 B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \ 2753 B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \ 2754 B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \ 2755 B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \ 2756 B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \ 2757 B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \ 2758 B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \ 2759 B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \ 2760 B_AX_RX_GET_NULL_PKT_ERR_MSK) 2761 2762#define R_AX_TX_ERR_FLAG_IMR 0xC870 2763#define R_AX_TX_ERR_FLAG_IMR_C1 0xE870 2764#define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31) 2765#define B_AX_TX_RU1_FSM_HANG_ERR_MSK BIT(30) 2766#define B_AX_TX_RU2_FSM_HANG_ERR_MSK BIT(29) 2767#define B_AX_TX_RU3_FSM_HANG_ERR_MSK BIT(28) 2768#define B_AX_TX_RU4_FSM_HANG_ERR_MSK BIT(27) 2769#define B_AX_TX_RU5_FSM_HANG_ERR_MSK BIT(26) 2770#define B_AX_TX_RU6_FSM_HANG_ERR_MSK BIT(25) 2771#define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24) 2772#define B_AX_TX_RU8_FSM_HANG_ERR_MSK BIT(23) 2773#define B_AX_TX_RU9_FSM_HANG_ERR_MSK BIT(22) 2774#define B_AX_TX_RU10_FSM_HANG_ERR_MSK BIT(21) 2775#define B_AX_TX_RU11_FSM_HANG_ERR_MSK BIT(20) 2776#define B_AX_TX_RU12_FSM_HANG_ERR_MSK BIT(19) 2777#define B_AX_TX_RU13_FSM_HANG_ERR_MSK BIT(18) 2778#define B_AX_TX_RU14_FSM_HANG_ERR_MSK BIT(17) 2779#define B_AX_TX_RU15_FSM_HANG_ERR_MSK BIT(16) 2780#define B_AX_TX_CSI_FSM_HANG_ERR_MSK BIT(15) 2781#define B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK BIT(14) 2782#define B_AX_TX_ERR_IMR_CLR_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \ 2783 B_AX_TX_CSI_FSM_HANG_ERR_MSK | \ 2784 B_AX_TX_RU7_FSM_HANG_ERR_MSK | \ 2785 B_AX_TX_RU6_FSM_HANG_ERR_MSK | \ 2786 B_AX_TX_RU5_FSM_HANG_ERR_MSK | \ 2787 B_AX_TX_RU4_FSM_HANG_ERR_MSK | \ 2788 B_AX_TX_RU3_FSM_HANG_ERR_MSK | \ 2789 B_AX_TX_RU2_FSM_HANG_ERR_MSK | \ 2790 B_AX_TX_RU1_FSM_HANG_ERR_MSK | \ 2791 B_AX_TX_RU0_FSM_HANG_ERR_MSK) 2792#define B_AX_TX_ERR_IMR_SET_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \ 2793 B_AX_TX_CSI_FSM_HANG_ERR_MSK | \ 2794 B_AX_TX_RU7_FSM_HANG_ERR_MSK | \ 2795 B_AX_TX_RU6_FSM_HANG_ERR_MSK | \ 2796 B_AX_TX_RU5_FSM_HANG_ERR_MSK | \ 2797 B_AX_TX_RU4_FSM_HANG_ERR_MSK | \ 2798 B_AX_TX_RU3_FSM_HANG_ERR_MSK | \ 2799 B_AX_TX_RU2_FSM_HANG_ERR_MSK | \ 2800 B_AX_TX_RU1_FSM_HANG_ERR_MSK | \ 2801 B_AX_TX_RU0_FSM_HANG_ERR_MSK) 2802 2803#define R_AX_TCR0 0xCA00 2804#define R_AX_TCR0_C1 0xEA00 2805#define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24) 2806#define B_AX_TCR_UDF_EN BIT(23) 2807#define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16) 2808#define TCR_UDF_THSD 0x6 2809#define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10) 2810#define B_AX_TCR_VHTSIGA1_TXPS BIT(9) 2811#define B_AX_TCR_PLCP_ERRHDL_EN BIT(8) 2812#define B_AX_TCR_PADSEL BIT(7) 2813#define B_AX_TCR_MASK_SIGBCRC BIT(6) 2814#define B_AX_TCR_SR_VAL15_ALLOW BIT(5) 2815#define B_AX_TCR_EN_EOF BIT(4) 2816#define B_AX_TCR_EN_SCRAM_INC BIT(3) 2817#define B_AX_TCR_EN_20MST BIT(2) 2818#define B_AX_TCR_CRC BIT(1) 2819#define B_AX_TCR_DISGCLK BIT(0) 2820 2821#define R_AX_TCR1 0xCA04 2822#define R_AX_TCR1_C1 0xEA04 2823#define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28) 2824#define B_AX_TCR_CCK_LOCK_CLK BIT(27) 2825#define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26) 2826#define B_AX_TCR_USTIME GENMASK(23, 16) 2827#define B_AX_TCR_SMOOTH_VAL BIT(15) 2828#define B_AX_TCR_SMOOTH_CTRL BIT(14) 2829#define B_AX_CS_REQ_VAL BIT(13) 2830#define B_AX_CS_REQ_SEL BIT(12) 2831#define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8) 2832#define B_AX_TCR_TXTIMEOUT GENMASK(7, 0) 2833 2834#define R_AX_MD_TSFT_STMP_CTL 0xCA08 2835#define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08 2836#define B_AX_TSFT_OFS_MASK GENMASK(31, 16) 2837#define B_AX_STMP_THSD_MASK GENMASK(15, 8) 2838#define B_AX_UPD_HGQMD BIT(1) 2839#define B_AX_UPD_TIMIE BIT(0) 2840 2841#define R_AX_PPWRBIT_SETTING 0xCA0C 2842#define R_AX_PPWRBIT_SETTING_C1 0xEA0C 2843 2844#define R_AX_TXD_FIFO_CTRL 0xCA1C 2845#define R_AX_TXD_FIFO_CTRL_C1 0xEA1C 2846#define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24) 2847#define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16) 2848#define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12) 2849#define TXDFIFO_HIGH_MCS_THRE 0x7 2850#define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8) 2851#define TXDFIFO_LOW_MCS_THRE 0x7 2852#define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4) 2853#define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0) 2854 2855#define R_AX_MACTX_DBG_SEL_CNT 0xCA20 2856#define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20 2857#define B_AX_MACTX_MPDU_CNT GENMASK(31, 24) 2858#define B_AX_MACTX_DMA_CNT GENMASK(23, 16) 2859#define B_AX_LENGTH_ERR_FLAG_U3 BIT(11) 2860#define B_AX_LENGTH_ERR_FLAG_U2 BIT(10) 2861#define B_AX_LENGTH_ERR_FLAG_U1 BIT(9) 2862#define B_AX_LENGTH_ERR_FLAG_U0 BIT(8) 2863#define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0) 2864 2865#define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4 2866#define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4 2867#define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0) 2868 2869#define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8 2870#define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8 2871#define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0) 2872 2873#define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC 2874#define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC 2875#define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0) 2876 2877#define R_AX_RSP_CHK_SIG 0xCC00 2878#define R_AX_RSP_CHK_SIG_C1 0xEC00 2879#define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) 2880#define B_AX_RSP_TBPPDU_CHK_PWR BIT(29) 2881#define B_AX_RSP_CHK_BASIC_NAV BIT(21) 2882#define B_AX_RSP_CHK_INTRA_NAV BIT(20) 2883#define B_AX_RSP_CHK_TXNAV BIT(19) 2884#define B_AX_TXDATA_END_PS_OPT BIT(18) 2885#define B_AX_CHECK_SOUNDING_SEQ BIT(17) 2886#define B_AX_RXBA_IGNOREA2 BIT(16) 2887#define B_AX_ACKTO_CCK_MASK GENMASK(15, 8) 2888#define B_AX_ACKTO_MASK GENMASK(7, 0) 2889 2890#define R_AX_TRXPTCL_RESP_0 0xCC04 2891#define R_AX_TRXPTCL_RESP_0_C1 0xEC04 2892#define B_AX_WMAC_RESP_STBC_EN BIT(31) 2893#define B_AX_WMAC_RXFTM_TXACK_SC BIT(30) 2894#define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29) 2895#define B_AX_RSP_CHK_SEC_CCA_80 BIT(28) 2896#define B_AX_RSP_CHK_SEC_CCA_40 BIT(27) 2897#define B_AX_RSP_CHK_SEC_CCA_20 BIT(26) 2898#define B_AX_RSP_CHK_BTCCA BIT(25) 2899#define B_AX_RSP_CHK_EDCCA BIT(24) 2900#define B_AX_RSP_CHK_CCA BIT(23) 2901#define B_AX_WMAC_LDPC_EN BIT(22) 2902#define B_AX_WMAC_SGIEN BIT(21) 2903#define B_AX_WMAC_SPLCPEN BIT(20) 2904#define B_AX_WMAC_BESP_EARLY_TXBA BIT(17) 2905#define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8) 2906#define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) 2907#define WMAC_SPEC_SIFS_OFDM_52A 0x15 2908#define WMAC_SPEC_SIFS_OFDM_52B 0x11 2909#define WMAC_SPEC_SIFS_OFDM_52C 0x11 2910#define WMAC_SPEC_SIFS_CCK 0xA 2911 2912#define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08 2913#define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08 2914#define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31) 2915#define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28) 2916#define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24) 2917#define B_AX_NESS_MASK GENMASK(23, 22) 2918#define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21) 2919#define B_AX_WMAC_RESP_DCM_EN BIT(20) 2920#define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16) 2921#define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12) 2922#define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10) 2923#define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9) 2924#define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0) 2925 2926#define R_AX_MAC_LOOPBACK 0xCC20 2927#define R_AX_MAC_LOOPBACK_C1 0xEC20 2928#define B_AX_MACLBK_EN BIT(0) 2929 2930#define R_AX_WMAC_NAV_CTL 0xCC80 2931#define R_AX_WMAC_NAV_CTL_C1 0xEC80 2932#define B_AX_WMAC_NAV_UPPER_EN BIT(26) 2933#define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18) 2934#define B_AX_WMAC_PLCP_UP_NAV_EN BIT(17) 2935#define B_AX_WMAC_TF_UP_NAV_EN BIT(16) 2936#define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8) 2937#define NAV_12MS 0xBC 2938#define NAV_25MS 0xC4 2939#define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0) 2940 2941#define R_AX_RXTRIG_TEST_USER_2 0xCCB0 2942#define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0 2943#define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24) 2944#define B_AX_RXTRIG_RU26_DIS BIT(21) 2945#define B_AX_RXTRIG_FCSCHK_EN BIT(20) 2946#define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) 2947#define B_AX_RXTRIG_EN BIT(16) 2948#define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) 2949 2950#define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC 2951#define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC 2952#define B_AX_WMAC_MODE BIT(22) 2953#define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16) 2954#define B_AX_RMAC_FTM BIT(8) 2955#define B_AX_RMAC_CSI BIT(7) 2956#define B_AX_TMAC_MIMO_CTRL BIT(6) 2957#define B_AX_TMAC_RXTB BIT(5) 2958#define B_AX_TMAC_HWSIGB_GEN BIT(4) 2959#define B_AX_TMAC_TXPLCP BIT(3) 2960#define B_AX_TMAC_RESP BIT(2) 2961#define B_AX_TMAC_TXCTL BIT(1) 2962#define B_AX_TMAC_MACTX BIT(0) 2963#define B_AX_TMAC_IMR_CLR_V1 (B_AX_TMAC_MACTX | \ 2964 B_AX_TMAC_TXCTL | \ 2965 B_AX_TMAC_RESP | \ 2966 B_AX_TMAC_TXPLCP | \ 2967 B_AX_TMAC_HWSIGB_GEN | \ 2968 B_AX_TMAC_RXTB | \ 2969 B_AX_TMAC_MIMO_CTRL | \ 2970 B_AX_RMAC_CSI | \ 2971 B_AX_RMAC_FTM) 2972#define B_AX_TMAC_IMR_SET_V1 (B_AX_TMAC_MACTX | \ 2973 B_AX_TMAC_TXCTL | \ 2974 B_AX_TMAC_RESP | \ 2975 B_AX_TMAC_TXPLCP | \ 2976 B_AX_TMAC_HWSIGB_GEN | \ 2977 B_AX_TMAC_RXTB | \ 2978 B_AX_TMAC_MIMO_CTRL | \ 2979 B_AX_RMAC_FTM) 2980 2981#define R_AX_TRXPTCL_ERROR_INDICA 0xCCC0 2982#define R_AX_TRXPTCL_ERROR_INDICA_C1 0xECC0 2983#define B_AX_FTM_ERROR_FLAG_CLR BIT(8) 2984#define B_AX_CSI_ERROR_FLAG_CLR BIT(7) 2985#define B_AX_MIMOCTRL_ERROR_FLAG_CLR BIT(6) 2986#define B_AX_RXTB_ERROR_FLAG_CLR BIT(5) 2987#define B_AX_HWSIGB_GEN_ERROR_FLAG_CLR BIT(4) 2988#define B_AX_TXPLCP_ERROR_FLAG_CLR BIT(3) 2989#define B_AX_RESP_ERROR_FLAG_CLR BIT(2) 2990#define B_AX_TXCTL_ERROR_FLAG_CLR BIT(1) 2991#define B_AX_MACTX_ERROR_FLAG_CLR BIT(0) 2992 2993#define R_AX_WMAC_TX_TF_INFO_0 0xCCD0 2994#define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0 2995#define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0) 2996 2997#define R_AX_WMAC_TX_TF_INFO_1 0xCCD4 2998#define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4 2999#define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0) 3000 3001#define R_AX_WMAC_TX_TF_INFO_2 0xCCD8 3002#define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8 3003#define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0) 3004 3005#define R_AX_TMAC_ERR_IMR_ISR 0xCCEC 3006#define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC 3007#define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19) 3008#define B_AX_TMAC_RESP_ERR_CLR BIT(18) 3009#define B_AX_TMAC_TXCTL_ERR_CLR BIT(17) 3010#define B_AX_TMAC_MACTX_ERR_CLR BIT(16) 3011#define B_AX_TMAC_TXPLCP_ERR BIT(14) 3012#define B_AX_TMAC_RESP_ERR BIT(13) 3013#define B_AX_TMAC_TXCTL_ERR BIT(12) 3014#define B_AX_TMAC_MACTX_ERR BIT(11) 3015#define B_AX_TMAC_TXPLCP_INT_EN BIT(10) 3016#define B_AX_TMAC_RESP_INT_EN BIT(9) 3017#define B_AX_TMAC_TXCTL_INT_EN BIT(8) 3018#define B_AX_TMAC_MACTX_INT_EN BIT(7) 3019#define B_AX_WMAC_INT_MODE BIT(6) 3020#define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0) 3021#define B_AX_TMAC_IMR_CLR (B_AX_TMAC_MACTX_INT_EN | \ 3022 B_AX_TMAC_TXCTL_INT_EN | \ 3023 B_AX_TMAC_RESP_INT_EN | \ 3024 B_AX_TMAC_TXPLCP_INT_EN) 3025#define B_AX_TMAC_IMR_SET (B_AX_TMAC_MACTX_INT_EN | \ 3026 B_AX_TMAC_TXCTL_INT_EN | \ 3027 B_AX_TMAC_RESP_INT_EN | \ 3028 B_AX_TMAC_TXPLCP_INT_EN) 3029 3030#define R_AX_DBGSEL_TRXPTCL 0xCCF4 3031#define R_AX_DBGSEL_TRXPTCL_C1 0xECF4 3032#define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0) 3033 3034#define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8 3035#define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8 3036#define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16) 3037#define B_AX_CSI_ON_TIMEOUT_EN BIT(5) 3038#define B_AX_STS_ON_TIMEOUT_EN BIT(4) 3039#define B_AX_DATA_ON_TIMEOUT_EN BIT(3) 3040#define B_AX_OFDM_CCA_TIMEOUT_EN BIT(2) 3041#define B_AX_CCK_CCA_TIMEOUT_EN BIT(1) 3042#define B_AX_PHY_TXON_TIMEOUT_EN BIT(0) 3043#define B_AX_PHYINFO_IMR_CLR_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \ 3044 B_AX_CCK_CCA_TIMEOUT_EN | \ 3045 B_AX_OFDM_CCA_TIMEOUT_EN | \ 3046 B_AX_DATA_ON_TIMEOUT_EN | \ 3047 B_AX_STS_ON_TIMEOUT_EN | \ 3048 B_AX_CSI_ON_TIMEOUT_EN) 3049#define B_AX_PHYINFO_IMR_SET_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \ 3050 B_AX_CCK_CCA_TIMEOUT_EN | \ 3051 B_AX_OFDM_CCA_TIMEOUT_EN | \ 3052 B_AX_DATA_ON_TIMEOUT_EN | \ 3053 B_AX_STS_ON_TIMEOUT_EN | \ 3054 B_AX_CSI_ON_TIMEOUT_EN) 3055 3056#define R_AX_PHYINFO_ERR_IMR 0xCCFC 3057#define R_AX_PHYINFO_ERR_IMR_C1 0xECFC 3058#define B_AX_CSI_ON_TIMEOUT BIT(29) 3059#define B_AX_STS_ON_TIMEOUT BIT(28) 3060#define B_AX_DATA_ON_TIMEOUT BIT(27) 3061#define B_AX_OFDM_CCA_TIMEOUT BIT(26) 3062#define B_AX_CCK_CCA_TIMEOUT BIT(25) 3063#define B_AXC_PHY_TXON_TIMEOUT BIT(24) 3064#define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21) 3065#define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20) 3066#define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19) 3067#define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18) 3068#define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17) 3069#define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16) 3070#define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0) 3071#define B_AX_PHYINFO_IMR_EN_ALL (B_AX_PHY_TXON_TIMEOUT_INT_EN | \ 3072 B_AX_CCK_CCA_TIMEOUT_INT_EN | \ 3073 B_AX_OFDM_CCA_TIMEOUT_INT_EN | \ 3074 B_AX_DATA_ON_TIMEOUT_INT_EN | \ 3075 B_AX_STS_ON_TIMEOUT_INT_EN | \ 3076 B_AX_CSI_ON_TIMEOUT_INT_EN) 3077 3078#define R_AX_PHYINFO_ERR_ISR 0xCCFC 3079#define R_AX_PHYINFO_ERR_ISR_C1 0xECFC 3080 3081#define R_AX_BFMER_CTRL_0 0xCD78 3082#define R_AX_BFMER_CTRL_0_C1 0xED78 3083#define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24) 3084#define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16) 3085#define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8) 3086#define B_AX_BFMER_NDP_BFEN BIT(2) 3087#define B_AX_BFMER_VHT_BFPRT_CHK BIT(0) 3088 3089#define R_AX_BFMEE_RESP_OPTION 0xCD80 3090#define R_AX_BFMEE_RESP_OPTION_C1 0xED80 3091#define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24) 3092#define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20) 3093#define BFRP_RX_STANDBY_TIMER_KEEP 0x0 3094#define BFRP_RX_STANDBY_TIMER_RELEASE 0x1 3095#define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17) 3096#define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16) 3097#define BFRP_RX_STANDBY_TIMER 0x0 3098#define NDP_RX_STANDBY_TIMER 0xFF 3099#define B_AX_BFMEE_HE_NDPA_EN BIT(2) 3100#define B_AX_BFMEE_VHT_NDPA_EN BIT(1) 3101#define B_AX_BFMEE_HT_NDPA_EN BIT(0) 3102 3103#define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88 3104#define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88 3105#define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94 3106#define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94 3107#define B_AX_BFMEE_CSISEQ_SEL BIT(29) 3108#define B_AX_BFMEE_BFPARAM_SEL BIT(28) 3109#define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) 3110#define B_AX_BFMEE_BF_PORT_SEL BIT(23) 3111#define B_AX_BFMEE_USE_NSTS BIT(22) 3112#define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21) 3113#define B_AX_BFMEE_CSI_GID_SEL BIT(20) 3114#define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18) 3115#define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17) 3116#define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16) 3117#define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15) 3118#define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14) 3119#define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13) 3120#define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12) 3121#define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) 3122#define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) 3123#define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) 3124#define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) 3125#define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) 3126 3127#define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C 3128#define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C 3129#define CSI_RRSC_BMAP 0x29292911 3130 3131#define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90 3132#define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90 3133#define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16) 3134#define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8) 3135#define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0) 3136#define CSI_INIT_RATE_HE 0x3 3137#define CSI_INIT_RATE_VHT 0x3 3138#define CSI_INIT_RATE_HT 0x3 3139 3140#define R_AX_RCR 0xCE00 3141#define R_AX_RCR_C1 0xEE00 3142#define B_AX_STOP_RX_IN BIT(11) 3143#define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8) 3144#define B_AX_CH_EN_MASK GENMASK(3, 0) 3145 3146#define R_AX_DLK_PROTECT_CTL 0xCE02 3147#define R_AX_DLK_PROTECT_CTL_C1 0xEE02 3148#define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) 3149#define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) 3150 3151#define R_AX_PLCP_HDR_FLTR 0xCE04 3152#define R_AX_PLCP_HDR_FLTR_C1 0xEE04 3153#define B_AX_DIS_CHK_MIN_LEN BIT(8) 3154#define B_AX_HE_SIGB_CRC_CHK BIT(6) 3155#define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5) 3156#define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4) 3157#define B_AX_SIGA_CRC_CHK BIT(3) 3158#define B_AX_LSIG_PARITY_CHK_EN BIT(2) 3159#define B_AX_CCK_SIG_CHK BIT(1) 3160#define B_AX_CCK_CRC_CHK BIT(0) 3161 3162#define R_AX_RX_FLTR_OPT 0xCE20 3163#define R_AX_RX_FLTR_OPT_C1 0xEE20 3164#define B_AX_UID_FILTER_MASK GENMASK(31, 24) 3165#define B_AX_UNSPT_FILTER_SH 22 3166#define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22) 3167#define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) 3168#define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f 3169#define B_AX_A_FTM_REQ BIT(14) 3170#define B_AX_A_ERR_PKT BIT(13) 3171#define B_AX_A_UNSUP_PKT BIT(12) 3172#define B_AX_A_CRC32_ERR BIT(11) 3173#define B_AX_A_PWR_MGNT BIT(10) 3174#define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8) 3175#define B_AX_A_BCN_CHK_EN BIT(7) 3176#define B_AX_A_MC_LIST_CAM_MATCH BIT(6) 3177#define B_AX_A_BC_CAM_MATCH BIT(5) 3178#define B_AX_A_UC_CAM_MATCH BIT(4) 3179#define B_AX_A_MC BIT(3) 3180#define B_AX_A_BC BIT(2) 3181#define B_AX_A_A1_MATCH BIT(1) 3182#define B_AX_SNIFFER_MODE BIT(0) 3183#define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC | \ 3184 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH | \ 3185 B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ | \ 3186 u32_encode_bits(3, B_AX_UID_FILTER_MASK) | \ 3187 B_AX_A_BCN_CHK_EN) 3188#define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK) 3189 3190#define R_AX_CTRL_FLTR 0xCE24 3191#define R_AX_CTRL_FLTR_C1 0xEE24 3192#define R_AX_MGNT_FLTR 0xCE28 3193#define R_AX_MGNT_FLTR_C1 0xEE28 3194#define R_AX_DATA_FLTR 0xCE2C 3195#define R_AX_DATA_FLTR_C1 0xEE2C 3196#define RX_FLTR_FRAME_DROP 0x00000000 3197#define RX_FLTR_FRAME_TO_HOST 0x55555555 3198#define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA 3199 3200#define R_AX_ADDR_CAM_CTRL 0xCE34 3201#define R_AX_ADDR_CAM_CTRL_C1 0xEE34 3202#define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16) 3203#define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) 3204#define B_AX_ADDR_CAM_CLR BIT(8) 3205#define B_AX_ADDR_CAM_A2_B0_CHK BIT(2) 3206#define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1) 3207#define B_AX_ADDR_CAM_EN BIT(0) 3208 3209#define R_AX_RESPBA_CAM_CTRL 0xCE3C 3210#define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C 3211#define B_AX_SSN_SEL BIT(2) 3212#define B_AX_BACAM_RST_MASK GENMASK(1, 0) 3213#define S_AX_BACAM_RST_ALL 2 3214 3215#define R_AX_PPDU_STAT 0xCE40 3216#define R_AX_PPDU_STAT_C1 0xEE40 3217#define B_AX_PPDU_STAT_RPT_TRIG BIT(8) 3218#define B_AX_PPDU_STAT_RPT_CRC32 BIT(5) 3219#define B_AX_PPDU_STAT_RPT_A1M BIT(4) 3220#define B_AX_APP_PLCP_HDR_RPT BIT(3) 3221#define B_AX_APP_RX_CNT_RPT BIT(2) 3222#define B_AX_APP_MAC_INFO_RPT BIT(1) 3223#define B_AX_PPDU_STAT_RPT_EN BIT(0) 3224 3225#define R_AX_RX_SR_CTRL 0xCE4A 3226#define R_AX_RX_SR_CTRL_C1 0xEE4A 3227#define B_AX_SR_EN BIT(0) 3228 3229#define R_AX_CSIRPT_OPTION 0xCE64 3230#define R_AX_CSIRPT_OPTION_C1 0xEE64 3231#define B_AX_CSIPRT_HESU_AID_EN BIT(25) 3232#define B_AX_CSIPRT_VHTSU_AID_EN BIT(24) 3233 3234#define R_AX_RX_STATE_MONITOR 0xCEF0 3235#define R_AX_RX_STATE_MONITOR_C1 0xEEF0 3236#define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0) 3237#define B_AX_STATE_CUR_MASK GENMASK(31, 16) 3238#define B_AX_STATE_NXT_MASK GENMASK(13, 8) 3239#define B_AX_STATE_UPD BIT(7) 3240#define B_AX_STATE_SEL_MASK GENMASK(4, 0) 3241 3242#define R_AX_RMAC_ERR_ISR 0xCEF4 3243#define R_AX_RMAC_ERR_ISR_C1 0xEEF4 3244#define B_AX_RXERR_INTPS_EN BIT(31) 3245#define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19) 3246#define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18) 3247#define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17) 3248#define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16) 3249#define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15) 3250#define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14) 3251#define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13) 3252#define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12) 3253#define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7) 3254#define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6) 3255#define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5) 3256#define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4) 3257#define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3) 3258#define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2) 3259#define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1) 3260#define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0) 3261#define B_AX_RMAC_IMR_CLR (B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | \ 3262 B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | \ 3263 B_AX_RMAC_DMA_TIMEOUT_INT_EN | \ 3264 B_AX_RMAC_CCA_TIMEOUT_INT_EN | \ 3265 B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | \ 3266 B_AX_RMAC_CSI_TIMEOUT_INT_EN | \ 3267 B_AX_RMAC_RX_TIMEOUT_INT_EN | \ 3268 B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN) 3269#define B_AX_RMAC_IMR_SET (B_AX_RMAC_DMA_TIMEOUT_INT_EN | \ 3270 B_AX_RMAC_CSI_TIMEOUT_INT_EN | \ 3271 B_AX_RMAC_RX_TIMEOUT_INT_EN | \ 3272 B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN) 3273 3274#define R_AX_RX_ERR_IMR 0xCEF8 3275#define R_AX_RX_ERR_IMR_C1 0xEEF8 3276#define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9) 3277#define B_AX_RX_ERR_STS_ACT_TO_MSK BIT(8) 3278#define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7) 3279#define B_AX_RX_ERR_ACT_TO_MSK BIT(6) 3280#define B_AX_CSI_DATAON_ASSERT_TO_MSK BIT(5) 3281#define B_AX_DATAON_ASSERT_TO_MSK BIT(4) 3282#define B_AX_CCA_ASSERT_TO_MSK BIT(3) 3283#define B_AX_RX_ERR_DMA_TO_MSK BIT(2) 3284#define B_AX_RX_ERR_DATA_TO_MSK BIT(1) 3285#define B_AX_RX_ERR_CCA_TO_MSK BIT(0) 3286#define B_AX_RMAC_IMR_CLR_V1 (B_AX_RX_ERR_CCA_TO_MSK | \ 3287 B_AX_RX_ERR_DATA_TO_MSK | \ 3288 B_AX_RX_ERR_DMA_TO_MSK | \ 3289 B_AX_CCA_ASSERT_TO_MSK | \ 3290 B_AX_DATAON_ASSERT_TO_MSK | \ 3291 B_AX_CSI_DATAON_ASSERT_TO_MSK | \ 3292 B_AX_RX_ERR_ACT_TO_MSK | \ 3293 B_AX_RX_ERR_CSI_ACT_TO_MSK | \ 3294 B_AX_RX_ERR_STS_ACT_TO_MSK | \ 3295 B_AX_RX_ERR_TRIG_ACT_TO_MSK) 3296#define B_AX_RMAC_IMR_SET_V1 (B_AX_RX_ERR_CCA_TO_MSK | \ 3297 B_AX_RX_ERR_DATA_TO_MSK | \ 3298 B_AX_RX_ERR_DMA_TO_MSK | \ 3299 B_AX_CCA_ASSERT_TO_MSK | \ 3300 B_AX_DATAON_ASSERT_TO_MSK | \ 3301 B_AX_CSI_DATAON_ASSERT_TO_MSK | \ 3302 B_AX_RX_ERR_ACT_TO_MSK | \ 3303 B_AX_RX_ERR_CSI_ACT_TO_MSK | \ 3304 B_AX_RX_ERR_STS_ACT_TO_MSK | \ 3305 B_AX_RX_ERR_TRIG_ACT_TO_MSK) 3306 3307#define R_AX_RMAC_PLCP_MON 0xCEF8 3308#define R_AX_RMAC_PLCP_MON_C1 0xEEF8 3309#define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0) 3310#define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28) 3311#define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0) 3312 3313#define R_AX_RX_DEBUG_SELECT 0xCEFC 3314#define R_AX_RX_DEBUG_SELECT_C1 0xEEFC 3315#define B_AX_DEBUG_SEL_MASK GENMASK(7, 0) 3316 3317#define R_AX_PWR_RATE_CTRL 0xD200 3318#define R_AX_PWR_RATE_CTRL_C1 0xF200 3319#define B_AX_PWR_REF GENMASK(27, 10) 3320#define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) 3321#define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0) 3322 3323#define R_AX_PWR_RATE_OFST_CTRL 0xD204 3324#define R_AX_PWR_COEXT_CTRL 0xD220 3325#define B_AX_TXAGC_BT_EN BIT(1) 3326#define B_AX_TXAGC_BT_MASK GENMASK(11, 3) 3327 3328#define R_AX_PWR_SWING_OTHER_CTRL0 0xD230 3329#define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230 3330#define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0) 3331 3332#define R_AX_PWR_UL_CTRL0 0xD240 3333#define R_AX_PWR_UL_CTRL2 0xD248 3334#define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0) 3335#define B_AX_PWR_UL_CTRL2_MASK 0x07700007 3336 3337#define R_AX_PWR_NORM_FORCE1 0xD260 3338#define R_AX_PWR_NORM_FORCE1_C1 0xF260 3339#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29) 3340#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24) 3341#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23) 3342#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22) 3343#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21) 3344#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20) 3345#define B_AX_FORCE_BT_GRANT_EN BIT(19) 3346#define B_AX_FORCE_BT_GRANT_VALUE BIT(18) 3347#define B_AX_FORCE_RX_LTE_EN BIT(17) 3348#define B_AX_FORCE_RX_LTE_VALUE BIT(16) 3349#define B_AX_FORCE_TXBF_EN_EN BIT(15) 3350#define B_AX_FORCE_TXBF_EN_VALUE BIT(14) 3351#define B_AX_FORCE_TXSC_EN BIT(13) 3352#define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9) 3353#define B_AX_FORCE_NTX_EN BIT(6) 3354#define B_AX_FORCE_NTX_VALUE BIT(5) 3355#define B_AX_FORCE_PWR_MODE_EN BIT(3) 3356#define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0) 3357 3358#define R_AX_PWR_UL_TB_CTRL 0xD288 3359#define B_AX_PWR_UL_TB_CTRL_EN BIT(31) 3360#define R_AX_PWR_UL_TB_1T 0xD28C 3361#define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0) 3362#define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0) 3363#define R_AX_PWR_UL_TB_2T 0xD290 3364#define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) 3365#define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0) 3366#define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 3367#define R_AX_PWR_BY_RATE_TABLE6 0xD2D8 3368#define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 3369#define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0 3370#define R_AX_PWR_BY_RATE_1SS_MAX R_AX_PWR_BY_RATE_TABLE6 3371#define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10 3372#define R_AX_PWR_LMT_TABLE0 0xD2EC 3373#define R_AX_PWR_LMT_TABLE9 0xD310 3374#define R_AX_PWR_LMT_TABLE19 0xD338 3375#define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0 3376#define R_AX_PWR_LMT_1SS_MAX R_AX_PWR_LMT_TABLE9 3377#define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19 3378#define R_AX_PWR_RU_LMT_TABLE0 0xD33C 3379#define R_AX_PWR_RU_LMT_TABLE5 0xD350 3380#define R_AX_PWR_RU_LMT_TABLE11 0xD368 3381#define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0 3382#define R_AX_PWR_RU_LMT_1SS_MAX R_AX_PWR_RU_LMT_TABLE5 3383#define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11 3384#define R_AX_PWR_MACID_LMT_TABLE0 0xD36C 3385#define R_AX_PWR_MACID_LMT_TABLE127 0xD568 3386 3387#define R_AX_PATH_COM0 0xD800 3388#define AX_PATH_COM0_DFVAL 0x00000000 3389#define AX_PATH_COM0_PATHA 0x08889880 3390#define AX_PATH_COM0_PATHB 0x11111900 3391#define AX_PATH_COM0_PATHAB 0x19999980 3392#define R_AX_PATH_COM1 0xD804 3393#define AX_PATH_COM1_DFVAL 0x00000000 3394#define AX_PATH_COM1_PATHA 0x13111111 3395#define AX_PATH_COM1_PATHB 0x23222222 3396#define AX_PATH_COM1_PATHAB 0x33333333 3397#define R_AX_PATH_COM2 0xD808 3398#define AX_PATH_COM2_DFVAL 0x00000000 3399#define AX_PATH_COM2_PATHA 0x01209313 3400#define AX_PATH_COM2_PATHB 0x01209323 3401#define AX_PATH_COM2_PATHAB 0x01209333 3402#define R_AX_PATH_COM3 0xD80C 3403#define AX_PATH_COM3_DFVAL 0x49249249 3404#define R_AX_PATH_COM4 0xD810 3405#define AX_PATH_COM4_DFVAL 0x1C9C9C49 3406#define R_AX_PATH_COM5 0xD814 3407#define AX_PATH_COM5_DFVAL 0x39393939 3408#define R_AX_PATH_COM6 0xD818 3409#define AX_PATH_COM6_DFVAL 0x39393939 3410#define R_AX_PATH_COM7 0xD81C 3411#define AX_PATH_COM7_DFVAL 0x39393939 3412#define AX_PATH_COM7_PATHA 0x39393939 3413#define AX_PATH_COM7_PATHB 0x39383939 3414#define AX_PATH_COM7_PATHAB 0x39393939 3415#define R_AX_PATH_COM8 0xD820 3416#define AX_PATH_COM8_DFVAL 0x00000000 3417#define AX_PATH_COM8_PATHA 0x00003939 3418#define AX_PATH_COM8_PATHB 0x00003938 3419#define AX_PATH_COM8_PATHAB 0x00003939 3420#define R_AX_PATH_COM9 0xD824 3421#define AX_PATH_COM9_DFVAL 0x000007C0 3422#define R_AX_PATH_COM10 0xD828 3423#define AX_PATH_COM10_DFVAL 0xE0000000 3424#define R_AX_PATH_COM11 0xD82C 3425#define AX_PATH_COM11_DFVAL 0x00000000 3426#define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848 3427#define B_P80_AT_HIGH_FREQ_BB_WRP BIT(28) 3428#define R_AX_TSSI_CTRL_HEAD 0xD908 3429#define R_AX_BANDEDGE_CFG 0xD94C 3430#define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30) 3431#define R_AX_TSSI_CTRL_TAIL 0xD95C 3432 3433#define R_AX_TXPWR_IMR 0xD9E0 3434#define R_AX_TXPWR_IMR_C1 0xF9E0 3435#define R_AX_TXPWR_ISR 0xD9E4 3436#define R_AX_TXPWR_ISR_C1 0xF9E4 3437 3438#define R_AX_BTC_CFG 0xDA00 3439#define B_AX_BTC_EN BIT(31) 3440#define B_AX_EN_EXT_BT_PINMUX BIT(29) 3441#define B_AX_BTC_RST BIT(28) 3442#define B_AX_BTC_DBG_SRC_SEL BIT(27) 3443#define B_AX_BTC_MODE_MASK GENMASK(25, 24) 3444#define B_AX_INV_WL_ACT2 BIT(17) 3445#define B_AX_BTG_LNA1_GAIN_SEL BIT(16) 3446#define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8) 3447#define B_AX_IGN_GNT_BT2_RX BIT(7) 3448#define B_AX_IGN_GNT_BT2_TX BIT(6) 3449#define B_AX_IGN_GNT_BT2 BIT(5) 3450#define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3) 3451#define B_AX_DIS_BTC_CLK_G BIT(2) 3452#define B_AX_GNT_WL_RX_CTRL BIT(1) 3453#define B_AX_WL_SRC BIT(0) 3454 3455#define R_AX_RTK_MODE_CFG_V1 0xDA04 3456#define R_AX_RTK_MODE_CFG_V1_C1 0xFA04 3457#define B_AX_BT_BLE_EN_V1 BIT(24) 3458#define B_AX_BT_ULTRA_EN BIT(16) 3459#define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14) 3460#define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12) 3461#define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10) 3462#define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8) 3463#define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0) 3464 3465#define R_AX_WL_PRI_MSK 0xDA10 3466#define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8) 3467 3468#define R_AX_BT_CNT_CFG 0xDA10 3469#define R_AX_BT_CNT_CFG_C1 0xFA10 3470#define B_AX_BT_CNT_RST_V1 BIT(1) 3471#define B_AX_BT_CNT_EN BIT(0) 3472 3473#define R_BTC_BT_CNT_HIGH 0xDA14 3474#define R_BTC_BT_CNT_LOW 0xDA18 3475 3476#define R_AX_BTC_FUNC_EN 0xDA20 3477#define R_AX_BTC_FUNC_EN_C1 0xFA20 3478#define B_AX_PTA_WL_TX_EN BIT(1) 3479#define B_AX_PTA_EDCCA_EN BIT(0) 3480 3481#define R_BTC_COEX_WL_REQ 0xDA24 3482#define B_BTC_TX_BCN_HI BIT(22) 3483#define B_BTC_RSP_ACK_HI BIT(10) 3484 3485#define R_BTC_BREAK_TABLE 0xDA2C 3486#define BTC_BREAK_PARAM 0xf0ffffff 3487 3488#define R_BTC_BT_COEX_MSK_TABLE 0xDA30 3489#define B_BTC_PRI_MASK_RXCCK_V1 BIT(28) 3490#define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) 3491 3492#define R_AX_BT_COEX_CFG_2 0xDA34 3493#define R_AX_BT_COEX_CFG_2_C1 0xFA34 3494#define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12) 3495#define B_AX_GNT_BT_POLARITY BIT(8) 3496#define B_AX_TIMER_MASK GENMASK(7, 0) 3497#define MAC_AX_CSR_RATE 80 3498 3499#define R_AX_CSR_MODE 0xDA40 3500#define R_AX_CSR_MODE_C1 0xFA40 3501#define B_AX_BT_CNT_RST BIT(16) 3502#define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12) 3503#define MAC_AX_CSR_DELAY 0 3504#define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8) 3505#define MAC_AX_CSR_TRX_TO 4 3506#define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4) 3507#define MAC_AX_CSR_PRI_TO 5 3508#define B_AX_WL_ACT_MSK BIT(3) 3509#define B_AX_STATIS_BT_EN BIT(2) 3510#define B_AX_WL_ACT_MASK_ENABLE BIT(1) 3511#define B_AX_ENHANCED_BT BIT(0) 3512 3513#define R_AX_BT_BREAK_TABLE 0xDA44 3514 3515#define R_AX_BT_STAST_HIGH 0xDA44 3516#define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16) 3517#define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0) 3518#define R_AX_BT_STAST_LOW 0xDA48 3519#define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0) 3520#define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16) 3521 3522#define R_AX_GNT_SW_CTRL 0xDA48 3523#define R_AX_GNT_SW_CTRL_C1 0xFA48 3524#define B_AX_WL_ACT2_VAL BIT(21) 3525#define B_AX_WL_ACT2_SWCTRL BIT(20) 3526#define B_AX_WL_ACT_VAL BIT(19) 3527#define B_AX_WL_ACT_SWCTRL BIT(18) 3528#define B_AX_GNT_BT_RX_VAL BIT(17) 3529#define B_AX_GNT_BT_RX_SWCTRL BIT(16) 3530#define B_AX_GNT_BT_TX_VAL BIT(15) 3531#define B_AX_GNT_BT_TX_SWCTRL BIT(14) 3532#define B_AX_GNT_WL_RX_VAL BIT(13) 3533#define B_AX_GNT_WL_RX_SWCTRL BIT(12) 3534#define B_AX_GNT_WL_TX_VAL BIT(11) 3535#define B_AX_GNT_WL_TX_SWCTRL BIT(10) 3536#define B_AX_GNT_BT_RFC_S1_VAL BIT(9) 3537#define B_AX_GNT_BT_RFC_S1_SWCTRL BIT(8) 3538#define B_AX_GNT_WL_RFC_S1_VAL BIT(7) 3539#define B_AX_GNT_WL_RFC_S1_SWCTRL BIT(6) 3540#define B_AX_GNT_BT_RFC_S0_VAL BIT(5) 3541#define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4) 3542#define B_AX_GNT_WL_RFC_S0_VAL BIT(3) 3543#define B_AX_GNT_WL_RFC_S0_SWCTRL BIT(2) 3544#define B_AX_GNT_WL_BB_VAL BIT(1) 3545#define B_AX_GNT_WL_BB_SWCTRL BIT(0) 3546 3547#define R_AX_GNT_VAL 0x0054 3548#define B_AX_GNT_BT_RFC_S1_STA BIT(5) 3549#define B_AX_GNT_WL_RFC_S1_STA BIT(4) 3550#define B_AX_GNT_BT_RFC_S0_STA BIT(3) 3551#define B_AX_GNT_WL_RFC_S0_STA BIT(2) 3552 3553#define R_AX_GNT_VAL_V1 0xDA4C 3554#define B_AX_GNT_BT_RFC_S1 BIT(4) 3555#define B_AX_GNT_BT_RFC_S0 BIT(3) 3556#define B_AX_GNT_WL_RFC_S1 BIT(2) 3557#define B_AX_GNT_WL_RFC_S0 BIT(1) 3558 3559#define R_AX_TDMA_MODE 0xDA4C 3560#define R_AX_TDMA_MODE_C1 0xFA4C 3561#define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16) 3562#define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8) 3563#define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6) 3564#define B_AX_TDMA_BT_START_NOTIFY BIT(5) 3565#define B_AX_ENABLE_TDMA_FW_MODE BIT(4) 3566#define B_AX_ENABLE_PTA_TDMA_MODE BIT(3) 3567#define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) 3568#define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) 3569#define B_AX_RTK_BT_ENABLE BIT(0) 3570 3571#define R_AX_BT_COEX_CFG_5 0xDA6C 3572#define R_AX_BT_COEX_CFG_5_C1 0xFA6C 3573#define B_AX_BT_TIME_MASK GENMASK(31, 6) 3574#define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0) 3575#define MAC_AX_RTK_RATE 5 3576 3577#define R_AX_LTE_CTRL 0xDAF0 3578#define R_AX_LTE_WDATA 0xDAF4 3579#define R_AX_LTE_RDATA 0xDAF8 3580 3581#define R_AX_MACID_ANT_TABLE 0xDC00 3582#define R_AX_MACID_ANT_TABLE_LAST 0xDDFC 3583 3584#define CMAC1_START_ADDR 0xE000 3585#define CMAC1_END_ADDR 0xFFFF 3586#define R_AX_CMAC_REG_END 0xFFFF 3587 3588#define R_AX_LTE_SW_CFG_1 0x0038 3589#define R_AX_LTE_SW_CFG_1_C1 0x2038 3590#define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31) 3591#define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30) 3592#define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29) 3593#define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28) 3594#define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27) 3595#define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26) 3596#define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25) 3597#define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24) 3598#define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19) 3599#define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18) 3600#define B_AX_LTE_PATTERN_2_EN BIT(17) 3601#define B_AX_LTE_PATTERN_1_EN BIT(16) 3602#define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15) 3603#define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14) 3604#define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13) 3605#define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12) 3606#define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11) 3607#define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10) 3608#define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9) 3609#define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8) 3610#define B_AX_LTECOEX_FUN_EN BIT(7) 3611#define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6) 3612#define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4) 3613#define B_AX_LTECOEX_UART_MUX BIT(3) 3614#define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0) 3615 3616#define R_AX_LTE_SW_CFG_2 0x003C 3617#define R_AX_LTE_SW_CFG_2_C1 0x203C 3618#define B_AX_WL_RX_CTRL BIT(8) 3619#define B_AX_GNT_WL_RX_SW_VAL BIT(7) 3620#define B_AX_GNT_WL_RX_SW_CTRL BIT(6) 3621#define B_AX_GNT_WL_TX_SW_VAL BIT(5) 3622#define B_AX_GNT_WL_TX_SW_CTRL BIT(4) 3623#define B_AX_GNT_BT_RX_SW_VAL BIT(3) 3624#define B_AX_GNT_BT_RX_SW_CTRL BIT(2) 3625#define B_AX_GNT_BT_TX_SW_VAL BIT(1) 3626#define B_AX_GNT_BT_TX_SW_CTRL BIT(0) 3627 3628#define RR_MOD 0x00 3629#define RR_MOD_V1 0x10000 3630#define RR_MOD_IQK GENMASK(19, 4) 3631#define RR_MOD_DPK GENMASK(19, 5) 3632#define RR_MOD_MASK GENMASK(19, 16) 3633#define RR_MOD_DCK GENMASK(14, 10) 3634#define RR_MOD_RGM GENMASK(13, 4) 3635#define RR_MOD_RXB GENMASK(9, 5) 3636#define RR_MOD_V_DOWN 0x0 3637#define RR_MOD_V_STANDBY 0x1 3638#define RR_TXAGC 0x10001 3639#define RR_MOD_V_TX 0x2 3640#define RR_MOD_V_RX 0x3 3641#define RR_MOD_V_TXIQK 0x4 3642#define RR_MOD_V_DPK 0x5 3643#define RR_MOD_V_RXK1 0x6 3644#define RR_MOD_V_RXK2 0x7 3645#define RR_MOD_NBW GENMASK(15, 14) 3646#define RR_MOD_M_RXG GENMASK(13, 4) 3647#define RR_MOD_M_RXBB GENMASK(9, 5) 3648#define RR_MOD_LO_SEL BIT(1) 3649#define RR_MODOPT 0x01 3650#define RR_MODOPT_M_TXPWR GENMASK(5, 0) 3651#define RR_WLSEL 0x02 3652#define RR_WLSEL_AG GENMASK(18, 16) 3653#define RR_RSV1 0x05 3654#define RR_RSV1_RST BIT(0) 3655#define RR_BBDC 0x10005 3656#define RR_BBDC_SEL BIT(0) 3657#define RR_DTXLOK 0x08 3658#define RR_RSV2 0x09 3659#define RR_LOKVB 0x0a 3660#define RR_LOKVB_COI GENMASK(19, 14) 3661#define RR_LOKVB_COQ GENMASK(9, 4) 3662#define RR_TXIG 0x11 3663#define RR_TXIG_TG GENMASK(16, 12) 3664#define RR_TXIG_GR1 GENMASK(6, 4) 3665#define RR_TXIG_GR0 GENMASK(1, 0) 3666#define RR_CHTR 0x17 3667#define RR_CHTR_MOD GENMASK(11, 10) 3668#define RR_CHTR_TXRX GENMASK(9, 0) 3669#define RR_CFGCH 0x18 3670#define RR_CFGCH_V1 0x10018 3671#define RR_CFGCH_BAND1 GENMASK(17, 16) 3672#define CFGCH_BAND1_2G 0 3673#define CFGCH_BAND1_5G 1 3674#define CFGCH_BAND1_6G 3 3675#define RR_CFGCH_POW_LCK BIT(15) 3676#define RR_CFGCH_TRX_AH BIT(14) 3677#define RR_CFGCH_BCN BIT(13) 3678#define RR_CFGCH_BW2 BIT(12) 3679#define RR_CFGCH_BAND0 GENMASK(9, 8) 3680#define CFGCH_BAND0_2G 0 3681#define CFGCH_BAND0_5G 1 3682#define CFGCH_BAND0_6G 0 3683#define RR_CFGCH_BW GENMASK(11, 10) 3684#define RR_CFGCH_CH GENMASK(7, 0) 3685#define CFGCH_BW_20M 3 3686#define CFGCH_BW_40M 2 3687#define CFGCH_BW_80M 1 3688#define CFGCH_BW_160M 0 3689#define RR_APK 0x19 3690#define RR_APK_MOD GENMASK(5, 4) 3691#define RR_BTC 0x1a 3692#define RR_BTC_TXBB GENMASK(14, 12) 3693#define RR_BTC_RXBB GENMASK(11, 10) 3694#define RR_RCKC 0x1b 3695#define RR_RCKC_CA GENMASK(14, 10) 3696#define RR_RCKS 0x1c 3697#define RR_RCKO 0x1d 3698#define RR_RCKO_OFF GENMASK(13, 9) 3699#define RR_RXKPLL 0x1e 3700#define RR_RXKPLL_OFF GENMASK(5, 0) 3701#define RR_RXKPLL_POW BIT(19) 3702#define RR_RSV4 0x1f 3703#define RR_RSV4_AGH GENMASK(17, 16) 3704#define RR_RSV4_PLLCH GENMASK(9, 0) 3705#define RR_RXK 0x20 3706#define RR_RXK_SEL2G BIT(8) 3707#define RR_RXK_SEL5G BIT(7) 3708#define RR_RXK_PLLEN BIT(5) 3709#define RR_LUTWA 0x33 3710#define RR_LUTWA_MASK GENMASK(9, 0) 3711#define RR_LUTWA_M1 GENMASK(7, 0) 3712#define RR_LUTWA_M2 GENMASK(4, 0) 3713#define RR_LUTWD1 0x3e 3714#define RR_LUTWD0 0x3f 3715#define RR_LUTWD0_MB GENMASK(11, 6) 3716#define RR_LUTWD0_LB GENMASK(5, 0) 3717#define RR_TM 0x42 3718#define RR_TM_TRI BIT(19) 3719#define RR_TM_VAL GENMASK(6, 1) 3720#define RR_TM2 0x43 3721#define RR_TM2_OFF GENMASK(19, 16) 3722#define RR_TXG1 0x51 3723#define RR_TXG1_ATT2 BIT(19) 3724#define RR_TXG1_ATT1 BIT(11) 3725#define RR_TXG2 0x52 3726#define RR_TXG2_ATT0 BIT(11) 3727#define RR_BSPAD 0x54 3728#define RR_TXGA 0x55 3729#define RR_TXGA_TRK_EN BIT(7) 3730#define RR_TXGA_LOK_EXT GENMASK(4, 0) 3731#define RR_TXGA_LOK_EN BIT(0) 3732#define RR_TXGA_V1 0x10055 3733#define RR_TXGA_V1_TRK_EN BIT(7) 3734#define RR_GAINTX 0x56 3735#define RR_GAINTX_ALL GENMASK(15, 0) 3736#define RR_GAINTX_PAD GENMASK(9, 5) 3737#define RR_GAINTX_BB GENMASK(4, 0) 3738#define RR_TXMO 0x58 3739#define RR_TXMO_COI GENMASK(19, 15) 3740#define RR_TXMO_COQ GENMASK(14, 10) 3741#define RR_TXMO_FII GENMASK(9, 6) 3742#define RR_TXMO_FIQ GENMASK(5, 2) 3743#define RR_TXA 0x5d 3744#define RR_TXA_TRK GENMASK(19, 14) 3745#define RR_TXRSV 0x5c 3746#define RR_TXRSV_GAPK BIT(19) 3747#define RR_BIAS 0x5e 3748#define RR_BIAS_GAPK BIT(19) 3749#define RR_TXAC 0x5f 3750#define RR_TXAC_IQG GENMASK(3, 0) 3751#define RR_BIASA 0x60 3752#define RR_BIASA_TXG GENMASK(15, 12) 3753#define RR_BIASA_TXA GENMASK(19, 16) 3754#define RR_BIASA_A GENMASK(2, 0) 3755#define RR_BIASA2 0x63 3756#define RR_BIASA2_LB GENMASK(4, 2) 3757#define RR_TXATANK 0x64 3758#define RR_TXATANK_LBSW2 GENMASK(17, 15) 3759#define RR_TXATANK_LBSW GENMASK(16, 15) 3760#define RR_TXA2 0x65 3761#define RR_TXA2_LDO GENMASK(19, 16) 3762#define RR_TRXIQ 0x66 3763#define RR_RSV6 0x6d 3764#define RR_TXVBUF 0x7c 3765#define RR_TXVBUF_DACEN BIT(5) 3766#define RR_TXPOW 0x7f 3767#define RR_TXPOW_TXA BIT(8) 3768#define RR_TXPOW_TXAS BIT(7) 3769#define RR_TXPOW_TXG BIT(1) 3770#define RR_RXPOW 0x80 3771#define RR_RXPOW_IQK GENMASK(17, 16) 3772#define RR_RXBB 0x83 3773#define RR_RXBB_VOBUF GENMASK(15, 12) 3774#define RR_RXBB_C2G GENMASK(16, 10) 3775#define RR_RXBB_C2 GENMASK(11, 8) 3776#define RR_RXBB_C1G GENMASK(9, 8) 3777#define RR_RXBB_FATT GENMASK(7, 0) 3778#define RR_RXBB_ATTR GENMASK(7, 4) 3779#define RR_RXBB_ATTC GENMASK(2, 0) 3780#define RR_RXG 0x84 3781#define RR_RXG_IQKMOD GENMASK(19, 16) 3782#define RR_XGLNA2 0x85 3783#define RR_XGLNA2_SW GENMASK(1, 0) 3784#define RR_RXAE 0x89 3785#define RR_RXAE_IQKMOD GENMASK(3, 0) 3786#define RR_RXA 0x8a 3787#define RR_RXA_DPK GENMASK(9, 8) 3788#define RR_RXA_LNA 0x8b 3789#define RR_RXA2 0x8c 3790#define RR_RAA2_SATT GENMASK(15, 13) 3791#define RR_RAA2_SWATT GENMASK(15, 9) 3792#define RR_RXA2_C1 GENMASK(12, 10) 3793#define RR_RXA2_C2 GENMASK(9, 3) 3794#define RR_RXA2_CC2 GENMASK(8, 7) 3795#define RR_RXA2_IATT GENMASK(7, 4) 3796#define RR_RXA2_HATT GENMASK(6, 0) 3797#define RR_RXA2_ATT GENMASK(3, 0) 3798#define RR_RXIQGEN 0x8d 3799#define RR_RXIQGEN_ATTL GENMASK(12, 8) 3800#define RR_RXIQGEN_ATTH GENMASK(14, 13) 3801#define RR_RXBB2 0x8f 3802#define RR_RXBB2_DAC_EN BIT(13) 3803#define RR_RXBB2_CKT BIT(12) 3804#define RR_EN_TIA_IDA GENMASK(11, 10) 3805#define RR_RXBB2_IDAC GENMASK(11, 9) 3806#define RR_RXBB2_EBW GENMASK(6, 5) 3807#define RR_XALNA2 0x90 3808#define RR_XALNA2_SW2 GENMASK(9, 8) 3809#define RR_XALNA2_SW GENMASK(1, 0) 3810#define RR_DCK 0x92 3811#define RR_DCK_S1 GENMASK(19, 16) 3812#define RR_DCK_TIA GENMASK(15, 9) 3813#define RR_DCK_DONE GENMASK(7, 5) 3814#define RR_DCK_FINE BIT(1) 3815#define RR_DCK_LV BIT(0) 3816#define RR_DCK1 0x93 3817#define RR_DCK1_S1 GENMASK(19, 16) 3818#define RR_DCK1_TIA GENMASK(15, 9) 3819#define RR_DCK1_DONE BIT(5) 3820#define RR_DCK1_CLR GENMASK(3, 0) 3821#define RR_DCK1_SEL BIT(3) 3822#define RR_DCK2 0x94 3823#define RR_DCK2_CYCLE GENMASK(7, 2) 3824#define RR_DCKC 0x95 3825#define RR_DCKC_CHK BIT(3) 3826#define RR_IQGEN 0x97 3827#define RR_IQGEN_BIAS GENMASK(11, 8) 3828#define RR_TXIQK 0x98 3829#define RR_TXIQK_ATT2 GENMASK(15, 12) 3830#define RR_TXIQK_ATT1 GENMASK(6, 0) 3831#define RR_TIA 0x9e 3832#define RR_TIA_N6 BIT(8) 3833#define RR_MIXER 0x9f 3834#define RR_MIXER_GN GENMASK(4, 3) 3835#define RR_POW 0xa0 3836#define RR_POW_SYN GENMASK(3, 2) 3837#define RR_LOGEN 0xa3 3838#define RR_LOGEN_RPT GENMASK(19, 16) 3839#define RR_SX 0xaf 3840#define RR_IBD 0xc9 3841#define RR_IBD_VAL GENMASK(4, 0) 3842#define RR_LDO 0xb1 3843#define RR_LDO_SEL GENMASK(8, 6) 3844#define RR_VCO 0xb2 3845#define RR_VCO_SEL GENMASK(9, 8) 3846#define RR_VCI 0xb3 3847#define RR_VCI_ON BIT(7) 3848#define RR_LPF 0xb7 3849#define RR_LPF_BUSY BIT(8) 3850#define RR_XTALX2 0xb8 3851#define RR_MALSEL 0xbe 3852#define RR_SYNFB 0xc5 3853#define RR_SYNFB_LK BIT(15) 3854#define RR_AACK 0xca 3855#define RR_LCKST 0xcf 3856#define RR_LCKST_BIN BIT(0) 3857#define RR_LCK_TRG 0xd3 3858#define RR_LCK_TRGSEL BIT(8) 3859#define RR_LCK_ST BIT(4) 3860#define RR_MMD 0xd5 3861#define RR_MMD_RST_EN BIT(8) 3862#define RR_MMD_RST_SYN BIT(6) 3863#define RR_IQKPLL 0xdc 3864#define RR_IQKPLL_MOD GENMASK(9, 8) 3865#define RR_SYNLUT 0xdd 3866#define RR_SYNLUT_MOD BIT(4) 3867#define RR_RCKD 0xde 3868#define RR_RCKD_POW GENMASK(19, 13) 3869#define RR_RCKD_BW BIT(2) 3870#define RR_TXADBG 0xde 3871#define RR_LUTDBG 0xdf 3872#define RR_LUTDBG_TIA BIT(12) 3873#define RR_LUTDBG_LOK BIT(2) 3874#define RR_LUTPLL 0xec 3875#define RR_CAL_RW BIT(19) 3876#define RR_LUTWE2 0xee 3877#define RR_LUTWE2_RTXBW BIT(2) 3878#define RR_LUTWE2_DIS BIT(6) 3879#define RR_LUTWE 0xef 3880#define RR_LUTWE_LOK BIT(2) 3881#define RR_RFC 0xf0 3882#define RR_WCAL BIT(16) 3883#define RR_RFC_CKEN BIT(1) 3884 3885#define R_UPD_P0 0x0000 3886#define R_RSTB_WATCH_DOG 0x000C 3887#define B_P0_RSTB_WATCH_DOG BIT(0) 3888#define B_P1_RSTB_WATCH_DOG BIT(1) 3889#define B_UPD_P0_EN BIT(31) 3890#define R_ANAPAR_PW15 0x030C 3891#define B_ANAPAR_PW15 GENMASK(31, 24) 3892#define B_ANAPAR_PW15_H GENMASK(27, 24) 3893#define B_ANAPAR_PW15_H2 GENMASK(27, 26) 3894#define R_ANAPAR 0x032C 3895#define B_ANAPAR_15 GENMASK(31, 16) 3896#define B_ANAPAR_ADCCLK BIT(30) 3897#define B_ANAPAR_FLTRST BIT(22) 3898#define B_ANAPAR_CRXBB GENMASK(18, 16) 3899#define B_ANAPAR_EN BIT(16) 3900#define B_ANAPAR_14 GENMASK(15, 0) 3901#define R_RFE_E_A2 0x0334 3902#define R_RFE_O_SEL_A2 0x0338 3903#define R_RFE_SEL0_A2 0x033C 3904#define B_RFE_SEL0_MASK GENMASK(1, 0) 3905#define R_RFE_SEL32_A2 0x0340 3906#define R_CIRST 0x035c 3907#define B_CIRST_SYN GENMASK(11, 10) 3908#define R_SWSI_DATA_V1 0x0370 3909#define B_SWSI_DATA_VAL_V1 GENMASK(19, 0) 3910#define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20) 3911#define B_SWSI_DATA_PATH_V1 GENMASK(30, 28) 3912#define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31) 3913#define R_SWSI_BIT_MASK_V1 0x0374 3914#define B_SWSI_BIT_MASK_V1 GENMASK(19, 0) 3915#define R_SWSI_READ_ADDR_V1 0x0378 3916#define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0) 3917#define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8) 3918#define B_SWSI_READ_ADDR_V1 GENMASK(10, 0) 3919#define R_UPD_CLK_ADC 0x0700 3920#define B_UPD_CLK_ADC_VAL GENMASK(26, 25) 3921#define B_UPD_CLK_ADC_ON BIT(24) 3922#define B_ENABLE_CCK BIT(5) 3923#define R_RSTB_ASYNC 0x0704 3924#define B_RSTB_ASYNC_ALL BIT(1) 3925#define R_P0_ANT_SW 0x0728 3926#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12) 3927#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0) 3928#define R_MAC_PIN_SEL 0x0734 3929#define B_CH_IDX_SEG0 GENMASK(23, 16) 3930#define R_PLCP_HISTOGRAM 0x0738 3931#define B_STS_PARSING_TIME GENMASK(19, 16) 3932#define B_STS_DIS_TRIG_BY_FAIL BIT(3) 3933#define B_STS_DIS_TRIG_BY_BRK BIT(2) 3934#define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL 3935#define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2) 3936#define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C 3937#define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f 3938#define R_PHY_STS_BITMAP_R2T 0x0740 3939#define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744 3940#define R_PHY_STS_BITMAP_OFDM_BRK 0x0748 3941#define R_PHY_STS_BITMAP_CCK_BRK 0x074C 3942#define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750 3943#define R_PHY_STS_BITMAP_HE_MU 0x0754 3944#define R_PHY_STS_BITMAP_VHT_MU 0x0758 3945#define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C 3946#define R_PHY_STS_BITMAP_TRIGBASE 0x0760 3947#define R_PHY_STS_BITMAP_CCK 0x0764 3948#define R_PHY_STS_BITMAP_LEGACY 0x0768 3949#define R_PHY_STS_BITMAP_HT 0x076C 3950#define R_PHY_STS_BITMAP_VHT 0x0770 3951#define R_PHY_STS_BITMAP_HE 0x0774 3952#define R_PMAC_GNT 0x0980 3953#define B_PMAC_GNT_TXEN BIT(0) 3954#define B_PMAC_GNT_RXEN BIT(16) 3955#define B_PMAC_GNT_P1 GENMASK(20, 17) 3956#define B_PMAC_GNT_P2 GENMASK(29, 26) 3957#define R_PMAC_RX_CFG1 0x0988 3958#define B_PMAC_OPT1_MSK GENMASK(11, 0) 3959#define R_PMAC_RXMOD 0x0994 3960#define B_PMAC_RXMOD_MSK GENMASK(7, 4) 3961#define R_MAC_SEL 0x09A4 3962#define B_MAC_SEL_OFDM_TRI_FILTER BIT(31) 3963#define B_MAC_SEL_PWR_EN BIT(16) 3964#define B_MAC_SEL_DPD_EN BIT(10) 3965#define B_MAC_SEL_MOD GENMASK(4, 2) 3966#define R_PMAC_TX_CTRL 0x09C0 3967#define B_PMAC_TXEN_DIS BIT(0) 3968#define R_PMAC_TX_PRD 0x09C4 3969#define B_PMAC_TX_PRD_MSK GENMASK(31, 8) 3970#define B_PMAC_CTX_EN BIT(0) 3971#define B_PMAC_PTX_EN BIT(4) 3972#define R_PMAC_TX_CNT 0x09C8 3973#define B_PMAC_TX_CNT_MSK GENMASK(31, 0) 3974#define R_P80_AT_HIGH_FREQ 0x09D8 3975#define B_P80_AT_HIGH_FREQ BIT(26) 3976#define R_DBCC_80P80_SEL_EVM_RPT 0x0A10 3977#define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0) 3978#define R_CCX 0x0C00 3979#define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) 3980#define B_MEASUREMENT_TRIG_MSK BIT(2) 3981#define B_CCX_TRIG_OPT_MSK BIT(1) 3982#define B_CCX_EN_MSK BIT(0) 3983#define R_IFS_COUNTER 0x0C28 3984#define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) 3985#define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) 3986#define B_IFS_COUNTER_CLR_MSK BIT(13) 3987#define B_IFS_COLLECT_EN BIT(12) 3988#define R_IFS_T1 0x0C2C 3989#define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) 3990#define B_IFS_T1_EN_MSK BIT(15) 3991#define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) 3992#define R_IFS_T2 0x0C30 3993#define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) 3994#define B_IFS_T2_EN_MSK BIT(15) 3995#define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) 3996#define R_IFS_T3 0x0C34 3997#define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) 3998#define B_IFS_T3_EN_MSK BIT(15) 3999#define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) 4000#define R_IFS_T4 0x0C38 4001#define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) 4002#define B_IFS_T4_EN_MSK BIT(15) 4003#define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) 4004#define R_PD_CTRL 0x0C3C 4005#define B_PD_HIT_DIS BIT(9) 4006#define R_IOQ_IQK_DPK 0x0C60 4007#define B_IOQ_IQK_DPK_EN BIT(1) 4008#define R_GNT_BT_WGT_EN 0x0C6C 4009#define B_GNT_BT_WGT_EN BIT(21) 4010#define R_PD_ARBITER_OFF 0x0C80 4011#define B_PD_ARBITER_OFF BIT(31) 4012#define R_SNDCCA_A1 0x0C9C 4013#define B_SNDCCA_A1_EN GENMASK(19, 12) 4014#define R_SNDCCA_A2 0x0CA0 4015#define B_SNDCCA_A2_VAL GENMASK(19, 12) 4016#define R_RXHT_MCS_LIMIT 0x0D18 4017#define B_RXHT_MCS_LIMIT GENMASK(9, 8) 4018#define R_RXVHT_MCS_LIMIT 0x0D18 4019#define B_RXVHT_MCS_LIMIT GENMASK(22, 21) 4020#define R_P0_EN_SOUND_WO_NDP 0x0D7C 4021#define B_P0_EN_SOUND_WO_NDP BIT(1) 4022#define R_RXHE 0x0D80 4023#define B_RXHETB_MAX_NSS GENMASK(25, 23) 4024#define B_RXHE_MAX_NSS GENMASK(16, 14) 4025#define B_RXHE_USER_MAX GENMASK(13, 6) 4026#define R_SPOOF_ASYNC_RST 0x0D84 4027#define B_SPOOF_ASYNC_RST BIT(15) 4028#define R_NDP_BRK0 0xDA0 4029#define R_NDP_BRK1 0xDA4 4030#define B_NDP_RU_BRK BIT(0) 4031#define R_BRK_ASYNC_RST_EN_1 0x0DC0 4032#define R_BRK_ASYNC_RST_EN_2 0x0DC4 4033#define R_BRK_ASYNC_RST_EN_3 0x0DC8 4034#define R_S0_HW_SI_DIS 0x1200 4035#define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) 4036#define R_P0_RXCK 0x12A0 4037#define B_P0_RXCK_ADJ GENMASK(31, 23) 4038#define B_P0_RXCK_BW3 BIT(30) 4039#define B_P0_TXCK_ALL GENMASK(19, 12) 4040#define B_P0_RXCK_ON BIT(19) 4041#define B_P0_RXCK_VAL GENMASK(18, 16) 4042#define B_P0_TXCK_ON BIT(15) 4043#define B_P0_TXCK_VAL GENMASK(14, 12) 4044#define R_P0_RFMODE 0x12AC 4045#define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) 4046#define B_P0_RFMODE_MUX GENMASK(11, 4) 4047#define R_P0_RFMODE_ORI_RX 0x12AC 4048#define B_P0_RFMODE_ORI_RX_ALL GENMASK(23, 12) 4049#define R_P0_RFMODE_FTM_RX 0x12B0 4050#define B_P0_RFMODE_FTM_RX GENMASK(11, 0) 4051#define R_P0_NRBW 0x12B8 4052#define B_P0_NRBW_DBG BIT(30) 4053#define R_S0_RXDC 0x12D4 4054#define B_S0_RXDC_I GENMASK(25, 16) 4055#define B_S0_RXDC_Q GENMASK(31, 26) 4056#define R_S0_RXDC2 0x12D8 4057#define B_S0_RXDC2_SEL GENMASK(9, 8) 4058#define B_S0_RXDC2_AVG GENMASK(7, 6) 4059#define B_S0_RXDC2_MEN GENMASK(5, 4) 4060#define B_S0_RXDC2_Q2 GENMASK(3, 0) 4061#define R_CFO_COMP_SEG0_L 0x1384 4062#define R_CFO_COMP_SEG0_H 0x1388 4063#define R_CFO_COMP_SEG0_CTRL 0x138C 4064#define R_DBG32_D 0x1730 4065#define R_SWSI_V1 0x174C 4066#define B_SWSI_W_BUSY_V1 BIT(24) 4067#define B_SWSI_R_BUSY_V1 BIT(25) 4068#define B_SWSI_R_DATA_DONE_V1 BIT(26) 4069#define R_TX_COUNTER 0x1A40 4070#define R_IFS_CLM_TX_CNT 0x1ACC 4071#define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) 4072#define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) 4073#define R_IFS_CLM_CCA 0x1AD0 4074#define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) 4075#define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) 4076#define R_IFS_CLM_FA 0x1AD4 4077#define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) 4078#define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) 4079#define R_IFS_HIS 0x1AD8 4080#define B_IFS_T4_HIS_MSK GENMASK(31, 24) 4081#define B_IFS_T3_HIS_MSK GENMASK(23, 16) 4082#define B_IFS_T2_HIS_MSK GENMASK(15, 8) 4083#define B_IFS_T1_HIS_MSK GENMASK(7, 0) 4084#define R_IFS_AVG_L 0x1ADC 4085#define B_IFS_T2_AVG_MSK GENMASK(31, 16) 4086#define B_IFS_T1_AVG_MSK GENMASK(15, 0) 4087#define R_IFS_AVG_H 0x1AE0 4088#define B_IFS_T4_AVG_MSK GENMASK(31, 16) 4089#define B_IFS_T3_AVG_MSK GENMASK(15, 0) 4090#define R_IFS_CCA_L 0x1AE4 4091#define B_IFS_T2_CCA_MSK GENMASK(31, 16) 4092#define B_IFS_T1_CCA_MSK GENMASK(15, 0) 4093#define R_IFS_CCA_H 0x1AE8 4094#define B_IFS_T4_CCA_MSK GENMASK(31, 16) 4095#define B_IFS_T3_CCA_MSK GENMASK(15, 0) 4096#define R_IFSCNT 0x1AEC 4097#define B_IFSCNT_DONE_MSK BIT(16) 4098#define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0) 4099#define R_TXAGC_TP 0x1C04 4100#define B_TXAGC_TP GENMASK(2, 0) 4101#define R_TSSI_THER 0x1C10 4102#define B_TSSI_THER GENMASK(29, 24) 4103#define R_TSSI_CWRPT 0x1C18 4104#define B_TSSI_CWRPT_RDY BIT(16) 4105#define B_TSSI_CWRPT GENMASK(8, 0) 4106#define R_TXAGC_BTP 0x1CA0 4107#define B_TXAGC_BTP GENMASK(31, 24) 4108#define R_TXAGC_BB 0x1C60 4109#define B_TXAGC_BB_OFT GENMASK(31, 16) 4110#define B_TXAGC_BB GENMASK(31, 24) 4111#define B_TXAGC_RF GENMASK(5, 0) 4112#define R_S0_ADDCK 0x1E00 4113#define B_S0_ADDCK_I GENMASK(9, 0) 4114#define B_S0_ADDCK_Q GENMASK(19, 10) 4115#define R_ADC_FIFO 0x20fc 4116#define B_ADC_FIFO_RST GENMASK(31, 24) 4117#define B_ADC_FIFO_RXK GENMASK(31, 16) 4118#define B_ADC_FIFO_A3 BIT(28) 4119#define B_ADC_FIFO_A2 BIT(24) 4120#define B_ADC_FIFO_A1 BIT(20) 4121#define B_ADC_FIFO_A0 BIT(16) 4122#define R_TXFIR0 0x2300 4123#define B_TXFIR_C01 GENMASK(23, 0) 4124#define R_TXFIR2 0x2304 4125#define B_TXFIR_C23 GENMASK(23, 0) 4126#define R_TXFIR4 0x2308 4127#define B_TXFIR_C45 GENMASK(23, 0) 4128#define R_TXFIR6 0x230c 4129#define B_TXFIR_C67 GENMASK(23, 0) 4130#define R_TXFIR8 0x2310 4131#define B_TXFIR_C89 GENMASK(23, 0) 4132#define R_TXFIRA 0x2314 4133#define B_TXFIR_CAB GENMASK(23, 0) 4134#define R_TXFIRC 0x2318 4135#define B_TXFIR_CCD GENMASK(23, 0) 4136#define R_TXFIRE 0x231c 4137#define B_TXFIR_CEF GENMASK(23, 0) 4138#define R_11B_RX_V1 0x2320 4139#define B_11B_RXCCA_DIS_V1 BIT(0) 4140#define R_RPL_OFST 0x2340 4141#define B_RPL_OFST_MASK GENMASK(14, 8) 4142#define R_RXCCA 0x2344 4143#define B_RXCCA_DIS BIT(31) 4144#define R_RXCCA_V1 0x2320 4145#define B_RXCCA_DIS_V1 BIT(0) 4146#define R_RXSC 0x237C 4147#define B_RXSC_EN BIT(0) 4148#define R_RX_RPL_OFST 0x23AC 4149#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0) 4150#define R_RXSCOBC 0x23B0 4151#define B_RXSCOBC_TH GENMASK(18, 0) 4152#define R_RXSCOCCK 0x23B4 4153#define B_RXSCOCCK_TH GENMASK(18, 0) 4154#define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410 4155#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14) 4156#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13) 4157#define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10 4158#define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0) 4159#define R_P1_EN_SOUND_WO_NDP 0x2D7C 4160#define B_P1_EN_SOUND_WO_NDP BIT(1) 4161#define R_S1_HW_SI_DIS 0x3200 4162#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) 4163#define R_P1_RXCK 0x32A0 4164#define B_P1_RXCK_BW3 BIT(30) 4165#define B_P1_TXCK_ALL GENMASK(19, 12) 4166#define B_P1_RXCK_ON BIT(19) 4167#define B_P1_RXCK_VAL GENMASK(18, 16) 4168#define R_P1_RFMODE 0x32AC 4169#define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) 4170#define B_P1_RFMODE_MUX GENMASK(11, 4) 4171#define R_P1_RFMODE_ORI_RX 0x32AC 4172#define B_P1_RFMODE_ORI_RX_ALL GENMASK(23, 12) 4173#define R_P1_RFMODE_FTM_RX 0x32B0 4174#define B_P1_RFMODE_FTM_RX GENMASK(11, 0) 4175#define R_P1_DBGMOD 0x32B8 4176#define B_P1_DBGMOD_ON BIT(30) 4177#define R_S1_RXDC 0x32D4 4178#define B_S1_RXDC_I GENMASK(25, 16) 4179#define B_S1_RXDC_Q GENMASK(31, 26) 4180#define R_S1_RXDC2 0x32D8 4181#define B_S1_RXDC2_EN GENMASK(5, 4) 4182#define B_S1_RXDC2_SEL GENMASK(9, 8) 4183#define B_S1_RXDC2_Q2 GENMASK(3, 0) 4184#define R_TXAGC_BB_S1 0x3C60 4185#define B_TXAGC_BB_S1_OFT GENMASK(31, 16) 4186#define B_TXAGC_BB_S1 GENMASK(31, 24) 4187#define R_S1_ADDCK 0x3E00 4188#define B_S1_ADDCK_I GENMASK(9, 0) 4189#define B_S1_ADDCK_Q GENMASK(19, 10) 4190#define R_MUIC 0x40F8 4191#define B_MUIC_EN BIT(0) 4192#define R_DCFO 0x4264 4193#define B_DCFO GENMASK(7, 0) 4194#define R_SEG0CSI 0x42AC 4195#define R_SEG0CSI_V1 0x42B0 4196#define B_SEG0CSI_IDX GENMASK(10, 0) 4197#define R_SEG0CSI_EN 0x42C4 4198#define R_SEG0CSI_EN_V1 0x42C8 4199#define B_SEG0CSI_EN BIT(23) 4200#define R_BSS_CLR_MAP 0x43ac 4201#define R_BSS_CLR_MAP_V1 0x43B0 4202#define B_BSS_CLR_MAP_VLD0 BIT(28) 4203#define B_BSS_CLR_MAP_TGT GENMASK(27, 22) 4204#define B_BSS_CLR_MAP_STAID GENMASK(21, 11) 4205#define R_CFO_TRK0 0x4404 4206#define R_CFO_TRK1 0x440C 4207#define B_CFO_TRK_MSK GENMASK(14, 10) 4208#define R_T2F_GI_COMB 0x4424 4209#define B_T2F_GI_COMB_EN BIT(2) 4210#define R_BT_DYN_DC_EST_EN 0x441C 4211#define R_BT_DYN_DC_EST_EN_V1 0x4420 4212#define B_BT_DYN_DC_EST_EN_MSK BIT(31) 4213#define R_ASSIGN_SBD_OPT_V1 0x4440 4214#define B_ASSIGN_SBD_OPT_EN_V1 BIT(31) 4215#define R_ASSIGN_SBD_OPT 0x4450 4216#define B_ASSIGN_SBD_OPT_EN BIT(24) 4217#define R_DCFO_COMP_S0 0x448C 4218#define B_DCFO_COMP_S0_MSK GENMASK(11, 0) 4219#define R_DCFO_WEIGHT 0x4490 4220#define B_DCFO_WEIGHT_MSK GENMASK(27, 24) 4221#define R_DCFO_OPT 0x4494 4222#define B_DCFO_OPT_EN BIT(29) 4223#define B_TXSHAPE_TRIANGULAR_CFG GENMASK(25, 24) 4224#define R_BANDEDGE 0x4498 4225#define B_BANDEDGE_EN BIT(30) 4226#define R_DPD_BF 0x44a0 4227#define B_DPD_BF_OFDM GENMASK(16, 12) 4228#define B_DPD_BF_SCA GENMASK(6, 0) 4229#define R_TXPATH_SEL 0x458C 4230#define B_TXPATH_SEL_MSK GENMASK(31, 28) 4231#define R_TXPWR 0x4594 4232#define B_TXPWR_MSK GENMASK(30, 22) 4233#define R_TXNSS_MAP 0x45B4 4234#define B_TXNSS_MAP_MSK GENMASK(20, 17) 4235#define R_PCOEFF0_V1 0x45BC 4236#define B_PCOEFF01_MSK_V1 GENMASK(23, 0) 4237#define R_PCOEFF2_V1 0x45CC 4238#define B_PCOEFF23_MSK_V1 GENMASK(23, 0) 4239#define R_PCOEFF4_V1 0x45D0 4240#define B_PCOEFF45_MSK_V1 GENMASK(23, 0) 4241#define R_PCOEFF6_V1 0x45D4 4242#define B_PCOEFF67_MSK_V1 GENMASK(23, 0) 4243#define R_PCOEFF8_V1 0x45D8 4244#define B_PCOEFF89_MSK_V1 GENMASK(23, 0) 4245#define R_PCOEFFA_V1 0x45C0 4246#define B_PCOEFFAB_MSK_V1 GENMASK(23, 0) 4247#define R_PCOEFFC_V1 0x45C4 4248#define B_PCOEFFCD_MSK_V1 GENMASK(23, 0) 4249#define R_PCOEFFE_V1 0x45C8 4250#define B_PCOEFFEF_MSK_V1 GENMASK(23, 0) 4251#define R_PATH0_IB_PKPW 0x4628 4252#define B_PATH0_IB_PKPW_MSK GENMASK(11, 6) 4253#define R_PATH0_LNA_ERR1 0x462C 4254#define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24) 4255#define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12) 4256#define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6) 4257#define R_PATH0_LNA_ERR2 0x4630 4258#define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18) 4259#define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12) 4260#define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0) 4261#define R_PATH0_LNA_ERR3 0x4634 4262#define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24) 4263#define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18) 4264#define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6) 4265#define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0) 4266#define R_PATH0_LNA_ERR4 0x4638 4267#define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24) 4268#define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12) 4269#define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6) 4270#define R_PATH0_LNA_ERR5 0x463C 4271#define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0) 4272#define R_PATH0_TIA_ERR_G0 0x4640 4273#define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18) 4274#define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12) 4275#define R_PATH0_TIA_ERR_G1 0x4644 4276#define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30) 4277#define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6) 4278#define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0) 4279#define R_PATH0_IB_PBK 0x4650 4280#define B_PATH0_IB_PBK_MSK GENMASK(14, 10) 4281#define R_PATH0_RXB_INIT 0x4658 4282#define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5) 4283#define R_PATH0_LNA_INIT 0x4668 4284#define R_PATH0_LNA_INIT_V1 0x472C 4285#define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24) 4286#define R_PATH0_BTG 0x466C 4287#define B_PATH0_BTG_SHEN GENMASK(18, 17) 4288#define R_PATH0_TIA_INIT 0x4674 4289#define B_PATH0_TIA_INIT_IDX_MSK BIT(17) 4290#define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0 4291#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24 4292#define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8 4293#define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 4294#define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4 4295#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28 4296#define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC 4297#define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 4298#define R_PATH0_RXB_INIT_V1 0x46A8 4299#define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10) 4300#define R_PATH0_G_LNA6_OP1DB_V1 0x4688 4301#define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24) 4302#define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694 4303#define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0) 4304#define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694 4305#define B_PATH0_R_G_OFST_MASK GENMASK(23, 16) 4306#define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8) 4307#define R_CDD_EVM_CHK_EN 0x46C0 4308#define B_CDD_EVM_CHK_EN BIT(0) 4309#define R_PATH0_BAND_SEL_V1 0x4738 4310#define B_PATH0_BAND_SEL_MSK_V1 BIT(17) 4311#define R_PATH0_BT_SHARE_V1 0x4738 4312#define B_PATH0_BT_SHARE_V1 BIT(19) 4313#define R_PATH0_BTG_PATH_V1 0x4738 4314#define B_PATH0_BTG_PATH_V1 BIT(22) 4315#define R_P0_NBIIDX 0x469C 4316#define B_P0_NBIIDX_VAL GENMASK(11, 0) 4317#define B_P0_NBIIDX_NOTCH_EN BIT(12) 4318#define R_P0_BACKOFF_IBADC_V1 0x469C 4319#define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26) 4320#define B_P0_NBIIDX_NOTCH_EN_V1 BIT(12) 4321#define R_P1_MODE 0x4718 4322#define B_P1_MODE_SEL GENMASK(31, 30) 4323#define R_P0_AGC_CTL 0x4730 4324#define B_P0_AGC_EN BIT(31) 4325#define R_PATH1_LNA_INIT 0x473C 4326#define R_PATH1_LNA_INIT_V1 0x4A80 4327#define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24) 4328#define R_PATH0_TIA_INIT_V1 0x473C 4329#define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9) 4330#define R_PATH1_TIA_INIT 0x4748 4331#define B_PATH1_TIA_INIT_IDX_MSK BIT(17) 4332#define R_PATH1_BTG 0x4740 4333#define B_PATH1_BTG_SHEN GENMASK(18, 17) 4334#define R_PATH1_RXB_INIT 0x472C 4335#define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5) 4336#define R_PATH1_G_LNA6_OP1DB_V1 0x476C 4337#define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24) 4338#define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774 4339#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8 4340#define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8 4341#define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 4342#define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778 4343#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC 4344#define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC 4345#define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 4346#define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778 4347#define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0) 4348#define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778 4349#define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8) 4350#define R_PATH1_BAND_SEL_V1 0x4AA4 4351#define B_PATH1_BAND_SEL_MSK_V1 BIT(17) 4352#define R_PATH1_BT_SHARE_V1 0x4AA4 4353#define B_PATH1_BT_SHARE_V1 BIT(19) 4354#define R_PATH1_BTG_PATH_V1 0x4AA4 4355#define B_PATH1_BTG_PATH_V1 BIT(22) 4356#define R_P1_NBIIDX 0x4770 4357#define B_P1_NBIIDX_VAL GENMASK(11, 0) 4358#define B_P1_NBIIDX_NOTCH_EN BIT(12) 4359#define R_PKT_CTRL 0x47D4 4360#define B_PKT_POP_EN BIT(8) 4361#define R_SEG0R_PD 0x481C 4362#define R_SEG0R_PD_V1 0x4860 4363#define R_SEG0R_EDCCA_LVL 0x4840 4364#define R_SEG0R_EDCCA_LVL_V1 0x4884 4365#define B_SEG0R_PPDU_LVL_MSK GENMASK(31, 24) 4366#define B_SEG0R_EDCCA_LVL_P_MSK GENMASK(15, 8) 4367#define B_SEG0R_EDCCA_LVL_A_MSK GENMASK(7, 0) 4368#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30) 4369#define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29) 4370#define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6) 4371#define R_2P4G_BAND 0x4970 4372#define B_2P4G_BAND_SEL BIT(1) 4373#define R_FC0_BW 0x4974 4374#define R_FC0_BW_V1 0x49C0 4375#define B_FC0_BW_SET GENMASK(31, 30) 4376#define B_ANT_RX_BT_SEG0 GENMASK(25, 22) 4377#define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18) 4378#define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14) 4379#define B_FC0_BW_INV GENMASK(6, 0) 4380#define R_CHBW_MOD 0x4978 4381#define R_CHBW_MOD_V1 0x49C4 4382#define B_BT_SHARE BIT(14) 4383#define B_CHBW_MOD_SBW GENMASK(13, 12) 4384#define B_CHBW_MOD_PRICH GENMASK(11, 8) 4385#define B_ANT_RX_SEG0 GENMASK(3, 0) 4386#define R_P0_RPL1 0x49B0 4387#define B_P0_RPL1_41_MASK GENMASK(31, 24) 4388#define B_P0_RPL1_40_MASK GENMASK(23, 16) 4389#define B_P0_RPL1_20_MASK GENMASK(15, 8) 4390#define B_P0_RPL1_MASK (B_P0_RPL1_41_MASK | B_P0_RPL1_40_MASK | B_P0_RPL1_20_MASK) 4391#define B_P0_RPL1_SHIFT 8 4392#define B_P0_RPL1_BIAS_MASK GENMASK(7, 0) 4393#define R_P0_RPL2 0x49B4 4394#define B_P0_RTL2_8A_MASK GENMASK(31, 24) 4395#define B_P0_RTL2_81_MASK GENMASK(23, 16) 4396#define B_P0_RTL2_80_MASK GENMASK(15, 8) 4397#define B_P0_RTL2_42_MASK GENMASK(7, 0) 4398#define R_P0_RPL3 0x49B8 4399#define B_P0_RTL3_89_MASK GENMASK(31, 24) 4400#define B_P0_RTL3_84_MASK GENMASK(23, 16) 4401#define B_P0_RTL3_83_MASK GENMASK(15, 8) 4402#define B_P0_RTL3_82_MASK GENMASK(7, 0) 4403#define R_PD_BOOST_EN 0x49E8 4404#define B_PD_BOOST_EN BIT(7) 4405#define R_P1_BACKOFF_IBADC_V1 0x49F0 4406#define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26) 4407#define R_P1_RPL1 0x4A00 4408#define R_P1_RPL2 0x4A04 4409#define R_P1_RPL3 0x4A08 4410#define R_BK_FC0_INV_V1 0x4A1C 4411#define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0) 4412#define R_CCK_FC0_INV_V1 0x4A20 4413#define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0) 4414#define R_PATH1_RXB_INIT_V1 0x4A5C 4415#define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10) 4416#define R_P1_AGC_CTL 0x4A9C 4417#define B_P1_AGC_EN BIT(31) 4418#define R_PATH1_TIA_INIT_V1 0x4AA8 4419#define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9) 4420#define R_P0_AGC_RSVD 0x4ACC 4421#define R_PATH0_RXBB_V1 0x4AD4 4422#define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0) 4423#define R_P1_AGC_RSVD 0x4AD8 4424#define R_PATH1_RXBB_V1 0x4AE0 4425#define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0) 4426#define R_PATH0_BT_BACKOFF_V1 0x4AE4 4427#define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0) 4428#define R_PATH1_BT_BACKOFF_V1 0x4AEC 4429#define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0) 4430#define R_DCFO_COMP_S0_V2 0x4B20 4431#define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0) 4432#define R_PATH0_TX_CFR 0x4B30 4433#define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10) 4434#define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0) 4435#define R_PATH0_TX_POLAR_CLIPPING 0x4B3C 4436#define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16) 4437#define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12) 4438#define R_PATH0_FRC_FIR_TYPE_V1 0x4C00 4439#define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) 4440#define R_PATH0_NOTCH 0x4C14 4441#define B_PATH0_NOTCH_EN BIT(12) 4442#define B_PATH0_NOTCH_VAL GENMASK(11, 0) 4443#define R_PATH0_NOTCH2 0x4C20 4444#define B_PATH0_NOTCH2_EN BIT(12) 4445#define B_PATH0_NOTCH2_VAL GENMASK(11, 0) 4446#define R_PATH0_5MDET 0x4C4C 4447#define R_PATH0_5MDET_V1 0x46F8 4448#define B_PATH0_5MDET_EN BIT(12) 4449#define B_PATH0_5MDET_SB2 BIT(8) 4450#define B_PATH0_5MDET_SB0 BIT(6) 4451#define B_PATH0_5MDET_TH GENMASK(5, 0) 4452#define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4 4453#define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) 4454#define R_PATH1_NOTCH 0x4CD8 4455#define B_PATH1_NOTCH_EN BIT(12) 4456#define B_PATH1_NOTCH_VAL GENMASK(11, 0) 4457#define R_PATH1_NOTCH2 0x4CE4 4458#define B_PATH1_NOTCH2_EN BIT(12) 4459#define B_PATH1_NOTCH2_VAL GENMASK(11, 0) 4460#define R_PATH1_5MDET 0x4D10 4461#define R_PATH1_5MDET_V1 0x47B8 4462#define B_PATH1_5MDET_EN BIT(12) 4463#define B_PATH1_5MDET_SB2 BIT(8) 4464#define B_PATH1_5MDET_SB0 BIT(6) 4465#define B_PATH1_5MDET_TH GENMASK(5, 0) 4466#define R_RPL_BIAS_COMP 0x4DF0 4467#define B_RPL_BIAS_COMP_MASK GENMASK(7, 0) 4468#define R_RPL_PATHAB 0x4E0C 4469#define B_RPL_PATHB_MASK GENMASK(23, 16) 4470#define B_RPL_PATHA_MASK GENMASK(15, 8) 4471#define R_RSSI_M_PATHAB 0x4E2C 4472#define B_RSSI_M_PATHB_MASK GENMASK(15, 8) 4473#define B_RSSI_M_PATHA_MASK GENMASK(7, 0) 4474#define R_FC0_V1 0x4E30 4475#define B_FC0_MSK_V1 GENMASK(12, 0) 4476#define R_RX_BW40_2XFFT_EN_V1 0x4E30 4477#define B_RX_BW40_2XFFT_EN_MSK_V1 BIT(26) 4478#define R_DCFO_COMP_S0_V1 0x4A40 4479#define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0) 4480#define R_BMODE_PDTH_V1 0x4B64 4481#define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24) 4482#define R_BMODE_PDTH_EN_V1 0x4B74 4483#define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30) 4484#define R_CFO_COMP_SEG1_L 0x5384 4485#define R_CFO_COMP_SEG1_H 0x5388 4486#define R_CFO_COMP_SEG1_CTRL 0x538C 4487#define B_CFO_COMP_VALID_BIT BIT(29) 4488#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) 4489#define B_CFO_COMP_VAL_MSK GENMASK(11, 0) 4490#define R_TSSI_PA_K1 0x5600 4491#define R_TSSI_PA_K2 0x5604 4492#define R_P0_TSSI_ALIM1 0x5630 4493#define B_P0_TSSI_ALIM1 GENMASK(29, 0) 4494#define B_P0_TSSI_ALIM11 GENMASK(29, 20) 4495#define B_P0_TSSI_ALIM12 GENMASK(19, 10) 4496#define B_P0_TSSI_ALIM13 GENMASK(9, 0) 4497#define R_P0_TSSI_ALIM3 0x5634 4498#define B_P0_TSSI_ALIM31 GENMASK(9, 0) 4499#define R_TSSI_PA_K5 0x5638 4500#define R_P0_TSSI_ALIM2 0x563c 4501#define B_P0_TSSI_ALIM2 GENMASK(29, 0) 4502#define R_P0_TSSI_ALIM4 0x5640 4503#define R_TSSI_PA_K8 0x5644 4504#define R_UPD_CLK 0x5670 4505#define B_DAC_VAL BIT(31) 4506#define B_ACK_VAL GENMASK(30, 29) 4507#define B_DPD_DIS BIT(14) 4508#define B_DPD_GDIS BIT(13) 4509#define B_IQK_RFC_ON BIT(1) 4510#define R_TXPWRB 0x56CC 4511#define B_TXPWRB_ON BIT(28) 4512#define B_TXPWRB_VAL GENMASK(27, 19) 4513#define R_DPD_OFT_EN 0x5800 4514#define B_DPD_OFT_EN BIT(28) 4515#define B_DPD_TSSI_CW GENMASK(26, 18) 4516#define B_DPD_PWR_CW GENMASK(17, 9) 4517#define B_DPD_REF GENMASK(8, 0) 4518#define R_P0_TSSIC 0x5814 4519#define B_P0_TSSIC_BYPASS BIT(11) 4520#define R_DPD_OFT_ADDR 0x5804 4521#define B_DPD_OFT_ADDR GENMASK(31, 27) 4522#define R_TXPWRB_H 0x580c 4523#define B_TXPWRB_RDY BIT(15) 4524#define R_P0_TMETER 0x5810 4525#define B_P0_TMETER GENMASK(15, 10) 4526#define B_P0_TMETER_DIS BIT(16) 4527#define B_P0_TMETER_TRK BIT(24) 4528#define R_P1_TSSIC 0x7814 4529#define B_P1_TSSIC_BYPASS BIT(11) 4530#define R_P0_TSSI_TRK 0x5818 4531#define B_P0_TSSI_TRK_EN BIT(30) 4532#define B_P0_TSSI_RFC GENMASK(28, 27) 4533#define B_P0_TSSI_OFT_EN BIT(28) 4534#define B_P0_TSSI_OFT GENMASK(7, 0) 4535#define R_P0_TSSI_AVG 0x5820 4536#define B_P0_TSSI_EN BIT(31) 4537#define B_P0_TSSI_AVG GENMASK(15, 12) 4538#define R_P0_RFCTM 0x5864 4539#define B_P0_RFCTM_EN BIT(29) 4540#define B_P0_RFCTM_VAL GENMASK(25, 20) 4541#define R_P0_RFCTM_RDY BIT(26) 4542#define R_P0_TRSW 0x5868 4543#define B_P0_BT_FORCE_ANTIDX_EN BIT(12) 4544#define B_P0_TRSW_X BIT(2) 4545#define B_P0_TRSW_A BIT(1) 4546#define B_P0_TX_ANT_SEL BIT(1) 4547#define B_P0_TRSW_B BIT(0) 4548#define B_P0_ANT_TRAIN_EN BIT(0) 4549#define B_P0_TRSW_SO_A2 GENMASK(7, 5) 4550#define R_P0_ANTSEL 0x586C 4551#define B_P0_ANTSEL_SW_5G BIT(25) 4552#define B_P0_ANTSEL_SW_2G BIT(23) 4553#define B_P0_ANTSEL_BTG_TRX BIT(21) 4554#define B_P0_ANTSEL_CGCS_CTRL BIT(17) 4555#define B_P0_ANTSEL_HW_CTRL BIT(16) 4556#define B_P0_ANTSEL_TX_ORI GENMASK(15, 12) 4557#define B_P0_ANTSEL_RX_ALT GENMASK(11, 8) 4558#define B_P0_ANTSEL_RX_ORI GENMASK(7, 4) 4559#define R_RFSW_CTRL_ANT0_BASE 0x5870 4560#define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0) 4561#define R_RFE_SEL0_BASE 0x5880 4562#define B_RFE_SEL0_SRC_MASK GENMASK(3, 0) 4563#define R_RFE_SEL32_BASE 0x5884 4564#define RFE_SEL0_SRC_ANTSEL_0 8 4565#define R_RFE_INV0 0x5890 4566#define R_P0_RFM 0x5894 4567#define B_P0_RFM_DIS_WL BIT(7) 4568#define B_P0_RFM_TX_OPT BIT(6) 4569#define B_P0_RFM_BT_EN BIT(5) 4570#define B_P0_RFM_OUT GENMASK(4, 0) 4571#define R_P0_PATH_RST 0x58AC 4572#define R_P0_TXDPD 0x58D4 4573#define B_P0_TXDPD GENMASK(31, 28) 4574#define R_P0_TXPW_RSTB 0x58DC 4575#define B_P0_TXPW_RSTB_MANON BIT(30) 4576#define B_P0_TXPW_RSTB_TSSI BIT(31) 4577#define R_P0_TSSI_MV_AVG 0x58E4 4578#define B_P0_TSSI_MV_MIX GENMASK(19, 11) 4579#define B_P0_TSSI_MV_AVG GENMASK(13, 11) 4580#define B_P0_TSSI_MV_CLR BIT(14) 4581#define R_TXGAIN_SCALE 0x58F0 4582#define B_TXGAIN_SCALE_EN BIT(19) 4583#define B_TXGAIN_SCALE_OFT GENMASK(31, 24) 4584#define R_P0_TSSI_BASE 0x5C00 4585#define R_S0_DACKI 0x5E00 4586#define B_S0_DACKI_AR GENMASK(31, 28) 4587#define B_S0_DACKI_EN BIT(3) 4588#define R_S0_DACKI2 0x5E30 4589#define B_S0_DACKI2_K GENMASK(21, 12) 4590#define R_S0_DACKI7 0x5E44 4591#define B_S0_DACKI7_K GENMASK(15, 8) 4592#define R_S0_DACKI8 0x5E48 4593#define B_S0_DACKI8_K GENMASK(15, 8) 4594#define R_S0_DACKQ 0x5E50 4595#define B_S0_DACKQ_AR GENMASK(31, 28) 4596#define B_S0_DACKQ_EN BIT(3) 4597#define R_S0_DACKQ2 0x5E80 4598#define B_S0_DACKQ2_K GENMASK(21, 12) 4599#define R_S0_DACKQ7 0x5E94 4600#define B_S0_DACKQ7_K GENMASK(15, 8) 4601#define R_S0_DACKQ8 0x5E98 4602#define B_S0_DACKQ8_K GENMASK(15, 8) 4603#define R_RPL_BIAS_COMP1 0x6DF0 4604#define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0) 4605#define R_P1_TSSI_ALIM1 0x7630 4606#define B_P1_TSSI_ALIM1 GENMASK(29, 0) 4607#define B_P1_TSSI_ALIM11 GENMASK(29, 20) 4608#define B_P1_TSSI_ALIM12 GENMASK(19, 10) 4609#define B_P1_TSSI_ALIM13 GENMASK(9, 0) 4610#define R_P1_TSSI_ALIM3 0x7634 4611#define B_P1_TSSI_ALIM31 GENMASK(9, 0) 4612#define R_P1_TSSI_ALIM2 0x763c 4613#define B_P1_TSSI_ALIM2 GENMASK(29, 0) 4614#define R_P1_TSSIC 0x7814 4615#define B_P1_TSSIC_BYPASS BIT(11) 4616#define R_P1_TMETER 0x7810 4617#define B_P1_TMETER GENMASK(15, 10) 4618#define B_P1_TMETER_DIS BIT(16) 4619#define B_P1_TMETER_TRK BIT(24) 4620#define R_P1_TSSI_TRK 0x7818 4621#define B_P1_TSSI_TRK_EN BIT(30) 4622#define B_P1_TSSI_RFC GENMASK(28, 27) 4623#define B_P1_TSSI_OFT_EN BIT(28) 4624#define B_P1_TSSI_OFT GENMASK(7, 0) 4625#define R_P1_TSSI_AVG 0x7820 4626#define B_P1_TSSI_EN BIT(31) 4627#define B_P1_TSSI_AVG GENMASK(15, 12) 4628#define R_P1_RFCTM 0x7864 4629#define R_P1_RFCTM_RDY BIT(26) 4630#define B_P1_RFCTM_VAL GENMASK(25, 20) 4631#define B_P1_RFCTM_DEL GENMASK(19, 11) 4632#define R_P1_PATH_RST 0x78AC 4633#define R_P1_TXPW_RSTB 0x78DC 4634#define B_P1_TXPW_RSTB_MANON BIT(30) 4635#define B_P1_TXPW_RSTB_TSSI BIT(31) 4636#define R_P1_TSSI_MV_AVG 0x78E4 4637#define B_P1_TSSI_MV_MIX GENMASK(19, 11) 4638#define B_P1_TSSI_MV_AVG GENMASK(13, 11) 4639#define B_P1_TSSI_MV_CLR BIT(14) 4640#define R_TSSI_THOF 0x7C00 4641#define R_S1_DACKI 0x7E00 4642#define B_S1_DACKI_AR GENMASK(31, 28) 4643#define B_S1_DACKI_EN BIT(3) 4644#define R_S1_DACKI2 0x7E30 4645#define B_S1_DACKI2_K GENMASK(21, 12) 4646#define R_S1_DACKI7 0x7E44 4647#define B_S1_DACKI_K GENMASK(15, 8) 4648#define R_S1_DACKI8 0x7E48 4649#define B_S1_DACKI8_K GENMASK(15, 8) 4650#define R_S1_DACKQ 0x7E50 4651#define B_S1_DACKQ_AR GENMASK(31, 28) 4652#define B_S1_DACKQ_EN BIT(3) 4653#define R_S1_DACKQ2 0x7E80 4654#define B_S1_DACKQ2_K GENMASK(21, 12) 4655#define R_S1_DACKQ7 0x7E94 4656#define B_S1_DACKQ7_K GENMASK(15, 8) 4657#define R_S1_DACKQ8 0x7E98 4658#define B_S1_DACKQ8_K GENMASK(15, 8) 4659#define R_NCTL_CFG 0x8000 4660#define B_NCTL_CFG_SPAGE GENMASK(2, 1) 4661#define R_NCTL_RPT 0x8008 4662#define B_NCTL_RPT_FLG BIT(26) 4663#define R_NCTL_N1 0x8010 4664#define B_NCTL_N1_CIP GENMASK(7, 0) 4665#define R_NCTL_N2 0x8014 4666#define R_IQK_COM 0x8018 4667#define R_IQK_DIF 0x801C 4668#define B_IQK_DIF_TRX GENMASK(1, 0) 4669#define R_IQK_DIF1 0x8020 4670#define B_IQK_DIF1_TXPI GENMASK(19, 0) 4671#define R_IQK_DIF2 0x8024 4672#define B_IQK_DIF2_RXPI GENMASK(19, 0) 4673#define R_IQK_DIF4 0x802C 4674#define B_IQK_DIF4_RXT GENMASK(27, 16) 4675#define B_IQK_DIF4_TXT GENMASK(11, 0) 4676#define IQK_DF4_TXT_8_25MHZ 0x021 4677#define R_IQK_CFG 0x8034 4678#define B_IQK_CFG_SET GENMASK(5, 4) 4679#define R_IQK_RXA 0x8044 4680#define B_IQK_RXAGC GENMASK(15, 13) 4681#define R_TPG_SEL 0x8068 4682#define R_TPG_MOD 0x806C 4683#define B_TPG_MOD_F GENMASK(2, 1) 4684#define R_MDPK_SYNC 0x8070 4685#define B_MDPK_SYNC_SEL BIT(31) 4686#define B_MDPK_SYNC_MAN GENMASK(31, 28) 4687#define B_MDPK_SYNC_DMAN GENMASK(30, 28) 4688#define R_MDPK_RX_DCK 0x8074 4689#define B_MDPK_RX_DCK_EN BIT(31) 4690#define R_KIP_MOD 0x8078 4691#define B_KIP_MOD GENMASK(19, 0) 4692#define R_NCTL_RW 0x8080 4693#define R_KIP_SYSCFG 0x8088 4694#define R_KIP_CLK 0x808C 4695#define R_DPK_IDL 0x809C 4696#define B_DPK_IDL_SEL GENMASK(10, 9) 4697#define B_DPK_IDL BIT(8) 4698#define R_LDL_NORM 0x80A0 4699#define B_LDL_NORM_MA BIT(16) 4700#define B_LDL_NORM_PN GENMASK(12, 8) 4701#define B_LDL_NORM_OP GENMASK(1, 0) 4702#define R_DPK_CTL 0x80B0 4703#define B_DPK_CTL_EN BIT(28) 4704#define R_DPK_CFG 0x80B8 4705#define B_DPK_CFG_IDX GENMASK(14, 12) 4706#define R_DPK_CFG2 0x80BC 4707#define B_DPK_CFG2_ST BIT(14) 4708#define R_DPK_CFG3 0x80C0 4709#define R_KPATH_CFG 0x80D0 4710#define B_KPATH_CFG_ED GENMASK(21, 20) 4711#define R_KIP_RPT1 0x80D4 4712#define B_KIP_RPT1_SEL GENMASK(21, 16) 4713#define B_KIP_RPT1_SEL_V1 GENMASK(19, 16) 4714#define R_SRAM_IQRX 0x80D8 4715#define R_IDL_MPA 0x80DC 4716#define B_IDL_DN BIT(31) 4717#define B_IDL_MD530 BIT(1) 4718#define B_IDL_MD500 BIT(0) 4719#define R_GAPK 0x80E0 4720#define B_GAPK_ADR BIT(0) 4721#define R_SRAM_IQRX2 0x80E8 4722#define R_DPK_MPA 0x80EC 4723#define B_DPK_MPA_T0 BIT(10) 4724#define B_DPK_MPA_T1 BIT(9) 4725#define B_DPK_MPA_T2 BIT(8) 4726#define R_DPK_WR 0x80F4 4727#define B_DPK_WR_ST BIT(29) 4728#define R_DPK_TRK 0x80f0 4729#define B_DPK_TRK_DIS BIT(31) 4730#define R_RPT_COM 0x80FC 4731#define B_PRT_COM_SYNERR BIT(30) 4732#define B_PRT_COM_DCI GENMASK(27, 16) 4733#define B_PRT_COM_CORV GENMASK(15, 8) 4734#define B_RPT_COM_RDY GENMASK(15, 0) 4735#define B_PRT_COM_DCQ GENMASK(11, 0) 4736#define B_PRT_COM_RXOV BIT(8) 4737#define B_PRT_COM_GL GENMASK(7, 4) 4738#define B_PRT_COM_CORI GENMASK(7, 0) 4739#define B_PRT_COM_RXBB GENMASK(5, 0) 4740#define B_PRT_COM_RXBB_V1 GENMASK(4, 0) 4741#define B_PRT_COM_DONE BIT(0) 4742#define R_COEF_SEL 0x8104 4743#define B_COEF_SEL_IQC BIT(0) 4744#define B_COEF_SEL_MDPD BIT(8) 4745#define R_CFIR_SYS 0x8120 4746#define R_IQK_RES 0x8124 4747#define B_IQK_RES_K BIT(28) 4748#define B_IQK_RES_TXCFIR GENMASK(11, 8) 4749#define B_IQK_RES_RXCFIR GENMASK(3, 0) 4750#define R_TXIQC 0x8138 4751#define R_RXIQC 0x813c 4752#define B_RXIQC_BYPASS BIT(0) 4753#define B_RXIQC_BYPASS2 BIT(2) 4754#define B_RXIQC_NEWP GENMASK(19, 8) 4755#define B_RXIQC_NEWX GENMASK(31, 20) 4756#define R_KIP 0x8140 4757#define B_KIP_DBCC BIT(0) 4758#define B_KIP_RFGAIN BIT(8) 4759#define R_RFGAIN 0x8144 4760#define B_RFGAIN_PAD GENMASK(4, 0) 4761#define B_RFGAIN_TXBB GENMASK(12, 8) 4762#define R_RFGAIN_BND 0x8148 4763#define B_RFGAIN_BND GENMASK(4, 0) 4764#define R_CFIR_MAP 0x8150 4765#define R_CFIR_LUT 0x8154 4766#define B_CFIR_LUT_SEL BIT(8) 4767#define B_CFIR_LUT_SET BIT(4) 4768#define B_CFIR_LUT_G3 BIT(3) 4769#define B_CFIR_LUT_G2 BIT(2) 4770#define B_CFIR_LUT_GP_V1 GENMASK(2, 0) 4771#define B_CFIR_LUT_GP GENMASK(1, 0) 4772#define R_DPK_GN 0x819C 4773#define B_DPK_GN_EN GENMASK(17, 16) 4774#define B_DPK_GN_AG GENMASK(9, 0) 4775#define R_DPD_V1 0x81a0 4776#define B_DPD_LBK BIT(7) 4777#define R_DPD_CH0 0x81AC 4778#define R_DPD_BND 0x81B4 4779#define B_DPD_BND_1 GENMASK(24, 16) 4780#define B_DPD_BND_0 GENMASK(8, 0) 4781#define R_DPD_CH0A 0x81BC 4782#define B_DPD_MEN GENMASK(31, 28) 4783#define B_DPD_ORDER GENMASK(26, 24) 4784#define B_DPD_ORDER_V1 GENMASK(26, 25) 4785#define B_DPD_CFG GENMASK(22, 0) 4786#define B_DPD_SEL GENMASK(13, 8) 4787#define R_TXAGC_RFK 0x81C4 4788#define B_TXAGC_RFK_CH0 GENMASK(5, 0) 4789#define R_DPD_COM 0x81C8 4790#define B_DPD_COM_OF BIT(15) 4791#define R_KIP_IQP 0x81CC 4792#define B_KIP_IQP_SW GENMASK(13, 12) 4793#define B_KIP_IQP_IQSW GENMASK(5, 0) 4794#define R_KIP_RPT 0x81D4 4795#define B_KIP_RPT_SEL GENMASK(21, 16) 4796#define R_W_COEF 0x81D8 4797#define R_LOAD_COEF 0x81DC 4798#define B_LOAD_COEF_MDPD BIT(16) 4799#define B_LOAD_COEF_CFIR GENMASK(1, 0) 4800#define B_LOAD_COEF_DI BIT(1) 4801#define B_LOAD_COEF_AUTO BIT(0) 4802#define R_DPK_GL 0x81F0 4803#define B_DPK_GL_A0 GENMASK(31, 28) 4804#define B_DPK_GL_A1 GENMASK(17, 0) 4805#define R_RPT_PER 0x81FC 4806#define B_RPT_PER_KSET GENMASK(31, 29) 4807#define B_RPT_PER_TSSI GENMASK(28, 16) 4808#define B_RPT_PER_OF GENMASK(15, 8) 4809#define B_RPT_PER_TH GENMASK(5, 0) 4810#define R_IQRSN 0x8220 4811#define B_IQRSN_K1 BIT(28) 4812#define B_IQRSN_K2 BIT(16) 4813#define R_RXCFIR_P0C0 0x8D40 4814#define R_RXCFIR_P0C1 0x8D84 4815#define R_RXCFIR_P0C2 0x8DC8 4816#define R_RXCFIR_P0C3 0x8E0C 4817#define R_TXCFIR_P0C0 0x8F50 4818#define R_TXCFIR_P0C1 0x8F84 4819#define R_TXCFIR_P0C2 0x8FB8 4820#define R_TXCFIR_P0C3 0x8FEC 4821#define R_RXCFIR_P1C0 0x9140 4822#define R_RXCFIR_P1C1 0x9184 4823#define R_RXCFIR_P1C2 0x91C8 4824#define R_RXCFIR_P1C3 0x920C 4825#define R_TXCFIR_P1C0 0x9350 4826#define R_TXCFIR_P1C1 0x9384 4827#define R_TXCFIR_P1C2 0x93B8 4828#define R_TXCFIR_P1C3 0x93EC 4829#define R_IQKINF 0x9FE0 4830#define B_IQKINF_VER GENMASK(31, 24) 4831#define B_IQKINF_FAIL_RXGRP GENMASK(23, 16) 4832#define B_IQKINF_FAIL_TXGRP GENMASK(15, 8) 4833#define B_IQKINF_FAIL GENMASK(3, 0) 4834#define B_IQKINF_F_RX BIT(3) 4835#define B_IQKINF_FTX BIT(2) 4836#define B_IQKINF_FFIN BIT(1) 4837#define B_IQKINF_FCOR BIT(0) 4838#define R_IQKCH 0x9FE4 4839#define B_IQKCH_CH GENMASK(15, 8) 4840#define B_IQKCH_BW GENMASK(7, 4) 4841#define B_IQKCH_BAND GENMASK(3, 0) 4842#define R_IQKINF2 0x9FE8 4843#define B_IQKINF2_FCNT GENMASK(23, 16) 4844#define B_IQKINF2_KCNT GENMASK(15, 8) 4845#define B_IQKINF2_NCTLV GENMASK(7, 0) 4846#define R_DCOF0 0xC000 4847#define B_DCOF0_RST BIT(17) 4848#define B_DCOF0_V GENMASK(4, 1) 4849#define R_DCOF1 0xC004 4850#define B_DCOF1_RST BIT(17) 4851#define B_DCOF1_S BIT(0) 4852#define R_DCOF8 0xC020 4853#define B_DCOF8_V GENMASK(4, 1) 4854#define R_DCOF9 0xC024 4855#define B_DCOF9_RST BIT(17) 4856#define R_DACK_S0P0 0xC040 4857#define B_DACK_S0P0_OK BIT(31) 4858#define R_DACK_BIAS00 0xc048 4859#define B_DACK_BIAS00 GENMASK(11, 2) 4860#define R_DACK_S0P2 0xC05C 4861#define B_DACK_S0M0 GENMASK(31, 24) 4862#define B_DACK_S0P2_OK BIT(2) 4863#define R_DACK_DADCK00 0xC060 4864#define B_DACK_DADCK00 GENMASK(31, 24) 4865#define R_DACK_S0P1 0xC064 4866#define B_DACK_S0P1_OK BIT(31) 4867#define R_DACK_BIAS01 0xC06C 4868#define B_DACK_BIAS01 GENMASK(11, 2) 4869#define R_DACK_S0P3 0xC080 4870#define B_DACK_S0M1 GENMASK(31, 24) 4871#define B_DACK_S0P3_OK BIT(2) 4872#define R_DACK_DADCK01 0xC084 4873#define B_DACK_DADCK01 GENMASK(31, 24) 4874#define R_DRCK_FH 0xC094 4875#define B_DRCK_LAT BIT(9) 4876#define R_DRCK 0xC0C4 4877#define B_DRCK_MUL GENMASK(21, 17) 4878#define B_DRCK_IDLE BIT(9) 4879#define B_DRCK_EN BIT(6) 4880#define B_DRCK_VAL GENMASK(4, 0) 4881#define R_DRCK_RES 0xC0C8 4882#define B_DRCK_RES GENMASK(19, 15) 4883#define B_DRCK_POL BIT(3) 4884#define R_DRCK_V1 0xC0CC 4885#define B_DRCK_V1_SEL BIT(9) 4886#define B_DRCK_V1_KICK BIT(6) 4887#define B_DRCK_V1_CV GENMASK(4, 0) 4888#define R_DRCK_RS 0xC0D0 4889#define B_DRCK_RS_LPS GENMASK(19, 15) 4890#define B_DRCK_RS_DONE BIT(3) 4891#define R_PATH0_SAMPL_DLY_T_V1 0xC0D4 4892#define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) 4893#define R_P0_CFCH_BW0 0xC0D4 4894#define B_P0_CFCH_BW0 GENMASK(27, 26) 4895#define B_P0_CFCH_EN GENMASK(14, 11) 4896#define B_P0_CFCH_CTL GENMASK(10, 7) 4897#define R_P0_CFCH_BW1 0xC0D8 4898#define B_P0_CFCH_EX BIT(13) 4899#define B_P0_CFCH_BW1 GENMASK(8, 5) 4900#define R_WDADC 0xC0E4 4901#define B_WDADC_SEL GENMASK(5, 4) 4902#define R_ADCMOD 0xC0E8 4903#define B_ADCMOD_LP GENMASK(31, 16) 4904#define R_DCIM 0xC0EC 4905#define B_DCIM_FR GENMASK(14, 13) 4906#define R_ADDCK0D 0xC0F0 4907#define B_ADDCK0D_VAL2 GENMASK(31, 26) 4908#define B_ADDCK0D_VAL GENMASK(25, 16) 4909#define B_ADDCK_DS BIT(16) 4910#define R_ADDCK0 0xC0F4 4911#define B_ADDCK0_TRG BIT(11) 4912#define B_ADDCK0_IQ BIT(10) 4913#define B_ADDCK0 GENMASK(9, 8) 4914#define B_ADDCK0_MAN GENMASK(5, 4) 4915#define B_ADDCK0_EN BIT(4) 4916#define B_ADDCK0_VAL GENMASK(3, 0) 4917#define B_ADDCK0_RST BIT(2) 4918#define R_ADDCK0_RL 0xC0F8 4919#define B_ADDCK0_RLS GENMASK(29, 28) 4920#define B_ADDCK0_RL1 GENMASK(27, 18) 4921#define B_ADDCK0_RL0 GENMASK(17, 8) 4922#define R_ADDCKR0 0xC0FC 4923#define B_ADDCKR0_A0 GENMASK(19, 10) 4924#define B_ADDCKR0_DC GENMASK(15, 4) 4925#define B_ADDCKR0_A1 GENMASK(9, 0) 4926#define R_DACK10 0xC100 4927#define B_DACK10 GENMASK(4, 1) 4928#define R_DACK1_K 0xc104 4929#define B_DACK1_EN BIT(0) 4930#define R_DACK11 0xC120 4931#define B_DACK11 GENMASK(4, 1) 4932#define R_DACK_S1P0 0xC140 4933#define B_DACK_S1P0_OK BIT(31) 4934#define R_DACK_BIAS10 0xC148 4935#define B_DACK_BIAS10 GENMASK(11, 2) 4936#define R_DACK10S 0xC15C 4937#define B_DACK10S GENMASK(31, 24) 4938#define R_DACK_S1P2 0xC15C 4939#define B_DACK_S1P2_OK BIT(2) 4940#define R_DACK_DADCK10 0xC160 4941#define B_DACK_DADCK10 GENMASK(31, 24) 4942#define R_DACK_S1P1 0xC164 4943#define B_DACK_S1P1_OK BIT(31) 4944#define R_DACK_BIAS11 0xC16C 4945#define B_DACK_BIAS11 GENMASK(11, 2) 4946#define R_DACK11S 0xC180 4947#define B_DACK11S GENMASK(31, 24) 4948#define R_DACK_S1P3 0xC180 4949#define B_DACK_S1P3_OK BIT(2) 4950#define R_DACK_DADCK11 0xC184 4951#define B_DACK_DADCK11 GENMASK(31, 24) 4952#define R_PATH1_SAMPL_DLY_T_V1 0xC1D4 4953#define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) 4954#define R_PATH0_BW_SEL_V1 0xC0D8 4955#define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5) 4956#define R_PATH1_BW_SEL_V1 0xC1D8 4957#define B_PATH1_BW_SEL_EX BIT(13) 4958#define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5) 4959#define R_ADDCK1D 0xC1F0 4960#define B_ADDCK1D_VAL2 GENMASK(31, 26) 4961#define B_ADDCK1D_VAL GENMASK(25, 16) 4962#define R_ADDCK1 0xC1F4 4963#define B_ADDCK1_TRG BIT(11) 4964#define B_ADDCK1 GENMASK(9, 8) 4965#define B_ADDCK1_MAN GENMASK(5, 4) 4966#define B_ADDCK1_EN BIT(4) 4967#define B_ADDCK1_RST BIT(2) 4968#define R_ADDCK1_RL 0xC1F8 4969#define B_ADDCK1_RLS GENMASK(29, 28) 4970#define B_ADDCK1_RL1 GENMASK(27, 18) 4971#define B_ADDCK1_RL0 GENMASK(17, 8) 4972#define R_ADDCKR1 0xC1fC 4973#define B_ADDCKR1_A0 GENMASK(19, 10) 4974#define B_ADDCKR1_A1 GENMASK(9, 0) 4975#define R_DACKN0_CTL 0xC210 4976#define B_DACKN0_EN BIT(0) 4977#define B_DACKN0_V GENMASK(21, 14) 4978#define R_DACKN1_CTL 0xC224 4979#define B_DACKN1_V GENMASK(21, 14) 4980 4981/* WiFi CPU local domain */ 4982#define R_AX_WDT_CTRL 0x0040 4983#define B_AX_WDT_EN BIT(31) 4984#define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29) 4985#define B_AX_IO_HANG_IMR BIT(27) 4986#define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26) 4987#define B_AX_IO_HANG_DMAC_EN BIT(25) 4988#define B_AX_WDT_CLR BIT(16) 4989#define B_AX_WDT_COUNT_MASK GENMASK(15, 0) 4990#define WDT_CTRL_ALL_DIS 0 4991 4992#define R_AX_WDT_STATUS 0x0044 4993#define B_AX_FS_WDT_INT BIT(8) 4994#define B_AX_FS_WDT_INT_MSK BIT(0) 4995 4996#endif 4997