1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5#if defined(__FreeBSD__) 6#define LINUXKPI_PARAM_PREFIX rtw89_debug_ 7#endif 8 9#include <linux/vmalloc.h> 10 11#include "coex.h" 12#include "debug.h" 13#include "fw.h" 14#include "mac.h" 15#include "pci.h" 16#include "ps.h" 17#include "reg.h" 18#include "sar.h" 19#if defined(__FreeBSD__) 20#ifdef CONFIG_RTW89_DEBUGFS 21#include <linux/debugfs.h> 22#endif 23#endif 24 25#ifdef CONFIG_RTW89_DEBUGMSG 26unsigned int rtw89_debug_mask; 27EXPORT_SYMBOL(rtw89_debug_mask); 28module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 29MODULE_PARM_DESC(debug_mask, "Debugging mask"); 30#endif 31 32#ifdef CONFIG_RTW89_DEBUGFS 33struct rtw89_debugfs_priv { 34 struct rtw89_dev *rtwdev; 35 int (*cb_read)(struct seq_file *m, void *v); 36 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 37 size_t count, loff_t *loff); 38 union { 39 u32 cb_data; 40 struct { 41 u32 addr; 42 u32 len; 43 } read_reg; 44 struct { 45 u32 addr; 46 u32 mask; 47 u8 path; 48 } read_rf; 49 struct { 50 u8 ss_dbg:1; 51 u8 dle_dbg:1; 52 u8 dmac_dbg:1; 53 u8 cmac_dbg:1; 54 u8 dbg_port:1; 55 } dbgpkg_en; 56 struct { 57 u32 start; 58 u32 len; 59 u8 sel; 60 } mac_mem; 61 }; 62}; 63 64static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 65 [RATE_INFO_BW_20] = 20, 66 [RATE_INFO_BW_40] = 40, 67 [RATE_INFO_BW_80] = 80, 68 [RATE_INFO_BW_160] = 160, 69 [RATE_INFO_BW_320] = 320, 70}; 71 72static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 73{ 74 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 75 return rtw89_rate_info_bw_to_mhz_map[bw]; 76 77 return 0; 78} 79 80static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 81{ 82 struct rtw89_debugfs_priv *debugfs_priv = m->private; 83 84 return debugfs_priv->cb_read(m, v); 85} 86 87static ssize_t rtw89_debugfs_single_write(struct file *filp, 88 const char __user *buffer, 89 size_t count, loff_t *loff) 90{ 91 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 92 93 return debugfs_priv->cb_write(filp, buffer, count, loff); 94} 95 96static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 97 const char __user *buffer, 98 size_t count, loff_t *loff) 99{ 100 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 101 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 102 103 return debugfs_priv->cb_write(filp, buffer, count, loff); 104} 105 106static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 107{ 108 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 109} 110 111static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 112{ 113 return 0; 114} 115 116static const struct file_operations file_ops_single_r = { 117 .owner = THIS_MODULE, 118 .open = rtw89_debugfs_single_open, 119 .read = seq_read, 120 .llseek = seq_lseek, 121 .release = single_release, 122}; 123 124static const struct file_operations file_ops_common_rw = { 125 .owner = THIS_MODULE, 126 .open = rtw89_debugfs_single_open, 127 .release = single_release, 128 .read = seq_read, 129 .llseek = seq_lseek, 130 .write = rtw89_debugfs_seq_file_write, 131}; 132 133static const struct file_operations file_ops_single_w = { 134 .owner = THIS_MODULE, 135 .write = rtw89_debugfs_single_write, 136 .open = simple_open, 137 .release = rtw89_debugfs_close, 138}; 139 140static ssize_t 141rtw89_debug_priv_read_reg_select(struct file *filp, 142 const char __user *user_buf, 143 size_t count, loff_t *loff) 144{ 145 struct seq_file *m = (struct seq_file *)filp->private_data; 146 struct rtw89_debugfs_priv *debugfs_priv = m->private; 147 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 148 char buf[32]; 149 size_t buf_size; 150 u32 addr, len; 151 int num; 152 153 buf_size = min(count, sizeof(buf) - 1); 154 if (copy_from_user(buf, user_buf, buf_size)) 155 return -EFAULT; 156 157 buf[buf_size] = '\0'; 158 num = sscanf(buf, "%x %x", &addr, &len); 159 if (num != 2) { 160 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 161 return -EINVAL; 162 } 163 164 debugfs_priv->read_reg.addr = addr; 165 debugfs_priv->read_reg.len = len; 166 167 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 168 169 return count; 170} 171 172static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 173{ 174 struct rtw89_debugfs_priv *debugfs_priv = m->private; 175 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 176 u32 addr, end, data, k; 177 u32 len; 178 179 len = debugfs_priv->read_reg.len; 180 addr = debugfs_priv->read_reg.addr; 181 182 if (len > 4) 183 goto ndata; 184 185 switch (len) { 186 case 1: 187 data = rtw89_read8(rtwdev, addr); 188 break; 189 case 2: 190 data = rtw89_read16(rtwdev, addr); 191 break; 192 case 4: 193 data = rtw89_read32(rtwdev, addr); 194 break; 195 default: 196 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 197 return -EINVAL; 198 } 199 200 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 201 202 return 0; 203 204ndata: 205 end = addr + len; 206 207 for (; addr < end; addr += 16) { 208 seq_printf(m, "%08xh : ", 0x18600000 + addr); 209 for (k = 0; k < 16; k += 4) { 210 data = rtw89_read32(rtwdev, addr + k); 211 seq_printf(m, "%08x ", data); 212 } 213 seq_puts(m, "\n"); 214 } 215 216 return 0; 217} 218 219static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 220 const char __user *user_buf, 221 size_t count, loff_t *loff) 222{ 223 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 224 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 225 char buf[32]; 226 size_t buf_size; 227 u32 addr, val, len; 228 int num; 229 230 buf_size = min(count, sizeof(buf) - 1); 231 if (copy_from_user(buf, user_buf, buf_size)) 232 return -EFAULT; 233 234 buf[buf_size] = '\0'; 235 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 236 if (num != 3) { 237 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 238 return -EINVAL; 239 } 240 241 switch (len) { 242 case 1: 243 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 244 rtw89_write8(rtwdev, addr, (u8)val); 245 break; 246 case 2: 247 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 248 rtw89_write16(rtwdev, addr, (u16)val); 249 break; 250 case 4: 251 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 252 rtw89_write32(rtwdev, addr, (u32)val); 253 break; 254 default: 255 rtw89_info(rtwdev, "invalid read write len %d\n", len); 256 break; 257 } 258 259 return count; 260} 261 262static ssize_t 263rtw89_debug_priv_read_rf_select(struct file *filp, 264 const char __user *user_buf, 265 size_t count, loff_t *loff) 266{ 267 struct seq_file *m = (struct seq_file *)filp->private_data; 268 struct rtw89_debugfs_priv *debugfs_priv = m->private; 269 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 270 char buf[32]; 271 size_t buf_size; 272 u32 addr, mask; 273 u8 path; 274 int num; 275 276 buf_size = min(count, sizeof(buf) - 1); 277 if (copy_from_user(buf, user_buf, buf_size)) 278 return -EFAULT; 279 280 buf[buf_size] = '\0'; 281 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 282 if (num != 3) { 283 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 284 return -EINVAL; 285 } 286 287 if (path >= rtwdev->chip->rf_path_num) { 288 rtw89_info(rtwdev, "wrong rf path\n"); 289 return -EINVAL; 290 } 291 debugfs_priv->read_rf.addr = addr; 292 debugfs_priv->read_rf.mask = mask; 293 debugfs_priv->read_rf.path = path; 294 295 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 296 297 return count; 298} 299 300static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 301{ 302 struct rtw89_debugfs_priv *debugfs_priv = m->private; 303 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 304 u32 addr, data, mask; 305 u8 path; 306 307 addr = debugfs_priv->read_rf.addr; 308 mask = debugfs_priv->read_rf.mask; 309 path = debugfs_priv->read_rf.path; 310 311 data = rtw89_read_rf(rtwdev, path, addr, mask); 312 313 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 314 315 return 0; 316} 317 318static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 319 const char __user *user_buf, 320 size_t count, loff_t *loff) 321{ 322 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 323 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 324 char buf[32]; 325 size_t buf_size; 326 u32 addr, val, mask; 327 u8 path; 328 int num; 329 330 buf_size = min(count, sizeof(buf) - 1); 331 if (copy_from_user(buf, user_buf, buf_size)) 332 return -EFAULT; 333 334 buf[buf_size] = '\0'; 335 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 336 if (num != 4) { 337 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 338 return -EINVAL; 339 } 340 341 if (path >= rtwdev->chip->rf_path_num) { 342 rtw89_info(rtwdev, "wrong rf path\n"); 343 return -EINVAL; 344 } 345 346 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 347 path, addr, val, mask); 348 rtw89_write_rf(rtwdev, path, addr, mask, val); 349 350 return count; 351} 352 353static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 354{ 355 struct rtw89_debugfs_priv *debugfs_priv = m->private; 356 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 357 const struct rtw89_chip_info *chip = rtwdev->chip; 358 u32 addr, offset, data; 359 u8 path; 360 361 for (path = 0; path < chip->rf_path_num; path++) { 362 seq_printf(m, "RF path %d:\n\n", path); 363 for (addr = 0; addr < 0x100; addr += 4) { 364 seq_printf(m, "0x%08x: ", addr); 365 for (offset = 0; offset < 4; offset++) { 366 data = rtw89_read_rf(rtwdev, path, 367 addr + offset, RFREG_MASK); 368 seq_printf(m, "0x%05x ", data); 369 } 370 seq_puts(m, "\n"); 371 } 372 seq_puts(m, "\n"); 373 } 374 375 return 0; 376} 377 378struct txpwr_ent { 379 const char *txt; 380 u8 len; 381}; 382 383struct txpwr_map { 384 const struct txpwr_ent *ent; 385 u8 size; 386 u32 addr_from; 387 u32 addr_to; 388 u32 addr_to_1ss; 389}; 390 391#define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 392 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 393 394#define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 395 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 396 397#define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 398 { .len = 8, .txt = _t "\t- " \ 399 _e0 " " _e1 " " _e2 " " _e3 " " \ 400 _e4 " " _e5 " " _e6 " " _e7 } 401 402static const struct txpwr_ent __txpwr_ent_byr[] = { 403 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 404 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 405 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 406 /* 1NSS */ 407 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 408 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 409 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 410 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 411 /* 2NSS */ 412 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 413 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 414 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 415 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 416}; 417 418#if defined(__linux__) 419static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 420#elif defined(__FreeBSD__) 421rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 422#endif 423 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 424 425static const struct txpwr_map __txpwr_map_byr = { 426 .ent = __txpwr_ent_byr, 427 .size = ARRAY_SIZE(__txpwr_ent_byr), 428 .addr_from = R_AX_PWR_BY_RATE, 429 .addr_to = R_AX_PWR_BY_RATE_MAX, 430 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 431}; 432 433static const struct txpwr_ent __txpwr_ent_lmt[] = { 434 /* 1TX */ 435 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 436 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 437 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 438 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 439 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 440 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 441 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 442 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 443 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 444 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 445 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 446 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 447 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 448 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 449 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 450 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 451 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 452 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 453 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 454 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 455 /* 2TX */ 456 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 457 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 458 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 459 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 460 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 461 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 462 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 463 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 464 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 465 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 466 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 467 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 468 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 469 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 470 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 471 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 472 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 473 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 474 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 475 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 476}; 477 478#if defined(__linux__) 479static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 480#elif defined(__FreeBSD__) 481rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 482#endif 483 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 484 485static const struct txpwr_map __txpwr_map_lmt = { 486 .ent = __txpwr_ent_lmt, 487 .size = ARRAY_SIZE(__txpwr_ent_lmt), 488 .addr_from = R_AX_PWR_LMT, 489 .addr_to = R_AX_PWR_LMT_MAX, 490 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 491}; 492 493static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 494 /* 1TX */ 495 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 496 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 497 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 498 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 499 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 500 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 501 /* 2TX */ 502 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 503 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 504 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 505 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 506 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 507 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 508}; 509 510#if defined(__linux__) 511static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 512#elif defined(__FreeBSD__) 513rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 514#endif 515 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 516 517static const struct txpwr_map __txpwr_map_lmt_ru = { 518 .ent = __txpwr_ent_lmt_ru, 519 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 520 .addr_from = R_AX_PWR_RU_LMT, 521 .addr_to = R_AX_PWR_RU_LMT_MAX, 522 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 523}; 524 525static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 526 const s8 *buf, const u8 cur) 527{ 528 char *fmt; 529 530 switch (ent->len) { 531 case 2: 532 fmt = "%s\t| %3d, %3d,\tdBm\n"; 533 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 534 return 2; 535 case 4: 536 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 537 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 538 buf[cur + 2], buf[cur + 3]); 539 return 4; 540 case 8: 541 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 542 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 543 buf[cur + 2], buf[cur + 3], buf[cur + 4], 544 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 545 return 8; 546 default: 547 return 0; 548 } 549} 550 551static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 552 const struct txpwr_map *map) 553{ 554 u8 fct = rtwdev->chip->txpwr_factor_mac; 555 u8 path_num = rtwdev->chip->rf_path_num; 556 u32 max_valid_addr; 557 u32 val, addr; 558 s8 *buf, tmp; 559 u8 cur, i; 560 int ret; 561 562 buf = vzalloc(map->addr_to - map->addr_from + 4); 563 if (!buf) 564 return -ENOMEM; 565 566 if (path_num == 1) 567 max_valid_addr = map->addr_to_1ss; 568 else 569 max_valid_addr = map->addr_to; 570 571 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 572 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 573 if (ret) 574 val = MASKDWORD; 575 576 cur = addr - map->addr_from; 577 for (i = 0; i < 4; i++, val >>= 8) { 578 /* signed 7 bits, and reserved BIT(7) */ 579 tmp = sign_extend32(val, 6); 580 buf[cur + i] = tmp >> fct; 581 } 582 } 583 584 for (cur = 0, i = 0; i < map->size; i++) 585 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 586 587 vfree(buf); 588 return 0; 589} 590 591#define case_REGD(_regd) \ 592 case RTW89_ ## _regd: \ 593 seq_puts(m, #_regd "\n"); \ 594 break 595 596static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 597{ 598 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 599 u8 band = chan->band_type; 600 u8 regd = rtw89_regd_get(rtwdev, band); 601 602 switch (regd) { 603 default: 604 seq_printf(m, "UNKNOWN: %d\n", regd); 605 break; 606 case_REGD(WW); 607 case_REGD(ETSI); 608 case_REGD(FCC); 609 case_REGD(MKK); 610 case_REGD(NA); 611 case_REGD(IC); 612 case_REGD(KCC); 613 case_REGD(NCC); 614 case_REGD(CHILE); 615 case_REGD(ACMA); 616 case_REGD(MEXICO); 617 case_REGD(UKRAINE); 618 case_REGD(CN); 619 } 620} 621 622#undef case_REGD 623 624static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 625{ 626 struct rtw89_debugfs_priv *debugfs_priv = m->private; 627 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 628 int ret = 0; 629 630 mutex_lock(&rtwdev->mutex); 631 rtw89_leave_ps_mode(rtwdev); 632 633 seq_puts(m, "[Regulatory] "); 634 __print_regd(m, rtwdev); 635 636 seq_puts(m, "[SAR]\n"); 637 rtw89_print_sar(m, rtwdev); 638 639 seq_puts(m, "\n[TX power byrate]\n"); 640 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 641 if (ret) 642 goto err; 643 644 seq_puts(m, "\n[TX power limit]\n"); 645 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 646 if (ret) 647 goto err; 648 649 seq_puts(m, "\n[TX power limit_ru]\n"); 650 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 651 if (ret) 652 goto err; 653 654err: 655 mutex_unlock(&rtwdev->mutex); 656 return ret; 657} 658 659static ssize_t 660rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 661 const char __user *user_buf, 662 size_t count, loff_t *loff) 663{ 664 struct seq_file *m = (struct seq_file *)filp->private_data; 665 struct rtw89_debugfs_priv *debugfs_priv = m->private; 666 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 667 const struct rtw89_chip_info *chip = rtwdev->chip; 668 char buf[32]; 669 size_t buf_size; 670 int sel; 671 int ret; 672 673 buf_size = min(count, sizeof(buf) - 1); 674 if (copy_from_user(buf, user_buf, buf_size)) 675 return -EFAULT; 676 677 buf[buf_size] = '\0'; 678 ret = kstrtoint(buf, 0, &sel); 679 if (ret) 680 return ret; 681 682 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 683 rtw89_info(rtwdev, "invalid args: %d\n", sel); 684 return -EINVAL; 685 } 686 687 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 688 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 689 chip->chip_id); 690 return -EINVAL; 691 } 692 693 debugfs_priv->cb_data = sel; 694 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 695 696 return count; 697} 698 699#define RTW89_MAC_PAGE_SIZE 0x100 700 701static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 702{ 703 struct rtw89_debugfs_priv *debugfs_priv = m->private; 704 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 705 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 706 u32 start, end; 707 u32 i, j, k, page; 708 u32 val; 709 710 switch (reg_sel) { 711 case RTW89_DBG_SEL_MAC_00: 712 seq_puts(m, "Debug selected MAC page 0x00\n"); 713 start = 0x000; 714 end = 0x014; 715 break; 716 case RTW89_DBG_SEL_MAC_30: 717 seq_puts(m, "Debug selected MAC page 0x30\n"); 718 start = 0x030; 719 end = 0x033; 720 break; 721 case RTW89_DBG_SEL_MAC_40: 722 seq_puts(m, "Debug selected MAC page 0x40\n"); 723 start = 0x040; 724 end = 0x07f; 725 break; 726 case RTW89_DBG_SEL_MAC_80: 727 seq_puts(m, "Debug selected MAC page 0x80\n"); 728 start = 0x080; 729 end = 0x09f; 730 break; 731 case RTW89_DBG_SEL_MAC_C0: 732 seq_puts(m, "Debug selected MAC page 0xc0\n"); 733 start = 0x0c0; 734 end = 0x0df; 735 break; 736 case RTW89_DBG_SEL_MAC_E0: 737 seq_puts(m, "Debug selected MAC page 0xe0\n"); 738 start = 0x0e0; 739 end = 0x0ff; 740 break; 741 case RTW89_DBG_SEL_BB: 742 seq_puts(m, "Debug selected BB register\n"); 743 start = 0x100; 744 end = 0x17f; 745 break; 746 case RTW89_DBG_SEL_IQK: 747 seq_puts(m, "Debug selected IQK register\n"); 748 start = 0x180; 749 end = 0x1bf; 750 break; 751 case RTW89_DBG_SEL_RFC: 752 seq_puts(m, "Debug selected RFC register\n"); 753 start = 0x1c0; 754 end = 0x1ff; 755 break; 756 default: 757 seq_puts(m, "Selected invalid register page\n"); 758 return -EINVAL; 759 } 760 761 for (i = start; i <= end; i++) { 762 page = i << 8; 763 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 764 seq_printf(m, "%08xh : ", 0x18600000 + j); 765 for (k = 0; k < 4; k++) { 766 val = rtw89_read32(rtwdev, j + (k << 2)); 767 seq_printf(m, "%08x ", val); 768 } 769 seq_puts(m, "\n"); 770 } 771 } 772 773 return 0; 774} 775 776static ssize_t 777rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 778 const char __user *user_buf, 779 size_t count, loff_t *loff) 780{ 781 struct seq_file *m = (struct seq_file *)filp->private_data; 782 struct rtw89_debugfs_priv *debugfs_priv = m->private; 783 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 784 char buf[32]; 785 size_t buf_size; 786 u32 sel, start_addr, len; 787 int num; 788 789 buf_size = min(count, sizeof(buf) - 1); 790 if (copy_from_user(buf, user_buf, buf_size)) 791 return -EFAULT; 792 793 buf[buf_size] = '\0'; 794 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 795 if (num != 3) { 796 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 797 return -EINVAL; 798 } 799 800 debugfs_priv->mac_mem.sel = sel; 801 debugfs_priv->mac_mem.start = start_addr; 802 debugfs_priv->mac_mem.len = len; 803 804 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 805 sel, start_addr, len); 806 807 return count; 808} 809 810static void rtw89_debug_dump_mac_mem(struct seq_file *m, 811 struct rtw89_dev *rtwdev, 812 u8 sel, u32 start_addr, u32 len) 813{ 814 u32 base_addr, start_page, residue; 815 u32 i, j, p, pages; 816 u32 dump_len, remain; 817 u32 val; 818 819 remain = len; 820 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 821 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 822 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 823 base_addr = rtw89_mac_mem_base_addrs[sel]; 824 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 825 826 for (p = 0; p < pages; p++) { 827 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 828 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 829 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 830 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 831 seq_printf(m, "%08xh:", i); 832 for (j = 0; 833 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 834 j++, i += 4) { 835 val = rtw89_read32(rtwdev, i); 836 seq_printf(m, " %08x", val); 837 remain -= 4; 838 } 839 seq_puts(m, "\n"); 840 } 841 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 842 } 843} 844 845static int 846rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 847{ 848 struct rtw89_debugfs_priv *debugfs_priv = m->private; 849 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 850 bool grant_read = false; 851 852 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 853 return -ENOENT; 854 855 if (rtwdev->chip->chip_id == RTL8852C) { 856 switch (debugfs_priv->mac_mem.sel) { 857 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 858 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 859 case RTW89_MAC_MEM_TXDATA_FIFO_0: 860 case RTW89_MAC_MEM_TXDATA_FIFO_1: 861 grant_read = true; 862 break; 863 default: 864 break; 865 } 866 } 867 868 mutex_lock(&rtwdev->mutex); 869 rtw89_leave_ps_mode(rtwdev); 870 if (grant_read) 871 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 872 rtw89_debug_dump_mac_mem(m, rtwdev, 873 debugfs_priv->mac_mem.sel, 874 debugfs_priv->mac_mem.start, 875 debugfs_priv->mac_mem.len); 876 if (grant_read) 877 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 878 mutex_unlock(&rtwdev->mutex); 879 880 return 0; 881} 882 883static ssize_t 884rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 885 const char __user *user_buf, 886 size_t count, loff_t *loff) 887{ 888 struct seq_file *m = (struct seq_file *)filp->private_data; 889 struct rtw89_debugfs_priv *debugfs_priv = m->private; 890 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 891 char buf[32]; 892 size_t buf_size; 893 int sel, set; 894 int num; 895 bool enable; 896 897 buf_size = min(count, sizeof(buf) - 1); 898 if (copy_from_user(buf, user_buf, buf_size)) 899 return -EFAULT; 900 901 buf[buf_size] = '\0'; 902 num = sscanf(buf, "%d %d", &sel, &set); 903 if (num != 2) { 904 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 905 return -EINVAL; 906 } 907 908 enable = set != 0; 909 switch (sel) { 910 case 0: 911 debugfs_priv->dbgpkg_en.ss_dbg = enable; 912 break; 913 case 1: 914 debugfs_priv->dbgpkg_en.dle_dbg = enable; 915 break; 916 case 2: 917 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 918 break; 919 case 3: 920 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 921 break; 922 case 4: 923 debugfs_priv->dbgpkg_en.dbg_port = enable; 924 break; 925 default: 926 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 927 return -EINVAL; 928 } 929 930 rtw89_info(rtwdev, "%s debug port dump %d\n", 931 enable ? "Enable" : "Disable", sel); 932 933 return count; 934} 935 936static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 937 struct seq_file *m) 938{ 939 return 0; 940} 941 942static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 943 struct seq_file *m) 944{ 945#define DLE_DFI_DUMP(__type, __target, __sel) \ 946({ \ 947 u32 __ctrl; \ 948 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 949 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 950 u32 __data, __val32; \ 951 int __ret; \ 952 \ 953 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 954 DLE_DFI_TYPE_##__target) | \ 955 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 956 B_AX_WDE_DFI_ACTIVE; \ 957 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 958 __ret = read_poll_timeout(rtw89_read32, __val32, \ 959 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 960 1000, 50000, false, \ 961 rtwdev, __reg_ctrl); \ 962 if (__ret) { \ 963 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 964 #__type, #__target, __sel); \ 965 return __ret; \ 966 } \ 967 \ 968 __data = rtw89_read32(rtwdev, __reg_data); \ 969 __data; \ 970}) 971 972#define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 973({ \ 974 u32 __freepg, __pubpg; \ 975 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 976 \ 977 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 978 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 979 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 980 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 981 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 982 seq_printf(__m, "[%s] freepg head: %d\n", \ 983 #__type, __freepg_head); \ 984 seq_printf(__m, "[%s] freepg tail: %d\n", \ 985 #__type, __freepg_tail); \ 986 seq_printf(__m, "[%s] pubpg num : %d\n", \ 987 #__type, __pubpg_num); \ 988}) 989 990#define case_QUOTA(__m, __type, __id) \ 991 case __type##_QTAID_##__id: \ 992 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 993 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 994 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 995 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 996 #__type, #__id, rsv_pgnum); \ 997 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 998 #__type, #__id, use_pgnum); \ 999 break 1000 u32 quota_id; 1001 u32 val32; 1002 u16 rsv_pgnum, use_pgnum; 1003 int ret; 1004 1005 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1006 if (ret) { 1007 seq_puts(m, "[DLE] : DMAC not enabled\n"); 1008 return ret; 1009 } 1010 1011 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 1012 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 1013 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1014 switch (quota_id) { 1015 case_QUOTA(m, WDE, HOST_IF); 1016 case_QUOTA(m, WDE, WLAN_CPU); 1017 case_QUOTA(m, WDE, DATA_CPU); 1018 case_QUOTA(m, WDE, PKTIN); 1019 case_QUOTA(m, WDE, CPUIO); 1020 } 1021 } 1022 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1023 switch (quota_id) { 1024 case_QUOTA(m, PLE, B0_TXPL); 1025 case_QUOTA(m, PLE, B1_TXPL); 1026 case_QUOTA(m, PLE, C2H); 1027 case_QUOTA(m, PLE, H2C); 1028 case_QUOTA(m, PLE, WLAN_CPU); 1029 case_QUOTA(m, PLE, MPDU); 1030 case_QUOTA(m, PLE, CMAC0_RX); 1031 case_QUOTA(m, PLE, CMAC1_RX); 1032 case_QUOTA(m, PLE, CMAC1_BBRPT); 1033 case_QUOTA(m, PLE, WDRLS); 1034 case_QUOTA(m, PLE, CPUIO); 1035 } 1036 } 1037 1038 return 0; 1039 1040#undef case_QUOTA 1041#undef DLE_DFI_DUMP 1042#undef DLE_DFI_FREE_PAGE_DUMP 1043} 1044 1045static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1046 struct seq_file *m) 1047{ 1048 const struct rtw89_chip_info *chip = rtwdev->chip; 1049 u32 dmac_err; 1050 int i, ret; 1051 1052 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1053 if (ret) { 1054 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1055 return ret; 1056 } 1057 1058 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1059 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1060 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1061 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1062 1063 if (dmac_err) { 1064 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1065 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1066 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1067 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1068 if (chip->chip_id == RTL8852C) { 1069 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1070 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1071 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1072 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1073 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1074 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1075 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1076 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1077 } 1078 } 1079 1080 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1081 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1082 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1083 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1084 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1085 if (chip->chip_id == RTL8852C) 1086 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1087 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1088 else 1089 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1090 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1091 } 1092 1093 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1094 if (chip->chip_id == RTL8852C) { 1095 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1096 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1097 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1098 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1099 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1100 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1101 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1102 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1103 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1104 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1105 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1106 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1107 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1108 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1109 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1110 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1111 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1112 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1113 1114 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1115 B_AX_DBG_SEL0, 0x8B); 1116 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1117 B_AX_DBG_SEL1, 0x8B); 1118 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1119 B_AX_SEL_0XC0_MASK, 1); 1120 for (i = 0; i < 0x10; i++) { 1121 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1122 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1123 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1124 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1125 } 1126 } else { 1127 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1128 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1129 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1130 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1131 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1132 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1133 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1134 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1135 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1136 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1137 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1138 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1139 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1140 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1141 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1142 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1143 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1144 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1145 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1146 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1147 } 1148 } 1149 1150 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1151 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1152 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1153 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1154 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1155 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1156 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1157 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1158 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1159 } 1160 1161 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1162 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1163 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1164 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1165 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1166 } 1167 1168 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1169 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1170 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1171 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1172 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1173 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1174 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1175 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1176 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1177 } 1178 1179 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1180 if (chip->chip_id == RTL8852C) { 1181 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1182 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1183 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1184 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1185 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1186 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1187 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1188 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1189 } else { 1190 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1191 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1192 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1193 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1194 } 1195 } 1196 1197 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1198 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1199 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1200 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1201 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1202 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1203 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1204 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1205 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1206 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1207 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1208 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1209 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1210 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1211 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1212 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1213 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1214 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1215 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1216 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1217 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1218 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1219 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1220 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1221 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1222 if (chip->chip_id == RTL8852C) { 1223 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1224 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1225 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1226 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1227 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1228 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1229 } else { 1230 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1231 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1232 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1233 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1234 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1235 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1236 } 1237 } 1238 1239 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1240 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1241 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1242 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1243 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1244 } 1245 1246 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1247 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1248 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1249 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1250 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1251 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1252 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1253 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1254 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1255 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1256 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1257 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1258 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1259 } 1260 1261 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1262 if (chip->chip_id == RTL8852C) { 1263 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1264 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1265 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1266 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1267 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1268 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1269 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1270 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1271 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1272 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1273 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1274 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1275 } else { 1276 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1277 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1278 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1279 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1280 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1281 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1282 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1283 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1284 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1285 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1286 } 1287 } 1288 1289 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1290 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1291 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1292 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1293 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1294 } 1295 1296 return 0; 1297} 1298 1299static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1300 struct seq_file *m, 1301 enum rtw89_mac_idx band) 1302{ 1303 const struct rtw89_chip_info *chip = rtwdev->chip; 1304 u32 offset = 0; 1305 u32 cmac_err; 1306 int ret; 1307 1308 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1309 if (ret) { 1310 if (band) 1311 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1312 else 1313 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1314 return ret; 1315 } 1316 1317 if (band) 1318 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1319 1320 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1321 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1322 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1323 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1324 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1325 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1326 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1327 1328 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1329 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1330 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1331 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1332 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1333 } 1334 1335 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1336 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1337 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1338 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1339 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1340 } 1341 1342 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1343 if (chip->chip_id == RTL8852C) { 1344 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1345 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1346 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1347 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1348 } else { 1349 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1350 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1351 } 1352 } 1353 1354 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1355 if (chip->chip_id == RTL8852C) { 1356 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1357 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1358 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1359 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1360 } else { 1361 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1362 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1363 } 1364 } 1365 1366 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1367 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1368 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1369 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1370 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1371 } 1372 1373 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1374 if (chip->chip_id == RTL8852C) { 1375 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1376 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1377 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1378 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1379 } else { 1380 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1381 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1382 } 1383 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1384 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1385 } 1386 1387 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1388 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1389 1390 return 0; 1391} 1392 1393static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1394 struct seq_file *m) 1395{ 1396 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1397 if (rtwdev->dbcc_en) 1398 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1399 1400 return 0; 1401} 1402 1403static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1404 .sel_addr = R_AX_PTCL_DBG, 1405 .sel_byte = 1, 1406 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1407 .srt = 0x00, 1408 .end = 0x3F, 1409 .rd_addr = R_AX_PTCL_DBG_INFO, 1410 .rd_byte = 4, 1411 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1412}; 1413 1414static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1415 .sel_addr = R_AX_PTCL_DBG_C1, 1416 .sel_byte = 1, 1417 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1418 .srt = 0x00, 1419 .end = 0x3F, 1420 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1421 .rd_byte = 4, 1422 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1423}; 1424 1425static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1426 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1427 .sel_byte = 2, 1428 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1429 .srt = 0x0, 1430 .end = 0xD, 1431 .rd_addr = R_AX_DBG_PORT_SEL, 1432 .rd_byte = 4, 1433 .rd_msk = B_AX_DEBUG_ST_MASK 1434}; 1435 1436static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1437 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1438 .sel_byte = 2, 1439 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1440 .srt = 0x0, 1441 .end = 0x5, 1442 .rd_addr = R_AX_DBG_PORT_SEL, 1443 .rd_byte = 4, 1444 .rd_msk = B_AX_DEBUG_ST_MASK 1445}; 1446 1447static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1448 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1449 .sel_byte = 2, 1450 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1451 .srt = 0x0, 1452 .end = 0x9, 1453 .rd_addr = R_AX_DBG_PORT_SEL, 1454 .rd_byte = 4, 1455 .rd_msk = B_AX_DEBUG_ST_MASK 1456}; 1457 1458static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1459 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1460 .sel_byte = 2, 1461 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1462 .srt = 0x0, 1463 .end = 0x3, 1464 .rd_addr = R_AX_DBG_PORT_SEL, 1465 .rd_byte = 4, 1466 .rd_msk = B_AX_DEBUG_ST_MASK 1467}; 1468 1469static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1470 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1471 .sel_byte = 2, 1472 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1473 .srt = 0x0, 1474 .end = 0x1, 1475 .rd_addr = R_AX_DBG_PORT_SEL, 1476 .rd_byte = 4, 1477 .rd_msk = B_AX_DEBUG_ST_MASK 1478}; 1479 1480static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1481 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1482 .sel_byte = 2, 1483 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1484 .srt = 0x0, 1485 .end = 0x0, 1486 .rd_addr = R_AX_DBG_PORT_SEL, 1487 .rd_byte = 4, 1488 .rd_msk = B_AX_DEBUG_ST_MASK 1489}; 1490 1491static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1492 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1493 .sel_byte = 2, 1494 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1495 .srt = 0x0, 1496 .end = 0xB, 1497 .rd_addr = R_AX_DBG_PORT_SEL, 1498 .rd_byte = 4, 1499 .rd_msk = B_AX_DEBUG_ST_MASK 1500}; 1501 1502static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1503 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1504 .sel_byte = 2, 1505 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1506 .srt = 0x0, 1507 .end = 0x4, 1508 .rd_addr = R_AX_DBG_PORT_SEL, 1509 .rd_byte = 4, 1510 .rd_msk = B_AX_DEBUG_ST_MASK 1511}; 1512 1513static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1514 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1515 .sel_byte = 2, 1516 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1517 .srt = 0x0, 1518 .end = 0x8, 1519 .rd_addr = R_AX_DBG_PORT_SEL, 1520 .rd_byte = 4, 1521 .rd_msk = B_AX_DEBUG_ST_MASK 1522}; 1523 1524static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1525 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1526 .sel_byte = 2, 1527 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1528 .srt = 0x0, 1529 .end = 0x7, 1530 .rd_addr = R_AX_DBG_PORT_SEL, 1531 .rd_byte = 4, 1532 .rd_msk = B_AX_DEBUG_ST_MASK 1533}; 1534 1535static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1536 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1537 .sel_byte = 2, 1538 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1539 .srt = 0x0, 1540 .end = 0x1, 1541 .rd_addr = R_AX_DBG_PORT_SEL, 1542 .rd_byte = 4, 1543 .rd_msk = B_AX_DEBUG_ST_MASK 1544}; 1545 1546static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1547 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1548 .sel_byte = 2, 1549 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1550 .srt = 0x0, 1551 .end = 0x3, 1552 .rd_addr = R_AX_DBG_PORT_SEL, 1553 .rd_byte = 4, 1554 .rd_msk = B_AX_DEBUG_ST_MASK 1555}; 1556 1557static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1558 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1559 .sel_byte = 2, 1560 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1561 .srt = 0x0, 1562 .end = 0x0, 1563 .rd_addr = R_AX_DBG_PORT_SEL, 1564 .rd_byte = 4, 1565 .rd_msk = B_AX_DEBUG_ST_MASK 1566}; 1567 1568static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1569 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1570 .sel_byte = 2, 1571 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1572 .srt = 0x0, 1573 .end = 0x8, 1574 .rd_addr = R_AX_DBG_PORT_SEL, 1575 .rd_byte = 4, 1576 .rd_msk = B_AX_DEBUG_ST_MASK 1577}; 1578 1579static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1580 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1581 .sel_byte = 2, 1582 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1583 .srt = 0x0, 1584 .end = 0x0, 1585 .rd_addr = R_AX_DBG_PORT_SEL, 1586 .rd_byte = 4, 1587 .rd_msk = B_AX_DEBUG_ST_MASK 1588}; 1589 1590static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1591 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1592 .sel_byte = 2, 1593 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1594 .srt = 0x0, 1595 .end = 0x6, 1596 .rd_addr = R_AX_DBG_PORT_SEL, 1597 .rd_byte = 4, 1598 .rd_msk = B_AX_DEBUG_ST_MASK 1599}; 1600 1601static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1602 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1603 .sel_byte = 2, 1604 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1605 .srt = 0x0, 1606 .end = 0x0, 1607 .rd_addr = R_AX_DBG_PORT_SEL, 1608 .rd_byte = 4, 1609 .rd_msk = B_AX_DEBUG_ST_MASK 1610}; 1611 1612static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1613 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1614 .sel_byte = 2, 1615 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1616 .srt = 0x0, 1617 .end = 0x0, 1618 .rd_addr = R_AX_DBG_PORT_SEL, 1619 .rd_byte = 4, 1620 .rd_msk = B_AX_DEBUG_ST_MASK 1621}; 1622 1623static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1624 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1625 .sel_byte = 1, 1626 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1627 .srt = 0x0, 1628 .end = 0x3, 1629 .rd_addr = R_AX_DBG_PORT_SEL, 1630 .rd_byte = 4, 1631 .rd_msk = B_AX_DEBUG_ST_MASK 1632}; 1633 1634static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1635 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1636 .sel_byte = 1, 1637 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1638 .srt = 0x0, 1639 .end = 0x6, 1640 .rd_addr = R_AX_DBG_PORT_SEL, 1641 .rd_byte = 4, 1642 .rd_msk = B_AX_DEBUG_ST_MASK 1643}; 1644 1645static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1646 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1647 .sel_byte = 1, 1648 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1649 .srt = 0x0, 1650 .end = 0x0, 1651 .rd_addr = R_AX_DBG_PORT_SEL, 1652 .rd_byte = 4, 1653 .rd_msk = B_AX_DEBUG_ST_MASK 1654}; 1655 1656static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1657 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1658 .sel_byte = 1, 1659 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1660 .srt = 0x8, 1661 .end = 0xE, 1662 .rd_addr = R_AX_DBG_PORT_SEL, 1663 .rd_byte = 4, 1664 .rd_msk = B_AX_DEBUG_ST_MASK 1665}; 1666 1667static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1668 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1669 .sel_byte = 1, 1670 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1671 .srt = 0x0, 1672 .end = 0x5, 1673 .rd_addr = R_AX_DBG_PORT_SEL, 1674 .rd_byte = 4, 1675 .rd_msk = B_AX_DEBUG_ST_MASK 1676}; 1677 1678static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1679 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1680 .sel_byte = 1, 1681 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1682 .srt = 0x0, 1683 .end = 0x6, 1684 .rd_addr = R_AX_DBG_PORT_SEL, 1685 .rd_byte = 4, 1686 .rd_msk = B_AX_DEBUG_ST_MASK 1687}; 1688 1689static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1690 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1691 .sel_byte = 1, 1692 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1693 .srt = 0x0, 1694 .end = 0xF, 1695 .rd_addr = R_AX_DBG_PORT_SEL, 1696 .rd_byte = 4, 1697 .rd_msk = B_AX_DEBUG_ST_MASK 1698}; 1699 1700static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1701 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1702 .sel_byte = 1, 1703 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1704 .srt = 0x0, 1705 .end = 0x9, 1706 .rd_addr = R_AX_DBG_PORT_SEL, 1707 .rd_byte = 4, 1708 .rd_msk = B_AX_DEBUG_ST_MASK 1709}; 1710 1711static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1712 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1713 .sel_byte = 1, 1714 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1715 .srt = 0x0, 1716 .end = 0x3, 1717 .rd_addr = R_AX_DBG_PORT_SEL, 1718 .rd_byte = 4, 1719 .rd_msk = B_AX_DEBUG_ST_MASK 1720}; 1721 1722static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1723 .sel_addr = R_AX_SCH_DBG_SEL, 1724 .sel_byte = 1, 1725 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1726 .srt = 0x00, 1727 .end = 0x2F, 1728 .rd_addr = R_AX_SCH_DBG, 1729 .rd_byte = 4, 1730 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1731}; 1732 1733static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1734 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1735 .sel_byte = 1, 1736 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1737 .srt = 0x00, 1738 .end = 0x2F, 1739 .rd_addr = R_AX_SCH_DBG_C1, 1740 .rd_byte = 4, 1741 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1742}; 1743 1744static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1745 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1746 .sel_byte = 1, 1747 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1748 .srt = 0x00, 1749 .end = 0x19, 1750 .rd_addr = R_AX_DBG_PORT_SEL, 1751 .rd_byte = 4, 1752 .rd_msk = B_AX_DEBUG_ST_MASK 1753}; 1754 1755static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1756 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1757 .sel_byte = 1, 1758 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1759 .srt = 0x00, 1760 .end = 0x19, 1761 .rd_addr = R_AX_DBG_PORT_SEL, 1762 .rd_byte = 4, 1763 .rd_msk = B_AX_DEBUG_ST_MASK 1764}; 1765 1766static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1767 .sel_addr = R_AX_RX_DEBUG_SELECT, 1768 .sel_byte = 1, 1769 .sel_msk = B_AX_DEBUG_SEL_MASK, 1770 .srt = 0x00, 1771 .end = 0x58, 1772 .rd_addr = R_AX_DBG_PORT_SEL, 1773 .rd_byte = 4, 1774 .rd_msk = B_AX_DEBUG_ST_MASK 1775}; 1776 1777static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1778 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1779 .sel_byte = 1, 1780 .sel_msk = B_AX_DEBUG_SEL_MASK, 1781 .srt = 0x00, 1782 .end = 0x58, 1783 .rd_addr = R_AX_DBG_PORT_SEL, 1784 .rd_byte = 4, 1785 .rd_msk = B_AX_DEBUG_ST_MASK 1786}; 1787 1788static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1789 .sel_addr = R_AX_RX_STATE_MONITOR, 1790 .sel_byte = 1, 1791 .sel_msk = B_AX_STATE_SEL_MASK, 1792 .srt = 0x00, 1793 .end = 0x17, 1794 .rd_addr = R_AX_RX_STATE_MONITOR, 1795 .rd_byte = 4, 1796 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1797}; 1798 1799static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1800 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1801 .sel_byte = 1, 1802 .sel_msk = B_AX_STATE_SEL_MASK, 1803 .srt = 0x00, 1804 .end = 0x17, 1805 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1806 .rd_byte = 4, 1807 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1808}; 1809 1810static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1811 .sel_addr = R_AX_RMAC_PLCP_MON, 1812 .sel_byte = 4, 1813 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1814 .srt = 0x0, 1815 .end = 0xF, 1816 .rd_addr = R_AX_RMAC_PLCP_MON, 1817 .rd_byte = 4, 1818 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1819}; 1820 1821static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1822 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1823 .sel_byte = 4, 1824 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1825 .srt = 0x0, 1826 .end = 0xF, 1827 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1828 .rd_byte = 4, 1829 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1830}; 1831 1832static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1833 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1834 .sel_byte = 1, 1835 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1836 .srt = 0x08, 1837 .end = 0x10, 1838 .rd_addr = R_AX_DBG_PORT_SEL, 1839 .rd_byte = 4, 1840 .rd_msk = B_AX_DEBUG_ST_MASK 1841}; 1842 1843static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1844 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1845 .sel_byte = 1, 1846 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1847 .srt = 0x08, 1848 .end = 0x10, 1849 .rd_addr = R_AX_DBG_PORT_SEL, 1850 .rd_byte = 4, 1851 .rd_msk = B_AX_DEBUG_ST_MASK 1852}; 1853 1854static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1855 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1856 .sel_byte = 1, 1857 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1858 .srt = 0x00, 1859 .end = 0x07, 1860 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1861 .rd_byte = 4, 1862 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1863}; 1864 1865static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1866 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1867 .sel_byte = 1, 1868 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1869 .srt = 0x00, 1870 .end = 0x07, 1871 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1872 .rd_byte = 4, 1873 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1874}; 1875 1876static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1877 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1878 .sel_byte = 1, 1879 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1880 .srt = 0x00, 1881 .end = 0x07, 1882 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1883 .rd_byte = 4, 1884 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1885}; 1886 1887static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1888 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1889 .sel_byte = 1, 1890 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1891 .srt = 0x00, 1892 .end = 0x07, 1893 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1894 .rd_byte = 4, 1895 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1896}; 1897 1898static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1899 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1900 .sel_byte = 1, 1901 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1902 .srt = 0x00, 1903 .end = 0x04, 1904 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1905 .rd_byte = 4, 1906 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1907}; 1908 1909static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1910 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1911 .sel_byte = 1, 1912 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1913 .srt = 0x00, 1914 .end = 0x04, 1915 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1916 .rd_byte = 4, 1917 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1918}; 1919 1920static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1921 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1922 .sel_byte = 1, 1923 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1924 .srt = 0x00, 1925 .end = 0x04, 1926 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1927 .rd_byte = 4, 1928 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1929}; 1930 1931static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1932 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1933 .sel_byte = 1, 1934 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1935 .srt = 0x00, 1936 .end = 0x04, 1937 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1938 .rd_byte = 4, 1939 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1940}; 1941 1942static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1943 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1944 .sel_byte = 4, 1945 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1946 .srt = 0x80000000, 1947 .end = 0x80000001, 1948 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1949 .rd_byte = 4, 1950 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1951}; 1952 1953static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1954 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1955 .sel_byte = 4, 1956 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1957 .srt = 0x80010000, 1958 .end = 0x80010004, 1959 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1960 .rd_byte = 4, 1961 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1962}; 1963 1964static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1965 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1966 .sel_byte = 4, 1967 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1968 .srt = 0x80020000, 1969 .end = 0x80020FFF, 1970 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1971 .rd_byte = 4, 1972 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1973}; 1974 1975static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1976 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1977 .sel_byte = 4, 1978 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1979 .srt = 0x80030000, 1980 .end = 0x80030FFF, 1981 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1982 .rd_byte = 4, 1983 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1984}; 1985 1986static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1987 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1988 .sel_byte = 4, 1989 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1990 .srt = 0x80040000, 1991 .end = 0x80040FFF, 1992 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1993 .rd_byte = 4, 1994 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1995}; 1996 1997static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1998 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1999 .sel_byte = 4, 2000 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2001 .srt = 0x80050000, 2002 .end = 0x80050FFF, 2003 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2004 .rd_byte = 4, 2005 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2006}; 2007 2008static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2009 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2010 .sel_byte = 4, 2011 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2012 .srt = 0x80060000, 2013 .end = 0x80060453, 2014 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2015 .rd_byte = 4, 2016 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2017}; 2018 2019static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2020 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2021 .sel_byte = 4, 2022 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2023 .srt = 0x80070000, 2024 .end = 0x80070011, 2025 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2026 .rd_byte = 4, 2027 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2028}; 2029 2030static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2031 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2032 .sel_byte = 4, 2033 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2034 .srt = 0x80000000, 2035 .end = 0x80000001, 2036 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2037 .rd_byte = 4, 2038 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2039}; 2040 2041static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2042 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2043 .sel_byte = 4, 2044 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2045 .srt = 0x80010000, 2046 .end = 0x8001000A, 2047 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2048 .rd_byte = 4, 2049 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2050}; 2051 2052static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2053 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2054 .sel_byte = 4, 2055 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2056 .srt = 0x80020000, 2057 .end = 0x80020DBF, 2058 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2059 .rd_byte = 4, 2060 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2061}; 2062 2063static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2064 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2065 .sel_byte = 4, 2066 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2067 .srt = 0x80030000, 2068 .end = 0x80030DBF, 2069 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2070 .rd_byte = 4, 2071 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2072}; 2073 2074static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2075 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2076 .sel_byte = 4, 2077 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2078 .srt = 0x80040000, 2079 .end = 0x80040DBF, 2080 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2081 .rd_byte = 4, 2082 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2083}; 2084 2085static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2086 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2087 .sel_byte = 4, 2088 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2089 .srt = 0x80050000, 2090 .end = 0x80050DBF, 2091 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2092 .rd_byte = 4, 2093 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2094}; 2095 2096static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2097 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2098 .sel_byte = 4, 2099 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2100 .srt = 0x80060000, 2101 .end = 0x80060041, 2102 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2103 .rd_byte = 4, 2104 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2105}; 2106 2107static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2108 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2109 .sel_byte = 4, 2110 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2111 .srt = 0x80070000, 2112 .end = 0x80070001, 2113 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2114 .rd_byte = 4, 2115 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2116}; 2117 2118static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2119 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2120 .sel_byte = 4, 2121 .sel_msk = B_AX_DFI_DATA_MASK, 2122 .srt = 0x80000000, 2123 .end = 0x8000017f, 2124 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2125 .rd_byte = 4, 2126 .rd_msk = B_AX_DFI_DATA_MASK 2127}; 2128 2129static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2130 .sel_addr = R_AX_PCIE_DBG_CTRL, 2131 .sel_byte = 2, 2132 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2133 .srt = 0x00, 2134 .end = 0x03, 2135 .rd_addr = R_AX_DBG_PORT_SEL, 2136 .rd_byte = 4, 2137 .rd_msk = B_AX_DEBUG_ST_MASK 2138}; 2139 2140static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2141 .sel_addr = R_AX_PCIE_DBG_CTRL, 2142 .sel_byte = 2, 2143 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2144 .srt = 0x00, 2145 .end = 0x04, 2146 .rd_addr = R_AX_DBG_PORT_SEL, 2147 .rd_byte = 4, 2148 .rd_msk = B_AX_DEBUG_ST_MASK 2149}; 2150 2151static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2152 .sel_addr = R_AX_PCIE_DBG_CTRL, 2153 .sel_byte = 2, 2154 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2155 .srt = 0x00, 2156 .end = 0x01, 2157 .rd_addr = R_AX_DBG_PORT_SEL, 2158 .rd_byte = 4, 2159 .rd_msk = B_AX_DEBUG_ST_MASK 2160}; 2161 2162static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2163 .sel_addr = R_AX_PCIE_DBG_CTRL, 2164 .sel_byte = 2, 2165 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2166 .srt = 0x00, 2167 .end = 0x05, 2168 .rd_addr = R_AX_DBG_PORT_SEL, 2169 .rd_byte = 4, 2170 .rd_msk = B_AX_DEBUG_ST_MASK 2171}; 2172 2173static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2174 .sel_addr = R_AX_PCIE_DBG_CTRL, 2175 .sel_byte = 2, 2176 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2177 .srt = 0x00, 2178 .end = 0x05, 2179 .rd_addr = R_AX_DBG_PORT_SEL, 2180 .rd_byte = 4, 2181 .rd_msk = B_AX_DEBUG_ST_MASK 2182}; 2183 2184static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2185 .sel_addr = R_AX_PCIE_DBG_CTRL, 2186 .sel_byte = 2, 2187 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2188 .srt = 0x00, 2189 .end = 0x06, 2190 .rd_addr = R_AX_DBG_PORT_SEL, 2191 .rd_byte = 4, 2192 .rd_msk = B_AX_DEBUG_ST_MASK 2193}; 2194 2195static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2196 .sel_addr = R_AX_DBG_CTRL, 2197 .sel_byte = 1, 2198 .sel_msk = B_AX_DBG_SEL0, 2199 .srt = 0x34, 2200 .end = 0x3C, 2201 .rd_addr = R_AX_DBG_PORT_SEL, 2202 .rd_byte = 4, 2203 .rd_msk = B_AX_DEBUG_ST_MASK 2204}; 2205 2206static const struct rtw89_mac_dbg_port_info * 2207rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2208 struct rtw89_dev *rtwdev, u32 sel) 2209{ 2210 const struct rtw89_mac_dbg_port_info *info; 2211 u32 index; 2212 u32 val32; 2213 u16 val16; 2214 u8 val8; 2215 2216 switch (sel) { 2217 case RTW89_DBG_PORT_SEL_PTCL_C0: 2218 info = &dbg_port_ptcl_c0; 2219 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2220 val16 |= B_AX_PTCL_DBG_EN; 2221 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2222 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2223 break; 2224 case RTW89_DBG_PORT_SEL_PTCL_C1: 2225 info = &dbg_port_ptcl_c1; 2226 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2227 val16 |= B_AX_PTCL_DBG_EN; 2228 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2229 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2230 break; 2231 case RTW89_DBG_PORT_SEL_SCH_C0: 2232 info = &dbg_port_sch_c0; 2233 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2234 val32 |= B_AX_SCH_DBG_EN; 2235 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2236 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2237 break; 2238 case RTW89_DBG_PORT_SEL_SCH_C1: 2239 info = &dbg_port_sch_c1; 2240 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2241 val32 |= B_AX_SCH_DBG_EN; 2242 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2243 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2244 break; 2245 case RTW89_DBG_PORT_SEL_TMAC_C0: 2246 info = &dbg_port_tmac_c0; 2247 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2248 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2249 B_AX_DBGSEL_TRXPTCL_MASK); 2250 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2251 2252 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2253 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2254 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2255 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2256 2257 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2258 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2259 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2260 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2261 break; 2262 case RTW89_DBG_PORT_SEL_TMAC_C1: 2263 info = &dbg_port_tmac_c1; 2264 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2265 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2266 B_AX_DBGSEL_TRXPTCL_MASK); 2267 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2268 2269 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2270 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2271 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2272 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2273 2274 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2275 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2276 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2277 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2278 break; 2279 case RTW89_DBG_PORT_SEL_RMAC_C0: 2280 info = &dbg_port_rmac_c0; 2281 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2282 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2283 B_AX_DBGSEL_TRXPTCL_MASK); 2284 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2285 2286 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2287 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2288 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2289 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2290 2291 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2292 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2293 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2294 2295 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2296 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2297 B_AX_DBGSEL_TRXPTCL_MASK); 2298 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2299 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2300 break; 2301 case RTW89_DBG_PORT_SEL_RMAC_C1: 2302 info = &dbg_port_rmac_c1; 2303 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2304 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2305 B_AX_DBGSEL_TRXPTCL_MASK); 2306 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2307 2308 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2309 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2310 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2311 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2312 2313 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2314 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2315 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2316 2317 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2318 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2319 B_AX_DBGSEL_TRXPTCL_MASK); 2320 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2321 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2322 break; 2323 case RTW89_DBG_PORT_SEL_RMACST_C0: 2324 info = &dbg_port_rmacst_c0; 2325 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2326 break; 2327 case RTW89_DBG_PORT_SEL_RMACST_C1: 2328 info = &dbg_port_rmacst_c1; 2329 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2330 break; 2331 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2332 info = &dbg_port_rmac_plcp_c0; 2333 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2334 break; 2335 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2336 info = &dbg_port_rmac_plcp_c1; 2337 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2338 break; 2339 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2340 info = &dbg_port_trxptcl_c0; 2341 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2342 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2343 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2344 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2345 2346 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2347 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2348 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2349 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2350 break; 2351 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2352 info = &dbg_port_trxptcl_c1; 2353 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2354 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2355 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2356 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2357 2358 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2359 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2360 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2361 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2362 break; 2363 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2364 info = &dbg_port_tx_infol_c0; 2365 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2366 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2367 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2368 seq_puts(m, "Enable tx infol dump.\n"); 2369 break; 2370 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2371 info = &dbg_port_tx_infoh_c0; 2372 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2373 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2374 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2375 seq_puts(m, "Enable tx infoh dump.\n"); 2376 break; 2377 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2378 info = &dbg_port_tx_infol_c1; 2379 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2380 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2381 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2382 seq_puts(m, "Enable tx infol dump.\n"); 2383 break; 2384 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2385 info = &dbg_port_tx_infoh_c1; 2386 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2387 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2388 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2389 seq_puts(m, "Enable tx infoh dump.\n"); 2390 break; 2391 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2392 info = &dbg_port_txtf_infol_c0; 2393 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2394 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2395 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2396 seq_puts(m, "Enable tx tf infol dump.\n"); 2397 break; 2398 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2399 info = &dbg_port_txtf_infoh_c0; 2400 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2401 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2402 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2403 seq_puts(m, "Enable tx tf infoh dump.\n"); 2404 break; 2405 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2406 info = &dbg_port_txtf_infol_c1; 2407 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2408 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2409 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2410 seq_puts(m, "Enable tx tf infol dump.\n"); 2411 break; 2412 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2413 info = &dbg_port_txtf_infoh_c1; 2414 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2415 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2416 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2417 seq_puts(m, "Enable tx tf infoh dump.\n"); 2418 break; 2419 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2420 info = &dbg_port_wde_bufmgn_freepg; 2421 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2422 break; 2423 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2424 info = &dbg_port_wde_bufmgn_quota; 2425 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2426 break; 2427 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2428 info = &dbg_port_wde_bufmgn_pagellt; 2429 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2430 break; 2431 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2432 info = &dbg_port_wde_bufmgn_pktinfo; 2433 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2434 break; 2435 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2436 info = &dbg_port_wde_quemgn_prepkt; 2437 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2438 break; 2439 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2440 info = &dbg_port_wde_quemgn_nxtpkt; 2441 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2442 break; 2443 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2444 info = &dbg_port_wde_quemgn_qlnktbl; 2445 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2446 break; 2447 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2448 info = &dbg_port_wde_quemgn_qempty; 2449 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2450 break; 2451 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2452 info = &dbg_port_ple_bufmgn_freepg; 2453 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2454 break; 2455 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2456 info = &dbg_port_ple_bufmgn_quota; 2457 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2458 break; 2459 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2460 info = &dbg_port_ple_bufmgn_pagellt; 2461 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2462 break; 2463 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2464 info = &dbg_port_ple_bufmgn_pktinfo; 2465 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2466 break; 2467 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2468 info = &dbg_port_ple_quemgn_prepkt; 2469 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2470 break; 2471 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2472 info = &dbg_port_ple_quemgn_nxtpkt; 2473 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2474 break; 2475 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2476 info = &dbg_port_ple_quemgn_qlnktbl; 2477 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2478 break; 2479 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2480 info = &dbg_port_ple_quemgn_qempty; 2481 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2482 break; 2483 case RTW89_DBG_PORT_SEL_PKTINFO: 2484 info = &dbg_port_pktinfo; 2485 seq_puts(m, "Enable pktinfo dump.\n"); 2486 break; 2487 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2488 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2489 B_AX_DBG_SEL0, 0x80); 2490 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2491 B_AX_SEL_0XC0_MASK, 1); 2492 fallthrough; 2493 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2494 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2495 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2496 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2497 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2498 info = &dbg_port_dspt_hdt_tx0_5; 2499 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2500 rtw89_write16_mask(rtwdev, info->sel_addr, 2501 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2502 rtw89_write16_mask(rtwdev, info->sel_addr, 2503 B_AX_DISPATCHER_CH_SEL_MASK, index); 2504 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2505 break; 2506 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2507 info = &dbg_port_dspt_hdt_tx6; 2508 rtw89_write16_mask(rtwdev, info->sel_addr, 2509 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2510 rtw89_write16_mask(rtwdev, info->sel_addr, 2511 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2512 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2513 break; 2514 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2515 info = &dbg_port_dspt_hdt_tx7; 2516 rtw89_write16_mask(rtwdev, info->sel_addr, 2517 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2518 rtw89_write16_mask(rtwdev, info->sel_addr, 2519 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2520 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2521 break; 2522 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2523 info = &dbg_port_dspt_hdt_tx8; 2524 rtw89_write16_mask(rtwdev, info->sel_addr, 2525 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2526 rtw89_write16_mask(rtwdev, info->sel_addr, 2527 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2528 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2529 break; 2530 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2531 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2532 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2533 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2534 info = &dbg_port_dspt_hdt_tx9_C; 2535 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2536 rtw89_write16_mask(rtwdev, info->sel_addr, 2537 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2538 rtw89_write16_mask(rtwdev, info->sel_addr, 2539 B_AX_DISPATCHER_CH_SEL_MASK, index); 2540 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2541 break; 2542 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2543 info = &dbg_port_dspt_hdt_txD; 2544 rtw89_write16_mask(rtwdev, info->sel_addr, 2545 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2546 rtw89_write16_mask(rtwdev, info->sel_addr, 2547 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2548 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2549 break; 2550 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2551 info = &dbg_port_dspt_cdt_tx0; 2552 rtw89_write16_mask(rtwdev, info->sel_addr, 2553 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2554 rtw89_write16_mask(rtwdev, info->sel_addr, 2555 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2556 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2557 break; 2558 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2559 info = &dbg_port_dspt_cdt_tx1; 2560 rtw89_write16_mask(rtwdev, info->sel_addr, 2561 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2562 rtw89_write16_mask(rtwdev, info->sel_addr, 2563 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2564 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2565 break; 2566 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2567 info = &dbg_port_dspt_cdt_tx3; 2568 rtw89_write16_mask(rtwdev, info->sel_addr, 2569 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2570 rtw89_write16_mask(rtwdev, info->sel_addr, 2571 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2572 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2573 break; 2574 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2575 info = &dbg_port_dspt_cdt_tx4; 2576 rtw89_write16_mask(rtwdev, info->sel_addr, 2577 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2578 rtw89_write16_mask(rtwdev, info->sel_addr, 2579 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2580 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2581 break; 2582 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2583 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2584 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2585 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2586 info = &dbg_port_dspt_cdt_tx5_8; 2587 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2588 rtw89_write16_mask(rtwdev, info->sel_addr, 2589 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2590 rtw89_write16_mask(rtwdev, info->sel_addr, 2591 B_AX_DISPATCHER_CH_SEL_MASK, index); 2592 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2593 break; 2594 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2595 info = &dbg_port_dspt_cdt_tx9; 2596 rtw89_write16_mask(rtwdev, info->sel_addr, 2597 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2598 rtw89_write16_mask(rtwdev, info->sel_addr, 2599 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2600 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2601 break; 2602 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2603 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2604 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2605 info = &dbg_port_dspt_cdt_txA_C; 2606 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2607 rtw89_write16_mask(rtwdev, info->sel_addr, 2608 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2609 rtw89_write16_mask(rtwdev, info->sel_addr, 2610 B_AX_DISPATCHER_CH_SEL_MASK, index); 2611 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2612 break; 2613 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2614 info = &dbg_port_dspt_hdt_rx0; 2615 rtw89_write16_mask(rtwdev, info->sel_addr, 2616 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2617 rtw89_write16_mask(rtwdev, info->sel_addr, 2618 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2619 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2620 break; 2621 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2622 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2623 info = &dbg_port_dspt_hdt_rx1_2; 2624 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2625 rtw89_write16_mask(rtwdev, info->sel_addr, 2626 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2627 rtw89_write16_mask(rtwdev, info->sel_addr, 2628 B_AX_DISPATCHER_CH_SEL_MASK, index); 2629 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2630 break; 2631 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2632 info = &dbg_port_dspt_hdt_rx3; 2633 rtw89_write16_mask(rtwdev, info->sel_addr, 2634 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2635 rtw89_write16_mask(rtwdev, info->sel_addr, 2636 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2637 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2638 break; 2639 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2640 info = &dbg_port_dspt_hdt_rx4; 2641 rtw89_write16_mask(rtwdev, info->sel_addr, 2642 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2643 rtw89_write16_mask(rtwdev, info->sel_addr, 2644 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2645 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2646 break; 2647 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2648 info = &dbg_port_dspt_hdt_rx5; 2649 rtw89_write16_mask(rtwdev, info->sel_addr, 2650 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2651 rtw89_write16_mask(rtwdev, info->sel_addr, 2652 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2653 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2654 break; 2655 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2656 info = &dbg_port_dspt_cdt_rx_p0_0; 2657 rtw89_write16_mask(rtwdev, info->sel_addr, 2658 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2659 rtw89_write16_mask(rtwdev, info->sel_addr, 2660 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2661 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2662 break; 2663 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2664 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2665 info = &dbg_port_dspt_cdt_rx_p0_1; 2666 rtw89_write16_mask(rtwdev, info->sel_addr, 2667 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2668 rtw89_write16_mask(rtwdev, info->sel_addr, 2669 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2670 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2671 break; 2672 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2673 info = &dbg_port_dspt_cdt_rx_p0_2; 2674 rtw89_write16_mask(rtwdev, info->sel_addr, 2675 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2676 rtw89_write16_mask(rtwdev, info->sel_addr, 2677 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2678 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2679 break; 2680 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2681 info = &dbg_port_dspt_cdt_rx_p1; 2682 rtw89_write8_mask(rtwdev, info->sel_addr, 2683 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2684 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2685 break; 2686 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2687 info = &dbg_port_dspt_stf_ctrl; 2688 rtw89_write8_mask(rtwdev, info->sel_addr, 2689 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2690 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2691 break; 2692 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2693 info = &dbg_port_dspt_addr_ctrl; 2694 rtw89_write8_mask(rtwdev, info->sel_addr, 2695 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2696 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2697 break; 2698 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2699 info = &dbg_port_dspt_wde_intf; 2700 rtw89_write8_mask(rtwdev, info->sel_addr, 2701 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2702 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2703 break; 2704 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2705 info = &dbg_port_dspt_ple_intf; 2706 rtw89_write8_mask(rtwdev, info->sel_addr, 2707 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2708 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2709 break; 2710 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2711 info = &dbg_port_dspt_flow_ctrl; 2712 rtw89_write8_mask(rtwdev, info->sel_addr, 2713 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2714 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2715 break; 2716 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2717 info = &dbg_port_pcie_txdma; 2718 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2719 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2720 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2721 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2722 seq_puts(m, "Enable pcie txdma dump.\n"); 2723 break; 2724 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2725 info = &dbg_port_pcie_rxdma; 2726 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2727 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2728 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2729 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2730 seq_puts(m, "Enable pcie rxdma dump.\n"); 2731 break; 2732 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2733 info = &dbg_port_pcie_cvt; 2734 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2735 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2736 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2737 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2738 seq_puts(m, "Enable pcie cvt dump.\n"); 2739 break; 2740 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 2741 info = &dbg_port_pcie_cxpl; 2742 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2743 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 2744 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 2745 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2746 seq_puts(m, "Enable pcie cxpl dump.\n"); 2747 break; 2748 case RTW89_DBG_PORT_SEL_PCIE_IO: 2749 info = &dbg_port_pcie_io; 2750 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2751 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 2752 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 2753 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2754 seq_puts(m, "Enable pcie io dump.\n"); 2755 break; 2756 case RTW89_DBG_PORT_SEL_PCIE_MISC: 2757 info = &dbg_port_pcie_misc; 2758 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2759 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 2760 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 2761 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2762 seq_puts(m, "Enable pcie misc dump.\n"); 2763 break; 2764 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 2765 info = &dbg_port_pcie_misc2; 2766 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 2767 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 2768 B_AX_PCIE_DBG_SEL_MASK); 2769 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 2770 seq_puts(m, "Enable pcie misc2 dump.\n"); 2771 break; 2772 default: 2773 seq_puts(m, "Dbg port select err\n"); 2774 return NULL; 2775 } 2776 2777 return info; 2778} 2779 2780static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 2781{ 2782 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 2783 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 2784 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 2785 return false; 2786 if (rtwdev->chip->chip_id == RTL8852B && 2787 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2788 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2789 return false; 2790 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2791 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 2792 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 2793 return false; 2794 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 2795 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 2796 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 2797 return false; 2798 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 2799 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 2800 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 2801 return false; 2802 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 2803 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 2804 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 2805 return false; 2806 2807 return true; 2808} 2809 2810static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 2811 struct seq_file *m, u32 sel) 2812{ 2813 const struct rtw89_mac_dbg_port_info *info; 2814 u8 val8; 2815 u16 val16; 2816 u32 val32; 2817 u32 i; 2818 2819 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 2820 if (!info) { 2821 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 2822 return -EINVAL; 2823 } 2824 2825#define case_DBG_SEL(__sel) \ 2826 case RTW89_DBG_PORT_SEL_##__sel: \ 2827 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 2828 break 2829 2830 switch (sel) { 2831 case_DBG_SEL(PTCL_C0); 2832 case_DBG_SEL(PTCL_C1); 2833 case_DBG_SEL(SCH_C0); 2834 case_DBG_SEL(SCH_C1); 2835 case_DBG_SEL(TMAC_C0); 2836 case_DBG_SEL(TMAC_C1); 2837 case_DBG_SEL(RMAC_C0); 2838 case_DBG_SEL(RMAC_C1); 2839 case_DBG_SEL(RMACST_C0); 2840 case_DBG_SEL(RMACST_C1); 2841 case_DBG_SEL(TRXPTCL_C0); 2842 case_DBG_SEL(TRXPTCL_C1); 2843 case_DBG_SEL(TX_INFOL_C0); 2844 case_DBG_SEL(TX_INFOH_C0); 2845 case_DBG_SEL(TX_INFOL_C1); 2846 case_DBG_SEL(TX_INFOH_C1); 2847 case_DBG_SEL(TXTF_INFOL_C0); 2848 case_DBG_SEL(TXTF_INFOH_C0); 2849 case_DBG_SEL(TXTF_INFOL_C1); 2850 case_DBG_SEL(TXTF_INFOH_C1); 2851 case_DBG_SEL(WDE_BUFMGN_FREEPG); 2852 case_DBG_SEL(WDE_BUFMGN_QUOTA); 2853 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 2854 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 2855 case_DBG_SEL(WDE_QUEMGN_PREPKT); 2856 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 2857 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 2858 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 2859 case_DBG_SEL(PLE_BUFMGN_FREEPG); 2860 case_DBG_SEL(PLE_BUFMGN_QUOTA); 2861 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 2862 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 2863 case_DBG_SEL(PLE_QUEMGN_PREPKT); 2864 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 2865 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2866 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2867 case_DBG_SEL(PKTINFO); 2868 case_DBG_SEL(DSPT_HDT_TX0); 2869 case_DBG_SEL(DSPT_HDT_TX1); 2870 case_DBG_SEL(DSPT_HDT_TX2); 2871 case_DBG_SEL(DSPT_HDT_TX3); 2872 case_DBG_SEL(DSPT_HDT_TX4); 2873 case_DBG_SEL(DSPT_HDT_TX5); 2874 case_DBG_SEL(DSPT_HDT_TX6); 2875 case_DBG_SEL(DSPT_HDT_TX7); 2876 case_DBG_SEL(DSPT_HDT_TX8); 2877 case_DBG_SEL(DSPT_HDT_TX9); 2878 case_DBG_SEL(DSPT_HDT_TXA); 2879 case_DBG_SEL(DSPT_HDT_TXB); 2880 case_DBG_SEL(DSPT_HDT_TXC); 2881 case_DBG_SEL(DSPT_HDT_TXD); 2882 case_DBG_SEL(DSPT_HDT_TXE); 2883 case_DBG_SEL(DSPT_HDT_TXF); 2884 case_DBG_SEL(DSPT_CDT_TX0); 2885 case_DBG_SEL(DSPT_CDT_TX1); 2886 case_DBG_SEL(DSPT_CDT_TX3); 2887 case_DBG_SEL(DSPT_CDT_TX4); 2888 case_DBG_SEL(DSPT_CDT_TX5); 2889 case_DBG_SEL(DSPT_CDT_TX6); 2890 case_DBG_SEL(DSPT_CDT_TX7); 2891 case_DBG_SEL(DSPT_CDT_TX8); 2892 case_DBG_SEL(DSPT_CDT_TX9); 2893 case_DBG_SEL(DSPT_CDT_TXA); 2894 case_DBG_SEL(DSPT_CDT_TXB); 2895 case_DBG_SEL(DSPT_CDT_TXC); 2896 case_DBG_SEL(DSPT_HDT_RX0); 2897 case_DBG_SEL(DSPT_HDT_RX1); 2898 case_DBG_SEL(DSPT_HDT_RX2); 2899 case_DBG_SEL(DSPT_HDT_RX3); 2900 case_DBG_SEL(DSPT_HDT_RX4); 2901 case_DBG_SEL(DSPT_HDT_RX5); 2902 case_DBG_SEL(DSPT_CDT_RX_P0); 2903 case_DBG_SEL(DSPT_CDT_RX_P0_0); 2904 case_DBG_SEL(DSPT_CDT_RX_P0_1); 2905 case_DBG_SEL(DSPT_CDT_RX_P0_2); 2906 case_DBG_SEL(DSPT_CDT_RX_P1); 2907 case_DBG_SEL(DSPT_STF_CTRL); 2908 case_DBG_SEL(DSPT_ADDR_CTRL); 2909 case_DBG_SEL(DSPT_WDE_INTF); 2910 case_DBG_SEL(DSPT_PLE_INTF); 2911 case_DBG_SEL(DSPT_FLOW_CTRL); 2912 case_DBG_SEL(PCIE_TXDMA); 2913 case_DBG_SEL(PCIE_RXDMA); 2914 case_DBG_SEL(PCIE_CVT); 2915 case_DBG_SEL(PCIE_CXPL); 2916 case_DBG_SEL(PCIE_IO); 2917 case_DBG_SEL(PCIE_MISC); 2918 case_DBG_SEL(PCIE_MISC2); 2919 } 2920 2921#undef case_DBG_SEL 2922 2923 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2924 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2925 2926 for (i = info->srt; i <= info->end; i++) { 2927 switch (info->sel_byte) { 2928 case 1: 2929 default: 2930 rtw89_write8_mask(rtwdev, info->sel_addr, 2931 info->sel_msk, i); 2932 seq_printf(m, "0x%02X: ", i); 2933 break; 2934 case 2: 2935 rtw89_write16_mask(rtwdev, info->sel_addr, 2936 info->sel_msk, i); 2937 seq_printf(m, "0x%04X: ", i); 2938 break; 2939 case 4: 2940 rtw89_write32_mask(rtwdev, info->sel_addr, 2941 info->sel_msk, i); 2942 seq_printf(m, "0x%04X: ", i); 2943 break; 2944 } 2945 2946 udelay(10); 2947 2948 switch (info->rd_byte) { 2949 case 1: 2950 default: 2951 val8 = rtw89_read8_mask(rtwdev, 2952 info->rd_addr, info->rd_msk); 2953 seq_printf(m, "0x%02X\n", val8); 2954 break; 2955 case 2: 2956 val16 = rtw89_read16_mask(rtwdev, 2957 info->rd_addr, info->rd_msk); 2958 seq_printf(m, "0x%04X\n", val16); 2959 break; 2960 case 4: 2961 val32 = rtw89_read32_mask(rtwdev, 2962 info->rd_addr, info->rd_msk); 2963 seq_printf(m, "0x%08X\n", val32); 2964 break; 2965 } 2966 } 2967 2968 return 0; 2969} 2970 2971static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2972 struct seq_file *m) 2973{ 2974 u32 sel; 2975 int ret = 0; 2976 2977 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2978 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2979 if (!is_dbg_port_valid(rtwdev, sel)) 2980 continue; 2981 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2982 if (ret) { 2983 rtw89_err(rtwdev, 2984 "failed to dump debug port %d\n", sel); 2985 break; 2986 } 2987 } 2988 2989 return ret; 2990} 2991 2992static int 2993rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2994{ 2995 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2996 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2997 2998 if (debugfs_priv->dbgpkg_en.ss_dbg) 2999 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 3000 if (debugfs_priv->dbgpkg_en.dle_dbg) 3001 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 3002 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3003 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 3004 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3005 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 3006 if (debugfs_priv->dbgpkg_en.dbg_port) 3007 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 3008 3009 return 0; 3010}; 3011 3012static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 3013 const char __user *user_buf, size_t count) 3014{ 3015 char *buf; 3016 u8 *bin; 3017 int num; 3018 int err = 0; 3019 3020 buf = memdup_user(user_buf, count); 3021 if (IS_ERR(buf)) 3022 return buf; 3023 3024 num = count / 2; 3025 bin = kmalloc(num, GFP_KERNEL); 3026 if (!bin) { 3027 err = -EFAULT; 3028 goto out; 3029 } 3030 3031 if (hex2bin(bin, buf, num)) { 3032 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3033 kfree(bin); 3034 err = -EINVAL; 3035 } 3036 3037out: 3038 kfree(buf); 3039 3040 return err ? ERR_PTR(err) : bin; 3041} 3042 3043static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 3044 const char __user *user_buf, 3045 size_t count, loff_t *loff) 3046{ 3047 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3048 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3049 u8 *h2c; 3050 int ret; 3051 u16 h2c_len = count / 2; 3052 3053 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3054 if (IS_ERR(h2c)) 3055 return -EFAULT; 3056 3057 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3058 3059 kfree(h2c); 3060 3061 return ret ? ret : count; 3062} 3063 3064static int 3065rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3066{ 3067 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3068 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3069 struct rtw89_early_h2c *early_h2c; 3070 int seq = 0; 3071 3072 mutex_lock(&rtwdev->mutex); 3073 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3074 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3075 mutex_unlock(&rtwdev->mutex); 3076 3077 return 0; 3078} 3079 3080static ssize_t 3081rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3082 size_t count, loff_t *loff) 3083{ 3084 struct seq_file *m = (struct seq_file *)filp->private_data; 3085 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3086 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3087 struct rtw89_early_h2c *early_h2c; 3088 u8 *h2c; 3089 u16 h2c_len = count / 2; 3090 3091 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3092 if (IS_ERR(h2c)) 3093 return -EFAULT; 3094 3095 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3096 kfree(h2c); 3097 rtw89_fw_free_all_early_h2c(rtwdev); 3098 goto out; 3099 } 3100 3101 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3102 if (!early_h2c) { 3103 kfree(h2c); 3104 return -EFAULT; 3105 } 3106 3107 early_h2c->h2c = h2c; 3108 early_h2c->h2c_len = h2c_len; 3109 3110 mutex_lock(&rtwdev->mutex); 3111 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3112 mutex_unlock(&rtwdev->mutex); 3113 3114out: 3115 return count; 3116} 3117 3118static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3119{ 3120 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3121 u16 pkt_id; 3122 int ret; 3123 3124 rtw89_leave_ps_mode(rtwdev); 3125 3126 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3127 if (ret) 3128 return ret; 3129 3130 /* intentionally, enqueue two pkt, but has only one pkt id */ 3131 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3132 ctrl_para.start_pktid = pkt_id; 3133 ctrl_para.end_pktid = pkt_id; 3134 ctrl_para.pkt_num = 1; /* start from 0 */ 3135 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3136 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3137 3138 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true)) 3139 return -EFAULT; 3140 3141 return 0; 3142} 3143 3144static int 3145rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3146{ 3147 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3148 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3149 3150 seq_printf(m, "%d\n", 3151 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3152 return 0; 3153} 3154 3155enum rtw89_dbg_crash_simulation_type { 3156 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3157 RTW89_DBG_SIM_CTRL_ERROR = 2, 3158}; 3159 3160static ssize_t 3161rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3162 size_t count, loff_t *loff) 3163{ 3164 struct seq_file *m = (struct seq_file *)filp->private_data; 3165 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3166 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3167 int (*sim)(struct rtw89_dev *rtwdev); 3168 u8 crash_type; 3169 int ret; 3170 3171 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3172 if (ret) 3173 return -EINVAL; 3174 3175 switch (crash_type) { 3176 case RTW89_DBG_SIM_CPU_EXCEPTION: 3177 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3178 return -EOPNOTSUPP; 3179 sim = rtw89_fw_h2c_trigger_cpu_exception; 3180 break; 3181 case RTW89_DBG_SIM_CTRL_ERROR: 3182 sim = rtw89_dbg_trigger_ctrl_error; 3183 break; 3184 default: 3185 return -EINVAL; 3186 } 3187 3188 mutex_lock(&rtwdev->mutex); 3189 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3190 ret = sim(rtwdev); 3191 mutex_unlock(&rtwdev->mutex); 3192 3193 if (ret) 3194 return ret; 3195 3196 return count; 3197} 3198 3199static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3200{ 3201 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3202 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3203 3204 rtw89_btc_dump_info(rtwdev, m); 3205 3206 return 0; 3207} 3208 3209static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3210 const char __user *user_buf, 3211 size_t count, loff_t *loff) 3212{ 3213 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3214 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3215 struct rtw89_btc *btc = &rtwdev->btc; 3216 bool btc_manual; 3217 int ret; 3218 3219 ret = kstrtobool_from_user(user_buf, count, &btc_manual); 3220 if (ret) 3221 return ret; 3222 3223 btc->ctrl.manual = btc_manual; 3224 3225 return count; 3226} 3227 3228static ssize_t rtw89_debug_fw_log_manual_set(struct file *filp, 3229 const char __user *user_buf, 3230 size_t count, loff_t *loff) 3231{ 3232 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3233 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3234 struct rtw89_fw_log *log = &rtwdev->fw.log; 3235 bool fw_log_manual; 3236 3237 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3238 goto out; 3239 3240 mutex_lock(&rtwdev->mutex); 3241 log->enable = fw_log_manual; 3242 if (log->enable) 3243 rtw89_fw_log_prepare(rtwdev); 3244 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3245 mutex_unlock(&rtwdev->mutex); 3246out: 3247 return count; 3248} 3249 3250static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3251{ 3252 static const char * const he_gi_str[] = { 3253 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3254 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3255 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3256 }; 3257 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3258 struct rate_info *rate = &rtwsta->ra_report.txrate; 3259 struct ieee80211_rx_status *status = &rtwsta->rx_status; 3260 struct seq_file *m = (struct seq_file *)data; 3261 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3262 struct rtw89_hal *hal = &rtwdev->hal; 3263 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3264 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3265 u8 evm_min, evm_max; 3266 u8 rssi; 3267 u8 snr; 3268 int i; 3269 3270 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 3271 3272 if (rate->flags & RATE_INFO_FLAGS_MCS) 3273 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3274 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3275 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3276 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3277 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3278 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3279 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3280 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3281 he_gi_str[rate->he_gi] : "N/A"); 3282 else 3283 seq_printf(m, "Legacy %d", rate->legacy); 3284 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 3285 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3286 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 3287 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 3288 sta->deflink.agg.max_rc_amsdu_len); 3289 3290 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 3291 3292 switch (status->encoding) { 3293 case RX_ENC_LEGACY: 3294 seq_printf(m, "Legacy %d", status->rate_idx + 3295 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3296 break; 3297 case RX_ENC_HT: 3298 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3299 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3300 break; 3301 case RX_ENC_VHT: 3302 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3303 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3304 break; 3305 case RX_ENC_HE: 3306 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3307 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3308 he_gi_str[rate->he_gi] : "N/A"); 3309 break; 3310 } 3311 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3312 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 3313 3314 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 3315 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3316 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 3317 for (i = 0; i < ant_num; i++) { 3318 rssi = ewma_rssi_read(&rtwsta->rssi[i]); 3319 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3320 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3321 i + 1 == ant_num ? "" : ", "); 3322 } 3323 seq_puts(m, "]\n"); 3324 3325 seq_puts(m, "EVM: ["); 3326 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3327 evm_min = ewma_evm_read(&rtwsta->evm_min[i]); 3328 evm_max = ewma_evm_read(&rtwsta->evm_max[i]); 3329 3330 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3331 evm_min >> 2, (evm_min & 0x3) * 25, 3332 evm_max >> 2, (evm_max & 0x3) * 25); 3333 } 3334 seq_puts(m, "]\t"); 3335 3336 snr = ewma_snr_read(&rtwsta->avg_snr); 3337 seq_printf(m, "SNR: %u\n", snr); 3338} 3339 3340static void 3341rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3342 enum rtw89_hw_rate first_rate, int len) 3343{ 3344 int i; 3345 3346 for (i = 0; i < len; i++) 3347 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3348 pkt_stat->rx_rate_cnt[first_rate + i]); 3349} 3350 3351#define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3352#define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3353#define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3354 3355static const struct rtw89_rx_rate_cnt_info { 3356 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3357 int len; 3358 int ext; 3359 const char *rate_mode; 3360} rtw89_rx_rate_cnt_infos[] = { 3361 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3362 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3363 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3364 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3365 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3366 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3367 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3368 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3369 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3370 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3371}; 3372 3373static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3374{ 3375 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3376 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3377 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3378 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3379 const struct rtw89_chip_info *chip = rtwdev->chip; 3380 const struct rtw89_rx_rate_cnt_info *info; 3381 enum rtw89_hw_rate first_rate; 3382 int i; 3383 3384 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 3385 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 3386 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3387 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 3388 stats->rx_tf_periodic); 3389 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3390 stats->rx_avg_len); 3391 3392 seq_puts(m, "RX count:\n"); 3393 3394 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3395 info = &rtw89_rx_rate_cnt_infos[i]; 3396 first_rate = info->first_rate[chip->chip_gen]; 3397 if (first_rate >= RTW89_HW_RATE_NR) 3398 continue; 3399 3400 seq_printf(m, "%10s [", info->rate_mode); 3401 rtw89_debug_append_rx_rate(m, pkt_stat, 3402 first_rate, info->len); 3403 if (info->ext) { 3404 seq_puts(m, "]["); 3405 rtw89_debug_append_rx_rate(m, pkt_stat, 3406 first_rate + info->len, info->ext); 3407 } 3408 seq_puts(m, "]\n"); 3409 } 3410 3411 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3412 3413 return 0; 3414} 3415 3416static void rtw89_dump_addr_cam(struct seq_file *m, 3417 struct rtw89_addr_cam_entry *addr_cam) 3418{ 3419 struct rtw89_sec_cam_entry *sec_entry; 3420 int i; 3421 3422 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3423 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3424 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3425 addr_cam->sec_cam_map); 3426 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 3427 sec_entry = addr_cam->sec_entries[i]; 3428 if (!sec_entry) 3429 continue; 3430 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3431 if (sec_entry->ext_key) 3432 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3433 seq_puts(m, "\n"); 3434 } 3435} 3436 3437__printf(3, 4) 3438static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3439 const char *fmt, ...) 3440{ 3441 struct rtw89_pktofld_info *info; 3442 struct va_format vaf; 3443 va_list args; 3444 3445 if (list_empty(pkt_list)) 3446 return; 3447 3448 va_start(args, fmt); 3449 vaf.va = &args; 3450 vaf.fmt = fmt; 3451 3452 seq_printf(m, "%pV", &vaf); 3453 3454 va_end(args); 3455 3456 list_for_each_entry(info, pkt_list, list) 3457 seq_printf(m, "%d ", info->id); 3458 3459 seq_puts(m, "\n"); 3460} 3461 3462static 3463void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3464{ 3465 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3466 struct seq_file *m = (struct seq_file *)data; 3467 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 3468 3469 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 3470 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3471 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 3472 rtw89_dump_pkt_offload(m, &rtwvif->general_pkt_list, "\tpkt_ofld[GENERAL]: "); 3473} 3474 3475static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 3476{ 3477 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3478 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3479 struct rtw89_ba_cam_entry *entry; 3480 bool first = true; 3481 3482 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 3483 if (first) { 3484 seq_puts(m, "\tba_cam "); 3485 first = false; 3486 } else { 3487 seq_puts(m, ", "); 3488 } 3489 seq_printf(m, "tid[%u]=%d", entry->tid, 3490 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3491 } 3492 seq_puts(m, "\n"); 3493} 3494 3495static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3496{ 3497 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3498 struct seq_file *m = (struct seq_file *)data; 3499 3500 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 3501 sta->tdls ? "(TDLS)" : ""); 3502 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 3503 rtw89_dump_ba_cam(m, rtwsta); 3504} 3505 3506static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3507{ 3508 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3509 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3510 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3511 u8 idx; 3512 3513 mutex_lock(&rtwdev->mutex); 3514 3515 seq_puts(m, "map:\n"); 3516 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3517 rtwdev->mac_id_map); 3518 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3519 cam_info->addr_cam_map); 3520 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3521 cam_info->bssid_cam_map); 3522 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3523 cam_info->sec_cam_map); 3524 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3525 cam_info->ba_cam_map); 3526 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3527 rtwdev->pkt_offload); 3528 3529 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3530 if (!(rtwdev->chip->support_bands & BIT(idx))) 3531 continue; 3532 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3533 "\t\t[SCAN %u]: ", idx); 3534 } 3535 3536 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3537 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3538 3539 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3540 3541 mutex_unlock(&rtwdev->mutex); 3542 3543 return 0; 3544} 3545 3546static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 3547 .cb_read = rtw89_debug_priv_read_reg_get, 3548 .cb_write = rtw89_debug_priv_read_reg_select, 3549}; 3550 3551static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 3552 .cb_write = rtw89_debug_priv_write_reg_set, 3553}; 3554 3555static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 3556 .cb_read = rtw89_debug_priv_read_rf_get, 3557 .cb_write = rtw89_debug_priv_read_rf_select, 3558}; 3559 3560static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 3561 .cb_write = rtw89_debug_priv_write_rf_set, 3562}; 3563 3564static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 3565 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 3566}; 3567 3568static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 3569 .cb_read = rtw89_debug_priv_txpwr_table_get, 3570}; 3571 3572static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 3573 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 3574 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 3575}; 3576 3577static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 3578 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 3579 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 3580}; 3581 3582static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 3583 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 3584 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 3585}; 3586 3587static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 3588 .cb_write = rtw89_debug_priv_send_h2c_set, 3589}; 3590 3591static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 3592 .cb_read = rtw89_debug_priv_early_h2c_get, 3593 .cb_write = rtw89_debug_priv_early_h2c_set, 3594}; 3595 3596static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 3597 .cb_read = rtw89_debug_priv_fw_crash_get, 3598 .cb_write = rtw89_debug_priv_fw_crash_set, 3599}; 3600 3601static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 3602 .cb_read = rtw89_debug_priv_btc_info_get, 3603}; 3604 3605static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 3606 .cb_write = rtw89_debug_priv_btc_manual_set, 3607}; 3608 3609static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 3610 .cb_write = rtw89_debug_fw_log_manual_set, 3611}; 3612 3613static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 3614 .cb_read = rtw89_debug_priv_phy_info_get, 3615}; 3616 3617static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 3618 .cb_read = rtw89_debug_priv_stations_get, 3619}; 3620 3621#define rtw89_debugfs_add(name, mode, fopname, parent) \ 3622 do { \ 3623 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 3624 if (!debugfs_create_file(#name, mode, \ 3625 parent, &rtw89_debug_priv_ ##name, \ 3626 &file_ops_ ##fopname)) \ 3627 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3628 } while (0) 3629 3630#define rtw89_debugfs_add_w(name) \ 3631 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 3632#define rtw89_debugfs_add_rw(name) \ 3633 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 3634#define rtw89_debugfs_add_r(name) \ 3635 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 3636 3637void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 3638{ 3639 struct dentry *debugfs_topdir; 3640 3641 debugfs_topdir = debugfs_create_dir("rtw89", 3642 rtwdev->hw->wiphy->debugfsdir); 3643 3644 rtw89_debugfs_add_rw(read_reg); 3645 rtw89_debugfs_add_w(write_reg); 3646 rtw89_debugfs_add_rw(read_rf); 3647 rtw89_debugfs_add_w(write_rf); 3648 rtw89_debugfs_add_r(rf_reg_dump); 3649 rtw89_debugfs_add_r(txpwr_table); 3650 rtw89_debugfs_add_rw(mac_reg_dump); 3651 rtw89_debugfs_add_rw(mac_mem_dump); 3652 rtw89_debugfs_add_rw(mac_dbg_port_dump); 3653 rtw89_debugfs_add_w(send_h2c); 3654 rtw89_debugfs_add_rw(early_h2c); 3655 rtw89_debugfs_add_rw(fw_crash); 3656 rtw89_debugfs_add_r(btc_info); 3657 rtw89_debugfs_add_w(btc_manual); 3658 rtw89_debugfs_add_w(fw_log_manual); 3659 rtw89_debugfs_add_r(phy_info); 3660 rtw89_debugfs_add_r(stations); 3661} 3662#endif 3663 3664#ifdef CONFIG_RTW89_DEBUGMSG 3665void __rtw89_debug(struct rtw89_dev *rtwdev, 3666 enum rtw89_debug_mask mask, 3667 const char *fmt, ...) 3668{ 3669 struct va_format vaf = { 3670 .fmt = fmt, 3671 }; 3672 3673 va_list args; 3674 3675 va_start(args, fmt); 3676 vaf.va = &args; 3677 3678 if (rtw89_debug_mask & mask) 3679#if defined(__linux__) 3680 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 3681#elif defined(__FreeBSD__) 3682 { 3683 char *str; 3684 vasprintf(&str, M_KMALLOC, vaf.fmt, args); 3685 dev_printk(KERN_DEBUG, rtwdev->dev, "%s", str); 3686 free(str, M_KMALLOC); 3687 } 3688#endif 3689 3690 va_end(args); 3691} 3692EXPORT_SYMBOL(__rtw89_debug); 3693#endif 3694