1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com> 3 * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com> 4 */ 5 6#ifndef __REG_SDIO_H_ 7#define __REG_SDIO_H_ 8 9/* I/O bus domain address mapping */ 10#define SDIO_LOCAL_OFFSET 0x10250000 11#define WLAN_IOREG_OFFSET 0x10260000 12#define FIRMWARE_FIFO_OFFSET 0x10270000 13#define TX_HIQ_OFFSET 0x10310000 14#define TX_MIQ_OFFSET 0x10320000 15#define TX_LOQ_OFFSET 0x10330000 16#define TX_EPQ_OFFSET 0x10350000 17#define RX_RX0FF_OFFSET 0x10340000 18 19#define RTW_SDIO_BUS_MSK 0xffff0000 20#define SDIO_LOCAL_REG_MSK 0x00000fff 21#define WLAN_IOREG_REG_MSK 0x0000ffff 22 23/* SDIO Tx Control */ 24#define REG_SDIO_TX_CTRL (SDIO_LOCAL_OFFSET + 0x0000) 25 26/*SDIO status timeout*/ 27#define REG_SDIO_TIMEOUT (SDIO_LOCAL_OFFSET + 0x0002) 28 29/* SDIO Host Interrupt Mask */ 30#define REG_SDIO_HIMR (SDIO_LOCAL_OFFSET + 0x0014) 31#define REG_SDIO_HIMR_RX_REQUEST BIT(0) 32#define REG_SDIO_HIMR_AVAL BIT(1) 33#define REG_SDIO_HIMR_TXERR BIT(2) 34#define REG_SDIO_HIMR_RXERR BIT(3) 35#define REG_SDIO_HIMR_TXFOVW BIT(4) 36#define REG_SDIO_HIMR_RXFOVW BIT(5) 37#define REG_SDIO_HIMR_TXBCNOK BIT(6) 38#define REG_SDIO_HIMR_TXBCNERR BIT(7) 39#define REG_SDIO_HIMR_BCNERLY_INT BIT(16) 40#define REG_SDIO_HIMR_C2HCMD BIT(17) 41#define REG_SDIO_HIMR_CPWM1 BIT(18) 42#define REG_SDIO_HIMR_CPWM2 BIT(19) 43#define REG_SDIO_HIMR_HSISR_IND BIT(20) 44#define REG_SDIO_HIMR_GTINT3_IND BIT(21) 45#define REG_SDIO_HIMR_GTINT4_IND BIT(22) 46#define REG_SDIO_HIMR_PSTIMEOUT BIT(23) 47#define REG_SDIO_HIMR_OCPINT BIT(24) 48#define REG_SDIO_HIMR_ATIMEND BIT(25) 49#define REG_SDIO_HIMR_ATIMEND_E BIT(26) 50#define REG_SDIO_HIMR_CTWEND BIT(27) 51/* the following two are RTL8188 SDIO Specific */ 52#define REG_SDIO_HIMR_MCU_ERR BIT(28) 53#define REG_SDIO_HIMR_TSF_BIT32_TOGGLE BIT(29) 54 55/* SDIO Host Interrupt Service Routine */ 56#define REG_SDIO_HISR (SDIO_LOCAL_OFFSET + 0x0018) 57#define REG_SDIO_HISR_RX_REQUEST BIT(0) 58#define REG_SDIO_HISR_AVAL BIT(1) 59#define REG_SDIO_HISR_TXERR BIT(2) 60#define REG_SDIO_HISR_RXERR BIT(3) 61#define REG_SDIO_HISR_TXFOVW BIT(4) 62#define REG_SDIO_HISR_RXFOVW BIT(5) 63#define REG_SDIO_HISR_TXBCNOK BIT(6) 64#define REG_SDIO_HISR_TXBCNERR BIT(7) 65#define REG_SDIO_HISR_BCNERLY_INT BIT(16) 66#define REG_SDIO_HISR_C2HCMD BIT(17) 67#define REG_SDIO_HISR_CPWM1 BIT(18) 68#define REG_SDIO_HISR_CPWM2 BIT(19) 69#define REG_SDIO_HISR_HSISR_IND BIT(20) 70#define REG_SDIO_HISR_GTINT3_IND BIT(21) 71#define REG_SDIO_HISR_GTINT4_IND BIT(22) 72#define REG_SDIO_HISR_PSTIMEOUT BIT(23) 73#define REG_SDIO_HISR_OCPINT BIT(24) 74#define REG_SDIO_HISR_ATIMEND BIT(25) 75#define REG_SDIO_HISR_ATIMEND_E BIT(26) 76#define REG_SDIO_HISR_CTWEND BIT(27) 77/* the following two are RTL8188 SDIO Specific */ 78#define REG_SDIO_HISR_MCU_ERR BIT(28) 79#define REG_SDIO_HISR_TSF_BIT32_TOGGLE BIT(29) 80 81/* HCI Current Power Mode */ 82#define REG_SDIO_HCPWM (SDIO_LOCAL_OFFSET + 0x0019) 83/* RXDMA Request Length */ 84#define REG_SDIO_RX0_REQ_LEN (SDIO_LOCAL_OFFSET + 0x001C) 85/* OQT Free Page */ 86#define REG_SDIO_OQT_FREE_PG (SDIO_LOCAL_OFFSET + 0x001E) 87/* Free Tx Buffer Page */ 88#define REG_SDIO_FREE_TXPG (SDIO_LOCAL_OFFSET + 0x0020) 89/* HCI Current Power Mode 1 */ 90#define REG_SDIO_HCPWM1 (SDIO_LOCAL_OFFSET + 0x0024) 91/* HCI Current Power Mode 2 */ 92#define REG_SDIO_HCPWM2 (SDIO_LOCAL_OFFSET + 0x0026) 93/* Free Tx Page Sequence */ 94#define REG_SDIO_FREE_TXPG_SEQ (SDIO_LOCAL_OFFSET + 0x0028) 95/* HTSF Information */ 96#define REG_SDIO_HTSFR_INFO (SDIO_LOCAL_OFFSET + 0x0030) 97#define REG_SDIO_HCPWM1_V2 (SDIO_LOCAL_OFFSET + 0x0038) 98/* H2C */ 99#define REG_SDIO_H2C (SDIO_LOCAL_OFFSET + 0x0060) 100/* HCI Request Power Mode 1 */ 101#define REG_SDIO_HRPWM1 (SDIO_LOCAL_OFFSET + 0x0080) 102/* HCI Request Power Mode 2 */ 103#define REG_SDIO_HRPWM2 (SDIO_LOCAL_OFFSET + 0x0082) 104/* HCI Power Save Clock */ 105#define REG_SDIO_HPS_CLKR (SDIO_LOCAL_OFFSET + 0x0084) 106/* SDIO HCI Suspend Control */ 107#define REG_SDIO_HSUS_CTRL (SDIO_LOCAL_OFFSET + 0x0086) 108#define BIT_HCI_SUS_REQ BIT(0) 109#define BIT_HCI_RESUME_RDY BIT(1) 110/* SDIO Host Extension Interrupt Mask Always */ 111#define REG_SDIO_HIMR_ON (SDIO_LOCAL_OFFSET + 0x0090) 112/* SDIO Host Extension Interrupt Status Always */ 113#define REG_SDIO_HISR_ON (SDIO_LOCAL_OFFSET + 0x0091) 114 115#define REG_SDIO_INDIRECT_REG_CFG (SDIO_LOCAL_OFFSET + 0x0040) 116#define BIT_SDIO_INDIRECT_REG_CFG_WORD BIT(16) 117#define BIT_SDIO_INDIRECT_REG_CFG_DWORD BIT(17) 118#define BIT_SDIO_INDIRECT_REG_CFG_WRITE BIT(18) 119#define BIT_SDIO_INDIRECT_REG_CFG_READ BIT(19) 120#define BIT_SDIO_INDIRECT_REG_CFG_UNK20 BIT(20) 121#define REG_SDIO_INDIRECT_REG_DATA (SDIO_LOCAL_OFFSET + 0x0044) 122 123/* Sdio Address for SDIO Local Reg, TRX FIFO, MAC Reg */ 124#define REG_SDIO_CMD_ADDR_MSK GENMASK(16, 13) 125#define REG_SDIO_CMD_ADDR_SDIO_REG 0 126#define REG_SDIO_CMD_ADDR_MAC_REG 8 127#define REG_SDIO_CMD_ADDR_TXFF_HIGH 4 128#define REG_SDIO_CMD_ADDR_TXFF_LOW 6 129#define REG_SDIO_CMD_ADDR_TXFF_NORMAL 5 130#define REG_SDIO_CMD_ADDR_TXFF_EXTRA 7 131#define REG_SDIO_CMD_ADDR_RXFF 7 132 133#define RTW_SDIO_BLOCK_SIZE 512 134#define RTW_SDIO_ADDR_RX_RX0FF_GEN(_id) (0x0e000 | ((_id) & 0x3)) 135 136#define RTW_SDIO_DATA_PTR_ALIGN 8 137 138struct sdio_func; 139struct sdio_device_id; 140 141struct rtw_sdio_tx_data { 142 u8 sn; 143}; 144 145struct rtw_sdio_work_data { 146 struct work_struct work; 147 struct rtw_dev *rtwdev; 148}; 149 150struct rtw_sdio { 151 struct sdio_func *sdio_func; 152 153 u32 irq_mask; 154 u8 rx_addr; 155 bool sdio3_bus_mode; 156 157 void *irq_thread; 158 159 struct workqueue_struct *txwq; 160 struct rtw_sdio_work_data *tx_handler_data; 161 struct sk_buff_head tx_queue[RTK_MAX_TX_QUEUE_NUM]; 162}; 163 164extern const struct dev_pm_ops rtw_sdio_pm_ops; 165 166int rtw_sdio_probe(struct sdio_func *sdio_func, 167 const struct sdio_device_id *id); 168void rtw_sdio_remove(struct sdio_func *sdio_func); 169void rtw_sdio_shutdown(struct device *dev); 170 171static inline bool rtw_sdio_is_sdio30_supported(struct rtw_dev *rtwdev) 172{ 173 struct rtw_sdio *rtwsdio = (struct rtw_sdio *)rtwdev->priv; 174 175 return rtwsdio->sdio3_bus_mode; 176} 177 178#endif 179