1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2018-2019  Realtek Corporation
3 */
4
5#ifndef __RTW8821C_H__
6#define __RTW8821C_H__
7
8#include <asm/byteorder.h>
9
10#define RCR_VHT_ACK		BIT(26)
11
12struct rtw8821cu_efuse {
13	u8 res4[4];			/* 0xd0 */
14	u8 usb_optional_function;
15	u8 res5[0x1e];
16	u8 res6[2];
17	u8 serial[0x0b];		/* 0xf5 */
18	u8 vid;				/* 0x100 */
19	u8 res7;
20	u8 pid;
21	u8 res8[4];
22	u8 mac_addr[ETH_ALEN];		/* 0x107 */
23	u8 res9[2];
24	u8 vendor_name[0x07];
25	u8 res10[2];
26	u8 device_name[0x14];
27	u8 res11[0xcf];
28	u8 package_type;		/* 0x1fb */
29	u8 res12[0x4];
30};
31
32struct rtw8821ce_efuse {
33	u8 mac_addr[ETH_ALEN];		/* 0xd0 */
34	u8 vender_id[2];
35	u8 device_id[2];
36	u8 sub_vender_id[2];
37	u8 sub_device_id[2];
38	u8 pmc[2];
39	u8 exp_device_cap[2];
40	u8 msi_cap;
41	u8 ltr_cap;			/* 0xe3 */
42	u8 exp_link_control[2];
43	u8 link_cap[4];
44	u8 link_control[2];
45	u8 serial_number[8];
46	u8 res0:2;			/* 0xf4 */
47	u8 ltr_en:1;
48	u8 res1:2;
49	u8 obff:2;
50	u8 res2:3;
51	u8 obff_cap:2;
52	u8 res3:4;
53	u8 res4[3];
54	u8 class_code[3];
55	u8 pci_pm_L1_2_supp:1;
56	u8 pci_pm_L1_1_supp:1;
57	u8 aspm_pm_L1_2_supp:1;
58	u8 aspm_pm_L1_1_supp:1;
59	u8 L1_pm_substates_supp:1;
60	u8 res5:3;
61	u8 port_common_mode_restore_time;
62	u8 port_t_power_on_scale:2;
63	u8 res6:1;
64	u8 port_t_power_on_value:5;
65	u8 res7;
66};
67
68struct rtw8821cs_efuse {
69	u8 res4[0x4a];			/* 0xd0 */
70	u8 mac_addr[ETH_ALEN];		/* 0x11a */
71} __packed;
72
73struct rtw8821c_efuse {
74	__le16 rtl_id;
75	u8 res0[0x0e];
76
77	/* power index for four RF paths */
78	struct rtw_txpwr_idx txpwr_idx_table[4];
79
80	u8 channel_plan;		/* 0xb8 */
81	u8 xtal_k;
82	u8 thermal_meter;
83	u8 iqk_lck;
84	u8 pa_type;			/* 0xbc */
85	u8 lna_type_2g[2];		/* 0xbd */
86	u8 lna_type_5g[2];
87	u8 rf_board_option;
88	u8 rf_feature_option;
89	u8 rf_bt_setting;
90	u8 eeprom_version;
91	u8 eeprom_customer_id;
92	u8 tx_bb_swing_setting_2g;
93	u8 tx_bb_swing_setting_5g;
94	u8 tx_pwr_calibrate_rate;
95	u8 rf_antenna_option;		/* 0xc9 */
96	u8 rfe_option;
97	u8 country_code[2];
98	u8 res[3];
99	union {
100		struct rtw8821ce_efuse e;
101		struct rtw8821cu_efuse u;
102		struct rtw8821cs_efuse s;
103	};
104};
105
106static inline void
107_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
108{
109	/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
110	rtw_write32_mask(rtwdev, addr, mask, data);
111	rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
112}
113
114extern const struct rtw_chip_info rtw8821c_hw_spec;
115
116#define rtw_write32s_mask(rtwdev, addr, mask, data)			       \
117	do {								       \
118		BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00);	       \
119									       \
120		_rtw_write32s_mask(rtwdev, addr, mask, data);		       \
121	} while (0)
122
123#define BIT_FEN_PCIEA BIT(6)
124#define WLAN_SLOT_TIME		0x09
125#define WLAN_PIFS_TIME		0x19
126#define WLAN_SIFS_CCK_CONT_TX	0xA
127#define WLAN_SIFS_OFDM_CONT_TX	0xE
128#define WLAN_SIFS_CCK_TRX	0x10
129#define WLAN_SIFS_OFDM_TRX	0x10
130#define WLAN_VO_TXOP_LIMIT	0x186
131#define WLAN_VI_TXOP_LIMIT	0x3BC
132#define WLAN_RDG_NAV		0x05
133#define WLAN_TXOP_NAV		0x1B
134#define WLAN_CCK_RX_TSF		0x30
135#define WLAN_OFDM_RX_TSF	0x30
136#define WLAN_TBTT_PROHIBIT	0x04
137#define WLAN_TBTT_HOLD_TIME	0x064
138#define WLAN_DRV_EARLY_INT	0x04
139#define WLAN_BCN_DMA_TIME	0x02
140
141#define WLAN_RX_FILTER0		0x0FFFFFFF
142#define WLAN_RX_FILTER2		0xFFFF
143#define WLAN_RCR_CFG		0xE400220E
144#define WLAN_RXPKT_MAX_SZ	12288
145#define WLAN_RXPKT_MAX_SZ_512	(WLAN_RXPKT_MAX_SZ >> 9)
146
147#define WLAN_AMPDU_MAX_TIME		0x70
148#define WLAN_RTS_LEN_TH			0xFF
149#define WLAN_RTS_TX_TIME_TH		0x08
150#define WLAN_MAX_AGG_PKT_LIMIT		0x20
151#define WLAN_RTS_MAX_AGG_PKT_LIMIT	0x20
152#define FAST_EDCA_VO_TH		0x06
153#define FAST_EDCA_VI_TH		0x06
154#define FAST_EDCA_BE_TH		0x06
155#define FAST_EDCA_BK_TH		0x06
156#define WLAN_BAR_RETRY_LIMIT		0x01
157#define WLAN_RA_TRY_RATE_AGG_LIMIT	0x08
158
159#define WLAN_TX_FUNC_CFG1		0x30
160#define WLAN_TX_FUNC_CFG2		0x30
161#define WLAN_MAC_OPT_NORM_FUNC1		0x98
162#define WLAN_MAC_OPT_LB_FUNC1		0x80
163#define WLAN_MAC_OPT_FUNC2		0xb0810041
164
165#define WLAN_SIFS_CFG	(WLAN_SIFS_CCK_CONT_TX | \
166			(WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
167			(WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
168			(WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
169
170#define WLAN_TBTT_TIME	(WLAN_TBTT_PROHIBIT |\
171			(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
172
173#define WLAN_NAV_CFG		(WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
174#define WLAN_RX_TSF_CFG		(WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
175#define WLAN_PRE_TXCNT_TIME_TH		0x1E4
176
177/* phy status page0 */
178#define GET_PHY_STAT_P0_PWDB(phy_stat)                                         \
179	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
180#define GET_PHY_STAT_P0_VGA(phy_stat)                                          \
181	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8))
182#define GET_PHY_STAT_P0_LNA_L(phy_stat)                                        \
183	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13))
184#define GET_PHY_STAT_P0_LNA_H(phy_stat)                                        \
185	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23))
186#define BIT_LNA_H_MASK BIT(3)
187#define BIT_LNA_L_MASK GENMASK(2, 0)
188
189/* phy status page1 */
190#define GET_PHY_STAT_P1_PWDB_A(phy_stat)                                       \
191	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
192#define GET_PHY_STAT_P1_PWDB_B(phy_stat)                                       \
193	le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
194#define GET_PHY_STAT_P1_RF_MODE(phy_stat)                                      \
195	le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
196#define GET_PHY_STAT_P1_L_RXSC(phy_stat)                                       \
197	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
198#define GET_PHY_STAT_P1_HT_RXSC(phy_stat)                                      \
199	le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
200#define GET_PHY_STAT_P1_RXEVM_A(phy_stat)                                      \
201	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
202#define GET_PHY_STAT_P1_RXEVM_B(phy_stat)                                      \
203	le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
204#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat)                                 \
205	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
206#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat)                                 \
207	le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
208#define GET_PHY_STAT_P1_RXSNR_A(phy_stat)                                      \
209	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
210#define GET_PHY_STAT_P1_RXSNR_B(phy_stat)                                      \
211	le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
212
213#define REG_SYS_CTRL	0x000
214#define BIT_FEN_EN	BIT(26)
215#define REG_INIRTS_RATE_SEL 0x0480
216#define REG_HTSTFWT	0x800
217#define REG_RXPSEL	0x808
218#define BIT_RX_PSEL_RST		(BIT(28) | BIT(29))
219#define REG_TXPSEL	0x80c
220#define REG_RXCCAMSK	0x814
221#define REG_CCASEL	0x82c
222#define REG_PDMFTH	0x830
223#define REG_CCA2ND	0x838
224#define REG_L1WT	0x83c
225#define REG_L1PKWT	0x840
226#define REG_MRC		0x850
227#define REG_CLKTRK	0x860
228#define REG_ADCCLK	0x8ac
229#define REG_ADC160	0x8c4
230#define REG_ADC40	0x8c8
231#define REG_CHFIR	0x8f0
232#define REG_CDDTXP	0x93c
233#define REG_TXPSEL1	0x940
234#define REG_ACBB0	0x948
235#define REG_ACBBRXFIR	0x94c
236#define REG_ACGG2TBL	0x958
237#define REG_FAS		0x9a4
238#define REG_RXSB	0xa00
239#define REG_ADCINI	0xa04
240#define REG_PWRTH	0xa08
241#define REG_TXSF2	0xa24
242#define REG_TXSF6	0xa28
243#define REG_FA_CCK	0xa5c
244#define REG_RXDESC	0xa2c
245#define REG_ENTXCCK	0xa80
246#define BTG_LNA		0xfc84
247#define WLG_LNA		0x7532
248#define REG_ENRXCCA	0xa84
249#define BTG_CCA		0x0e
250#define WLG_CCA		0x12
251#define REG_PWRTH2	0xaa8
252#define REG_CSRATIO	0xaaa
253#define REG_TXFILTER	0xaac
254#define REG_CNTRST	0xb58
255#define REG_AGCTR_A	0xc08
256#define REG_TXSCALE_A	0xc1c
257#define REG_TXDFIR	0xc20
258#define REG_RXIGI_A	0xc50
259#define REG_TXAGCIDX	0xc94
260#define REG_TRSW	0xca0
261#define REG_RFESEL0	0xcb0
262#define REG_RFESEL8	0xcb4
263#define REG_RFECTL	0xcb8
264#define B_BTG_SWITCH	BIT(16)
265#define B_CTRL_SWITCH	BIT(18)
266#define B_WL_SWITCH	(BIT(20) | BIT(22))
267#define B_WLG_SWITCH	BIT(21)
268#define B_WLA_SWITCH	BIT(23)
269#define REG_RFEINV	0xcbc
270#define REG_AGCTR_B	0xe08
271#define REG_RXIGI_B	0xe50
272#define REG_CRC_CCK	0xf04
273#define REG_CRC_OFDM	0xf14
274#define REG_CRC_HT	0xf10
275#define REG_CRC_VHT	0xf0c
276#define REG_CCA_OFDM	0xf08
277#define REG_FA_OFDM	0xf48
278#define REG_CCA_CCK	0xfcc
279#define REG_DMEM_CTRL	0x1080
280#define BIT_WL_RST	BIT(16)
281#define REG_ANTWT	0x1904
282#define REG_IQKFAILMSK	0x1bf0
283#define BIT_MASK_R_RFE_SEL_15	GENMASK(31, 28)
284#define BIT_SDIO_INT BIT(18)
285#define BT_CNT_ENABLE	0x1
286#define BIT_BCN_QUEUE	BIT(3)
287#define BCN_PRI_EN	0x1
288#define PTA_CTRL_PIN	0x66
289#define DPDT_CTRL_PIN	0x77
290#define ANTDIC_CTRL_PIN	0x88
291#define REG_CTRL_TYPE	0x67
292#define BIT_CTRL_TYPE1	BIT(5)
293#define BIT_CTRL_TYPE2	BIT(4)
294#define CTRL_TYPE_MASK	GENMASK(15, 8)
295
296#define RF18_BAND_MASK		(BIT(16) | BIT(9) | BIT(8))
297#define RF18_BAND_2G		(0)
298#define RF18_BAND_5G		(BIT(16) | BIT(8))
299#define RF18_CHANNEL_MASK	(MASKBYTE0)
300#define RF18_RFSI_MASK		(BIT(18) | BIT(17))
301#define RF18_RFSI_GE		(BIT(17))
302#define RF18_RFSI_GT		(BIT(18))
303#define RF18_BW_MASK		(BIT(11) | BIT(10))
304#define RF18_BW_20M		(BIT(11) | BIT(10))
305#define RF18_BW_40M		(BIT(11))
306#define RF18_BW_80M		(BIT(10))
307
308#endif
309