1/* SPDX-License-Identifier: ISC */ 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#ifndef __MT76_CONNAC_MCU_H 5#define __MT76_CONNAC_MCU_H 6 7#include "mt76_connac.h" 8 9#define FW_FEATURE_SET_ENCRYPT BIT(0) 10#define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1) 11#define FW_FEATURE_ENCRY_MODE BIT(4) 12#define FW_FEATURE_OVERRIDE_ADDR BIT(5) 13#define FW_FEATURE_NON_DL BIT(6) 14 15#define DL_MODE_ENCRYPT BIT(0) 16#define DL_MODE_KEY_IDX GENMASK(2, 1) 17#define DL_MODE_RESET_SEC_IV BIT(3) 18#define DL_MODE_WORKING_PDA_CR4 BIT(4) 19#define DL_MODE_VALID_RAM_ENTRY BIT(5) 20#define DL_CONFIG_ENCRY_MODE_SEL BIT(6) 21#define DL_MODE_NEED_RSP BIT(31) 22 23#define FW_START_OVERRIDE BIT(0) 24#define FW_START_WORKING_PDA_CR4 BIT(2) 25#define FW_START_WORKING_PDA_DSP BIT(3) 26 27#define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0) 28#define PATCH_SEC_TYPE_MASK GENMASK(15, 0) 29#define PATCH_SEC_TYPE_INFO 0x2 30 31#define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24) 32#define PATCH_SEC_ENC_TYPE_PLAIN 0x00 33#define PATCH_SEC_ENC_TYPE_AES 0x01 34#define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02 35#define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0) 36#define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0) 37 38enum { 39 FW_TYPE_DEFAULT = 0, 40 FW_TYPE_CLC = 2, 41 FW_TYPE_MAX_NUM = 255 42}; 43 44#define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 45#define MCU_PKT_ID 0xa0 46 47struct mt76_connac2_mcu_txd { 48 __le32 txd[8]; 49 50 __le16 len; 51 __le16 pq_id; 52 53 u8 cid; 54 u8 pkt_type; 55 u8 set_query; /* FW don't care */ 56 u8 seq; 57 58 u8 uc_d2b0_rev; 59 u8 ext_cid; 60 u8 s2d_index; 61 u8 ext_cid_ack; 62 63 u32 rsv[5]; 64} __packed __aligned(4); 65 66/** 67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3 68 * @txd: hardware descriptor 69 * @len: total length not including txd 70 * @cid: command identifier 71 * @pkt_type: must be 0xa0 (cmd packet by long format) 72 * @frag_n: fragment number 73 * @seq: sequence number 74 * @checksum: 0 mean there is no checksum 75 * @s2d_index: index for command source and destination 76 * Definition | value | note 77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 81 * 82 * @option: command option 83 * BIT[0]: UNI_CMD_OPT_BIT_ACK 84 * set to 1 to request a fw reply 85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 86 * is set, mcu firmware will send response event EID = 0x01 87 * (UNI_EVENT_ID_CMD_RESULT) to the host. 88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 89 * 0: original command 90 * 1: unified command 91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 92 * 0: QUERY command 93 * 1: SET command 94 */ 95struct mt76_connac2_mcu_uni_txd { 96 __le32 txd[8]; 97 98 /* DW1 */ 99 __le16 len; 100 __le16 cid; 101 102 /* DW2 */ 103 u8 rsv; 104 u8 pkt_type; 105 u8 frag_n; 106 u8 seq; 107 108 /* DW3 */ 109 __le16 checksum; 110 u8 s2d_index; 111 u8 option; 112 113 /* DW4 */ 114 u8 rsv1[4]; 115} __packed __aligned(4); 116 117struct mt76_connac2_mcu_rxd { 118 __le32 rxd[6]; 119 120 __le16 len; 121 __le16 pkt_type_id; 122 123 u8 eid; 124 u8 seq; 125 u8 option; 126 u8 rsv; 127 u8 ext_eid; 128 u8 rsv1[2]; 129 u8 s2d_index; 130 131#if defined(__linux__) 132 u8 tlv[]; 133#elif defined(__FreeBSD__) 134 u8 tlv[0]; 135#endif 136}; 137 138struct mt76_connac2_patch_hdr { 139 char build_date[16]; 140 char platform[4]; 141 __be32 hw_sw_ver; 142 __be32 patch_ver; 143 __be16 checksum; 144 u16 rsv; 145 struct { 146 __be32 patch_ver; 147 __be32 subsys; 148 __be32 feature; 149 __be32 n_region; 150 __be32 crc; 151 u32 rsv[11]; 152 } desc; 153} __packed; 154 155struct mt76_connac2_patch_sec { 156 __be32 type; 157 __be32 offs; 158 __be32 size; 159 union { 160 __be32 spec[13]; 161 struct { 162 __be32 addr; 163 __be32 len; 164 __be32 sec_key_idx; 165 __be32 align_len; 166 u32 rsv[9]; 167 } info; 168 }; 169} __packed; 170 171struct mt76_connac2_fw_trailer { 172 u8 chip_id; 173 u8 eco_code; 174 u8 n_region; 175 u8 format_ver; 176 u8 format_flag; 177 u8 rsv[2]; 178 char fw_ver[10]; 179 char build_date[15]; 180 __le32 crc; 181} __packed; 182 183struct mt76_connac2_fw_region { 184 __le32 decomp_crc; 185 __le32 decomp_len; 186 __le32 decomp_blk_sz; 187 u8 rsv[4]; 188 __le32 addr; 189 __le32 len; 190 u8 feature_set; 191 u8 type; 192 u8 rsv1[14]; 193} __packed; 194 195struct tlv { 196 __le16 tag; 197 __le16 len; 198} __packed; 199 200struct bss_info_omac { 201 __le16 tag; 202 __le16 len; 203 u8 hw_bss_idx; 204 u8 omac_idx; 205 u8 band_idx; 206 u8 rsv0; 207 __le32 conn_type; 208 u32 rsv1; 209} __packed; 210 211struct bss_info_basic { 212 __le16 tag; 213 __le16 len; 214 __le32 network_type; 215 u8 active; 216 u8 rsv0; 217 __le16 bcn_interval; 218 u8 bssid[ETH_ALEN]; 219 u8 wmm_idx; 220 u8 dtim_period; 221 u8 bmc_wcid_lo; 222 u8 cipher; 223 u8 phy_mode; 224 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */ 225 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */ 226 u8 bmc_wcid_hi; /* high Byte and version */ 227 u8 rsv[2]; 228} __packed; 229 230struct bss_info_rf_ch { 231 __le16 tag; 232 __le16 len; 233 u8 pri_ch; 234 u8 center_ch0; 235 u8 center_ch1; 236 u8 bw; 237 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */ 238 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */ 239 u8 rsv[2]; 240} __packed; 241 242struct bss_info_ext_bss { 243 __le16 tag; 244 __le16 len; 245 __le32 mbss_tsf_offset; /* in unit of us */ 246 u8 rsv[8]; 247} __packed; 248 249enum { 250 BSS_INFO_OMAC, 251 BSS_INFO_BASIC, 252 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 253 BSS_INFO_PM, /* sta only */ 254 BSS_INFO_UAPSD, /* sta only */ 255 BSS_INFO_ROAM_DETECT, /* obsoleted */ 256 BSS_INFO_LQ_RM, /* obsoleted */ 257 BSS_INFO_EXT_BSS, 258 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */ 259 BSS_INFO_SYNC_MODE, /* obsoleted */ 260 BSS_INFO_RA, 261 BSS_INFO_HW_AMSDU, 262 BSS_INFO_BSS_COLOR, 263 BSS_INFO_HE_BASIC, 264 BSS_INFO_PROTECT_INFO, 265 BSS_INFO_OFFLOAD, 266 BSS_INFO_11V_MBSSID, 267 BSS_INFO_MAX_NUM 268}; 269 270/* sta_rec */ 271 272struct sta_ntlv_hdr { 273 u8 rsv[2]; 274 __le16 tlv_num; 275} __packed; 276 277struct sta_req_hdr { 278 u8 bss_idx; 279 u8 wlan_idx_lo; 280 __le16 tlv_num; 281 u8 is_tlv_append; 282 u8 muar_idx; 283 u8 wlan_idx_hi; 284 u8 rsv; 285} __packed; 286 287struct sta_rec_basic { 288 __le16 tag; 289 __le16 len; 290 __le32 conn_type; 291 u8 conn_state; 292 u8 qos; 293 __le16 aid; 294 u8 peer_addr[ETH_ALEN]; 295#define EXTRA_INFO_VER BIT(0) 296#define EXTRA_INFO_NEW BIT(1) 297 __le16 extra_info; 298} __packed; 299 300struct sta_rec_ht { 301 __le16 tag; 302 __le16 len; 303 __le16 ht_cap; 304 u16 rsv; 305} __packed; 306 307struct sta_rec_vht { 308 __le16 tag; 309 __le16 len; 310 __le32 vht_cap; 311 __le16 vht_rx_mcs_map; 312 __le16 vht_tx_mcs_map; 313 /* mt7915 - mt7921 */ 314 u8 rts_bw_sig; 315 u8 rsv[3]; 316} __packed; 317 318struct sta_rec_uapsd { 319 __le16 tag; 320 __le16 len; 321 u8 dac_map; 322 u8 tac_map; 323 u8 max_sp; 324 u8 rsv0; 325 __le16 listen_interval; 326 u8 rsv1[2]; 327} __packed; 328 329struct sta_rec_ba { 330 __le16 tag; 331 __le16 len; 332 u8 tid; 333 u8 ba_type; 334 u8 amsdu; 335 u8 ba_en; 336 __le16 ssn; 337 __le16 winsize; 338} __packed; 339 340struct sta_rec_he { 341 __le16 tag; 342 __le16 len; 343 344 __le32 he_cap; 345 346 u8 t_frame_dur; 347 u8 max_ampdu_exp; 348 u8 bw_set; 349 u8 device_class; 350 u8 dcm_tx_mode; 351 u8 dcm_tx_max_nss; 352 u8 dcm_rx_mode; 353 u8 dcm_rx_max_nss; 354 u8 dcm_max_ru; 355 u8 punc_pream_rx; 356 u8 pkt_ext; 357 u8 rsv1; 358 359 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 360 361 u8 rsv2[2]; 362} __packed; 363 364struct sta_rec_he_v2 { 365 __le16 tag; 366 __le16 len; 367 u8 he_mac_cap[6]; 368 u8 he_phy_cap[11]; 369 u8 pkt_ext; 370 /* 0: BW80, 1: BW160, 2: BW8080 */ 371 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 372} __packed; 373 374struct sta_rec_amsdu { 375 __le16 tag; 376 __le16 len; 377 u8 max_amsdu_num; 378 u8 max_mpdu_size; 379 u8 amsdu_en; 380 u8 rsv; 381} __packed; 382 383struct sta_rec_state { 384 __le16 tag; 385 __le16 len; 386 __le32 flags; 387 u8 state; 388 u8 vht_opmode; 389 u8 action; 390 u8 rsv[1]; 391} __packed; 392 393#define RA_LEGACY_OFDM GENMASK(13, 6) 394#define RA_LEGACY_CCK GENMASK(3, 0) 395#define HT_MCS_MASK_NUM 10 396struct sta_rec_ra_info { 397 __le16 tag; 398 __le16 len; 399 __le16 legacy; 400 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 401} __packed; 402 403struct sta_rec_phy { 404 __le16 tag; 405 __le16 len; 406 __le16 basic_rate; 407 u8 phy_type; 408 u8 ampdu; 409 u8 rts_policy; 410 u8 rcpi; 411 u8 max_ampdu_len; /* connac3 */ 412 u8 rsv[1]; 413} __packed; 414 415struct sta_rec_he_6g_capa { 416 __le16 tag; 417 __le16 len; 418 __le16 capa; 419 u8 rsv[2]; 420} __packed; 421 422struct sec_key { 423 u8 cipher_id; 424 u8 cipher_len; 425 u8 key_id; 426 u8 key_len; 427 u8 key[32]; 428} __packed; 429 430struct sta_rec_sec { 431 __le16 tag; 432 __le16 len; 433 u8 add; 434 u8 n_cipher; 435 u8 rsv[2]; 436 437 struct sec_key key[2]; 438} __packed; 439 440struct sta_rec_bf { 441 __le16 tag; 442 __le16 len; 443 444 __le16 pfmu; /* 0xffff: no access right for PFMU */ 445 bool su_mu; /* 0: SU, 1: MU */ 446 u8 bf_cap; /* 0: iBF, 1: eBF */ 447 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */ 448 u8 ndpa_rate; 449 u8 ndp_rate; 450 u8 rept_poll_rate; 451 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */ 452 u8 ncol; 453 u8 nrow; 454 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */ 455 456 u8 mem_total; 457 u8 mem_20m; 458 struct { 459 u8 row; 460 u8 col: 6, row_msb: 2; 461 } mem[4]; 462 463 __le16 smart_ant; 464 u8 se_idx; 465 u8 auto_sounding; /* b7: low traffic indicator 466 * b6: Stop sounding for this entry 467 * b5 ~ b0: postpone sounding 468 */ 469 u8 ibf_timeout; 470 u8 ibf_dbw; 471 u8 ibf_ncol; 472 u8 ibf_nrow; 473 u8 nrow_gt_bw80; 474 u8 ncol_gt_bw80; 475 u8 ru_start_idx; 476 u8 ru_end_idx; 477 478 bool trigger_su; 479 bool trigger_mu; 480 bool ng16_su; 481 bool ng16_mu; 482 bool codebook42_su; 483 bool codebook75_mu; 484 485 u8 he_ltf; 486 u8 rsv[3]; 487} __packed; 488 489struct sta_rec_bfee { 490 __le16 tag; 491 __le16 len; 492 bool fb_identity_matrix; /* 1: feedback identity matrix */ 493 bool ignore_feedback; /* 1: ignore */ 494 u8 rsv[2]; 495} __packed; 496 497struct sta_rec_muru { 498 __le16 tag; 499 __le16 len; 500 501 struct { 502 bool ofdma_dl_en; 503 bool ofdma_ul_en; 504 bool mimo_dl_en; 505 bool mimo_ul_en; 506 u8 rsv[4]; 507 } cfg; 508 509 struct { 510 u8 punc_pream_rx; 511 bool he_20m_in_40m_2g; 512 bool he_20m_in_160m; 513 bool he_80m_in_160m; 514 bool lt16_sigb; 515 bool rx_su_comp_sigb; 516 bool rx_su_non_comp_sigb; 517 u8 rsv; 518 } ofdma_dl; 519 520 struct { 521 u8 t_frame_dur; 522 u8 mu_cascading; 523 u8 uo_ra; 524 u8 he_2x996_tone; 525 u8 rx_t_frame_11ac; 526 u8 rx_ctrl_frame_to_mbss; 527 u8 rsv[2]; 528 } ofdma_ul; 529 530 struct { 531 bool vht_mu_bfee; 532 bool partial_bw_dl_mimo; 533 u8 rsv[2]; 534 } mimo_dl; 535 536 struct { 537 bool full_ul_mimo; 538 bool partial_ul_mimo; 539 u8 rsv[2]; 540 } mimo_ul; 541} __packed; 542 543struct sta_phy { 544 u8 type; 545 u8 flag; 546 u8 stbc; 547 u8 sgi; 548 u8 bw; 549 u8 ldpc; 550 u8 mcs; 551 u8 nss; 552 u8 he_ltf; 553}; 554 555struct sta_rec_ra { 556 __le16 tag; 557 __le16 len; 558 559 u8 valid; 560 u8 auto_rate; 561 u8 phy_mode; 562 u8 channel; 563 u8 bw; 564 u8 disable_cck; 565 u8 ht_mcs32; 566 u8 ht_gf; 567 u8 ht_mcs[4]; 568 u8 mmps_mode; 569 u8 gband_256; 570 u8 af; 571 u8 auth_wapi_mode; 572 u8 rate_len; 573 574 u8 supp_mode; 575 u8 supp_cck_rate; 576 u8 supp_ofdm_rate; 577 __le32 supp_ht_mcs; 578 __le16 supp_vht_mcs[4]; 579 580 u8 op_mode; 581 u8 op_vht_chan_width; 582 u8 op_vht_rx_nss; 583 u8 op_vht_rx_nss_type; 584 585 __le32 sta_cap; 586 587 struct sta_phy phy; 588} __packed; 589 590struct sta_rec_ra_fixed { 591 __le16 tag; 592 __le16 len; 593 594 __le32 field; 595 u8 op_mode; 596 u8 op_vht_chan_width; 597 u8 op_vht_rx_nss; 598 u8 op_vht_rx_nss_type; 599 600 struct sta_phy phy; 601 602 u8 spe_idx; 603 u8 short_preamble; 604 u8 is_5g; 605 u8 mmps_mode; 606} __packed; 607 608/* wtbl_rec */ 609 610struct wtbl_req_hdr { 611 u8 wlan_idx_lo; 612 u8 operation; 613 __le16 tlv_num; 614 u8 wlan_idx_hi; 615 u8 rsv[3]; 616} __packed; 617 618struct wtbl_generic { 619 __le16 tag; 620 __le16 len; 621 u8 peer_addr[ETH_ALEN]; 622 u8 muar_idx; 623 u8 skip_tx; 624 u8 cf_ack; 625 u8 qos; 626 u8 mesh; 627 u8 adm; 628 __le16 partial_aid; 629 u8 baf_en; 630 u8 aad_om; 631} __packed; 632 633struct wtbl_rx { 634 __le16 tag; 635 __le16 len; 636 u8 rcid; 637 u8 rca1; 638 u8 rca2; 639 u8 rv; 640 u8 rsv[4]; 641} __packed; 642 643struct wtbl_ht { 644 __le16 tag; 645 __le16 len; 646 u8 ht; 647 u8 ldpc; 648 u8 af; 649 u8 mm; 650 u8 rsv[4]; 651} __packed; 652 653struct wtbl_vht { 654 __le16 tag; 655 __le16 len; 656 u8 ldpc; 657 u8 dyn_bw; 658 u8 vht; 659 u8 txop_ps; 660 u8 rsv[4]; 661} __packed; 662 663struct wtbl_tx_ps { 664 __le16 tag; 665 __le16 len; 666 u8 txps; 667 u8 rsv[3]; 668} __packed; 669 670struct wtbl_hdr_trans { 671 __le16 tag; 672 __le16 len; 673 u8 to_ds; 674 u8 from_ds; 675 u8 no_rx_trans; 676 u8 rsv; 677} __packed; 678 679struct wtbl_ba { 680 __le16 tag; 681 __le16 len; 682 /* common */ 683 u8 tid; 684 u8 ba_type; 685 u8 rsv0[2]; 686 /* originator only */ 687 __le16 sn; 688 u8 ba_en; 689 u8 ba_winsize_idx; 690 /* originator & recipient */ 691 __le16 ba_winsize; 692 /* recipient only */ 693 u8 peer_addr[ETH_ALEN]; 694 u8 rst_ba_tid; 695 u8 rst_ba_sel; 696 u8 rst_ba_sb; 697 u8 band_idx; 698 u8 rsv1[4]; 699} __packed; 700 701struct wtbl_smps { 702 __le16 tag; 703 __le16 len; 704 u8 smps; 705 u8 rsv[3]; 706} __packed; 707 708/* mt7615 only */ 709 710struct wtbl_bf { 711 __le16 tag; 712 __le16 len; 713 u8 ibf; 714 u8 ebf; 715 u8 ibf_vht; 716 u8 ebf_vht; 717 u8 gid; 718 u8 pfmu_idx; 719 u8 rsv[2]; 720} __packed; 721 722struct wtbl_pn { 723 __le16 tag; 724 __le16 len; 725 u8 pn[6]; 726 u8 rsv[2]; 727} __packed; 728 729struct wtbl_spe { 730 __le16 tag; 731 __le16 len; 732 u8 spe_idx; 733 u8 rsv[3]; 734} __packed; 735 736struct wtbl_raw { 737 __le16 tag; 738 __le16 len; 739 u8 wtbl_idx; 740 u8 dw; 741 u8 rsv[2]; 742 __le32 msk; 743 __le32 val; 744} __packed; 745 746#define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 747 sizeof(struct wtbl_generic) + \ 748 sizeof(struct wtbl_rx) + \ 749 sizeof(struct wtbl_ht) + \ 750 sizeof(struct wtbl_vht) + \ 751 sizeof(struct wtbl_tx_ps) + \ 752 sizeof(struct wtbl_hdr_trans) +\ 753 sizeof(struct wtbl_ba) + \ 754 sizeof(struct wtbl_bf) + \ 755 sizeof(struct wtbl_smps) + \ 756 sizeof(struct wtbl_pn) + \ 757 sizeof(struct wtbl_spe)) 758 759#define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 760 sizeof(struct sta_rec_basic) + \ 761 sizeof(struct sta_rec_bf) + \ 762 sizeof(struct sta_rec_ht) + \ 763 sizeof(struct sta_rec_he) + \ 764 sizeof(struct sta_rec_ba) + \ 765 sizeof(struct sta_rec_vht) + \ 766 sizeof(struct sta_rec_uapsd) + \ 767 sizeof(struct sta_rec_amsdu) + \ 768 sizeof(struct sta_rec_muru) + \ 769 sizeof(struct sta_rec_bfee) + \ 770 sizeof(struct sta_rec_ra) + \ 771 sizeof(struct sta_rec_sec) + \ 772 sizeof(struct sta_rec_ra_fixed) + \ 773 sizeof(struct sta_rec_he_6g_capa) + \ 774 sizeof(struct tlv) + \ 775 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE) 776 777enum { 778 STA_REC_BASIC, 779 STA_REC_RA, 780 STA_REC_RA_CMM_INFO, 781 STA_REC_RA_UPDATE, 782 STA_REC_BF, 783 STA_REC_AMSDU, 784 STA_REC_BA, 785 STA_REC_STATE, 786 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 787 STA_REC_HT, 788 STA_REC_VHT, 789 STA_REC_APPS, 790 STA_REC_KEY, 791 STA_REC_WTBL, 792 STA_REC_HE, 793 STA_REC_HW_AMSDU, 794 STA_REC_WTBL_AADOM, 795 STA_REC_KEY_V2, 796 STA_REC_MURU, 797 STA_REC_MUEDCA, 798 STA_REC_BFEE, 799 STA_REC_PHY = 0x15, 800 STA_REC_HE_6G = 0x17, 801 STA_REC_HE_V2 = 0x19, 802 STA_REC_EHT = 0x22, 803 STA_REC_HDRT = 0x28, 804 STA_REC_HDR_TRANS = 0x2B, 805 STA_REC_MAX_NUM 806}; 807 808enum { 809 WTBL_GENERIC, 810 WTBL_RX, 811 WTBL_HT, 812 WTBL_VHT, 813 WTBL_PEER_PS, /* not used */ 814 WTBL_TX_PS, 815 WTBL_HDR_TRANS, 816 WTBL_SEC_KEY, 817 WTBL_BA, 818 WTBL_RDG, /* obsoleted */ 819 WTBL_PROTECT, /* not used */ 820 WTBL_CLEAR, /* not used */ 821 WTBL_BF, 822 WTBL_SMPS, 823 WTBL_RAW_DATA, /* debug only */ 824 WTBL_PN, 825 WTBL_SPE, 826 WTBL_MAX_NUM 827}; 828 829#define STA_TYPE_STA BIT(0) 830#define STA_TYPE_AP BIT(1) 831#define STA_TYPE_ADHOC BIT(2) 832#define STA_TYPE_WDS BIT(4) 833#define STA_TYPE_BC BIT(5) 834 835#define NETWORK_INFRA BIT(16) 836#define NETWORK_P2P BIT(17) 837#define NETWORK_IBSS BIT(18) 838#define NETWORK_WDS BIT(21) 839 840#define SCAN_FUNC_RANDOM_MAC BIT(0) 841#define SCAN_FUNC_SPLIT_SCAN BIT(5) 842 843#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 844#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 845#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 846#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 847#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 848#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 849#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 850 851#define CONN_STATE_DISCONNECT 0 852#define CONN_STATE_CONNECT 1 853#define CONN_STATE_PORT_SECURE 2 854 855/* HE MAC */ 856#define STA_REC_HE_CAP_HTC BIT(0) 857#define STA_REC_HE_CAP_BQR BIT(1) 858#define STA_REC_HE_CAP_BSR BIT(2) 859#define STA_REC_HE_CAP_OM BIT(3) 860#define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 861/* HE PHY */ 862#define STA_REC_HE_CAP_DUAL_BAND BIT(5) 863#define STA_REC_HE_CAP_LDPC BIT(6) 864#define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 865#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 866/* STBC */ 867#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 868#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 869#define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 870#define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 871/* GI */ 872#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 873#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 874#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 875#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 876#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 877/* 242 TONE */ 878#define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 879#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 880#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 881 882#define PHY_MODE_A BIT(0) 883#define PHY_MODE_B BIT(1) 884#define PHY_MODE_G BIT(2) 885#define PHY_MODE_GN BIT(3) 886#define PHY_MODE_AN BIT(4) 887#define PHY_MODE_AC BIT(5) 888#define PHY_MODE_AX_24G BIT(6) 889#define PHY_MODE_AX_5G BIT(7) 890 891#define PHY_MODE_AX_6G BIT(0) /* phymode_ext */ 892#define PHY_MODE_BE_24G BIT(1) 893#define PHY_MODE_BE_5G BIT(2) 894#define PHY_MODE_BE_6G BIT(3) 895 896#define MODE_CCK BIT(0) 897#define MODE_OFDM BIT(1) 898#define MODE_HT BIT(2) 899#define MODE_VHT BIT(3) 900#define MODE_HE BIT(4) 901#define MODE_EHT BIT(5) 902 903#define STA_CAP_WMM BIT(0) 904#define STA_CAP_SGI_20 BIT(4) 905#define STA_CAP_SGI_40 BIT(5) 906#define STA_CAP_TX_STBC BIT(6) 907#define STA_CAP_RX_STBC BIT(7) 908#define STA_CAP_VHT_SGI_80 BIT(16) 909#define STA_CAP_VHT_SGI_160 BIT(17) 910#define STA_CAP_VHT_TX_STBC BIT(18) 911#define STA_CAP_VHT_RX_STBC BIT(19) 912#define STA_CAP_VHT_LDPC BIT(23) 913#define STA_CAP_LDPC BIT(24) 914#define STA_CAP_HT BIT(26) 915#define STA_CAP_VHT BIT(27) 916#define STA_CAP_HE BIT(28) 917 918enum { 919 PHY_TYPE_HR_DSSS_INDEX = 0, 920 PHY_TYPE_ERP_INDEX, 921 PHY_TYPE_ERP_P2P_INDEX, 922 PHY_TYPE_OFDM_INDEX, 923 PHY_TYPE_HT_INDEX, 924 PHY_TYPE_VHT_INDEX, 925 PHY_TYPE_HE_INDEX, 926 PHY_TYPE_INDEX_NUM 927}; 928 929#define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 930#define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 931#define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 932#define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 933#define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 934#define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 935 936#define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 937#define MT_WTBL_RATE_MCS GENMASK(5, 0) 938#define MT_WTBL_RATE_NSS GENMASK(12, 10) 939#define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 940#define MT_WTBL_RATE_GI GENMASK(3, 0) 941 942#define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5) 943#define MT_WTBL_W5_SHORT_GI_20 BIT(8) 944#define MT_WTBL_W5_SHORT_GI_40 BIT(9) 945#define MT_WTBL_W5_SHORT_GI_80 BIT(10) 946#define MT_WTBL_W5_SHORT_GI_160 BIT(11) 947#define MT_WTBL_W5_BW_CAP GENMASK(13, 12) 948#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) 949#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) 950#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) 951 952enum { 953 WTBL_RESET_AND_SET = 1, 954 WTBL_SET, 955 WTBL_QUERY, 956 WTBL_RESET_ALL 957}; 958 959enum { 960 MT_BA_TYPE_INVALID, 961 MT_BA_TYPE_ORIGINATOR, 962 MT_BA_TYPE_RECIPIENT 963}; 964 965enum { 966 RST_BA_MAC_TID_MATCH, 967 RST_BA_MAC_MATCH, 968 RST_BA_NO_MATCH 969}; 970 971enum { 972 DEV_INFO_ACTIVE, 973 DEV_INFO_MAX_NUM 974}; 975 976/* event table */ 977enum { 978 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 979 MCU_EVENT_FW_START = 0x01, 980 MCU_EVENT_GENERIC = 0x01, 981 MCU_EVENT_ACCESS_REG = 0x02, 982 MCU_EVENT_MT_PATCH_SEM = 0x04, 983 MCU_EVENT_REG_ACCESS = 0x05, 984 MCU_EVENT_LP_INFO = 0x07, 985 MCU_EVENT_SCAN_DONE = 0x0d, 986 MCU_EVENT_TX_DONE = 0x0f, 987 MCU_EVENT_ROC = 0x10, 988 MCU_EVENT_BSS_ABSENCE = 0x11, 989 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 990 MCU_EVENT_CH_PRIVILEGE = 0x18, 991 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 992 MCU_EVENT_DBG_MSG = 0x27, 993 MCU_EVENT_TXPWR = 0xd0, 994 MCU_EVENT_EXT = 0xed, 995 MCU_EVENT_RESTART_DL = 0xef, 996 MCU_EVENT_COREDUMP = 0xf0, 997}; 998 999/* ext event table */ 1000enum { 1001 MCU_EXT_EVENT_PS_SYNC = 0x5, 1002 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 1003 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 1004 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 1005 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 1006 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 1007 MCU_EXT_EVENT_WA_TX_STAT = 0x74, 1008 MCU_EXT_EVENT_BCC_NOTIFY = 0x75, 1009 MCU_EXT_EVENT_MURU_CTRL = 0x9f, 1010}; 1011 1012/* unified event table */ 1013enum { 1014 MCU_UNI_EVENT_RESULT = 0x01, 1015 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04, 1016 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09, 1017 MCU_UNI_EVENT_RDD_REPORT = 0x11, 1018}; 1019 1020#define MCU_UNI_CMD_EVENT BIT(1) 1021#define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2) 1022 1023enum { 1024 MCU_Q_QUERY, 1025 MCU_Q_SET, 1026 MCU_Q_RESERVED, 1027 MCU_Q_NA 1028}; 1029 1030enum { 1031 MCU_S2D_H2N, 1032 MCU_S2D_C2N, 1033 MCU_S2D_H2C, 1034 MCU_S2D_H2CN 1035}; 1036 1037enum { 1038 PATCH_NOT_DL_SEM_FAIL, 1039 PATCH_IS_DL, 1040 PATCH_NOT_DL_SEM_SUCCESS, 1041 PATCH_REL_SEM_SUCCESS 1042}; 1043 1044enum { 1045 FW_STATE_INITIAL, 1046 FW_STATE_FW_DOWNLOAD, 1047 FW_STATE_NORMAL_OPERATION, 1048 FW_STATE_NORMAL_TRX, 1049 FW_STATE_RDY = 7 1050}; 1051 1052enum { 1053 CH_SWITCH_NORMAL = 0, 1054 CH_SWITCH_SCAN = 3, 1055 CH_SWITCH_MCC = 4, 1056 CH_SWITCH_DFS = 5, 1057 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1058 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1059 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1060 CH_SWITCH_SCAN_BYPASS_DPD = 9 1061}; 1062 1063enum { 1064 THERMAL_SENSOR_TEMP_QUERY, 1065 THERMAL_SENSOR_MANUAL_CTRL, 1066 THERMAL_SENSOR_INFO_QUERY, 1067 THERMAL_SENSOR_TASK_CTRL, 1068}; 1069 1070enum mcu_cipher_type { 1071 MCU_CIPHER_NONE = 0, 1072 MCU_CIPHER_WEP40, 1073 MCU_CIPHER_WEP104, 1074 MCU_CIPHER_WEP128, 1075 MCU_CIPHER_TKIP, 1076 MCU_CIPHER_AES_CCMP, 1077 MCU_CIPHER_CCMP_256, 1078 MCU_CIPHER_GCMP, 1079 MCU_CIPHER_GCMP_256, 1080 MCU_CIPHER_WAPI, 1081 MCU_CIPHER_BIP_CMAC_128, 1082}; 1083 1084enum { 1085 EE_MODE_EFUSE, 1086 EE_MODE_BUFFER, 1087}; 1088 1089enum { 1090 EE_FORMAT_BIN, 1091 EE_FORMAT_WHOLE, 1092 EE_FORMAT_MULTIPLE, 1093}; 1094 1095enum { 1096 MCU_PHY_STATE_TX_RATE, 1097 MCU_PHY_STATE_RX_RATE, 1098 MCU_PHY_STATE_RSSI, 1099 MCU_PHY_STATE_CONTENTION_RX_RATE, 1100 MCU_PHY_STATE_OFDMLQ_CNINFO, 1101}; 1102 1103#define MCU_CMD_ACK BIT(0) 1104#define MCU_CMD_UNI BIT(1) 1105#define MCU_CMD_SET BIT(2) 1106 1107#define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \ 1108 MCU_CMD_SET) 1109#define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI) 1110 1111#define __MCU_CMD_FIELD_ID GENMASK(7, 0) 1112#define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8) 1113#define __MCU_CMD_FIELD_QUERY BIT(16) 1114#define __MCU_CMD_FIELD_UNI BIT(17) 1115#define __MCU_CMD_FIELD_CE BIT(18) 1116#define __MCU_CMD_FIELD_WA BIT(19) 1117#define __MCU_CMD_FIELD_WM BIT(20) 1118 1119#define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1120 MCU_CMD_##_t) 1121#define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \ 1122 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1123 MCU_EXT_CMD_##_t)) 1124#define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1125#define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \ 1126 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1127 MCU_UNI_CMD_##_t)) 1128#define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \ 1129 FIELD_PREP(__MCU_CMD_FIELD_ID, \ 1130 MCU_CE_CMD_##_t)) 1131#define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY) 1132 1133#define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA) 1134#define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA) 1135#define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \ 1136 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \ 1137 MCU_WA_PARAM_CMD_##_t)) 1138 1139#define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1140 __MCU_CMD_FIELD_WM) 1141#define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \ 1142 __MCU_CMD_FIELD_QUERY | \ 1143 __MCU_CMD_FIELD_WM) 1144#define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \ 1145 __MCU_CMD_FIELD_WA) 1146#define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \ 1147 __MCU_CMD_FIELD_WA) 1148 1149enum { 1150 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 1151 MCU_EXT_CMD_RF_REG_ACCESS = 0x02, 1152 MCU_EXT_CMD_RF_TEST = 0x04, 1153 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 1154 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 1155 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 1156 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 1157 MCU_EXT_CMD_TXBF_ACTION = 0x1e, 1158 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 1159 MCU_EXT_CMD_THERMAL_PROT = 0x23, 1160 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 1161 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 1162 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 1163 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 1164 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 1165 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 1166 MCU_EXT_CMD_SET_DRR_CTRL = 0x36, 1167 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 1168 MCU_EXT_CMD_ATE_CTRL = 0x3d, 1169 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 1170 MCU_EXT_CMD_DBDC_CTRL = 0x45, 1171 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 1172 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 1173 MCU_EXT_CMD_MUAR_UPDATE = 0x48, 1174 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 1175 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a, 1176 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 1177 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f, 1178 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 1179 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 1180 MCU_EXT_CMD_GET_MIB_INFO = 0x5a, 1181 MCU_EXT_CMD_TXDPD_CAL = 0x60, 1182 MCU_EXT_CMD_CAL_CACHE = 0x67, 1183 MCU_EXT_CMD_RED_ENABLE = 0x68, 1184 MCU_EXT_CMD_SET_RADAR_TH = 0x7c, 1185 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 1186 MCU_EXT_CMD_MWDS_SUPPORT = 0x80, 1187 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81, 1188 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94, 1189 MCU_EXT_CMD_FW_DBG_CTRL = 0x95, 1190 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a, 1191 MCU_EXT_CMD_SET_RDD_TH = 0x9d, 1192 MCU_EXT_CMD_MURU_CTRL = 0x9f, 1193 MCU_EXT_CMD_SET_SPR = 0xa8, 1194 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab, 1195 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac, 1196 MCU_EXT_CMD_PHY_STAT_INFO = 0xad, 1197}; 1198 1199enum { 1200 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01, 1201 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02, 1202 MCU_UNI_CMD_STA_REC_UPDATE = 0x03, 1203 MCU_UNI_CMD_EDCA_UPDATE = 0x04, 1204 MCU_UNI_CMD_SUSPEND = 0x05, 1205 MCU_UNI_CMD_OFFLOAD = 0x06, 1206 MCU_UNI_CMD_HIF_CTRL = 0x07, 1207 MCU_UNI_CMD_BAND_CONFIG = 0x08, 1208 MCU_UNI_CMD_REPT_MUAR = 0x09, 1209 MCU_UNI_CMD_WSYS_CONFIG = 0x0b, 1210 MCU_UNI_CMD_REG_ACCESS = 0x0d, 1211 MCU_UNI_CMD_CHIP_CONFIG = 0x0e, 1212 MCU_UNI_CMD_POWER_CTRL = 0x0f, 1213 MCU_UNI_CMD_RX_HDR_TRANS = 0x12, 1214 MCU_UNI_CMD_SER = 0x13, 1215 MCU_UNI_CMD_TWT = 0x14, 1216 MCU_UNI_CMD_RDD_CTRL = 0x19, 1217 MCU_UNI_CMD_GET_MIB_INFO = 0x22, 1218 MCU_UNI_CMD_SNIFFER = 0x24, 1219 MCU_UNI_CMD_SR = 0x25, 1220 MCU_UNI_CMD_ROC = 0x27, 1221 MCU_UNI_CMD_TXPOWER = 0x2b, 1222 MCU_UNI_CMD_EFUSE_CTRL = 0x2d, 1223 MCU_UNI_CMD_RA = 0x2f, 1224 MCU_UNI_CMD_MURU = 0x31, 1225 MCU_UNI_CMD_BF = 0x33, 1226 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34, 1227 MCU_UNI_CMD_THERMAL = 0x35, 1228 MCU_UNI_CMD_VOW = 0x37, 1229 MCU_UNI_CMD_RRO = 0x57, 1230 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58, 1231 MCU_UNI_CMD_ASSERT_DUMP = 0x6f, 1232}; 1233 1234enum { 1235 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01, 1236 MCU_CMD_FW_START_REQ = 0x02, 1237 MCU_CMD_INIT_ACCESS_REG = 0x3, 1238 MCU_CMD_NIC_POWER_CTRL = 0x4, 1239 MCU_CMD_PATCH_START_REQ = 0x05, 1240 MCU_CMD_PATCH_FINISH_REQ = 0x07, 1241 MCU_CMD_PATCH_SEM_CONTROL = 0x10, 1242 MCU_CMD_WA_PARAM = 0xc4, 1243 MCU_CMD_EXT_CID = 0xed, 1244 MCU_CMD_FW_SCATTER = 0xee, 1245 MCU_CMD_RESTART_DL_REQ = 0xef, 1246}; 1247 1248/* offload mcu commands */ 1249enum { 1250 MCU_CE_CMD_TEST_CTRL = 0x01, 1251 MCU_CE_CMD_START_HW_SCAN = 0x03, 1252 MCU_CE_CMD_SET_PS_PROFILE = 0x05, 1253 MCU_CE_CMD_SET_RX_FILTER = 0x0a, 1254 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f, 1255 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16, 1256 MCU_CE_CMD_SET_BSS_ABORT = 0x17, 1257 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b, 1258 MCU_CE_CMD_SET_ROC = 0x1c, 1259 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d, 1260 MCU_CE_CMD_SET_P2P_OPPPS = 0x33, 1261 MCU_CE_CMD_SET_CLC = 0x5c, 1262 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d, 1263 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61, 1264 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62, 1265 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a, 1266 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0, 1267 MCU_CE_CMD_REG_WRITE = 0xc0, 1268 MCU_CE_CMD_REG_READ = 0xc0, 1269 MCU_CE_CMD_CHIP_CONFIG = 0xca, 1270 MCU_CE_CMD_FWLOG_2_HOST = 0xc5, 1271 MCU_CE_CMD_GET_WTBL = 0xcd, 1272 MCU_CE_CMD_GET_TXPWR = 0xd0, 1273}; 1274 1275enum { 1276 PATCH_SEM_RELEASE, 1277 PATCH_SEM_GET 1278}; 1279 1280enum { 1281 UNI_BSS_INFO_BASIC = 0, 1282 UNI_BSS_INFO_RA = 1, 1283 UNI_BSS_INFO_RLM = 2, 1284 UNI_BSS_INFO_BSS_COLOR = 4, 1285 UNI_BSS_INFO_HE_BASIC = 5, 1286 UNI_BSS_INFO_BCN_CONTENT = 7, 1287 UNI_BSS_INFO_BCN_CSA = 8, 1288 UNI_BSS_INFO_BCN_BCC = 9, 1289 UNI_BSS_INFO_BCN_MBSSID = 10, 1290 UNI_BSS_INFO_RATE = 11, 1291 UNI_BSS_INFO_QBSS = 15, 1292 UNI_BSS_INFO_SEC = 16, 1293 UNI_BSS_INFO_TXCMD = 18, 1294 UNI_BSS_INFO_UAPSD = 19, 1295 UNI_BSS_INFO_PS = 21, 1296 UNI_BSS_INFO_BCNFT = 22, 1297 UNI_BSS_INFO_IFS_TIME = 23, 1298 UNI_BSS_INFO_OFFLOAD = 25, 1299 UNI_BSS_INFO_MLD = 26, 1300}; 1301 1302enum { 1303 UNI_OFFLOAD_OFFLOAD_ARP, 1304 UNI_OFFLOAD_OFFLOAD_ND, 1305 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 1306 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 1307}; 1308 1309enum { 1310 MT_NIC_CAP_TX_RESOURCE, 1311 MT_NIC_CAP_TX_EFUSE_ADDR, 1312 MT_NIC_CAP_COEX, 1313 MT_NIC_CAP_SINGLE_SKU, 1314 MT_NIC_CAP_CSUM_OFFLOAD, 1315 MT_NIC_CAP_HW_VER, 1316 MT_NIC_CAP_SW_VER, 1317 MT_NIC_CAP_MAC_ADDR, 1318 MT_NIC_CAP_PHY, 1319 MT_NIC_CAP_MAC, 1320 MT_NIC_CAP_FRAME_BUF, 1321 MT_NIC_CAP_BEAM_FORM, 1322 MT_NIC_CAP_LOCATION, 1323 MT_NIC_CAP_MUMIMO, 1324 MT_NIC_CAP_BUFFER_MODE_INFO, 1325 MT_NIC_CAP_HW_ADIE_VERSION = 0x14, 1326 MT_NIC_CAP_ANTSWP = 0x16, 1327 MT_NIC_CAP_WFDMA_REALLOC, 1328 MT_NIC_CAP_6G, 1329}; 1330 1331#define UNI_WOW_DETECT_TYPE_MAGIC BIT(0) 1332#define UNI_WOW_DETECT_TYPE_ANY BIT(1) 1333#define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2) 1334#define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3) 1335#define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4) 1336#define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5) 1337#define UNI_WOW_DETECT_TYPE_BITMAP BIT(6) 1338 1339enum { 1340 UNI_SUSPEND_MODE_SETTING, 1341 UNI_SUSPEND_WOW_CTRL, 1342 UNI_SUSPEND_WOW_GPIO_PARAM, 1343 UNI_SUSPEND_WOW_WAKEUP_PORT, 1344 UNI_SUSPEND_WOW_PATTERN, 1345}; 1346 1347enum { 1348 WOW_USB = 1, 1349 WOW_PCIE = 2, 1350 WOW_GPIO = 3, 1351}; 1352 1353struct mt76_connac_bss_basic_tlv { 1354 __le16 tag; 1355 __le16 len; 1356 u8 active; 1357 u8 omac_idx; 1358 u8 hw_bss_idx; 1359 u8 band_idx; 1360 __le32 conn_type; 1361 u8 conn_state; 1362 u8 wmm_idx; 1363 u8 bssid[ETH_ALEN]; 1364 __le16 bmc_tx_wlan_idx; 1365 __le16 bcn_interval; 1366 u8 dtim_period; 1367 u8 phymode; /* bit(0): A 1368 * bit(1): B 1369 * bit(2): G 1370 * bit(3): GN 1371 * bit(4): AN 1372 * bit(5): AC 1373 * bit(6): AX2 1374 * bit(7): AX5 1375 * bit(8): AX6 1376 */ 1377 __le16 sta_idx; 1378 __le16 nonht_basic_phy; 1379 u8 phymode_ext; /* bit(0) AX_6G */ 1380 u8 pad[1]; 1381} __packed; 1382 1383struct mt76_connac_bss_qos_tlv { 1384 __le16 tag; 1385 __le16 len; 1386 u8 qos; 1387 u8 pad[3]; 1388} __packed; 1389 1390struct mt76_connac_beacon_loss_event { 1391 u8 bss_idx; 1392 u8 reason; 1393 u8 pad[2]; 1394} __packed; 1395 1396struct mt76_connac_mcu_bss_event { 1397 u8 bss_idx; 1398 u8 is_absent; 1399 u8 free_quota; 1400 u8 pad; 1401} __packed; 1402 1403struct mt76_connac_mcu_scan_ssid { 1404 __le32 ssid_len; 1405 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1406} __packed; 1407 1408struct mt76_connac_mcu_scan_channel { 1409 u8 band; /* 1: 2.4GHz 1410 * 2: 5.0GHz 1411 * Others: Reserved 1412 */ 1413 u8 channel_num; 1414} __packed; 1415 1416struct mt76_connac_mcu_scan_match { 1417 __le32 rssi_th; 1418 u8 ssid[IEEE80211_MAX_SSID_LEN]; 1419 u8 ssid_len; 1420 u8 rsv[3]; 1421} __packed; 1422 1423struct mt76_connac_hw_scan_req { 1424 u8 seq_num; 1425 u8 bss_idx; 1426 u8 scan_type; /* 0: PASSIVE SCAN 1427 * 1: ACTIVE SCAN 1428 */ 1429 u8 ssid_type; /* BIT(0) wildcard SSID 1430 * BIT(1) P2P wildcard SSID 1431 * BIT(2) specified SSID + wildcard SSID 1432 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 1433 */ 1434 u8 ssids_num; 1435 u8 probe_req_num; /* Number of probe request for each SSID */ 1436 u8 scan_func; /* BIT(0) Enable random MAC scan 1437 * BIT(1) Disable DBDC scan type 1~3. 1438 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 1439 */ 1440 u8 version; /* 0: Not support fields after ies. 1441 * 1: Support fields after ies. 1442 */ 1443 struct mt76_connac_mcu_scan_ssid ssids[4]; 1444 __le16 probe_delay_time; 1445 __le16 channel_dwell_time; /* channel Dwell interval */ 1446 __le16 timeout_value; 1447 u8 channel_type; /* 0: Full channels 1448 * 1: Only 2.4GHz channels 1449 * 2: Only 5GHz channels 1450 * 3: P2P social channel only (channel #1, #6 and #11) 1451 * 4: Specified channels 1452 * Others: Reserved 1453 */ 1454 u8 channels_num; /* valid when channel_type is 4 */ 1455 /* valid when channels_num is set */ 1456 struct mt76_connac_mcu_scan_channel channels[32]; 1457 __le16 ies_len; 1458 u8 ies[MT76_CONNAC_SCAN_IE_LEN]; 1459 /* following fields are valid if version > 0 */ 1460 u8 ext_channels_num; 1461 u8 ext_ssids_num; 1462 __le16 channel_min_dwell_time; 1463 struct mt76_connac_mcu_scan_channel ext_channels[32]; 1464 struct mt76_connac_mcu_scan_ssid ext_ssids[6]; 1465 u8 bssid[ETH_ALEN]; 1466 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 1467 u8 pad[63]; 1468 u8 ssid_type_ext; 1469} __packed; 1470 1471#define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 1472 1473struct mt76_connac_hw_scan_done { 1474 u8 seq_num; 1475 u8 sparse_channel_num; 1476 struct mt76_connac_mcu_scan_channel sparse_channel; 1477 u8 complete_channel_num; 1478 u8 current_state; 1479 u8 version; 1480 u8 pad; 1481 __le32 beacon_scan_num; 1482 u8 pno_enabled; 1483 u8 pad2[3]; 1484 u8 sparse_channel_valid_num; 1485 u8 pad3[3]; 1486 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1487 /* idle format for channel_idle_time 1488 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 1489 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 1490 * 2: dwell time (16us) 1491 */ 1492 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1493 /* beacon and probe response count */ 1494 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1495 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 1496 __le32 beacon_2g_num; 1497 __le32 beacon_5g_num; 1498} __packed; 1499 1500struct mt76_connac_sched_scan_req { 1501 u8 version; 1502 u8 seq_num; 1503 u8 stop_on_match; 1504 u8 ssids_num; 1505 u8 match_num; 1506 u8 pad; 1507 __le16 ie_len; 1508 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID]; 1509 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH]; 1510 u8 channel_type; 1511 u8 channels_num; 1512 u8 intervals_num; 1513 u8 scan_func; /* MT7663: BIT(0) eable random mac address */ 1514 struct mt76_connac_mcu_scan_channel channels[64]; 1515 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL]; 1516 union { 1517 struct { 1518 u8 random_mac[ETH_ALEN]; 1519 u8 pad2[58]; 1520 } mt7663; 1521 struct { 1522 u8 bss_idx; 1523 u8 pad1[3]; 1524 __le32 delay; 1525 u8 pad2[12]; 1526 u8 random_mac[ETH_ALEN]; 1527 u8 pad3[38]; 1528 } mt7921; 1529 }; 1530} __packed; 1531 1532struct mt76_connac_sched_scan_done { 1533 u8 seq_num; 1534 u8 status; /* 0: ssid found */ 1535 __le16 pad; 1536} __packed; 1537 1538struct bss_info_uni_bss_color { 1539 __le16 tag; 1540 __le16 len; 1541 u8 enable; 1542 u8 bss_color; 1543 u8 rsv[2]; 1544} __packed; 1545 1546struct bss_info_uni_he { 1547 __le16 tag; 1548 __le16 len; 1549 __le16 he_rts_thres; 1550 u8 he_pe_duration; 1551 u8 su_disable; 1552 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 1553 u8 rsv[2]; 1554} __packed; 1555 1556struct mt76_connac_gtk_rekey_tlv { 1557 __le16 tag; 1558 __le16 len; 1559 u8 kek[NL80211_KEK_LEN]; 1560 u8 kck[NL80211_KCK_LEN]; 1561 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 1562 u8 rekey_mode; /* 0: rekey offload enable 1563 * 1: rekey offload disable 1564 * 2: rekey update 1565 */ 1566 u8 keyid; 1567 u8 option; /* 1: rekey data update without enabling offload */ 1568 u8 pad[1]; 1569 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 1570 __le32 pairwise_cipher; 1571 __le32 group_cipher; 1572 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 1573 __le32 mgmt_group_cipher; 1574 u8 reserverd[4]; 1575} __packed; 1576 1577#define MT76_CONNAC_WOW_MASK_MAX_LEN 16 1578#define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128 1579 1580struct mt76_connac_wow_pattern_tlv { 1581 __le16 tag; 1582 __le16 len; 1583 u8 index; /* pattern index */ 1584 u8 enable; /* 0: disable 1585 * 1: enable 1586 */ 1587 u8 data_len; /* pattern length */ 1588 u8 pad; 1589 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN]; 1590 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN]; 1591 u8 rsv[4]; 1592} __packed; 1593 1594struct mt76_connac_wow_ctrl_tlv { 1595 __le16 tag; 1596 __le16 len; 1597 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 1598 * 0x2: PM_WOWLAN_REQ_STOP 1599 * 0x3: PM_WOWLAN_PARAM_CLEAR 1600 */ 1601 u8 trigger; /* 0: NONE 1602 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 1603 * BIT(1): NL80211_WOWLAN_TRIG_ANY 1604 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 1605 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 1606 * BIT(4): BEACON_LOST 1607 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 1608 */ 1609 u8 wakeup_hif; /* 0x0: HIF_SDIO 1610 * 0x1: HIF_USB 1611 * 0x2: HIF_PCIE 1612 * 0x3: HIF_GPIO 1613 */ 1614 u8 pad; 1615 u8 rsv[4]; 1616} __packed; 1617 1618struct mt76_connac_wow_gpio_param_tlv { 1619 __le16 tag; 1620 __le16 len; 1621 u8 gpio_pin; 1622 u8 trigger_lvl; 1623 u8 pad[2]; 1624 __le32 gpio_interval; 1625 u8 rsv[4]; 1626} __packed; 1627 1628struct mt76_connac_arpns_tlv { 1629 __le16 tag; 1630 __le16 len; 1631 u8 mode; 1632 u8 ips_num; 1633 u8 option; 1634 u8 pad[1]; 1635} __packed; 1636 1637struct mt76_connac_suspend_tlv { 1638 __le16 tag; 1639 __le16 len; 1640 u8 enable; /* 0: suspend mode disabled 1641 * 1: suspend mode enabled 1642 */ 1643 u8 mdtim; /* LP parameter */ 1644 u8 wow_suspend; /* 0: update by origin policy 1645 * 1: update by wow dtim 1646 */ 1647 u8 pad[5]; 1648} __packed; 1649 1650enum mt76_sta_info_state { 1651 MT76_STA_INFO_STATE_NONE, 1652 MT76_STA_INFO_STATE_AUTH, 1653 MT76_STA_INFO_STATE_ASSOC 1654}; 1655 1656struct mt76_sta_cmd_info { 1657 struct ieee80211_sta *sta; 1658 struct mt76_wcid *wcid; 1659 1660 struct ieee80211_vif *vif; 1661 1662 bool offload_fw; 1663 bool enable; 1664 bool newly; 1665 int cmd; 1666 u8 rcpi; 1667 u8 state; 1668}; 1669 1670#define MT_SKU_POWER_LIMIT 161 1671 1672struct mt76_connac_sku_tlv { 1673 u8 channel; 1674 s8 pwr_limit[MT_SKU_POWER_LIMIT]; 1675} __packed; 1676 1677struct mt76_connac_tx_power_limit_tlv { 1678 /* DW0 - common info*/ 1679 u8 ver; 1680 u8 pad0; 1681 __le16 len; 1682 /* DW1 - cmd hint */ 1683 u8 n_chan; /* # channel */ 1684 u8 band; /* 2.4GHz - 5GHz - 6GHz */ 1685 u8 last_msg; 1686 u8 pad1; 1687 /* DW3 */ 1688 u8 alpha2[4]; /* regulatory_request.alpha2 */ 1689 u8 pad2[32]; 1690} __packed; 1691 1692struct mt76_connac_config { 1693 __le16 id; 1694 u8 type; 1695 u8 resp_type; 1696 __le16 data_size; 1697 __le16 resv; 1698 u8 data[320]; 1699} __packed; 1700 1701struct mt76_connac_mcu_uni_event { 1702 u8 cid; 1703 u8 pad[3]; 1704 __le32 status; /* 0: success, others: fail */ 1705} __packed; 1706 1707struct mt76_connac_mcu_reg_event { 1708 __le32 reg; 1709 __le32 val; 1710} __packed; 1711 1712static inline enum mcu_cipher_type 1713mt76_connac_mcu_get_cipher(int cipher) 1714{ 1715 switch (cipher) { 1716 case WLAN_CIPHER_SUITE_WEP40: 1717 return MCU_CIPHER_WEP40; 1718 case WLAN_CIPHER_SUITE_WEP104: 1719 return MCU_CIPHER_WEP104; 1720 case WLAN_CIPHER_SUITE_TKIP: 1721 return MCU_CIPHER_TKIP; 1722 case WLAN_CIPHER_SUITE_AES_CMAC: 1723 return MCU_CIPHER_BIP_CMAC_128; 1724 case WLAN_CIPHER_SUITE_CCMP: 1725 return MCU_CIPHER_AES_CCMP; 1726 case WLAN_CIPHER_SUITE_CCMP_256: 1727 return MCU_CIPHER_CCMP_256; 1728 case WLAN_CIPHER_SUITE_GCMP: 1729 return MCU_CIPHER_GCMP; 1730 case WLAN_CIPHER_SUITE_GCMP_256: 1731 return MCU_CIPHER_GCMP_256; 1732 case WLAN_CIPHER_SUITE_SMS4: 1733 return MCU_CIPHER_WAPI; 1734 default: 1735 return MCU_CIPHER_NONE; 1736 } 1737} 1738 1739static inline u32 1740mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa) 1741{ 1742 u32 ret = 0; 1743 1744 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ? 1745 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0; 1746 if (is_mt7921(dev)) 1747 ret |= feature_set & FW_FEATURE_ENCRY_MODE ? 1748 DL_CONFIG_ENCRY_MODE_SEL : 0; 1749 ret |= FIELD_PREP(DL_MODE_KEY_IDX, 1750 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set)); 1751 ret |= DL_MODE_NEED_RSP; 1752 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0; 1753 1754 return ret; 1755} 1756 1757#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id) 1758#define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id) 1759 1760static inline void 1761mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid, 1762 u8 *wlan_idx_lo, u8 *wlan_idx_hi) 1763{ 1764 *wlan_idx_hi = 0; 1765 1766 if (!is_connac_v1(dev)) { 1767 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0; 1768 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0; 1769 } else { 1770 *wlan_idx_lo = wcid ? wcid->idx : 0; 1771 } 1772} 1773 1774struct sk_buff * 1775__mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1776 struct mt76_wcid *wcid, int len); 1777static inline struct sk_buff * 1778mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif, 1779 struct mt76_wcid *wcid) 1780{ 1781 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid, 1782 MT76_CONNAC_STA_UPDATE_MAX_SIZE); 1783} 1784 1785struct wtbl_req_hdr * 1786mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid, 1787 int cmd, void *sta_wtbl, struct sk_buff **skb); 1788struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag, 1789 int len, void *sta_ntlv, 1790 void *sta_wtbl); 1791static inline struct tlv * 1792mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len) 1793{ 1794 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL); 1795} 1796 1797int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy); 1798int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif); 1799void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1800 struct ieee80211_vif *vif, 1801 struct ieee80211_sta *sta, bool enable, 1802 bool newly); 1803void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1804 struct ieee80211_vif *vif, 1805 struct ieee80211_sta *sta, void *sta_wtbl, 1806 void *wtbl_tlv); 1807void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb, 1808 struct ieee80211_vif *vif, 1809 struct mt76_wcid *wcid, 1810 void *sta_wtbl, void *wtbl_tlv); 1811int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev, 1812 struct ieee80211_vif *vif, 1813 struct mt76_wcid *wcid, int cmd); 1814int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev, 1815 struct ieee80211_vif *vif, 1816 struct ieee80211_sta *sta); 1817void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb, 1818 struct ieee80211_sta *sta, 1819 struct ieee80211_vif *vif, 1820 u8 rcpi, u8 state); 1821void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1822 struct ieee80211_sta *sta, void *sta_wtbl, 1823 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc); 1824void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb, 1825 struct ieee80211_ampdu_params *params, 1826 bool enable, bool tx, void *sta_wtbl, 1827 void *wtbl_tlv); 1828void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb, 1829 struct ieee80211_ampdu_params *params, 1830 bool enable, bool tx); 1831int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy, 1832 struct ieee80211_vif *vif, 1833 struct mt76_wcid *wcid, 1834 bool enable); 1835int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, 1836 struct ieee80211_ampdu_params *params, 1837 int cmd, bool enable, bool tx); 1838int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy, 1839 struct mt76_vif *vif, 1840 struct ieee80211_chanctx_conf *ctx); 1841int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy, 1842 struct ieee80211_vif *vif, 1843 struct mt76_wcid *wcid, 1844 bool enable, 1845 struct ieee80211_chanctx_conf *ctx); 1846int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy, 1847 struct mt76_sta_cmd_info *info); 1848void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac, 1849 struct ieee80211_vif *vif); 1850int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band); 1851int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable, 1852 bool hdr_trans); 1853int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len, 1854 u32 mode); 1855int mt76_connac_mcu_start_patch(struct mt76_dev *dev); 1856int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get); 1857int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option); 1858int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy); 1859 1860int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif, 1861 struct ieee80211_scan_request *scan_req); 1862int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy, 1863 struct ieee80211_vif *vif); 1864int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy, 1865 struct ieee80211_vif *vif, 1866 struct cfg80211_sched_scan_request *sreq); 1867int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy, 1868 struct ieee80211_vif *vif, 1869 bool enable); 1870int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev, 1871 struct mt76_vif *vif, 1872 struct ieee80211_bss_conf *info); 1873int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw, 1874 struct ieee80211_vif *vif, 1875 struct cfg80211_gtk_rekey_data *key); 1876int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend); 1877void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac, 1878 struct ieee80211_vif *vif); 1879int mt76_connac_sta_state_dp(struct mt76_dev *dev, 1880 enum ieee80211_sta_state old_state, 1881 enum ieee80211_sta_state new_state); 1882int mt76_connac_mcu_chip_config(struct mt76_dev *dev); 1883int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable); 1884void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb, 1885 struct mt76_connac_coredump *coredump); 1886int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy); 1887int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw, 1888 struct ieee80211_vif *vif); 1889u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset); 1890void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val); 1891 1892const struct ieee80211_sta_he_cap * 1893mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 1894const struct ieee80211_sta_eht_cap * 1895mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif); 1896u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif, 1897 enum nl80211_band band, struct ieee80211_sta *sta); 1898u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_vif *vif, 1899 enum nl80211_band band); 1900 1901int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 1902 struct mt76_connac_sta_key_conf *sta_key_conf, 1903 struct ieee80211_key_conf *key, int mcu_cmd, 1904 struct mt76_wcid *wcid, enum set_key_cmd cmd); 1905 1906void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif); 1907void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb, 1908 struct ieee80211_vif *vif); 1909int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb, 1910 struct ieee80211_vif *vif, 1911 struct ieee80211_sta *sta, 1912 struct mt76_phy *phy, u16 wlan_idx, 1913 bool enable); 1914void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif, 1915 struct ieee80211_sta *sta); 1916void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb, 1917 struct ieee80211_sta *sta, 1918 void *sta_wtbl, void *wtbl_tlv); 1919int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter); 1920int mt76_connac_mcu_restart(struct mt76_dev *dev); 1921int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, 1922 u8 rx_sel, u8 val); 1923int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb); 1924int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, 1925 const char *fw_wa); 1926int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); 1927int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb, 1928 int cmd, int *wait_seq); 1929#endif /* __MT76_CONNAC_MCU_H */ 1930