1// SPDX-License-Identifier: ISC 2/* Copyright (C) 2019 MediaTek Inc. 3 * 4 * Author: Roy Luo <royluo@google.com> 5 * Ryder Lee <ryder.lee@mediatek.com> 6 */ 7 8#include <linux/firmware.h> 9#include "mt7615.h" 10#include "mcu.h" 11#include "mac.h" 12#include "eeprom.h" 13 14static bool prefer_offload_fw = true; 15module_param(prefer_offload_fw, bool, 0644); 16MODULE_PARM_DESC(prefer_offload_fw, 17 "Prefer client mode offload firmware (MT7663)"); 18 19struct mt7615_patch_hdr { 20 char build_date[16]; 21 char platform[4]; 22 __be32 hw_sw_ver; 23 __be32 patch_ver; 24 __be16 checksum; 25} __packed; 26 27struct mt7615_fw_trailer { 28 __le32 addr; 29 u8 chip_id; 30 u8 feature_set; 31 u8 eco_code; 32 char fw_ver[10]; 33 char build_date[15]; 34 __le32 len; 35} __packed; 36 37#define FW_V3_COMMON_TAILER_SIZE 36 38#define FW_V3_REGION_TAILER_SIZE 40 39#define FW_START_OVERRIDE BIT(0) 40#define FW_START_DLYCAL BIT(1) 41#define FW_START_WORKING_PDA_CR4 BIT(2) 42 43struct mt7663_fw_buf { 44 __le32 crc; 45 __le32 d_img_size; 46 __le32 block_size; 47 u8 rsv[4]; 48 __le32 img_dest_addr; 49 __le32 img_size; 50 u8 feature_set; 51}; 52 53#define MT7615_PATCH_ADDRESS 0x80000 54#define MT7622_PATCH_ADDRESS 0x9c000 55#define MT7663_PATCH_ADDRESS 0xdc000 56 57#define N9_REGION_NUM 2 58#define CR4_REGION_NUM 1 59 60#define IMG_CRC_LEN 4 61 62void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb, 63 int cmd, int *wait_seq) 64{ 65 int txd_len, mcu_cmd = FIELD_GET(__MCU_CMD_FIELD_ID, cmd); 66 struct mt7615_uni_txd *uni_txd; 67 struct mt7615_mcu_txd *mcu_txd; 68 u8 seq, q_idx, pkt_fmt; 69 __le32 *txd; 70 u32 val; 71 72 /* TODO: make dynamic based on msg type */ 73 dev->mt76.mcu.timeout = 20 * HZ; 74 75 seq = ++dev->mt76.mcu.msg_seq & 0xf; 76 if (!seq) 77 seq = ++dev->mt76.mcu.msg_seq & 0xf; 78 if (wait_seq) 79 *wait_seq = seq; 80 81 txd_len = cmd & __MCU_CMD_FIELD_UNI ? sizeof(*uni_txd) : sizeof(*mcu_txd); 82 txd = (__le32 *)skb_push(skb, txd_len); 83 84 if (cmd != MCU_CMD(FW_SCATTER)) { 85 q_idx = MT_TX_MCU_PORT_RX_Q0; 86 pkt_fmt = MT_TX_TYPE_CMD; 87 } else { 88 q_idx = MT_TX_MCU_PORT_RX_FWDL; 89 pkt_fmt = MT_TX_TYPE_FW; 90 } 91 92 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) | 93 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) | 94 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); 95 txd[0] = cpu_to_le32(val); 96 97 val = MT_TXD1_LONG_FORMAT | 98 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) | 99 FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt); 100 txd[1] = cpu_to_le32(val); 101 102 if (cmd & __MCU_CMD_FIELD_UNI) { 103 uni_txd = (struct mt7615_uni_txd *)txd; 104 uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd)); 105 uni_txd->option = MCU_CMD_UNI_EXT_ACK; 106 uni_txd->cid = cpu_to_le16(mcu_cmd); 107 uni_txd->s2d_index = MCU_S2D_H2N; 108 uni_txd->pkt_type = MCU_PKT_ID; 109 uni_txd->seq = seq; 110 111 return; 112 } 113 114 mcu_txd = (struct mt7615_mcu_txd *)txd; 115 mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd)); 116 mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx)); 117 mcu_txd->s2d_index = MCU_S2D_H2N; 118 mcu_txd->pkt_type = MCU_PKT_ID; 119 mcu_txd->seq = seq; 120 mcu_txd->cid = mcu_cmd; 121 mcu_txd->ext_cid = FIELD_GET(__MCU_CMD_FIELD_EXT_ID, cmd); 122 123 if (mcu_txd->ext_cid || (cmd & __MCU_CMD_FIELD_CE)) { 124 if (cmd & __MCU_CMD_FIELD_QUERY) 125 mcu_txd->set_query = MCU_Q_QUERY; 126 else 127 mcu_txd->set_query = MCU_Q_SET; 128 mcu_txd->ext_cid_ack = !!mcu_txd->ext_cid; 129 } else { 130 mcu_txd->set_query = MCU_Q_NA; 131 } 132} 133EXPORT_SYMBOL_GPL(mt7615_mcu_fill_msg); 134 135int mt7615_mcu_parse_response(struct mt76_dev *mdev, int cmd, 136 struct sk_buff *skb, int seq) 137{ 138 struct mt7615_mcu_rxd *rxd; 139 int ret = 0; 140 141 if (!skb) { 142 dev_err(mdev->dev, "Message %08x (seq %d) timeout\n", 143 cmd, seq); 144 return -ETIMEDOUT; 145 } 146 147 rxd = (struct mt7615_mcu_rxd *)skb->data; 148 if (seq != rxd->seq) 149 return -EAGAIN; 150 151 if (cmd == MCU_CMD(PATCH_SEM_CONTROL)) { 152 skb_pull(skb, sizeof(*rxd) - 4); 153 ret = *skb->data; 154 } else if (cmd == MCU_EXT_CMD(THERMAL_CTRL)) { 155 skb_pull(skb, sizeof(*rxd)); 156 ret = le32_to_cpu(*(__le32 *)skb->data); 157 } else if (cmd == MCU_EXT_QUERY(RF_REG_ACCESS)) { 158 skb_pull(skb, sizeof(*rxd)); 159 ret = le32_to_cpu(*(__le32 *)&skb->data[8]); 160 } else if (cmd == MCU_UNI_CMD(DEV_INFO_UPDATE) || 161 cmd == MCU_UNI_CMD(BSS_INFO_UPDATE) || 162 cmd == MCU_UNI_CMD(STA_REC_UPDATE) || 163 cmd == MCU_UNI_CMD(HIF_CTRL) || 164 cmd == MCU_UNI_CMD(OFFLOAD) || 165 cmd == MCU_UNI_CMD(SUSPEND)) { 166 struct mt76_connac_mcu_uni_event *event; 167 168 skb_pull(skb, sizeof(*rxd)); 169 event = (struct mt76_connac_mcu_uni_event *)skb->data; 170 ret = le32_to_cpu(event->status); 171 } else if (cmd == MCU_CE_QUERY(REG_READ)) { 172 struct mt76_connac_mcu_reg_event *event; 173 174 skb_pull(skb, sizeof(*rxd)); 175 event = (struct mt76_connac_mcu_reg_event *)skb->data; 176 ret = (int)le32_to_cpu(event->val); 177 } 178 179 return ret; 180} 181EXPORT_SYMBOL_GPL(mt7615_mcu_parse_response); 182 183static int 184mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb, 185 int cmd, int *seq) 186{ 187 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 188 enum mt76_mcuq_id qid; 189 190 mt7615_mcu_fill_msg(dev, skb, cmd, seq); 191 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state)) 192 qid = MT_MCUQ_WM; 193 else 194 qid = MT_MCUQ_FWDL; 195 196 return mt76_tx_queue_skb_raw(dev, dev->mt76.q_mcu[qid], skb, 0); 197} 198 199u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg) 200{ 201 struct { 202 __le32 wifi_stream; 203 __le32 address; 204 __le32 data; 205 } req = { 206 .wifi_stream = cpu_to_le32(wf), 207 .address = cpu_to_le32(reg), 208 }; 209 210 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_QUERY(RF_REG_ACCESS), 211 &req, sizeof(req), true); 212} 213 214int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val) 215{ 216 struct { 217 __le32 wifi_stream; 218 __le32 address; 219 __le32 data; 220 } req = { 221 .wifi_stream = cpu_to_le32(wf), 222 .address = cpu_to_le32(reg), 223 .data = cpu_to_le32(val), 224 }; 225 226 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_REG_ACCESS), 227 &req, sizeof(req), false); 228} 229 230void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en) 231{ 232 if (!is_mt7622(&dev->mt76)) 233 return; 234 235 regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC, 236 MT_INFRACFG_MISC_AP2CONN_WAKE, 237 !en * MT_INFRACFG_MISC_AP2CONN_WAKE); 238} 239EXPORT_SYMBOL_GPL(mt7622_trigger_hif_int); 240 241static int mt7615_mcu_drv_pmctrl(struct mt7615_dev *dev) 242{ 243 struct mt76_phy *mphy = &dev->mt76.phy; 244 struct mt76_connac_pm *pm = &dev->pm; 245 struct mt76_dev *mdev = &dev->mt76; 246 u32 addr; 247 int err; 248 249 if (is_mt7663(mdev)) { 250 /* Clear firmware own via N9 eint */ 251 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN); 252 mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); 253 254 addr = MT_CONN_HIF_ON_LPCTL; 255 } else { 256 addr = MT_CFG_LPCR_HOST; 257 } 258 259 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN); 260 261 mt7622_trigger_hif_int(dev, true); 262 263 err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); 264 265 mt7622_trigger_hif_int(dev, false); 266 267 if (err) { 268 dev_err(mdev->dev, "driver own failed\n"); 269 return -ETIMEDOUT; 270 } 271 272 clear_bit(MT76_STATE_PM, &mphy->state); 273 274 pm->stats.last_wake_event = jiffies; 275 pm->stats.doze_time += pm->stats.last_wake_event - 276 pm->stats.last_doze_event; 277 278 return 0; 279} 280 281static int mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev *dev) 282{ 283 struct mt76_phy *mphy = &dev->mt76.phy; 284 struct mt76_connac_pm *pm = &dev->pm; 285 int i, err = 0; 286 287 mutex_lock(&pm->mutex); 288 289 if (!test_bit(MT76_STATE_PM, &mphy->state)) 290 goto out; 291 292 for (i = 0; i < MT7615_DRV_OWN_RETRY_COUNT; i++) { 293 mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN); 294 if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL, 295 MT_CFG_LPCR_HOST_FW_OWN, 0, 50)) 296 break; 297 } 298 299 if (i == MT7615_DRV_OWN_RETRY_COUNT) { 300 dev_err(dev->mt76.dev, "driver own failed\n"); 301 err = -EIO; 302 goto out; 303 } 304 clear_bit(MT76_STATE_PM, &mphy->state); 305 306 pm->stats.last_wake_event = jiffies; 307 pm->stats.doze_time += pm->stats.last_wake_event - 308 pm->stats.last_doze_event; 309out: 310 mutex_unlock(&pm->mutex); 311 312 return err; 313} 314 315static int mt7615_mcu_fw_pmctrl(struct mt7615_dev *dev) 316{ 317 struct mt76_phy *mphy = &dev->mt76.phy; 318 struct mt76_connac_pm *pm = &dev->pm; 319 int err = 0; 320 u32 addr; 321 322 mutex_lock(&pm->mutex); 323 324 if (mt76_connac_skip_fw_pmctrl(mphy, pm)) 325 goto out; 326 327 mt7622_trigger_hif_int(dev, true); 328 329 addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST; 330 mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN); 331 332 if (is_mt7622(&dev->mt76) && 333 !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 334 MT_CFG_LPCR_HOST_FW_OWN, 3000)) { 335 dev_err(dev->mt76.dev, "Timeout for firmware own\n"); 336 clear_bit(MT76_STATE_PM, &mphy->state); 337 err = -EIO; 338 } 339 340 mt7622_trigger_hif_int(dev, false); 341 if (!err) { 342 pm->stats.last_doze_event = jiffies; 343 pm->stats.awake_time += pm->stats.last_doze_event - 344 pm->stats.last_wake_event; 345 } 346out: 347 mutex_unlock(&pm->mutex); 348 349 return err; 350} 351 352static void 353mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif) 354{ 355 if (vif->bss_conf.csa_active) 356 ieee80211_csa_finish(vif); 357} 358 359static void 360mt7615_mcu_rx_csa_notify(struct mt7615_dev *dev, struct sk_buff *skb) 361{ 362 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev); 363 struct mt76_phy *mphy = &dev->mt76.phy; 364 struct mt7615_mcu_csa_notify *c; 365 366 c = (struct mt7615_mcu_csa_notify *)skb->data; 367 368 if (c->omac_idx > EXT_BSSID_MAX) 369 return; 370 371 if (ext_phy && ext_phy->omac_mask & BIT_ULL(c->omac_idx)) 372 mphy = dev->mt76.phys[MT_BAND1]; 373 374 ieee80211_iterate_active_interfaces_atomic(mphy->hw, 375 IEEE80211_IFACE_ITER_RESUME_ALL, 376 mt7615_mcu_csa_finish, mphy->hw); 377} 378 379static void 380mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb) 381{ 382 struct mt76_phy *mphy = &dev->mt76.phy; 383 struct mt7615_mcu_rdd_report *r; 384 385 r = (struct mt7615_mcu_rdd_report *)skb->data; 386 387 if (!dev->radar_pattern.n_pulses && !r->long_detected && 388 !r->constant_prf_detected && !r->staggered_prf_detected) 389 return; 390 391 if (r->band_idx && dev->mt76.phys[MT_BAND1]) 392 mphy = dev->mt76.phys[MT_BAND1]; 393 394 if (mt76_phy_dfs_state(mphy) < MT_DFS_STATE_CAC) 395 return; 396 397 ieee80211_radar_detected(mphy->hw); 398 dev->hw_pattern++; 399} 400 401static void 402mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb) 403{ 404 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 405 const char *data = (char *)&rxd[1]; 406 const char *type; 407 408 switch (rxd->s2d_index) { 409 case 0: 410 type = "N9"; 411 break; 412 case 2: 413 type = "CR4"; 414 break; 415 default: 416 type = "unknown"; 417 break; 418 } 419 420 wiphy_info(mt76_hw(dev)->wiphy, "%s: %.*s", type, 421 (int)(skb->len - sizeof(*rxd)), data); 422} 423 424static void 425mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb) 426{ 427 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 428 429 switch (rxd->ext_eid) { 430 case MCU_EXT_EVENT_RDD_REPORT: 431 mt7615_mcu_rx_radar_detected(dev, skb); 432 break; 433 case MCU_EXT_EVENT_CSA_NOTIFY: 434 mt7615_mcu_rx_csa_notify(dev, skb); 435 break; 436 case MCU_EXT_EVENT_FW_LOG_2_HOST: 437 mt7615_mcu_rx_log_message(dev, skb); 438 break; 439 default: 440 break; 441 } 442} 443 444static void 445mt7615_mcu_scan_event(struct mt7615_dev *dev, struct sk_buff *skb) 446{ 447 u8 *seq_num = skb->data + sizeof(struct mt7615_mcu_rxd); 448 struct mt7615_phy *phy; 449 struct mt76_phy *mphy; 450 451 if (*seq_num & BIT(7) && dev->mt76.phys[MT_BAND1]) 452 mphy = dev->mt76.phys[MT_BAND1]; 453 else 454 mphy = &dev->mt76.phy; 455 456 phy = (struct mt7615_phy *)mphy->priv; 457 458 spin_lock_bh(&dev->mt76.lock); 459 __skb_queue_tail(&phy->scan_event_list, skb); 460 spin_unlock_bh(&dev->mt76.lock); 461 462 ieee80211_queue_delayed_work(mphy->hw, &phy->scan_work, 463 MT7615_HW_SCAN_TIMEOUT); 464} 465 466static void 467mt7615_mcu_roc_event(struct mt7615_dev *dev, struct sk_buff *skb) 468{ 469 struct mt7615_roc_tlv *event; 470 struct mt7615_phy *phy; 471 struct mt76_phy *mphy; 472 int duration; 473 474 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 475 event = (struct mt7615_roc_tlv *)skb->data; 476 477 if (event->dbdc_band && dev->mt76.phys[MT_BAND1]) 478 mphy = dev->mt76.phys[MT_BAND1]; 479 else 480 mphy = &dev->mt76.phy; 481 482 ieee80211_ready_on_channel(mphy->hw); 483 484 phy = (struct mt7615_phy *)mphy->priv; 485 phy->roc_grant = true; 486 wake_up(&phy->roc_wait); 487 488 duration = le32_to_cpu(event->max_interval); 489 mod_timer(&phy->roc_timer, 490 round_jiffies_up(jiffies + msecs_to_jiffies(duration))); 491} 492 493static void 494mt7615_mcu_beacon_loss_event(struct mt7615_dev *dev, struct sk_buff *skb) 495{ 496 struct mt76_connac_beacon_loss_event *event; 497 struct mt76_phy *mphy; 498 u8 band_idx = 0; /* DBDC support */ 499 500 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 501 event = (struct mt76_connac_beacon_loss_event *)skb->data; 502 if (band_idx && dev->mt76.phys[MT_BAND1]) 503 mphy = dev->mt76.phys[MT_BAND1]; 504 else 505 mphy = &dev->mt76.phy; 506 507 ieee80211_iterate_active_interfaces_atomic(mphy->hw, 508 IEEE80211_IFACE_ITER_RESUME_ALL, 509 mt76_connac_mcu_beacon_loss_iter, 510 event); 511} 512 513static void 514mt7615_mcu_bss_event(struct mt7615_dev *dev, struct sk_buff *skb) 515{ 516 struct mt76_connac_mcu_bss_event *event; 517 struct mt76_phy *mphy; 518 u8 band_idx = 0; /* DBDC support */ 519 520 skb_pull(skb, sizeof(struct mt7615_mcu_rxd)); 521 event = (struct mt76_connac_mcu_bss_event *)skb->data; 522 523 if (band_idx && dev->mt76.phys[MT_BAND1]) 524 mphy = dev->mt76.phys[MT_BAND1]; 525 else 526 mphy = &dev->mt76.phy; 527 528 if (event->is_absent) 529 ieee80211_stop_queues(mphy->hw); 530 else 531 ieee80211_wake_queues(mphy->hw); 532} 533 534static void 535mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb) 536{ 537 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 538 539 switch (rxd->eid) { 540 case MCU_EVENT_EXT: 541 mt7615_mcu_rx_ext_event(dev, skb); 542 break; 543 case MCU_EVENT_BSS_BEACON_LOSS: 544 mt7615_mcu_beacon_loss_event(dev, skb); 545 break; 546 case MCU_EVENT_ROC: 547 mt7615_mcu_roc_event(dev, skb); 548 break; 549 case MCU_EVENT_SCHED_SCAN_DONE: 550 case MCU_EVENT_SCAN_DONE: 551 mt7615_mcu_scan_event(dev, skb); 552 return; 553 case MCU_EVENT_BSS_ABSENCE: 554 mt7615_mcu_bss_event(dev, skb); 555 break; 556 case MCU_EVENT_COREDUMP: 557 mt76_connac_mcu_coredump_event(&dev->mt76, skb, 558 &dev->coredump); 559 return; 560 default: 561 break; 562 } 563 dev_kfree_skb(skb); 564} 565 566void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb) 567{ 568 struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data; 569 570 if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT || 571 rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST || 572 rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP || 573 rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC || 574 rxd->eid == MCU_EVENT_BSS_BEACON_LOSS || 575 rxd->eid == MCU_EVENT_SCHED_SCAN_DONE || 576 rxd->eid == MCU_EVENT_BSS_ABSENCE || 577 rxd->eid == MCU_EVENT_SCAN_DONE || 578 rxd->eid == MCU_EVENT_COREDUMP || 579 rxd->eid == MCU_EVENT_ROC || 580 !rxd->seq) 581 mt7615_mcu_rx_unsolicited_event(dev, skb); 582 else 583 mt76_mcu_rx_event(&dev->mt76, skb); 584} 585 586static int 587mt7615_mcu_muar_config(struct mt7615_dev *dev, struct ieee80211_vif *vif, 588 bool bssid, bool enable) 589{ 590 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 591 u32 idx = mvif->mt76.omac_idx - REPEATER_BSSID_START; 592 u32 mask = dev->omac_mask >> 32 & ~BIT(idx); 593 const u8 *addr = vif->addr; 594 struct { 595 u8 mode; 596 u8 force_clear; 597 u8 clear_bitmap[8]; 598 u8 entry_count; 599 u8 write; 600 601 u8 index; 602 u8 bssid; 603 u8 addr[ETH_ALEN]; 604 } __packed req = { 605 .mode = !!mask || enable, 606 .entry_count = 1, 607 .write = 1, 608 609 .index = idx * 2 + bssid, 610 }; 611 612 if (bssid) 613 addr = vif->bss_conf.bssid; 614 615 if (enable) 616 ether_addr_copy(req.addr, addr); 617 618 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MUAR_UPDATE), 619 &req, sizeof(req), true); 620} 621 622static int 623mt7615_mcu_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif, 624 bool enable) 625{ 626 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 627 struct mt7615_dev *dev = phy->dev; 628 struct { 629 struct req_hdr { 630 u8 omac_idx; 631 u8 band_idx; 632 __le16 tlv_num; 633 u8 is_tlv_append; 634 u8 rsv[3]; 635 } __packed hdr; 636 struct req_tlv { 637 __le16 tag; 638 __le16 len; 639 u8 active; 640 u8 band_idx; 641 u8 omac_addr[ETH_ALEN]; 642 } __packed tlv; 643 } data = { 644 .hdr = { 645 .omac_idx = mvif->mt76.omac_idx, 646 .band_idx = mvif->mt76.band_idx, 647 .tlv_num = cpu_to_le16(1), 648 .is_tlv_append = 1, 649 }, 650 .tlv = { 651 .tag = cpu_to_le16(DEV_INFO_ACTIVE), 652 .len = cpu_to_le16(sizeof(struct req_tlv)), 653 .active = enable, 654 .band_idx = mvif->mt76.band_idx, 655 }, 656 }; 657 658 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START) 659 return mt7615_mcu_muar_config(dev, vif, false, enable); 660 661 memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN); 662 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DEV_INFO_UPDATE), 663 &data, sizeof(data), true); 664} 665 666static int 667mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev, 668 struct ieee80211_hw *hw, 669 struct ieee80211_vif *vif, bool enable) 670{ 671 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 672 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 673 struct ieee80211_mutable_offsets offs; 674 struct ieee80211_tx_info *info; 675 struct req { 676 u8 omac_idx; 677 u8 enable; 678 u8 wlan_idx; 679 u8 band_idx; 680 u8 pkt_type; 681 u8 need_pre_tbtt_int; 682 __le16 csa_ie_pos; 683 __le16 pkt_len; 684 __le16 tim_ie_pos; 685 u8 pkt[512]; 686 u8 csa_cnt; 687 /* bss color change */ 688 u8 bcc_cnt; 689 __le16 bcc_ie_pos; 690 } __packed req = { 691 .omac_idx = mvif->mt76.omac_idx, 692 .enable = enable, 693 .wlan_idx = wcid->idx, 694 .band_idx = mvif->mt76.band_idx, 695 }; 696 struct sk_buff *skb; 697 698 if (!enable) 699 goto out; 700 701 skb = ieee80211_beacon_get_template(hw, vif, &offs, 0); 702 if (!skb) 703 return -EINVAL; 704 705 if (skb->len > 512 - MT_TXD_SIZE) { 706 dev_err(dev->mt76.dev, "Bcn size limit exceed\n"); 707 dev_kfree_skb(skb); 708 return -EINVAL; 709 } 710 711 info = IEEE80211_SKB_CB(skb); 712 info->hw_queue |= FIELD_PREP(MT_TX_HW_QUEUE_PHY, mvif->mt76.band_idx); 713 714 mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL, 715 0, NULL, 0, true); 716 memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len); 717 req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 718 req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 719 if (offs.cntdwn_counter_offs[0]) { 720 u16 csa_offs; 721 722 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4; 723 req.csa_ie_pos = cpu_to_le16(csa_offs); 724 req.csa_cnt = skb->data[offs.cntdwn_counter_offs[0]]; 725 } 726 dev_kfree_skb(skb); 727 728out: 729 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(BCN_OFFLOAD), &req, 730 sizeof(req), true); 731} 732 733static int 734mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 735{ 736 return mt76_connac_mcu_set_pm(&dev->mt76, band, state); 737} 738 739static int 740mt7615_mcu_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif, 741 struct ieee80211_sta *sta, bool enable) 742{ 743 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 744 struct mt7615_dev *dev = phy->dev; 745 struct sk_buff *skb; 746 747 if (mvif->mt76.omac_idx >= REPEATER_BSSID_START) 748 mt7615_mcu_muar_config(dev, vif, true, enable); 749 750 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, NULL); 751 if (IS_ERR(skb)) 752 return PTR_ERR(skb); 753 754 if (enable) 755 mt76_connac_mcu_bss_omac_tlv(skb, vif); 756 757 mt76_connac_mcu_bss_basic_tlv(skb, vif, sta, phy->mt76, 758 mvif->sta.wcid.idx, enable); 759 760 if (enable && mvif->mt76.omac_idx >= EXT_BSSID_START && 761 mvif->mt76.omac_idx < REPEATER_BSSID_START) 762 mt76_connac_mcu_bss_ext_tlv(skb, &mvif->mt76); 763 764 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 765 MCU_EXT_CMD(BSS_INFO_UPDATE), true); 766} 767 768static int 769mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev, 770 struct ieee80211_ampdu_params *params, 771 bool enable) 772{ 773 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 774 struct mt7615_vif *mvif = msta->vif; 775 struct wtbl_req_hdr *wtbl_hdr; 776 struct sk_buff *skb = NULL; 777 int err; 778 779 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 780 WTBL_SET, NULL, &skb); 781 if (IS_ERR(wtbl_hdr)) 782 return PTR_ERR(wtbl_hdr); 783 784 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, true, 785 NULL, wtbl_hdr); 786 787 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, 788 MCU_EXT_CMD(WTBL_UPDATE), true); 789 if (err < 0) 790 return err; 791 792 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 793 &msta->wcid); 794 if (IS_ERR(skb)) 795 return PTR_ERR(skb); 796 797 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, true); 798 799 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 800 MCU_EXT_CMD(STA_REC_UPDATE), true); 801} 802 803static int 804mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev, 805 struct ieee80211_ampdu_params *params, 806 bool enable) 807{ 808 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 809 struct mt7615_vif *mvif = msta->vif; 810 struct wtbl_req_hdr *wtbl_hdr; 811 struct sk_buff *skb; 812 int err; 813 814 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 815 &msta->wcid); 816 if (IS_ERR(skb)) 817 return PTR_ERR(skb); 818 819 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false); 820 821 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, 822 MCU_EXT_CMD(STA_REC_UPDATE), true); 823 if (err < 0 || !enable) 824 return err; 825 826 skb = NULL; 827 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 828 WTBL_SET, NULL, &skb); 829 if (IS_ERR(wtbl_hdr)) 830 return PTR_ERR(wtbl_hdr); 831 832 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false, 833 NULL, wtbl_hdr); 834 835 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 836 MCU_EXT_CMD(WTBL_UPDATE), true); 837} 838 839static int 840mt7615_mcu_wtbl_sta_add(struct mt7615_phy *phy, struct ieee80211_vif *vif, 841 struct ieee80211_sta *sta, bool enable) 842{ 843 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 844 struct sk_buff *skb, *sskb, *wskb = NULL; 845 struct mt7615_dev *dev = phy->dev; 846 struct wtbl_req_hdr *wtbl_hdr; 847 struct mt7615_sta *msta; 848 bool new_entry = true; 849 int cmd, err; 850 851 msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta; 852 853 sskb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 854 &msta->wcid); 855 if (IS_ERR(sskb)) 856 return PTR_ERR(sskb); 857 858 if (!sta) { 859 if (mvif->sta_added) 860 new_entry = false; 861 else 862 mvif->sta_added = true; 863 } 864 mt76_connac_mcu_sta_basic_tlv(&dev->mt76, sskb, vif, sta, enable, 865 new_entry); 866 if (enable && sta) 867 mt76_connac_mcu_sta_tlv(phy->mt76, sskb, sta, vif, 0, 868 MT76_STA_INFO_STATE_ASSOC); 869 870 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 871 WTBL_RESET_AND_SET, NULL, 872 &wskb); 873 if (IS_ERR(wtbl_hdr)) 874 return PTR_ERR(wtbl_hdr); 875 876 if (enable) { 877 mt76_connac_mcu_wtbl_generic_tlv(&dev->mt76, wskb, vif, sta, 878 NULL, wtbl_hdr); 879 if (sta) 880 mt76_connac_mcu_wtbl_ht_tlv(&dev->mt76, wskb, sta, 881 NULL, wtbl_hdr, true, true); 882 mt76_connac_mcu_wtbl_hdr_trans_tlv(wskb, vif, &msta->wcid, 883 NULL, wtbl_hdr); 884 } 885 886 cmd = enable ? MCU_EXT_CMD(WTBL_UPDATE) : MCU_EXT_CMD(STA_REC_UPDATE); 887 skb = enable ? wskb : sskb; 888 889 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 890 if (err < 0) { 891 skb = enable ? sskb : wskb; 892 dev_kfree_skb(skb); 893 894 return err; 895 } 896 897 cmd = enable ? MCU_EXT_CMD(STA_REC_UPDATE) : MCU_EXT_CMD(WTBL_UPDATE); 898 skb = enable ? sskb : wskb; 899 900 return mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true); 901} 902 903static int 904mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev *dev, 905 struct ieee80211_vif *vif, 906 struct ieee80211_sta *sta) 907{ 908 return mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta); 909} 910 911static const struct mt7615_mcu_ops wtbl_update_ops = { 912 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 913 .set_pm_state = mt7615_mcu_ctrl_pm_state, 914 .add_dev_info = mt7615_mcu_add_dev, 915 .add_bss_info = mt7615_mcu_add_bss, 916 .add_tx_ba = mt7615_mcu_wtbl_tx_ba, 917 .add_rx_ba = mt7615_mcu_wtbl_rx_ba, 918 .sta_add = mt7615_mcu_wtbl_sta_add, 919 .set_drv_ctrl = mt7615_mcu_drv_pmctrl, 920 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 921 .set_sta_decap_offload = mt7615_mcu_wtbl_update_hdr_trans, 922}; 923 924static int 925mt7615_mcu_sta_ba(struct mt7615_dev *dev, 926 struct ieee80211_ampdu_params *params, 927 bool enable, bool tx) 928{ 929 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 930 struct mt7615_vif *mvif = msta->vif; 931 struct wtbl_req_hdr *wtbl_hdr; 932 struct tlv *sta_wtbl; 933 struct sk_buff *skb; 934 935 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 936 &msta->wcid); 937 if (IS_ERR(skb)) 938 return PTR_ERR(skb); 939 940 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx); 941 942 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv)); 943 944 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 945 WTBL_SET, sta_wtbl, &skb); 946 if (IS_ERR(wtbl_hdr)) 947 return PTR_ERR(wtbl_hdr); 948 949 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, tx, 950 sta_wtbl, wtbl_hdr); 951 952 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 953 MCU_EXT_CMD(STA_REC_UPDATE), true); 954} 955 956static int 957mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev, 958 struct ieee80211_ampdu_params *params, 959 bool enable) 960{ 961 return mt7615_mcu_sta_ba(dev, params, enable, true); 962} 963 964static int 965mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev, 966 struct ieee80211_ampdu_params *params, 967 bool enable) 968{ 969 return mt7615_mcu_sta_ba(dev, params, enable, false); 970} 971 972static int 973__mt7615_mcu_add_sta(struct mt76_phy *phy, struct ieee80211_vif *vif, 974 struct ieee80211_sta *sta, bool enable, int cmd, 975 bool offload_fw) 976{ 977 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 978 struct mt76_sta_cmd_info info = { 979 .sta = sta, 980 .vif = vif, 981 .offload_fw = offload_fw, 982 .enable = enable, 983 .newly = true, 984 .cmd = cmd, 985 }; 986 987 info.wcid = sta ? (struct mt76_wcid *)sta->drv_priv : &mvif->sta.wcid; 988 return mt76_connac_mcu_sta_cmd(phy, &info); 989} 990 991static int 992mt7615_mcu_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif, 993 struct ieee80211_sta *sta, bool enable) 994{ 995 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable, 996 MCU_EXT_CMD(STA_REC_UPDATE), false); 997} 998 999static int 1000mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev *dev, 1001 struct ieee80211_vif *vif, 1002 struct ieee80211_sta *sta) 1003{ 1004 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 1005 1006 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76, 1007 vif, &msta->wcid, 1008 MCU_EXT_CMD(STA_REC_UPDATE)); 1009} 1010 1011static const struct mt7615_mcu_ops sta_update_ops = { 1012 .add_beacon_offload = mt7615_mcu_add_beacon_offload, 1013 .set_pm_state = mt7615_mcu_ctrl_pm_state, 1014 .add_dev_info = mt7615_mcu_add_dev, 1015 .add_bss_info = mt7615_mcu_add_bss, 1016 .add_tx_ba = mt7615_mcu_sta_tx_ba, 1017 .add_rx_ba = mt7615_mcu_sta_rx_ba, 1018 .sta_add = mt7615_mcu_add_sta, 1019 .set_drv_ctrl = mt7615_mcu_drv_pmctrl, 1020 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1021 .set_sta_decap_offload = mt7615_mcu_sta_update_hdr_trans, 1022}; 1023 1024static int 1025mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state) 1026{ 1027 return 0; 1028} 1029 1030static int 1031mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev, 1032 struct ieee80211_hw *hw, 1033 struct ieee80211_vif *vif, 1034 bool enable) 1035{ 1036 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1037 struct mt76_wcid *wcid = &dev->mt76.global_wcid; 1038 struct ieee80211_mutable_offsets offs; 1039 struct { 1040 struct req_hdr { 1041 u8 bss_idx; 1042 u8 pad[3]; 1043 } __packed hdr; 1044 struct bcn_content_tlv { 1045 __le16 tag; 1046 __le16 len; 1047 __le16 tim_ie_pos; 1048 __le16 csa_ie_pos; 1049 __le16 bcc_ie_pos; 1050 /* 0: disable beacon offload 1051 * 1: enable beacon offload 1052 * 2: update probe respond offload 1053 */ 1054 u8 enable; 1055 /* 0: legacy format (TXD + payload) 1056 * 1: only cap field IE 1057 */ 1058 u8 type; 1059 __le16 pkt_len; 1060 u8 pkt[512]; 1061 } __packed beacon_tlv; 1062 } req = { 1063 .hdr = { 1064 .bss_idx = mvif->mt76.idx, 1065 }, 1066 .beacon_tlv = { 1067 .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT), 1068 .len = cpu_to_le16(sizeof(struct bcn_content_tlv)), 1069 .enable = enable, 1070 }, 1071 }; 1072 struct sk_buff *skb; 1073 1074 if (!enable) 1075 goto out; 1076 1077 skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs, 0); 1078 if (!skb) 1079 return -EINVAL; 1080 1081 if (skb->len > 512 - MT_TXD_SIZE) { 1082 dev_err(dev->mt76.dev, "beacon size limit exceed\n"); 1083 dev_kfree_skb(skb); 1084 return -EINVAL; 1085 } 1086 1087 mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb, 1088 wcid, NULL, 0, NULL, 0, true); 1089 memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len); 1090 req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len); 1091 req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset); 1092 1093 if (offs.cntdwn_counter_offs[0]) { 1094 u16 csa_offs; 1095 1096 csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4; 1097 req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs); 1098 } 1099 dev_kfree_skb(skb); 1100 1101out: 1102 return mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD(BSS_INFO_UPDATE), 1103 &req, sizeof(req), true); 1104} 1105 1106static int 1107mt7615_mcu_uni_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1108 bool enable) 1109{ 1110 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1111 1112 return mt76_connac_mcu_uni_add_dev(phy->mt76, vif, &mvif->sta.wcid, 1113 enable); 1114} 1115 1116static int 1117mt7615_mcu_uni_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1118 struct ieee80211_sta *sta, bool enable) 1119{ 1120 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 1121 1122 return mt76_connac_mcu_uni_add_bss(phy->mt76, vif, &mvif->sta.wcid, 1123 enable, NULL); 1124} 1125 1126static inline int 1127mt7615_mcu_uni_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif, 1128 struct ieee80211_sta *sta, bool enable) 1129{ 1130 return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable, 1131 MCU_UNI_CMD(STA_REC_UPDATE), true); 1132} 1133 1134static int 1135mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev, 1136 struct ieee80211_ampdu_params *params, 1137 bool enable) 1138{ 1139 struct mt7615_sta *sta = (struct mt7615_sta *)params->sta->drv_priv; 1140 1141 return mt76_connac_mcu_sta_ba(&dev->mt76, &sta->vif->mt76, params, 1142 MCU_UNI_CMD(STA_REC_UPDATE), enable, 1143 true); 1144} 1145 1146static int 1147mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev, 1148 struct ieee80211_ampdu_params *params, 1149 bool enable) 1150{ 1151 struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv; 1152 struct mt7615_vif *mvif = msta->vif; 1153 struct wtbl_req_hdr *wtbl_hdr; 1154 struct tlv *sta_wtbl; 1155 struct sk_buff *skb; 1156 int err; 1157 1158 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 1159 &msta->wcid); 1160 if (IS_ERR(skb)) 1161 return PTR_ERR(skb); 1162 1163 mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false); 1164 1165 err = mt76_mcu_skb_send_msg(&dev->mt76, skb, 1166 MCU_UNI_CMD(STA_REC_UPDATE), true); 1167 if (err < 0 || !enable) 1168 return err; 1169 1170 skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, 1171 &msta->wcid); 1172 if (IS_ERR(skb)) 1173 return PTR_ERR(skb); 1174 1175 sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, 1176 sizeof(struct tlv)); 1177 1178 wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid, 1179 WTBL_SET, sta_wtbl, &skb); 1180 if (IS_ERR(wtbl_hdr)) 1181 return PTR_ERR(wtbl_hdr); 1182 1183 mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false, 1184 sta_wtbl, wtbl_hdr); 1185 1186 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1187 MCU_UNI_CMD(STA_REC_UPDATE), true); 1188} 1189 1190static int 1191mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev *dev, 1192 struct ieee80211_vif *vif, 1193 struct ieee80211_sta *sta) 1194{ 1195 struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv; 1196 1197 return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76, 1198 vif, &msta->wcid, 1199 MCU_UNI_CMD(STA_REC_UPDATE)); 1200} 1201 1202static const struct mt7615_mcu_ops uni_update_ops = { 1203 .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload, 1204 .set_pm_state = mt7615_mcu_uni_ctrl_pm_state, 1205 .add_dev_info = mt7615_mcu_uni_add_dev, 1206 .add_bss_info = mt7615_mcu_uni_add_bss, 1207 .add_tx_ba = mt7615_mcu_uni_tx_ba, 1208 .add_rx_ba = mt7615_mcu_uni_rx_ba, 1209 .sta_add = mt7615_mcu_uni_add_sta, 1210 .set_drv_ctrl = mt7615_mcu_lp_drv_pmctrl, 1211 .set_fw_ctrl = mt7615_mcu_fw_pmctrl, 1212 .set_sta_decap_offload = mt7615_mcu_sta_uni_update_hdr_trans, 1213}; 1214 1215int mt7615_mcu_restart(struct mt76_dev *dev) 1216{ 1217 return mt76_mcu_send_msg(dev, MCU_CMD(RESTART_DL_REQ), NULL, 0, true); 1218} 1219EXPORT_SYMBOL_GPL(mt7615_mcu_restart); 1220 1221static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name) 1222{ 1223 const struct mt7615_patch_hdr *hdr; 1224 const struct firmware *fw = NULL; 1225 int len, ret, sem; 1226 1227 ret = firmware_request_nowarn(&fw, name, dev->mt76.dev); 1228 if (ret) 1229 return ret; 1230 1231 if (!fw || !fw->data || fw->size < sizeof(*hdr)) { 1232 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1233 ret = -EINVAL; 1234 goto release_fw; 1235 } 1236 1237 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, true); 1238 switch (sem) { 1239 case PATCH_IS_DL: 1240 goto release_fw; 1241 case PATCH_NOT_DL_SEM_SUCCESS: 1242 break; 1243 default: 1244 dev_err(dev->mt76.dev, "Failed to get patch semaphore\n"); 1245 ret = -EAGAIN; 1246 goto release_fw; 1247 } 1248 1249 hdr = (const struct mt7615_patch_hdr *)(fw->data); 1250 1251 dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n", 1252 be32_to_cpu(hdr->hw_sw_ver), hdr->build_date); 1253 1254 len = fw->size - sizeof(*hdr); 1255 1256 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len, 1257 DL_MODE_NEED_RSP); 1258 if (ret) { 1259 dev_err(dev->mt76.dev, "Download request failed\n"); 1260 goto out; 1261 } 1262 1263 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER), 1264 fw->data + sizeof(*hdr), len); 1265 if (ret) { 1266 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 1267 goto out; 1268 } 1269 1270 ret = mt76_connac_mcu_start_patch(&dev->mt76); 1271 if (ret) 1272 dev_err(dev->mt76.dev, "Failed to start patch\n"); 1273 1274out: 1275 sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, false); 1276 switch (sem) { 1277 case PATCH_REL_SEM_SUCCESS: 1278 break; 1279 default: 1280 ret = -EAGAIN; 1281 dev_err(dev->mt76.dev, "Failed to release patch semaphore\n"); 1282 break; 1283 } 1284 1285release_fw: 1286 release_firmware(fw); 1287 1288 return ret; 1289} 1290 1291static int 1292mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev, 1293 const struct mt7615_fw_trailer *hdr, 1294 const u8 *data, bool is_cr4) 1295{ 1296 int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM; 1297 int err, i, offset = 0; 1298 u32 len, addr, mode; 1299 1300 for (i = 0; i < n_region; i++) { 1301 mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76, 1302 hdr[i].feature_set, is_cr4); 1303 len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN; 1304 addr = le32_to_cpu(hdr[i].addr); 1305 1306 err = mt76_connac_mcu_init_download(&dev->mt76, addr, len, 1307 mode); 1308 if (err) { 1309 dev_err(dev->mt76.dev, "Download request failed\n"); 1310 return err; 1311 } 1312 1313 err = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER), 1314 data + offset, len); 1315 if (err) { 1316 dev_err(dev->mt76.dev, "Failed to send firmware to device\n"); 1317 return err; 1318 } 1319 1320 offset += len; 1321 } 1322 1323 return 0; 1324} 1325 1326static int mt7615_load_n9(struct mt7615_dev *dev, const char *name) 1327{ 1328 const struct mt7615_fw_trailer *hdr; 1329 const struct firmware *fw; 1330 int ret; 1331 1332 ret = request_firmware(&fw, name, dev->mt76.dev); 1333 if (ret) 1334 return ret; 1335 1336 if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) { 1337 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1338 ret = -EINVAL; 1339 goto out; 1340 } 1341 1342 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 1343 N9_REGION_NUM * sizeof(*hdr)); 1344 1345 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 1346 hdr->fw_ver, hdr->build_date); 1347 1348 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false); 1349 if (ret) 1350 goto out; 1351 1352 ret = mt76_connac_mcu_start_firmware(&dev->mt76, 1353 le32_to_cpu(hdr->addr), 1354 FW_START_OVERRIDE); 1355 if (ret) { 1356 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 1357 goto out; 1358 } 1359 1360 snprintf(dev->mt76.hw->wiphy->fw_version, 1361 sizeof(dev->mt76.hw->wiphy->fw_version), 1362 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 1363 1364 if (!is_mt7615(&dev->mt76)) { 1365 dev->fw_ver = MT7615_FIRMWARE_V2; 1366 dev->mcu_ops = &sta_update_ops; 1367 } else { 1368 dev->fw_ver = MT7615_FIRMWARE_V1; 1369 dev->mcu_ops = &wtbl_update_ops; 1370 } 1371 1372out: 1373 release_firmware(fw); 1374 return ret; 1375} 1376 1377static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name) 1378{ 1379 const struct mt7615_fw_trailer *hdr; 1380 const struct firmware *fw; 1381 int ret; 1382 1383 ret = request_firmware(&fw, name, dev->mt76.dev); 1384 if (ret) 1385 return ret; 1386 1387 if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) { 1388 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1389 ret = -EINVAL; 1390 goto out; 1391 } 1392 1393 hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size - 1394 CR4_REGION_NUM * sizeof(*hdr)); 1395 1396 dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n", 1397 hdr->fw_ver, hdr->build_date); 1398 1399 ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true); 1400 if (ret) 1401 goto out; 1402 1403 ret = mt76_connac_mcu_start_firmware(&dev->mt76, 0, 1404 FW_START_WORKING_PDA_CR4); 1405 if (ret) { 1406 dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n"); 1407 goto out; 1408 } 1409 1410out: 1411 release_firmware(fw); 1412 1413 return ret; 1414} 1415 1416static int mt7615_load_ram(struct mt7615_dev *dev) 1417{ 1418 int ret; 1419 1420 ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9); 1421 if (ret) 1422 return ret; 1423 1424 return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4); 1425} 1426 1427static int mt7615_load_firmware(struct mt7615_dev *dev) 1428{ 1429 int ret; 1430 u32 val; 1431 1432 val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE); 1433 1434 if (val != FW_STATE_FW_DOWNLOAD) { 1435 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 1436 return -EIO; 1437 } 1438 1439 ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH); 1440 if (ret) 1441 return ret; 1442 1443 ret = mt7615_load_ram(dev); 1444 if (ret) 1445 return ret; 1446 1447 if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE, 1448 FIELD_PREP(MT_TOP_MISC2_FW_STATE, 1449 FW_STATE_RDY), 500)) { 1450 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1451 return -EIO; 1452 } 1453 1454 return 0; 1455} 1456 1457static int mt7622_load_firmware(struct mt7615_dev *dev) 1458{ 1459 int ret; 1460 u32 val; 1461 1462 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1463 1464 val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE); 1465 if (val != FW_STATE_FW_DOWNLOAD) { 1466 dev_err(dev->mt76.dev, "Firmware is not ready for download\n"); 1467 return -EIO; 1468 } 1469 1470 ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH); 1471 if (ret) 1472 return ret; 1473 1474 ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9); 1475 if (ret) 1476 return ret; 1477 1478 if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE, 1479 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE, 1480 FW_STATE_NORMAL_TRX), 1500)) { 1481 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1482 return -EIO; 1483 } 1484 1485 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1486 1487 return 0; 1488} 1489 1490int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl) 1491{ 1492 struct { 1493 u8 ctrl_val; 1494 u8 pad[3]; 1495 } data = { 1496 .ctrl_val = ctrl 1497 }; 1498 1499 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(FW_LOG_2_HOST), 1500 &data, sizeof(data), true); 1501} 1502 1503static int mt7615_mcu_cal_cache_apply(struct mt7615_dev *dev) 1504{ 1505 struct { 1506 bool cache_enable; 1507 u8 pad[3]; 1508 } data = { 1509 .cache_enable = true 1510 }; 1511 1512 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CAL_CACHE), &data, 1513 sizeof(data), false); 1514} 1515 1516static int mt7663_load_n9(struct mt7615_dev *dev, const char *name) 1517{ 1518 u32 offset = 0, override_addr = 0, flag = FW_START_DLYCAL; 1519 const struct mt76_connac2_fw_trailer *hdr; 1520 const struct mt7663_fw_buf *buf; 1521 const struct firmware *fw; 1522 const u8 *base_addr; 1523 int i, ret; 1524 1525 ret = request_firmware(&fw, name, dev->mt76.dev); 1526 if (ret) 1527 return ret; 1528 1529 if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) { 1530 dev_err(dev->mt76.dev, "Invalid firmware\n"); 1531 ret = -EINVAL; 1532 goto out; 1533 } 1534 1535 hdr = (const void *)(fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE); 1536 dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n", 1537 hdr->fw_ver, hdr->build_date); 1538 dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region); 1539 1540 base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE; 1541 for (i = 0; i < hdr->n_region; i++) { 1542 u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE; 1543 u32 len, addr, mode; 1544 1545 dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i); 1546 1547 buf = (const struct mt7663_fw_buf *)(base_addr - shift); 1548 mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76, 1549 buf->feature_set, false); 1550 addr = le32_to_cpu(buf->img_dest_addr); 1551 len = le32_to_cpu(buf->img_size); 1552 1553 ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len, 1554 mode); 1555 if (ret) { 1556 dev_err(dev->mt76.dev, "Download request failed\n"); 1557 goto out; 1558 } 1559 1560 ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER), 1561 fw->data + offset, len); 1562 if (ret) { 1563 dev_err(dev->mt76.dev, "Failed to send firmware\n"); 1564 goto out; 1565 } 1566 1567 offset += le32_to_cpu(buf->img_size); 1568 if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) { 1569 override_addr = le32_to_cpu(buf->img_dest_addr); 1570 dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n", 1571 i, override_addr); 1572 } 1573 } 1574 1575 if (override_addr) 1576 flag |= FW_START_OVERRIDE; 1577 1578 dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n", 1579 override_addr, flag); 1580 1581 ret = mt76_connac_mcu_start_firmware(&dev->mt76, override_addr, flag); 1582 if (ret) { 1583 dev_err(dev->mt76.dev, "Failed to start N9 firmware\n"); 1584 goto out; 1585 } 1586 1587 snprintf(dev->mt76.hw->wiphy->fw_version, 1588 sizeof(dev->mt76.hw->wiphy->fw_version), 1589 "%.10s-%.15s", hdr->fw_ver, hdr->build_date); 1590 1591out: 1592 release_firmware(fw); 1593 1594 return ret; 1595} 1596 1597static int 1598mt7663_load_rom_patch(struct mt7615_dev *dev, const char **n9_firmware) 1599{ 1600 const char *selected_rom, *secondary_rom = MT7663_ROM_PATCH; 1601 const char *primary_rom = MT7663_OFFLOAD_ROM_PATCH; 1602 int ret; 1603 1604 if (!prefer_offload_fw) { 1605 secondary_rom = MT7663_OFFLOAD_ROM_PATCH; 1606 primary_rom = MT7663_ROM_PATCH; 1607 } 1608 selected_rom = primary_rom; 1609 1610 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, primary_rom); 1611 if (ret) { 1612 dev_info(dev->mt76.dev, "%s not found, switching to %s", 1613 primary_rom, secondary_rom); 1614 ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, 1615 secondary_rom); 1616 if (ret) { 1617 dev_err(dev->mt76.dev, "failed to load %s", 1618 secondary_rom); 1619 return ret; 1620 } 1621 selected_rom = secondary_rom; 1622 } 1623 1624 if (!strcmp(selected_rom, MT7663_OFFLOAD_ROM_PATCH)) { 1625 *n9_firmware = MT7663_OFFLOAD_FIRMWARE_N9; 1626 dev->fw_ver = MT7615_FIRMWARE_V3; 1627 dev->mcu_ops = &uni_update_ops; 1628 } else { 1629 *n9_firmware = MT7663_FIRMWARE_N9; 1630 dev->fw_ver = MT7615_FIRMWARE_V2; 1631 dev->mcu_ops = &sta_update_ops; 1632 } 1633 1634 return 0; 1635} 1636 1637int __mt7663_load_firmware(struct mt7615_dev *dev) 1638{ 1639 const char *n9_firmware; 1640 int ret; 1641 1642 ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY); 1643 if (ret) { 1644 dev_dbg(dev->mt76.dev, "Firmware is already download\n"); 1645 return -EIO; 1646 } 1647 1648 ret = mt7663_load_rom_patch(dev, &n9_firmware); 1649 if (ret) 1650 return ret; 1651 1652 ret = mt7663_load_n9(dev, n9_firmware); 1653 if (ret) 1654 return ret; 1655 1656 if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY, 1657 MT_TOP_MISC2_FW_N9_RDY, 1500)) { 1658 ret = mt76_get_field(dev, MT_CONN_ON_MISC, 1659 MT7663_TOP_MISC2_FW_STATE); 1660 dev_err(dev->mt76.dev, "Timeout for initializing firmware\n"); 1661 return -EIO; 1662 } 1663 1664#ifdef CONFIG_PM 1665 if (mt7615_firmware_offload(dev)) 1666 dev->mt76.hw->wiphy->wowlan = &mt76_connac_wowlan_support; 1667#endif /* CONFIG_PM */ 1668 1669 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 1670 1671 return 0; 1672} 1673EXPORT_SYMBOL_GPL(__mt7663_load_firmware); 1674 1675static int mt7663_load_firmware(struct mt7615_dev *dev) 1676{ 1677 int ret; 1678 1679 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1680 1681 ret = __mt7663_load_firmware(dev); 1682 if (ret) 1683 return ret; 1684 1685 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH); 1686 1687 return 0; 1688} 1689 1690int mt7615_mcu_init(struct mt7615_dev *dev) 1691{ 1692 static const struct mt76_mcu_ops mt7615_mcu_ops = { 1693 .headroom = sizeof(struct mt7615_mcu_txd), 1694 .mcu_skb_send_msg = mt7615_mcu_send_message, 1695 .mcu_parse_response = mt7615_mcu_parse_response, 1696 }; 1697 int ret; 1698 1699 dev->mt76.mcu_ops = &mt7615_mcu_ops, 1700 1701 ret = mt7615_mcu_drv_pmctrl(dev); 1702 if (ret) 1703 return ret; 1704 1705 switch (mt76_chip(&dev->mt76)) { 1706 case 0x7622: 1707 ret = mt7622_load_firmware(dev); 1708 break; 1709 case 0x7663: 1710 ret = mt7663_load_firmware(dev); 1711 break; 1712 default: 1713 ret = mt7615_load_firmware(dev); 1714 break; 1715 } 1716 if (ret) 1717 return ret; 1718 1719 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_FWDL], false); 1720 dev_dbg(dev->mt76.dev, "Firmware init done\n"); 1721 set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1722 1723 if (dev->dbdc_support) { 1724 ret = mt7615_mcu_cal_cache_apply(dev); 1725 if (ret) 1726 return ret; 1727 } 1728 1729 return mt7615_mcu_fw_log_2_host(dev, 0); 1730} 1731EXPORT_SYMBOL_GPL(mt7615_mcu_init); 1732 1733void mt7615_mcu_exit(struct mt7615_dev *dev) 1734{ 1735 mt7615_mcu_restart(&dev->mt76); 1736 mt7615_mcu_set_fw_ctrl(dev); 1737 skb_queue_purge(&dev->mt76.mcu.res_q); 1738} 1739EXPORT_SYMBOL_GPL(mt7615_mcu_exit); 1740 1741int mt7615_mcu_set_eeprom(struct mt7615_dev *dev) 1742{ 1743 struct { 1744 u8 buffer_mode; 1745 u8 content_format; 1746 __le16 len; 1747 } __packed req_hdr = { 1748 .buffer_mode = 1, 1749 }; 1750 u8 *eep = (u8 *)dev->mt76.eeprom.data; 1751 struct sk_buff *skb; 1752 int eep_len, offset; 1753 1754 switch (mt76_chip(&dev->mt76)) { 1755 case 0x7622: 1756 eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0; 1757 offset = MT_EE_NIC_CONF_0; 1758 break; 1759 case 0x7663: 1760 eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID; 1761 req_hdr.content_format = 1; 1762 offset = MT_EE_CHIP_ID; 1763 break; 1764 default: 1765 eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0; 1766 offset = MT_EE_NIC_CONF_0; 1767 break; 1768 } 1769 1770 req_hdr.len = cpu_to_le16(eep_len); 1771 1772 skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + eep_len); 1773 if (!skb) 1774 return -ENOMEM; 1775 1776 skb_put_data(skb, &req_hdr, sizeof(req_hdr)); 1777 skb_put_data(skb, eep + offset, eep_len); 1778 1779 return mt76_mcu_skb_send_msg(&dev->mt76, skb, 1780 MCU_EXT_CMD(EFUSE_BUFFER_MODE), true); 1781} 1782 1783int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue, 1784 const struct ieee80211_tx_queue_params *params) 1785{ 1786#define WMM_AIFS_SET BIT(0) 1787#define WMM_CW_MIN_SET BIT(1) 1788#define WMM_CW_MAX_SET BIT(2) 1789#define WMM_TXOP_SET BIT(3) 1790#define WMM_PARAM_SET (WMM_AIFS_SET | WMM_CW_MIN_SET | \ 1791 WMM_CW_MAX_SET | WMM_TXOP_SET) 1792 struct req_data { 1793 u8 number; 1794 u8 rsv[3]; 1795 u8 queue; 1796 u8 valid; 1797 u8 aifs; 1798 u8 cw_min; 1799 __le16 cw_max; 1800 __le16 txop; 1801 } __packed req = { 1802 .number = 1, 1803 .queue = queue, 1804 .valid = WMM_PARAM_SET, 1805 .aifs = params->aifs, 1806 .cw_min = 5, 1807 .cw_max = cpu_to_le16(10), 1808 .txop = cpu_to_le16(params->txop), 1809 }; 1810 1811 if (params->cw_min) 1812 req.cw_min = fls(params->cw_min); 1813 if (params->cw_max) 1814 req.cw_max = cpu_to_le16(fls(params->cw_max)); 1815 1816 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EDCA_UPDATE), 1817 &req, sizeof(req), true); 1818} 1819 1820int mt7615_mcu_set_dbdc(struct mt7615_dev *dev) 1821{ 1822 struct mt7615_phy *ext_phy = mt7615_ext_phy(dev); 1823 struct dbdc_entry { 1824 u8 type; 1825 u8 index; 1826 u8 band; 1827 u8 _rsv; 1828 }; 1829 struct { 1830 u8 enable; 1831 u8 num; 1832 u8 _rsv[2]; 1833 struct dbdc_entry entry[64]; 1834 } req = { 1835 .enable = !!ext_phy, 1836 }; 1837 int i; 1838 1839 if (!ext_phy) 1840 goto out; 1841 1842#define ADD_DBDC_ENTRY(_type, _idx, _band) \ 1843 do { \ 1844 req.entry[req.num].type = _type; \ 1845 req.entry[req.num].index = _idx; \ 1846 req.entry[req.num++].band = _band; \ 1847 } while (0) 1848 1849 for (i = 0; i < 4; i++) { 1850 bool band = !!(ext_phy->omac_mask & BIT_ULL(i)); 1851 1852 ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band); 1853 } 1854 1855 for (i = 0; i < 14; i++) { 1856 bool band = !!(ext_phy->omac_mask & BIT_ULL(0x11 + i)); 1857 1858 ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band); 1859 } 1860 1861 ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1); 1862 1863 for (i = 0; i < 3; i++) 1864 ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1); 1865 1866 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0); 1867 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0); 1868 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1); 1869 ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1); 1870 1871 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0); 1872 ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1); 1873 1874out: 1875 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DBDC_CTRL), &req, 1876 sizeof(req), true); 1877} 1878 1879int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev) 1880{ 1881 struct wtbl_req_hdr req = { 1882 .operation = WTBL_RESET_ALL, 1883 }; 1884 1885 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(WTBL_UPDATE), 1886 &req, sizeof(req), true); 1887} 1888 1889int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val) 1890{ 1891 struct { 1892 __le16 tag; 1893 __le16 min_lpn; 1894 } req = { 1895 .tag = cpu_to_le16(0x1), 1896 .min_lpn = cpu_to_le16(val), 1897 }; 1898 1899 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH), 1900 &req, sizeof(req), true); 1901} 1902 1903int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev, 1904 const struct mt7615_dfs_pulse *pulse) 1905{ 1906 struct { 1907 __le16 tag; 1908 __le32 max_width; /* us */ 1909 __le32 max_pwr; /* dbm */ 1910 __le32 min_pwr; /* dbm */ 1911 __le32 min_stgr_pri; /* us */ 1912 __le32 max_stgr_pri; /* us */ 1913 __le32 min_cr_pri; /* us */ 1914 __le32 max_cr_pri; /* us */ 1915 } req = { 1916 .tag = cpu_to_le16(0x3), 1917#define __req_field(field) .field = cpu_to_le32(pulse->field) 1918 __req_field(max_width), 1919 __req_field(max_pwr), 1920 __req_field(min_pwr), 1921 __req_field(min_stgr_pri), 1922 __req_field(max_stgr_pri), 1923 __req_field(min_cr_pri), 1924 __req_field(max_cr_pri), 1925#undef __req_field 1926 }; 1927 1928 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH), 1929 &req, sizeof(req), true); 1930} 1931 1932int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index, 1933 const struct mt7615_dfs_pattern *pattern) 1934{ 1935 struct { 1936 __le16 tag; 1937 __le16 radar_type; 1938 u8 enb; 1939 u8 stgr; 1940 u8 min_crpn; 1941 u8 max_crpn; 1942 u8 min_crpr; 1943 u8 min_pw; 1944 u8 max_pw; 1945 __le32 min_pri; 1946 __le32 max_pri; 1947 u8 min_crbn; 1948 u8 max_crbn; 1949 u8 min_stgpn; 1950 u8 max_stgpn; 1951 u8 min_stgpr; 1952 } req = { 1953 .tag = cpu_to_le16(0x2), 1954 .radar_type = cpu_to_le16(index), 1955#define __req_field_u8(field) .field = pattern->field 1956#define __req_field_u32(field) .field = cpu_to_le32(pattern->field) 1957 __req_field_u8(enb), 1958 __req_field_u8(stgr), 1959 __req_field_u8(min_crpn), 1960 __req_field_u8(max_crpn), 1961 __req_field_u8(min_crpr), 1962 __req_field_u8(min_pw), 1963 __req_field_u8(max_pw), 1964 __req_field_u32(min_pri), 1965 __req_field_u32(max_pri), 1966 __req_field_u8(min_crbn), 1967 __req_field_u8(max_crbn), 1968 __req_field_u8(min_stgpn), 1969 __req_field_u8(max_stgpn), 1970 __req_field_u8(min_stgpr), 1971#undef __req_field_u8 1972#undef __req_field_u32 1973 }; 1974 1975 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH), 1976 &req, sizeof(req), true); 1977} 1978 1979int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev) 1980{ 1981 struct { 1982 u8 pulse_num; 1983 u8 rsv[3]; 1984 struct { 1985 __le32 start_time; 1986 __le16 width; 1987 __le16 power; 1988 } pattern[32]; 1989 } req = { 1990 .pulse_num = dev->radar_pattern.n_pulses, 1991 }; 1992 u32 start_time = ktime_to_ms(ktime_get_boottime()); 1993 int i; 1994 1995 if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern)) 1996 return -EINVAL; 1997 1998 /* TODO: add some noise here */ 1999 for (i = 0; i < dev->radar_pattern.n_pulses; i++) { 2000 u32 ts = start_time + i * dev->radar_pattern.period; 2001 2002 req.pattern[i].width = cpu_to_le16(dev->radar_pattern.width); 2003 req.pattern[i].power = cpu_to_le16(dev->radar_pattern.power); 2004 req.pattern[i].start_time = cpu_to_le32(ts); 2005 } 2006 2007 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RDD_PATTERN), 2008 &req, sizeof(req), false); 2009} 2010 2011static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku) 2012{ 2013 struct mt76_phy *mphy = phy->mt76; 2014 struct ieee80211_hw *hw = mphy->hw; 2015 struct mt76_power_limits limits; 2016 s8 *limits_array = (s8 *)&limits; 2017 int n_chains = hweight8(mphy->antenna_mask); 2018 int tx_power = hw->conf.power_level * 2; 2019 int i; 2020 static const u8 sku_mapping[] = { 2021#define SKU_FIELD(_type, _field) \ 2022 [MT_SKU_##_type] = offsetof(struct mt76_power_limits, _field) 2023 SKU_FIELD(CCK_1_2, cck[0]), 2024 SKU_FIELD(CCK_55_11, cck[2]), 2025 SKU_FIELD(OFDM_6_9, ofdm[0]), 2026 SKU_FIELD(OFDM_12_18, ofdm[2]), 2027 SKU_FIELD(OFDM_24_36, ofdm[4]), 2028 SKU_FIELD(OFDM_48, ofdm[6]), 2029 SKU_FIELD(OFDM_54, ofdm[7]), 2030 SKU_FIELD(HT20_0_8, mcs[0][0]), 2031 SKU_FIELD(HT20_32, ofdm[0]), 2032 SKU_FIELD(HT20_1_2_9_10, mcs[0][1]), 2033 SKU_FIELD(HT20_3_4_11_12, mcs[0][3]), 2034 SKU_FIELD(HT20_5_13, mcs[0][5]), 2035 SKU_FIELD(HT20_6_14, mcs[0][6]), 2036 SKU_FIELD(HT20_7_15, mcs[0][7]), 2037 SKU_FIELD(HT40_0_8, mcs[1][0]), 2038 SKU_FIELD(HT40_32, ofdm[0]), 2039 SKU_FIELD(HT40_1_2_9_10, mcs[1][1]), 2040 SKU_FIELD(HT40_3_4_11_12, mcs[1][3]), 2041 SKU_FIELD(HT40_5_13, mcs[1][5]), 2042 SKU_FIELD(HT40_6_14, mcs[1][6]), 2043 SKU_FIELD(HT40_7_15, mcs[1][7]), 2044 SKU_FIELD(VHT20_0, mcs[0][0]), 2045 SKU_FIELD(VHT20_1_2, mcs[0][1]), 2046 SKU_FIELD(VHT20_3_4, mcs[0][3]), 2047 SKU_FIELD(VHT20_5_6, mcs[0][5]), 2048 SKU_FIELD(VHT20_7, mcs[0][7]), 2049 SKU_FIELD(VHT20_8, mcs[0][8]), 2050 SKU_FIELD(VHT20_9, mcs[0][9]), 2051 SKU_FIELD(VHT40_0, mcs[1][0]), 2052 SKU_FIELD(VHT40_1_2, mcs[1][1]), 2053 SKU_FIELD(VHT40_3_4, mcs[1][3]), 2054 SKU_FIELD(VHT40_5_6, mcs[1][5]), 2055 SKU_FIELD(VHT40_7, mcs[1][7]), 2056 SKU_FIELD(VHT40_8, mcs[1][8]), 2057 SKU_FIELD(VHT40_9, mcs[1][9]), 2058 SKU_FIELD(VHT80_0, mcs[2][0]), 2059 SKU_FIELD(VHT80_1_2, mcs[2][1]), 2060 SKU_FIELD(VHT80_3_4, mcs[2][3]), 2061 SKU_FIELD(VHT80_5_6, mcs[2][5]), 2062 SKU_FIELD(VHT80_7, mcs[2][7]), 2063 SKU_FIELD(VHT80_8, mcs[2][8]), 2064 SKU_FIELD(VHT80_9, mcs[2][9]), 2065 SKU_FIELD(VHT160_0, mcs[3][0]), 2066 SKU_FIELD(VHT160_1_2, mcs[3][1]), 2067 SKU_FIELD(VHT160_3_4, mcs[3][3]), 2068 SKU_FIELD(VHT160_5_6, mcs[3][5]), 2069 SKU_FIELD(VHT160_7, mcs[3][7]), 2070 SKU_FIELD(VHT160_8, mcs[3][8]), 2071 SKU_FIELD(VHT160_9, mcs[3][9]), 2072#undef SKU_FIELD 2073 }; 2074 2075 tx_power = mt76_get_sar_power(mphy, mphy->chandef.chan, tx_power); 2076 tx_power -= mt76_tx_power_nss_delta(n_chains); 2077 tx_power = mt76_get_rate_power_limits(mphy, mphy->chandef.chan, 2078 &limits, tx_power); 2079 mphy->txpower_cur = tx_power; 2080 2081 if (is_mt7663(mphy->dev)) { 2082 memset(sku, tx_power, MT_SKU_4SS_DELTA + 1); 2083 return; 2084 } 2085 2086 for (i = 0; i < MT_SKU_1SS_DELTA; i++) 2087 sku[i] = limits_array[sku_mapping[i]]; 2088 2089 for (i = 0; i < 4; i++) { 2090 int delta = 0; 2091 2092 if (i < n_chains - 1) 2093 delta = mt76_tx_power_nss_delta(n_chains) - 2094 mt76_tx_power_nss_delta(i + 1); 2095 sku[MT_SKU_1SS_DELTA + i] = delta; 2096 } 2097} 2098 2099static u8 mt7615_mcu_chan_bw(struct cfg80211_chan_def *chandef) 2100{ 2101 static const u8 width_to_bw[] = { 2102 [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ, 2103 [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ, 2104 [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ, 2105 [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ, 2106 [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ, 2107 [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ, 2108 [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ, 2109 [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ, 2110 }; 2111 2112 if (chandef->width >= ARRAY_SIZE(width_to_bw)) 2113 return 0; 2114 2115 return width_to_bw[chandef->width]; 2116} 2117 2118int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd) 2119{ 2120 struct mt7615_dev *dev = phy->dev; 2121 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2122 int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2; 2123 struct { 2124 u8 control_chan; 2125 u8 center_chan; 2126 u8 bw; 2127 u8 tx_streams; 2128 u8 rx_streams_mask; 2129 u8 switch_reason; 2130 u8 band_idx; 2131 /* for 80+80 only */ 2132 u8 center_chan2; 2133 __le16 cac_case; 2134 u8 channel_band; 2135 u8 rsv0; 2136 __le32 outband_freq; 2137 u8 txpower_drop; 2138 u8 rsv1[3]; 2139 u8 txpower_sku[53]; 2140 u8 rsv2[3]; 2141 } req = { 2142 .control_chan = chandef->chan->hw_value, 2143 .center_chan = ieee80211_frequency_to_channel(freq1), 2144 .tx_streams = hweight8(phy->mt76->antenna_mask), 2145 .rx_streams_mask = phy->mt76->chainmask, 2146 .center_chan2 = ieee80211_frequency_to_channel(freq2), 2147 }; 2148 2149 if (cmd == MCU_EXT_CMD(SET_RX_PATH) || 2150 dev->mt76.hw->conf.flags & IEEE80211_CONF_MONITOR) 2151 req.switch_reason = CH_SWITCH_NORMAL; 2152 else if (phy->mt76->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) 2153 req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD; 2154 else if (!cfg80211_reg_can_beacon(phy->mt76->hw->wiphy, chandef, 2155 NL80211_IFTYPE_AP)) 2156 req.switch_reason = CH_SWITCH_DFS; 2157 else 2158 req.switch_reason = CH_SWITCH_NORMAL; 2159 2160 req.band_idx = phy != &dev->phy; 2161 req.bw = mt7615_mcu_chan_bw(chandef); 2162 2163 if (mt76_testmode_enabled(phy->mt76)) 2164 memset(req.txpower_sku, 0x3f, 49); 2165 else 2166 mt7615_mcu_set_txpower_sku(phy, req.txpower_sku); 2167 2168 return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true); 2169} 2170 2171int mt7615_mcu_get_temperature(struct mt7615_dev *dev) 2172{ 2173 struct { 2174 u8 action; 2175 u8 rsv[3]; 2176 } req = {}; 2177 2178 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(THERMAL_CTRL), 2179 &req, sizeof(req), true); 2180} 2181 2182int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode, 2183 u32 val) 2184{ 2185 struct { 2186 u8 test_mode_en; 2187 u8 param_idx; 2188 u8 _rsv[2]; 2189 2190 __le32 value; 2191 2192 u8 pad[8]; 2193 } req = { 2194 .test_mode_en = test_mode, 2195 .param_idx = param, 2196 .value = cpu_to_le32(val), 2197 }; 2198 2199 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), 2200 &req, sizeof(req), false); 2201} 2202 2203int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable) 2204{ 2205 struct mt7615_dev *dev = phy->dev; 2206 struct { 2207 u8 format_id; 2208 u8 sku_enable; 2209 u8 band_idx; 2210 u8 rsv; 2211 } req = { 2212 .format_id = 0, 2213 .band_idx = phy != &dev->phy, 2214 .sku_enable = enable, 2215 }; 2216 2217 return mt76_mcu_send_msg(&dev->mt76, 2218 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL), 2219 &req, sizeof(req), true); 2220} 2221 2222static int mt7615_find_freq_idx(const u16 *freqs, int n_freqs, u16 cur) 2223{ 2224 int i; 2225 2226 for (i = 0; i < n_freqs; i++) 2227 if (cur == freqs[i]) 2228 return i; 2229 2230 return -1; 2231} 2232 2233static int mt7615_dcoc_freq_idx(u16 freq, u8 bw) 2234{ 2235 static const u16 freq_list[] = { 2236 4980, 5805, 5905, 5190, 2237 5230, 5270, 5310, 5350, 2238 5390, 5430, 5470, 5510, 2239 5550, 5590, 5630, 5670, 2240 5710, 5755, 5795, 5835, 2241 5875, 5210, 5290, 5370, 2242 5450, 5530, 5610, 5690, 2243 5775, 5855 2244 }; 2245 static const u16 freq_bw40[] = { 2246 5190, 5230, 5270, 5310, 2247 5350, 5390, 5430, 5470, 2248 5510, 5550, 5590, 5630, 2249 5670, 5710, 5755, 5795, 2250 5835, 5875 2251 }; 2252 int offset_2g = ARRAY_SIZE(freq_list); 2253 int idx; 2254 2255 if (freq < 4000) { 2256 if (freq < 2427) 2257 return offset_2g; 2258 if (freq < 2442) 2259 return offset_2g + 1; 2260 if (freq < 2457) 2261 return offset_2g + 2; 2262 2263 return offset_2g + 3; 2264 } 2265 2266 switch (bw) { 2267 case NL80211_CHAN_WIDTH_80: 2268 case NL80211_CHAN_WIDTH_80P80: 2269 case NL80211_CHAN_WIDTH_160: 2270 break; 2271 default: 2272 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 2273 freq + 10); 2274 if (idx >= 0) { 2275 freq = freq_bw40[idx]; 2276 break; 2277 } 2278 2279 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 2280 freq - 10); 2281 if (idx >= 0) { 2282 freq = freq_bw40[idx]; 2283 break; 2284 } 2285 fallthrough; 2286 case NL80211_CHAN_WIDTH_40: 2287 idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40), 2288 freq); 2289 if (idx >= 0) 2290 break; 2291 2292 return -1; 2293 2294 } 2295 2296 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq); 2297} 2298 2299int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy) 2300{ 2301 struct mt7615_dev *dev = phy->dev; 2302 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2303 int freq2 = chandef->center_freq2; 2304 int ret; 2305 struct { 2306 u8 direction; 2307 u8 runtime_calibration; 2308 u8 _rsv[2]; 2309 2310 __le16 center_freq; 2311 u8 bw; 2312 u8 band; 2313 u8 is_freq2; 2314 u8 success; 2315 u8 dbdc_en; 2316 2317 u8 _rsv2; 2318 2319 struct { 2320 __le32 sx0_i_lna[4]; 2321 __le32 sx0_q_lna[4]; 2322 2323 __le32 sx2_i_lna[4]; 2324 __le32 sx2_q_lna[4]; 2325 } dcoc_data[4]; 2326 } req = { 2327 .direction = 1, 2328 2329 .bw = mt7615_mcu_chan_bw(chandef), 2330 .band = chandef->center_freq1 > 4000, 2331 .dbdc_en = !!dev->mt76.phys[MT_BAND1], 2332 }; 2333 u16 center_freq = chandef->center_freq1; 2334 int freq_idx; 2335 u8 *eep = dev->mt76.eeprom.data; 2336 2337 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_RX_CAL)) 2338 return 0; 2339 2340 if (chandef->width == NL80211_CHAN_WIDTH_160) { 2341 freq2 = center_freq + 40; 2342 center_freq -= 40; 2343 } 2344 2345again: 2346 req.runtime_calibration = 1; 2347 freq_idx = mt7615_dcoc_freq_idx(center_freq, chandef->width); 2348 if (freq_idx < 0) 2349 goto out; 2350 2351 memcpy(req.dcoc_data, eep + MT7615_EEPROM_DCOC_OFFSET + 2352 freq_idx * MT7615_EEPROM_DCOC_SIZE, 2353 sizeof(req.dcoc_data)); 2354 req.runtime_calibration = 0; 2355 2356out: 2357 req.center_freq = cpu_to_le16(center_freq); 2358 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RXDCOC_CAL), &req, 2359 sizeof(req), true); 2360 2361 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 || 2362 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) { 2363 req.is_freq2 = true; 2364 center_freq = freq2; 2365 goto again; 2366 } 2367 2368 return ret; 2369} 2370 2371static int mt7615_dpd_freq_idx(u16 freq, u8 bw) 2372{ 2373 static const u16 freq_list[] = { 2374 4920, 4940, 4960, 4980, 2375 5040, 5060, 5080, 5180, 2376 5200, 5220, 5240, 5260, 2377 5280, 5300, 5320, 5340, 2378 5360, 5380, 5400, 5420, 2379 5440, 5460, 5480, 5500, 2380 5520, 5540, 5560, 5580, 2381 5600, 5620, 5640, 5660, 2382 5680, 5700, 5720, 5745, 2383 5765, 5785, 5805, 5825, 2384 5845, 5865, 5885, 5905 2385 }; 2386 int offset_2g = ARRAY_SIZE(freq_list); 2387 int idx; 2388 2389 if (freq < 4000) { 2390 if (freq < 2432) 2391 return offset_2g; 2392 if (freq < 2457) 2393 return offset_2g + 1; 2394 2395 return offset_2g + 2; 2396 } 2397 2398 if (bw != NL80211_CHAN_WIDTH_20) { 2399 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), 2400 freq + 10); 2401 if (idx >= 0) 2402 return idx; 2403 2404 idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), 2405 freq - 10); 2406 if (idx >= 0) 2407 return idx; 2408 } 2409 2410 return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq); 2411} 2412 2413 2414int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy) 2415{ 2416 struct mt7615_dev *dev = phy->dev; 2417 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2418 int freq2 = chandef->center_freq2; 2419 int ret; 2420 struct { 2421 u8 direction; 2422 u8 runtime_calibration; 2423 u8 _rsv[2]; 2424 2425 __le16 center_freq; 2426 u8 bw; 2427 u8 band; 2428 u8 is_freq2; 2429 u8 success; 2430 u8 dbdc_en; 2431 2432 u8 _rsv2; 2433 2434 struct { 2435 struct { 2436 u32 dpd_g0; 2437 u8 data[32]; 2438 } wf0, wf1; 2439 2440 struct { 2441 u32 dpd_g0_prim; 2442 u32 dpd_g0_sec; 2443 u8 data_prim[32]; 2444 u8 data_sec[32]; 2445 } wf2, wf3; 2446 } dpd_data; 2447 } req = { 2448 .direction = 1, 2449 2450 .bw = mt7615_mcu_chan_bw(chandef), 2451 .band = chandef->center_freq1 > 4000, 2452 .dbdc_en = !!dev->mt76.phys[MT_BAND1], 2453 }; 2454 u16 center_freq = chandef->center_freq1; 2455 int freq_idx; 2456 u8 *eep = dev->mt76.eeprom.data; 2457 2458 if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_TX_DPD)) 2459 return 0; 2460 2461 if (chandef->width == NL80211_CHAN_WIDTH_160) { 2462 freq2 = center_freq + 40; 2463 center_freq -= 40; 2464 } 2465 2466again: 2467 req.runtime_calibration = 1; 2468 freq_idx = mt7615_dpd_freq_idx(center_freq, chandef->width); 2469 if (freq_idx < 0) 2470 goto out; 2471 2472 memcpy(&req.dpd_data, eep + MT7615_EEPROM_TXDPD_OFFSET + 2473 freq_idx * MT7615_EEPROM_TXDPD_SIZE, 2474 sizeof(req.dpd_data)); 2475 req.runtime_calibration = 0; 2476 2477out: 2478 req.center_freq = cpu_to_le16(center_freq); 2479 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXDPD_CAL), 2480 &req, sizeof(req), true); 2481 2482 if ((chandef->width == NL80211_CHAN_WIDTH_80P80 || 2483 chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) { 2484 req.is_freq2 = true; 2485 center_freq = freq2; 2486 goto again; 2487 } 2488 2489 return ret; 2490} 2491 2492int mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev *dev) 2493{ 2494 struct { 2495 u8 operation; 2496 u8 count; 2497 u8 _rsv[2]; 2498 u8 index; 2499 u8 enable; 2500 __le16 etype; 2501 } req = { 2502 .operation = 1, 2503 .count = 1, 2504 .enable = 1, 2505 .etype = cpu_to_le16(ETH_P_PAE), 2506 }; 2507 2508 return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_HDR_TRANS), 2509 &req, sizeof(req), false); 2510} 2511 2512int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif, 2513 bool enable) 2514{ 2515 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 2516 struct { 2517 u8 bss_idx; 2518 u8 dtim_period; 2519 __le16 aid; 2520 __le16 bcn_interval; 2521 __le16 atim_window; 2522 u8 uapsd; 2523 u8 bmc_delivered_ac; 2524 u8 bmc_triggered_ac; 2525 u8 pad; 2526 } req = { 2527 .bss_idx = mvif->mt76.idx, 2528 .aid = cpu_to_le16(vif->cfg.aid), 2529 .dtim_period = vif->bss_conf.dtim_period, 2530 .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int), 2531 }; 2532 struct { 2533 u8 bss_idx; 2534 u8 pad[3]; 2535 } req_hdr = { 2536 .bss_idx = mvif->mt76.idx, 2537 }; 2538 int err; 2539 2540 if (vif->type != NL80211_IFTYPE_STATION) 2541 return 0; 2542 2543 err = mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_ABORT), 2544 &req_hdr, sizeof(req_hdr), false); 2545 if (err < 0 || !enable) 2546 return err; 2547 2548 return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_CONNECTED), 2549 &req, sizeof(req), false); 2550} 2551 2552int mt7615_mcu_set_roc(struct mt7615_phy *phy, struct ieee80211_vif *vif, 2553 struct ieee80211_channel *chan, int duration) 2554{ 2555 struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv; 2556 struct mt7615_dev *dev = phy->dev; 2557 struct mt7615_roc_tlv req = { 2558 .bss_idx = mvif->mt76.idx, 2559 .active = !chan, 2560 .max_interval = cpu_to_le32(duration), 2561 .primary_chan = chan ? chan->hw_value : 0, 2562 .band = chan ? chan->band : 0, 2563 .req_type = 2, 2564 }; 2565 2566 phy->roc_grant = false; 2567 2568 return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_ROC), 2569 &req, sizeof(req), false); 2570} 2571