1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 */
5#ifndef __MT76_DMA_H
6#define __MT76_DMA_H
7
8#define DMA_DUMMY_DATA			((void *)~0)
9
10#define MT_RING_SIZE			0x10
11
12#define MT_DMA_CTL_SD_LEN1		GENMASK(13, 0)
13#define MT_DMA_CTL_LAST_SEC1		BIT(14)
14#define MT_DMA_CTL_BURST		BIT(15)
15#define MT_DMA_CTL_SD_LEN0		GENMASK(29, 16)
16#define MT_DMA_CTL_LAST_SEC0		BIT(30)
17#define MT_DMA_CTL_DMA_DONE		BIT(31)
18#define MT_DMA_CTL_TO_HOST		BIT(8)
19#define MT_DMA_CTL_TO_HOST_A		BIT(12)
20#define MT_DMA_CTL_DROP			BIT(14)
21#define MT_DMA_CTL_TOKEN		GENMASK(31, 16)
22#define MT_DMA_CTL_WO_DROP		BIT(8)
23
24#define MT_DMA_PPE_CPU_REASON		GENMASK(15, 11)
25#define MT_DMA_PPE_ENTRY		GENMASK(30, 16)
26#define MT_DMA_INFO_PPE_VLD		BIT(31)
27
28#define MT_DMA_HDR_LEN			4
29#define MT_RX_INFO_LEN			4
30#define MT_FCE_INFO_LEN			4
31#define MT_RX_RXWI_LEN			32
32
33struct mt76_desc {
34	__le32 buf0;
35	__le32 ctrl;
36	__le32 buf1;
37	__le32 info;
38} __packed __aligned(4);
39
40enum mt76_qsel {
41	MT_QSEL_MGMT,
42	MT_QSEL_HCCA,
43	MT_QSEL_EDCA,
44	MT_QSEL_EDCA_2,
45};
46
47enum mt76_mcu_evt_type {
48	EVT_CMD_DONE,
49	EVT_CMD_ERROR,
50	EVT_CMD_RETRY,
51	EVT_EVENT_PWR_RSP,
52	EVT_EVENT_WOW_RSP,
53	EVT_EVENT_CARRIER_DETECT_RSP,
54	EVT_EVENT_DFS_DETECT_RSP,
55};
56
57int mt76_dma_rx_poll(struct napi_struct *napi, int budget);
58void mt76_dma_attach(struct mt76_dev *dev);
59void mt76_dma_cleanup(struct mt76_dev *dev);
60int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset);
61
62#endif
63