1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation 4 * Copyright (C) 2016-2017 Intel Deutschland GmbH 5 * Copyright (C) 2018-2023 Intel Corporation 6 */ 7#ifndef __IWL_CONFIG_H__ 8#define __IWL_CONFIG_H__ 9 10#include <linux/types.h> 11#include <linux/netdevice.h> 12#include <linux/ieee80211.h> 13#include <linux/nl80211.h> 14#include "iwl-csr.h" 15 16enum iwl_device_family { 17 IWL_DEVICE_FAMILY_UNDEFINED, 18 IWL_DEVICE_FAMILY_1000, 19 IWL_DEVICE_FAMILY_100, 20 IWL_DEVICE_FAMILY_2000, 21 IWL_DEVICE_FAMILY_2030, 22 IWL_DEVICE_FAMILY_105, 23 IWL_DEVICE_FAMILY_135, 24 IWL_DEVICE_FAMILY_5000, 25 IWL_DEVICE_FAMILY_5150, 26 IWL_DEVICE_FAMILY_6000, 27 IWL_DEVICE_FAMILY_6000i, 28 IWL_DEVICE_FAMILY_6005, 29 IWL_DEVICE_FAMILY_6030, 30 IWL_DEVICE_FAMILY_6050, 31 IWL_DEVICE_FAMILY_6150, 32 IWL_DEVICE_FAMILY_7000, 33 IWL_DEVICE_FAMILY_8000, 34 IWL_DEVICE_FAMILY_9000, 35 IWL_DEVICE_FAMILY_22000, 36 IWL_DEVICE_FAMILY_AX210, 37 IWL_DEVICE_FAMILY_BZ, 38 IWL_DEVICE_FAMILY_SC, 39}; 40 41/* 42 * LED mode 43 * IWL_LED_DEFAULT: use device default 44 * IWL_LED_RF_STATE: turn LED on/off based on RF state 45 * LED ON = RF ON 46 * LED OFF = RF OFF 47 * IWL_LED_BLINK: adjust led blink rate based on blink table 48 * IWL_LED_DISABLE: led disabled 49 */ 50enum iwl_led_mode { 51 IWL_LED_DEFAULT, 52 IWL_LED_RF_STATE, 53 IWL_LED_BLINK, 54 IWL_LED_DISABLE, 55}; 56 57/** 58 * enum iwl_nvm_type - nvm formats 59 * @IWL_NVM: the regular format 60 * @IWL_NVM_EXT: extended NVM format 61 * @IWL_NVM_SDP: NVM format used by 3168 series 62 */ 63enum iwl_nvm_type { 64 IWL_NVM, 65 IWL_NVM_EXT, 66 IWL_NVM_SDP, 67}; 68 69/* 70 * This is the threshold value of plcp error rate per 100mSecs. It is 71 * used to set and check for the validity of plcp_delta. 72 */ 73#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN 1 74#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF 50 75#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF 100 76#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF 200 77#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX 255 78#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE 0 79 80/* TX queue watchdog timeouts in mSecs */ 81#define IWL_WATCHDOG_DISABLED 0 82#define IWL_DEF_WD_TIMEOUT 2500 83#define IWL_LONG_WD_TIMEOUT 10000 84#define IWL_MAX_WD_TIMEOUT 120000 85 86#define IWL_DEFAULT_MAX_TX_POWER 22 87#define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\ 88 NETIF_F_TSO | NETIF_F_TSO6) 89#define IWL_TX_CSUM_NETIF_FLAGS_BZ (NETIF_F_HW_CSUM | NETIF_F_TSO | NETIF_F_TSO6) 90#define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | \ 91 IWL_TX_CSUM_NETIF_FLAGS_BZ | \ 92 NETIF_F_RXCSUM) 93 94/* Antenna presence definitions */ 95#define ANT_NONE 0x0 96#define ANT_INVALID 0xff 97#define ANT_A BIT(0) 98#define ANT_B BIT(1) 99#define ANT_C BIT(2) 100#define ANT_AB (ANT_A | ANT_B) 101#define ANT_AC (ANT_A | ANT_C) 102#define ANT_BC (ANT_B | ANT_C) 103#define ANT_ABC (ANT_A | ANT_B | ANT_C) 104 105 106static inline u8 num_of_ant(u8 mask) 107{ 108 return !!((mask) & ANT_A) + 109 !!((mask) & ANT_B) + 110 !!((mask) & ANT_C); 111} 112 113/** 114 * struct iwl_base_params - params not likely to change within a device family 115 * @max_ll_items: max number of OTP blocks 116 * @shadow_ram_support: shadow support for OTP memory 117 * @led_compensation: compensate on the led on/off time per HW according 118 * to the deviation to achieve the desired led frequency. 119 * The detail algorithm is described in iwl-led.c 120 * @wd_timeout: TX queues watchdog timeout 121 * @max_event_log_size: size of event log buffer size for ucode event logging 122 * @shadow_reg_enable: HW shadow register support 123 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command 124 * is in flight. This is due to a HW bug in 7260, 3160 and 7265. 125 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled. 126 * @max_tfd_queue_size: max number of entries in tfd queue. 127 */ 128struct iwl_base_params { 129 unsigned int wd_timeout; 130 131 u16 eeprom_size; 132 u16 max_event_log_size; 133 134 u8 pll_cfg:1, /* for iwl_pcie_apm_init() */ 135 shadow_ram_support:1, 136 shadow_reg_enable:1, 137 pcie_l1_allowed:1, 138 apmg_wake_up_wa:1, 139 scd_chain_ext_wa:1; 140 141 u16 num_of_queues; /* def: HW dependent */ 142 u32 max_tfd_queue_size; /* def: HW dependent */ 143 144 u8 max_ll_items; 145 u8 led_compensation; 146}; 147 148/* 149 * @stbc: support Tx STBC and 1*SS Rx STBC 150 * @ldpc: support Tx/Rx with LDPC 151 * @use_rts_for_aggregation: use rts/cts protection for HT traffic 152 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40 153 */ 154struct iwl_ht_params { 155 u8 ht_greenfield_support:1, 156 stbc:1, 157 ldpc:1, 158 use_rts_for_aggregation:1; 159 u8 ht40_bands; 160}; 161 162/* 163 * Tx-backoff threshold 164 * @temperature: The threshold in Celsius 165 * @backoff: The tx-backoff in uSec 166 */ 167struct iwl_tt_tx_backoff { 168 s32 temperature; 169 u32 backoff; 170}; 171 172#define TT_TX_BACKOFF_SIZE 6 173 174/** 175 * struct iwl_tt_params - thermal throttling parameters 176 * @ct_kill_entry: CT Kill entry threshold 177 * @ct_kill_exit: CT Kill exit threshold 178 * @ct_kill_duration: The time intervals (in uSec) in which the driver needs 179 * to checks whether to exit CT Kill. 180 * @dynamic_smps_entry: Dynamic SMPS entry threshold 181 * @dynamic_smps_exit: Dynamic SMPS exit threshold 182 * @tx_protection_entry: TX protection entry threshold 183 * @tx_protection_exit: TX protection exit threshold 184 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order. 185 * @support_ct_kill: Support CT Kill? 186 * @support_dynamic_smps: Support dynamic SMPS? 187 * @support_tx_protection: Support tx protection? 188 * @support_tx_backoff: Support tx-backoff? 189 */ 190struct iwl_tt_params { 191 u32 ct_kill_entry; 192 u32 ct_kill_exit; 193 u32 ct_kill_duration; 194 u32 dynamic_smps_entry; 195 u32 dynamic_smps_exit; 196 u32 tx_protection_entry; 197 u32 tx_protection_exit; 198 struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE]; 199 u8 support_ct_kill:1, 200 support_dynamic_smps:1, 201 support_tx_protection:1, 202 support_tx_backoff:1; 203}; 204 205/* 206 * information on how to parse the EEPROM 207 */ 208#define EEPROM_REG_BAND_1_CHANNELS 0x08 209#define EEPROM_REG_BAND_2_CHANNELS 0x26 210#define EEPROM_REG_BAND_3_CHANNELS 0x42 211#define EEPROM_REG_BAND_4_CHANNELS 0x5C 212#define EEPROM_REG_BAND_5_CHANNELS 0x74 213#define EEPROM_REG_BAND_24_HT40_CHANNELS 0x82 214#define EEPROM_REG_BAND_52_HT40_CHANNELS 0x92 215#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS 0x80 216#define EEPROM_REGULATORY_BAND_NO_HT40 0 217 218/* lower blocks contain EEPROM image and calibration data */ 219#define OTP_LOW_IMAGE_SIZE_2K (2 * 512 * sizeof(u16)) /* 2 KB */ 220#define OTP_LOW_IMAGE_SIZE_16K (16 * 512 * sizeof(u16)) /* 16 KB */ 221#define OTP_LOW_IMAGE_SIZE_32K (32 * 512 * sizeof(u16)) /* 32 KB */ 222 223struct iwl_eeprom_params { 224 const u8 regulatory_bands[7]; 225 bool enhanced_txpower; 226}; 227 228/* Tx-backoff power threshold 229 * @pwr: The power limit in mw 230 * @backoff: The tx-backoff in uSec 231 */ 232struct iwl_pwr_tx_backoff { 233 u32 pwr; 234 u32 backoff; 235}; 236 237enum iwl_cfg_trans_ltr_delay { 238 IWL_CFG_TRANS_LTR_DELAY_NONE = 0, 239 IWL_CFG_TRANS_LTR_DELAY_200US = 1, 240 IWL_CFG_TRANS_LTR_DELAY_2500US = 2, 241 IWL_CFG_TRANS_LTR_DELAY_1820US = 3, 242}; 243 244/** 245 * struct iwl_cfg_trans - information needed to start the trans 246 * 247 * These values are specific to the device ID and do not change when 248 * multiple configs are used for a single device ID. They values are 249 * used, among other things, to boot the NIC so that the HW REV or 250 * RFID can be read before deciding the remaining parameters to use. 251 * 252 * @base_params: pointer to basic parameters 253 * @csr: csr flags and addresses that are different across devices 254 * @device_family: the device family 255 * @umac_prph_offset: offset to add to UMAC periphery address 256 * @xtal_latency: power up latency to get the xtal stabilized 257 * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY 258 * @rf_id: need to read rf_id to determine the firmware image 259 * @gen2: 22000 and on transport operation 260 * @mq_rx_supported: multi-queue rx support 261 * @integrated: discrete or integrated 262 * @low_latency_xtal: use the low latency xtal if supported 263 * @ltr_delay: LTR delay parameter, &enum iwl_cfg_trans_ltr_delay. 264 * @imr_enabled: use the IMR if supported. 265 */ 266struct iwl_cfg_trans_params { 267 const struct iwl_base_params *base_params; 268 enum iwl_device_family device_family; 269 u32 umac_prph_offset; 270 u32 xtal_latency; 271 u32 extra_phy_cfg_flags; 272 u32 rf_id:1, 273 gen2:1, 274 mq_rx_supported:1, 275 integrated:1, 276 low_latency_xtal:1, 277 bisr_workaround:1, 278 ltr_delay:2, 279 imr_enabled:1; 280}; 281 282/** 283 * struct iwl_fw_mon_reg - FW monitor register info 284 * @addr: register address 285 * @mask: register mask 286 */ 287struct iwl_fw_mon_reg { 288 u32 addr; 289 u32 mask; 290}; 291 292/** 293 * struct iwl_fw_mon_regs - FW monitor registers 294 * @write_ptr: write pointer register 295 * @cycle_cnt: cycle count register 296 * @cur_frag: current fragment in use 297 */ 298struct iwl_fw_mon_regs { 299 struct iwl_fw_mon_reg write_ptr; 300 struct iwl_fw_mon_reg cycle_cnt; 301 struct iwl_fw_mon_reg cur_frag; 302}; 303 304/** 305 * struct iwl_cfg 306 * @trans: the trans-specific configuration part 307 * @name: Official name of the device 308 * @fw_name_pre: Firmware filename prefix. The api version and extension 309 * (.ucode) will be added to filename before loading from disk. The 310 * filename is constructed as <fw_name_pre>-<api>.ucode. 311 * @fw_name_mac: MAC name for this config, the remaining pieces of the 312 * name will be generated dynamically 313 * @ucode_api_max: Highest version of uCode API supported by driver. 314 * @ucode_api_min: Lowest version of uCode API supported by driver. 315 * @max_inst_size: The maximal length of the fw inst section (only DVM) 316 * @max_data_size: The maximal length of the fw data section (only DVM) 317 * @valid_tx_ant: valid transmit antenna 318 * @valid_rx_ant: valid receive antenna 319 * @non_shared_ant: the antenna that is for WiFi only 320 * @nvm_ver: NVM version 321 * @nvm_calib_ver: NVM calibration version 322 * @lib: pointer to the lib ops 323 * @ht_params: point to ht parameters 324 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off) 325 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity 326 * @tx_with_siso_diversity: 1x1 device with tx antenna diversity 327 * @internal_wimax_coex: internal wifi/wimax combo device 328 * @high_temp: Is this NIC is designated to be in high temperature. 329 * @host_interrupt_operation_mode: device needs host interrupt operation 330 * mode set 331 * @nvm_hw_section_num: the ID of the HW NVM section 332 * @mac_addr_from_csr: read HW address from CSR registers at this offset 333 * @features: hw features, any combination of feature_passlist 334 * @pwr_tx_backoffs: translation table between power limits and backoffs 335 * @max_tx_agg_size: max TX aggregation size of the ADDBA request/response 336 * @dccm_offset: offset from which DCCM begins 337 * @dccm_len: length of DCCM (including runtime stack CCM) 338 * @dccm2_offset: offset from which the second DCCM begins 339 * @dccm2_len: length of the second DCCM 340 * @smem_offset: offset from which the SMEM begins 341 * @smem_len: the length of SMEM 342 * @vht_mu_mimo_supported: VHT MU-MIMO support 343 * @cdb: CDB support 344 * @nvm_type: see &enum iwl_nvm_type 345 * @d3_debug_data_base_addr: base address where D3 debug data is stored 346 * @d3_debug_data_length: length of the D3 debug data 347 * @bisr_workaround: BISR hardware workaround (for 22260 series devices) 348 * @min_txq_size: minimum number of slots required in a TX queue 349 * @uhb_supported: ultra high band channels supported 350 * @min_ba_txq_size: minimum number of slots required in a TX queue which 351 * based on hardware support (HE - 256, EHT - 1K). 352 * @num_rbds: number of receive buffer descriptors to use 353 * (only used for multi-queue capable devices) 354 * @mac_addr_csr_base: CSR base register for MAC address access, if not set 355 * assume 0x380 356 * 357 * We enable the driver to be backward compatible wrt. hardware features. 358 * API differences in uCode shouldn't be handled here but through TLVs 359 * and/or the uCode API version instead. 360 */ 361struct iwl_cfg { 362 struct iwl_cfg_trans_params trans; 363 /* params specific to an individual device within a device family */ 364 const char *name; 365 const char *fw_name_pre; 366 const char *fw_name_mac; 367 /* params likely to change within a device family */ 368 const struct iwl_ht_params *ht_params; 369 const struct iwl_eeprom_params *eeprom_params; 370 const struct iwl_pwr_tx_backoff *pwr_tx_backoffs; 371 const char *default_nvm_file_C_step; 372 const struct iwl_tt_params *thermal_params; 373 enum iwl_led_mode led_mode; 374 enum iwl_nvm_type nvm_type; 375 u32 max_data_size; 376 u32 max_inst_size; 377 netdev_features_t features; 378 u32 dccm_offset; 379 u32 dccm_len; 380 u32 dccm2_offset; 381 u32 dccm2_len; 382 u32 smem_offset; 383 u32 smem_len; 384 u16 nvm_ver; 385 u16 nvm_calib_ver; 386 u32 rx_with_siso_diversity:1, 387 tx_with_siso_diversity:1, 388 bt_shared_single_ant:1, 389 internal_wimax_coex:1, 390 host_interrupt_operation_mode:1, 391 high_temp:1, 392 mac_addr_from_csr:10, 393 lp_xtal_workaround:1, 394 apmg_not_supported:1, 395 vht_mu_mimo_supported:1, 396 cdb:1, 397 dbgc_supported:1, 398 uhb_supported:1; 399 u8 valid_tx_ant; 400 u8 valid_rx_ant; 401 u8 non_shared_ant; 402 u8 nvm_hw_section_num; 403 u8 max_tx_agg_size; 404 u8 ucode_api_max; 405 u8 ucode_api_min; 406 u16 num_rbds; 407 u32 min_umac_error_event_table; 408 u32 d3_debug_data_base_addr; 409 u32 d3_debug_data_length; 410 u32 min_txq_size; 411 u32 gp2_reg_addr; 412 u32 min_ba_txq_size; 413 const struct iwl_fw_mon_regs mon_dram_regs; 414 const struct iwl_fw_mon_regs mon_smem_regs; 415 const struct iwl_fw_mon_regs mon_dbgi_regs; 416}; 417 418#define IWL_CFG_ANY (~0) 419 420#define IWL_CFG_MAC_TYPE_PU 0x31 421#define IWL_CFG_MAC_TYPE_TH 0x32 422#define IWL_CFG_MAC_TYPE_QU 0x33 423#define IWL_CFG_MAC_TYPE_QUZ 0x35 424#define IWL_CFG_MAC_TYPE_SO 0x37 425#define IWL_CFG_MAC_TYPE_SOF 0x43 426#define IWL_CFG_MAC_TYPE_MA 0x44 427#define IWL_CFG_MAC_TYPE_BZ 0x46 428#define IWL_CFG_MAC_TYPE_GL 0x47 429#define IWL_CFG_MAC_TYPE_SC 0x48 430 431#define IWL_CFG_RF_TYPE_TH 0x105 432#define IWL_CFG_RF_TYPE_TH1 0x108 433#define IWL_CFG_RF_TYPE_JF2 0x105 434#define IWL_CFG_RF_TYPE_JF1 0x108 435#define IWL_CFG_RF_TYPE_HR2 0x10A 436#define IWL_CFG_RF_TYPE_HR1 0x10C 437#define IWL_CFG_RF_TYPE_GF 0x10D 438#define IWL_CFG_RF_TYPE_MR 0x110 439#define IWL_CFG_RF_TYPE_MS 0x111 440#define IWL_CFG_RF_TYPE_FM 0x112 441#define IWL_CFG_RF_TYPE_WH 0x113 442 443#define IWL_CFG_RF_ID_TH 0x1 444#define IWL_CFG_RF_ID_TH1 0x1 445#define IWL_CFG_RF_ID_JF 0x3 446#define IWL_CFG_RF_ID_JF1 0x6 447#define IWL_CFG_RF_ID_JF1_DIV 0xA 448#define IWL_CFG_RF_ID_HR 0x7 449#define IWL_CFG_RF_ID_HR1 0x4 450 451#define IWL_CFG_NO_160 0x1 452#define IWL_CFG_160 0x0 453 454#define IWL_CFG_CORES_BT 0x0 455#define IWL_CFG_CORES_BT_GNSS 0x5 456 457#define IWL_CFG_NO_CDB 0x0 458#define IWL_CFG_CDB 0x1 459 460#define IWL_CFG_NO_JACKET 0x0 461#define IWL_CFG_IS_JACKET 0x1 462 463#define IWL_SUBDEVICE_RF_ID(subdevice) ((u16)((subdevice) & 0x00F0) >> 4) 464#define IWL_SUBDEVICE_NO_160(subdevice) ((u16)((subdevice) & 0x0200) >> 9) 465#define IWL_SUBDEVICE_CORES(subdevice) ((u16)((subdevice) & 0x1C00) >> 10) 466 467struct iwl_dev_info { 468 u16 device; 469 u16 subdevice; 470 u16 mac_type; 471 u16 rf_type; 472 u8 mac_step; 473 u8 rf_step; 474 u8 rf_id; 475 u8 no_160; 476 u8 cores; 477 u8 cdb; 478 u8 jacket; 479 const struct iwl_cfg *cfg; 480 const char *name; 481}; 482 483/* 484 * This list declares the config structures for all devices. 485 */ 486extern const struct iwl_cfg_trans_params iwl9000_trans_cfg; 487extern const struct iwl_cfg_trans_params iwl9560_trans_cfg; 488extern const struct iwl_cfg_trans_params iwl9560_long_latency_trans_cfg; 489extern const struct iwl_cfg_trans_params iwl9560_shared_clk_trans_cfg; 490extern const struct iwl_cfg_trans_params iwl_qu_trans_cfg; 491extern const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg; 492extern const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg; 493extern const struct iwl_cfg_trans_params iwl_ax200_trans_cfg; 494extern const struct iwl_cfg_trans_params iwl_so_trans_cfg; 495extern const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg; 496extern const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg; 497extern const struct iwl_cfg_trans_params iwl_ma_trans_cfg; 498extern const struct iwl_cfg_trans_params iwl_bz_trans_cfg; 499extern const struct iwl_cfg_trans_params iwl_sc_trans_cfg; 500extern const char iwl9162_name[]; 501extern const char iwl9260_name[]; 502extern const char iwl9260_1_name[]; 503extern const char iwl9270_name[]; 504extern const char iwl9461_name[]; 505extern const char iwl9462_name[]; 506extern const char iwl9560_name[]; 507extern const char iwl9162_160_name[]; 508extern const char iwl9260_160_name[]; 509extern const char iwl9270_160_name[]; 510extern const char iwl9461_160_name[]; 511extern const char iwl9462_160_name[]; 512extern const char iwl9560_160_name[]; 513extern const char iwl9260_killer_1550_name[]; 514extern const char iwl9560_killer_1550i_name[]; 515extern const char iwl9560_killer_1550s_name[]; 516extern const char iwl_ax200_name[]; 517extern const char iwl_ax203_name[]; 518extern const char iwl_ax204_name[]; 519extern const char iwl_ax201_name[]; 520extern const char iwl_ax101_name[]; 521extern const char iwl_ax200_killer_1650w_name[]; 522extern const char iwl_ax200_killer_1650x_name[]; 523extern const char iwl_ax201_killer_1650s_name[]; 524extern const char iwl_ax201_killer_1650i_name[]; 525extern const char iwl_ax210_killer_1675w_name[]; 526extern const char iwl_ax210_killer_1675x_name[]; 527extern const char iwl9560_killer_1550i_160_name[]; 528extern const char iwl9560_killer_1550s_160_name[]; 529extern const char iwl_ax211_killer_1675s_name[]; 530extern const char iwl_ax211_killer_1675i_name[]; 531extern const char iwl_ax411_killer_1690s_name[]; 532extern const char iwl_ax411_killer_1690i_name[]; 533extern const char iwl_ax211_name[]; 534extern const char iwl_ax221_name[]; 535extern const char iwl_ax231_name[]; 536extern const char iwl_ax411_name[]; 537extern const char iwl_bz_name[]; 538extern const char iwl_sc_name[]; 539#if IS_ENABLED(CONFIG_IWLDVM) 540extern const struct iwl_cfg iwl5300_agn_cfg; 541extern const struct iwl_cfg iwl5100_agn_cfg; 542extern const struct iwl_cfg iwl5350_agn_cfg; 543extern const struct iwl_cfg iwl5100_bgn_cfg; 544extern const struct iwl_cfg iwl5100_abg_cfg; 545extern const struct iwl_cfg iwl5150_agn_cfg; 546extern const struct iwl_cfg iwl5150_abg_cfg; 547extern const struct iwl_cfg iwl6005_2agn_cfg; 548extern const struct iwl_cfg iwl6005_2abg_cfg; 549extern const struct iwl_cfg iwl6005_2bg_cfg; 550extern const struct iwl_cfg iwl6005_2agn_sff_cfg; 551extern const struct iwl_cfg iwl6005_2agn_d_cfg; 552extern const struct iwl_cfg iwl6005_2agn_mow1_cfg; 553extern const struct iwl_cfg iwl6005_2agn_mow2_cfg; 554extern const struct iwl_cfg iwl1030_bgn_cfg; 555extern const struct iwl_cfg iwl1030_bg_cfg; 556extern const struct iwl_cfg iwl6030_2agn_cfg; 557extern const struct iwl_cfg iwl6030_2abg_cfg; 558extern const struct iwl_cfg iwl6030_2bgn_cfg; 559extern const struct iwl_cfg iwl6030_2bg_cfg; 560extern const struct iwl_cfg iwl6000i_2agn_cfg; 561extern const struct iwl_cfg iwl6000i_2abg_cfg; 562extern const struct iwl_cfg iwl6000i_2bg_cfg; 563extern const struct iwl_cfg iwl6000_3agn_cfg; 564extern const struct iwl_cfg iwl6050_2agn_cfg; 565extern const struct iwl_cfg iwl6050_2abg_cfg; 566extern const struct iwl_cfg iwl6150_bgn_cfg; 567extern const struct iwl_cfg iwl6150_bg_cfg; 568extern const struct iwl_cfg iwl1000_bgn_cfg; 569extern const struct iwl_cfg iwl1000_bg_cfg; 570extern const struct iwl_cfg iwl100_bgn_cfg; 571extern const struct iwl_cfg iwl100_bg_cfg; 572extern const struct iwl_cfg iwl130_bgn_cfg; 573extern const struct iwl_cfg iwl130_bg_cfg; 574extern const struct iwl_cfg iwl2000_2bgn_cfg; 575extern const struct iwl_cfg iwl2000_2bgn_d_cfg; 576extern const struct iwl_cfg iwl2030_2bgn_cfg; 577extern const struct iwl_cfg iwl6035_2agn_cfg; 578extern const struct iwl_cfg iwl6035_2agn_sff_cfg; 579extern const struct iwl_cfg iwl105_bgn_cfg; 580extern const struct iwl_cfg iwl105_bgn_d_cfg; 581extern const struct iwl_cfg iwl135_bgn_cfg; 582#endif /* CONFIG_IWLDVM */ 583#if IS_ENABLED(CONFIG_IWLMVM) 584extern const struct iwl_ht_params iwl_22000_ht_params; 585extern const struct iwl_cfg iwl7260_2ac_cfg; 586extern const struct iwl_cfg iwl7260_2ac_cfg_high_temp; 587extern const struct iwl_cfg iwl7260_2n_cfg; 588extern const struct iwl_cfg iwl7260_n_cfg; 589extern const struct iwl_cfg iwl3160_2ac_cfg; 590extern const struct iwl_cfg iwl3160_2n_cfg; 591extern const struct iwl_cfg iwl3160_n_cfg; 592extern const struct iwl_cfg iwl3165_2ac_cfg; 593extern const struct iwl_cfg iwl3168_2ac_cfg; 594extern const struct iwl_cfg iwl7265_2ac_cfg; 595extern const struct iwl_cfg iwl7265_2n_cfg; 596extern const struct iwl_cfg iwl7265_n_cfg; 597extern const struct iwl_cfg iwl7265d_2ac_cfg; 598extern const struct iwl_cfg iwl7265d_2n_cfg; 599extern const struct iwl_cfg iwl7265d_n_cfg; 600extern const struct iwl_cfg iwl8260_2n_cfg; 601extern const struct iwl_cfg iwl8260_2ac_cfg; 602extern const struct iwl_cfg iwl8265_2ac_cfg; 603extern const struct iwl_cfg iwl8275_2ac_cfg; 604extern const struct iwl_cfg iwl4165_2ac_cfg; 605extern const struct iwl_cfg iwl9260_2ac_cfg; 606extern const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg; 607extern const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg; 608extern const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg; 609extern const struct iwl_cfg iwl9560_2ac_cfg_soc; 610extern const struct iwl_cfg iwl_qu_b0_hr1_b0; 611extern const struct iwl_cfg iwl_qu_c0_hr1_b0; 612extern const struct iwl_cfg iwl_quz_a0_hr1_b0; 613extern const struct iwl_cfg iwl_qu_b0_hr_b0; 614extern const struct iwl_cfg iwl_qu_c0_hr_b0; 615extern const struct iwl_cfg iwl_ax200_cfg_cc; 616extern const struct iwl_cfg iwl_ax201_cfg_qu_hr; 617extern const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0; 618extern const struct iwl_cfg iwl_ax201_cfg_quz_hr; 619extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr; 620extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr; 621extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0; 622extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0; 623extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0; 624extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0; 625extern const struct iwl_cfg killer1650x_2ax_cfg; 626extern const struct iwl_cfg killer1650w_2ax_cfg; 627extern const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0; 628extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0; 629extern const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long; 630extern const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0; 631extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0; 632extern const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long; 633 634extern const struct iwl_cfg iwl_cfg_ma; 635 636extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0; 637extern const struct iwl_cfg iwl_cfg_so_a0_ms_a0; 638extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0; 639 640extern const struct iwl_cfg iwl_cfg_bz; 641extern const struct iwl_cfg iwl_cfg_gl; 642 643extern const struct iwl_cfg iwl_cfg_sc; 644#endif /* CONFIG_IWLMVM */ 645 646#endif /* __IWL_CONFIG_H__ */ 647