1// SPDX-License-Identifier: BSD-3-Clause-Clear 2/* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6#include "debug.h" 7#include "hal.h" 8#include "hal_tx.h" 9#include "hal_rx.h" 10#include "hal_desc.h" 11#include "hif.h" 12 13static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, 14 u8 owner, u8 buffer_type, u32 magic) 15{ 16 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) | 17 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type); 18 19 /* Magic pattern in reserved bits for debugging */ 20 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic); 21} 22 23static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv, 24 struct ath11k_hal_reo_cmd *cmd) 25{ 26 struct hal_reo_get_queue_stats *desc; 27 28 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) | 29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 30 31 desc = (struct hal_reo_get_queue_stats *)tlv->value; 32 memset_startat(desc, 0, queue_addr_lo); 33 34 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 35 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 36 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 37 38 desc->queue_addr_lo = cmd->addr_lo; 39 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI, 40 cmd->addr_hi); 41 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR) 42 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS; 43 44 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 45} 46 47static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv, 48 struct ath11k_hal_reo_cmd *cmd) 49{ 50 struct hal_reo_flush_cache *desc; 51 u8 avail_slot = ffz(hal->avail_blk_resource); 52 53 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 54 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES) 55 return -ENOSPC; 56 57 hal->current_blk_index = avail_slot; 58 } 59 60 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) | 61 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 62 63 desc = (struct hal_reo_flush_cache *)tlv->value; 64 memset_startat(desc, 0, cache_addr_lo); 65 66 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 67 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 68 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 69 70 desc->cache_addr_lo = cmd->addr_lo; 71 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI, 72 cmd->addr_hi); 73 74 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS) 75 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS; 76 77 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 78 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE; 79 desc->info0 |= 80 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX, 81 avail_slot); 82 } 83 84 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL) 85 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE; 86 87 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 88 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL; 89 90 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 91} 92 93static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv, 94 struct ath11k_hal_reo_cmd *cmd) 95{ 96 struct hal_reo_update_rx_queue *desc; 97 98 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) | 99 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); 100 101 desc = (struct hal_reo_update_rx_queue *)tlv->value; 102 memset_startat(desc, 0, queue_addr_lo); 103 104 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 105 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 106 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED; 107 108 desc->queue_addr_lo = cmd->addr_lo; 109 desc->info0 = 110 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI, 111 cmd->addr_hi) | 112 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM, 113 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) | 114 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD, 115 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) | 116 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT, 117 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) | 118 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION, 119 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) | 120 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN, 121 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) | 122 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC, 123 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) | 124 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR, 125 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) | 126 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY, 127 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) | 128 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE, 129 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) | 130 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE, 131 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) | 132 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE, 133 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) | 134 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK, 135 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) | 136 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN, 137 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) | 138 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN, 139 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) | 140 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE, 141 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) | 142 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE, 143 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) | 144 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG, 145 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) | 146 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD, 147 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) | 148 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN, 149 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) | 150 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR, 151 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) | 152 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID, 153 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) | 154 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN, 155 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN)); 156 157 desc->info1 = 158 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER, 159 cmd->rx_queue_num) | 160 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD, 161 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) | 162 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER, 163 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) | 164 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION, 165 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) | 166 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN, 167 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) | 168 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC, 169 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) | 170 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR, 171 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) | 172 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE, 173 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) | 174 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY, 175 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) | 176 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE, 177 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) | 178 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK, 179 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) | 180 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN, 181 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) | 182 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN, 183 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) | 184 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE, 185 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) | 186 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG, 187 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG)); 188 189 if (cmd->pn_size == 24) 190 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24; 191 else if (cmd->pn_size == 48) 192 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48; 193 else if (cmd->pn_size == 128) 194 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128; 195 196 if (cmd->ba_window_size < 1) 197 cmd->ba_window_size = 1; 198 199 if (cmd->ba_window_size == 1) 200 cmd->ba_window_size++; 201 202 desc->info2 = 203 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE, 204 cmd->ba_window_size - 1) | 205 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) | 206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD, 207 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) | 208 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN, 209 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) | 210 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR, 211 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) | 212 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR, 213 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR)); 214 215 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0); 216} 217 218int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng, 219 enum hal_reo_cmd_type type, 220 struct ath11k_hal_reo_cmd *cmd) 221{ 222 struct hal_tlv_hdr *reo_desc; 223 int ret; 224 225 spin_lock_bh(&srng->lock); 226 227 ath11k_hal_srng_access_begin(ab, srng); 228 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng); 229 if (!reo_desc) { 230 ret = -ENOBUFS; 231 goto out; 232 } 233 234 switch (type) { 235 case HAL_REO_CMD_GET_QUEUE_STATS: 236 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd); 237 break; 238 case HAL_REO_CMD_FLUSH_CACHE: 239 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd); 240 break; 241 case HAL_REO_CMD_UPDATE_RX_QUEUE: 242 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd); 243 break; 244 case HAL_REO_CMD_FLUSH_QUEUE: 245 case HAL_REO_CMD_UNBLOCK_CACHE: 246 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST: 247 ath11k_warn(ab, "Unsupported reo command %d\n", type); 248 ret = -ENOTSUPP; 249 break; 250 default: 251 ath11k_warn(ab, "Unknown reo command %d\n", type); 252 ret = -EINVAL; 253 break; 254 } 255 256 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer); 257 258out: 259 ath11k_hal_srng_access_end(ab, srng); 260 spin_unlock_bh(&srng->lock); 261 262 return ret; 263} 264 265void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr, 266 u32 cookie, u8 manager) 267{ 268 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc; 269 u32 paddr_lo, paddr_hi; 270 271 paddr_lo = lower_32_bits(paddr); 272 paddr_hi = upper_32_bits(paddr); 273 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo); 274 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) | 275 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) | 276 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager); 277} 278 279void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr, 280 u32 *cookie, u8 *rbm) 281{ 282 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc; 283 284 *paddr = 285 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) | 286 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0); 287 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1); 288 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1); 289} 290 291void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus, 292 u32 *msdu_cookies, 293 enum hal_rx_buf_return_buf_manager *rbm) 294{ 295 struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc; 296 struct hal_rx_msdu_details *msdu; 297 int i; 298 299 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC; 300 301 msdu = &link->msdu_link[0]; 302 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 303 msdu->buf_addr_info.info1); 304 305 for (i = 0; i < *num_msdus; i++) { 306 msdu = &link->msdu_link[i]; 307 308 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 309 msdu->buf_addr_info.info0)) { 310 *num_msdus = i; 311 break; 312 } 313 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 314 msdu->buf_addr_info.info1); 315 msdu_cookies++; 316 } 317} 318 319int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc, 320 dma_addr_t *paddr, u32 *desc_bank) 321{ 322 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc; 323 enum hal_reo_dest_ring_push_reason push_reason; 324 enum hal_reo_dest_ring_error_code err_code; 325 326 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON, 327 desc->info0); 328 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE, 329 desc->info0); 330 ab->soc_stats.reo_error[err_code]++; 331 332 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED && 333 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 334 ath11k_warn(ab, "expected error push reason code, received %d\n", 335 push_reason); 336 return -EINVAL; 337 } 338 339 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) != 340 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) { 341 ath11k_warn(ab, "expected buffer type link_desc"); 342 return -EINVAL; 343 } 344 345 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank); 346 347 return 0; 348} 349 350int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc, 351 struct hal_rx_wbm_rel_info *rel_info) 352{ 353 struct hal_wbm_release_ring *wbm_desc = desc; 354 enum hal_wbm_rel_desc_type type; 355 enum hal_wbm_rel_src_module rel_src; 356 enum hal_rx_buf_return_buf_manager ret_buf_mgr; 357 358 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE, 359 wbm_desc->info0); 360 /* We expect only WBM_REL buffer type */ 361 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) { 362 WARN_ON(1); 363 return -EINVAL; 364 } 365 366 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, 367 wbm_desc->info0); 368 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA && 369 rel_src != HAL_WBM_REL_SRC_MODULE_REO) 370 return -EINVAL; 371 372 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 373 wbm_desc->buf_addr_info.info1); 374 if (ret_buf_mgr != HAL_RX_BUF_RBM_SW3_BM) { 375 ab->soc_stats.invalid_rbm++; 376 return -EINVAL; 377 } 378 379 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 380 wbm_desc->buf_addr_info.info1); 381 rel_info->err_rel_src = rel_src; 382 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) { 383 rel_info->push_reason = 384 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON, 385 wbm_desc->info0); 386 rel_info->err_code = 387 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE, 388 wbm_desc->info0); 389 } else { 390 rel_info->push_reason = 391 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON, 392 wbm_desc->info0); 393 rel_info->err_code = 394 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE, 395 wbm_desc->info0); 396 } 397 398 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU, 399 wbm_desc->info2); 400 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU, 401 wbm_desc->info2); 402 return 0; 403} 404 405void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc, 406 dma_addr_t *paddr, u32 *desc_bank) 407{ 408 struct ath11k_buffer_addr *buff_addr = desc; 409 410 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) | 411 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0); 412 413 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1); 414} 415 416void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc, 417 void *link_desc, 418 enum hal_wbm_rel_bm_act action) 419{ 420 struct hal_wbm_release_ring *dst_desc = desc; 421 struct hal_wbm_release_ring *src_desc = link_desc; 422 423 dst_desc->buf_addr_info = src_desc->buf_addr_info; 424 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, 425 HAL_WBM_REL_SRC_MODULE_SW) | 426 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) | 427 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE, 428 HAL_WBM_REL_DESC_TYPE_MSDU_LINK); 429} 430 431void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc, 432 struct hal_reo_status *status) 433{ 434 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 435 struct hal_reo_get_queue_stats_status *desc = 436 (struct hal_reo_get_queue_stats_status *)tlv->value; 437 438 status->uniform_hdr.cmd_num = 439 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 440 desc->hdr.info0); 441 status->uniform_hdr.cmd_status = 442 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 443 desc->hdr.info0); 444 445 ath11k_dbg(ab, ATH11K_DBG_HAL, "Queue stats status:\n"); 446 ath11k_dbg(ab, ATH11K_DBG_HAL, "header: cmd_num %d status %d\n", 447 status->uniform_hdr.cmd_num, 448 status->uniform_hdr.cmd_status); 449 ath11k_dbg(ab, ATH11K_DBG_HAL, "ssn %ld cur_idx %ld\n", 450 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN, 451 desc->info0), 452 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX, 453 desc->info0)); 454 ath11k_dbg(ab, ATH11K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n", 455 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]); 456 ath11k_dbg(ab, ATH11K_DBG_HAL, 457 "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n", 458 desc->last_rx_enqueue_timestamp, 459 desc->last_rx_dequeue_timestamp); 460 ath11k_dbg(ab, ATH11K_DBG_HAL, 461 "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n", 462 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2], 463 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5], 464 desc->rx_bitmap[6], desc->rx_bitmap[7]); 465 ath11k_dbg(ab, ATH11K_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n", 466 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT, 467 desc->info1), 468 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT, 469 desc->info1)); 470 ath11k_dbg(ab, ATH11K_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n", 471 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT, 472 desc->info2), 473 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT, 474 desc->info2), 475 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT, 476 desc->info2)); 477 ath11k_dbg(ab, ATH11K_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n", 478 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT, 479 desc->info3), 480 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT, 481 desc->info3)); 482 ath11k_dbg(ab, ATH11K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n", 483 desc->num_mpdu_frames, desc->num_msdu_frames, 484 desc->total_bytes); 485 ath11k_dbg(ab, ATH11K_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n", 486 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU, 487 desc->info4), 488 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K, 489 desc->info4), 490 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT, 491 desc->info4)); 492 ath11k_dbg(ab, ATH11K_DBG_HAL, "looping count %ld\n", 493 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT, 494 desc->info5)); 495} 496 497int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status) 498{ 499 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 500 struct hal_reo_status_hdr *hdr; 501 502 hdr = (struct hal_reo_status_hdr *)tlv->value; 503 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0); 504 505 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0); 506} 507 508void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc, 509 struct hal_reo_status *status) 510{ 511 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 512 struct hal_reo_flush_queue_status *desc = 513 (struct hal_reo_flush_queue_status *)tlv->value; 514 515 status->uniform_hdr.cmd_num = 516 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 517 desc->hdr.info0); 518 status->uniform_hdr.cmd_status = 519 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 520 desc->hdr.info0); 521 status->u.flush_queue.err_detected = 522 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED, 523 desc->info0); 524} 525 526void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc, 527 struct hal_reo_status *status) 528{ 529 struct ath11k_hal *hal = &ab->hal; 530 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 531 struct hal_reo_flush_cache_status *desc = 532 (struct hal_reo_flush_cache_status *)tlv->value; 533 534 status->uniform_hdr.cmd_num = 535 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 536 desc->hdr.info0); 537 status->uniform_hdr.cmd_status = 538 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 539 desc->hdr.info0); 540 541 status->u.flush_cache.err_detected = 542 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR, 543 desc->info0); 544 status->u.flush_cache.err_code = 545 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE, 546 desc->info0); 547 if (!status->u.flush_cache.err_code) 548 hal->avail_blk_resource |= BIT(hal->current_blk_index); 549 550 status->u.flush_cache.cache_controller_flush_status_hit = 551 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT, 552 desc->info0); 553 554 status->u.flush_cache.cache_controller_flush_status_desc_type = 555 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE, 556 desc->info0); 557 status->u.flush_cache.cache_controller_flush_status_client_id = 558 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID, 559 desc->info0); 560 status->u.flush_cache.cache_controller_flush_status_err = 561 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR, 562 desc->info0); 563 status->u.flush_cache.cache_controller_flush_status_cnt = 564 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT, 565 desc->info0); 566} 567 568void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc, 569 struct hal_reo_status *status) 570{ 571 struct ath11k_hal *hal = &ab->hal; 572 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 573 struct hal_reo_unblock_cache_status *desc = 574 (struct hal_reo_unblock_cache_status *)tlv->value; 575 576 status->uniform_hdr.cmd_num = 577 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 578 desc->hdr.info0); 579 status->uniform_hdr.cmd_status = 580 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 581 desc->hdr.info0); 582 583 status->u.unblock_cache.err_detected = 584 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR, 585 desc->info0); 586 status->u.unblock_cache.unblock_type = 587 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE, 588 desc->info0); 589 590 if (!status->u.unblock_cache.err_detected && 591 status->u.unblock_cache.unblock_type == 592 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE) 593 hal->avail_blk_resource &= ~BIT(hal->current_blk_index); 594} 595 596void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab, 597 u32 *reo_desc, 598 struct hal_reo_status *status) 599{ 600 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 601 struct hal_reo_flush_timeout_list_status *desc = 602 (struct hal_reo_flush_timeout_list_status *)tlv->value; 603 604 status->uniform_hdr.cmd_num = 605 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 606 desc->hdr.info0); 607 status->uniform_hdr.cmd_status = 608 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 609 desc->hdr.info0); 610 611 status->u.timeout_list.err_detected = 612 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR, 613 desc->info0); 614 status->u.timeout_list.list_empty = 615 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY, 616 desc->info0); 617 618 status->u.timeout_list.release_desc_cnt = 619 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT, 620 desc->info1); 621 status->u.timeout_list.fwd_buf_cnt = 622 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT, 623 desc->info1); 624} 625 626void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab, 627 u32 *reo_desc, 628 struct hal_reo_status *status) 629{ 630 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 631 struct hal_reo_desc_thresh_reached_status *desc = 632 (struct hal_reo_desc_thresh_reached_status *)tlv->value; 633 634 status->uniform_hdr.cmd_num = 635 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 636 desc->hdr.info0); 637 status->uniform_hdr.cmd_status = 638 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 639 desc->hdr.info0); 640 641 status->u.desc_thresh_reached.threshold_idx = 642 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX, 643 desc->info0); 644 645 status->u.desc_thresh_reached.link_desc_counter0 = 646 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0, 647 desc->info1); 648 649 status->u.desc_thresh_reached.link_desc_counter1 = 650 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1, 651 desc->info2); 652 653 status->u.desc_thresh_reached.link_desc_counter2 = 654 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2, 655 desc->info3); 656 657 status->u.desc_thresh_reached.link_desc_counter_sum = 658 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM, 659 desc->info4); 660} 661 662void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab, 663 u32 *reo_desc, 664 struct hal_reo_status *status) 665{ 666 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc; 667 struct hal_reo_status_hdr *desc = 668 (struct hal_reo_status_hdr *)tlv->value; 669 670 status->uniform_hdr.cmd_num = 671 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, 672 desc->info0); 673 status->uniform_hdr.cmd_status = 674 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, 675 desc->info0); 676} 677 678u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) 679{ 680 u32 num_ext_desc; 681 682 if (ba_window_size <= 1) { 683 if (tid != HAL_DESC_REO_NON_QOS_TID) 684 num_ext_desc = 1; 685 else 686 num_ext_desc = 0; 687 } else if (ba_window_size <= 105) { 688 num_ext_desc = 1; 689 } else if (ba_window_size <= 210) { 690 num_ext_desc = 2; 691 } else { 692 num_ext_desc = 3; 693 } 694 695 return sizeof(struct hal_rx_reo_queue) + 696 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)); 697} 698 699void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 700 u32 start_seq, enum hal_pn_type type) 701{ 702 struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr; 703 struct hal_rx_reo_queue_ext *ext_desc; 704 705 memset(qdesc, 0, sizeof(*qdesc)); 706 707 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, 708 HAL_DESC_REO_QUEUE_DESC, 709 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); 710 711 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid); 712 713 qdesc->info0 = 714 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) | 715 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) | 716 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid)); 717 718 if (ba_window_size < 1) 719 ba_window_size = 1; 720 721 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID) 722 ba_window_size++; 723 724 if (ba_window_size == 1) 725 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1); 726 727 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE, 728 ba_window_size - 1); 729 switch (type) { 730 case HAL_PN_TYPE_NONE: 731 case HAL_PN_TYPE_WAPI_EVEN: 732 case HAL_PN_TYPE_WAPI_UNEVEN: 733 break; 734 case HAL_PN_TYPE_WPA: 735 qdesc->info0 |= 736 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) | 737 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE, 738 HAL_RX_REO_QUEUE_PN_SIZE_48); 739 break; 740 } 741 742 /* TODO: Set Ignore ampdu flags based on BA window size and/or 743 * AMPDU capabilities 744 */ 745 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1); 746 747 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0); 748 749 if (start_seq <= 0xfff) 750 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN, 751 start_seq); 752 753 if (tid == HAL_DESC_REO_NON_QOS_TID) 754 return; 755 756 ext_desc = qdesc->ext_desc; 757 758 /* TODO: HW queue descriptors are currently allocated for max BA 759 * window size for all QOS TIDs so that same descriptor can be used 760 * later when ADDBA request is received. This should be changed to 761 * allocate HW queue descriptors based on BA window size being 762 * negotiated (0 for non BA cases), and reallocate when BA window 763 * size changes and also send WMI message to FW to change the REO 764 * queue descriptor in Rx peer entry as part of dp_rx_tid_update. 765 */ 766 memset(ext_desc, 0, sizeof(*ext_desc)); 767 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 768 HAL_DESC_REO_QUEUE_EXT_DESC, 769 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); 770 ext_desc++; 771 memset(ext_desc, 0, sizeof(*ext_desc)); 772 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 773 HAL_DESC_REO_QUEUE_EXT_DESC, 774 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); 775 ext_desc++; 776 memset(ext_desc, 0, sizeof(*ext_desc)); 777 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 778 HAL_DESC_REO_QUEUE_EXT_DESC, 779 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); 780} 781 782void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 783 struct hal_srng *srng) 784{ 785 struct hal_srng_params params; 786 struct hal_tlv_hdr *tlv; 787 struct hal_reo_get_queue_stats *desc; 788 int i, cmd_num = 1; 789 int entry_size; 790 u8 *entry; 791 792 memset(¶ms, 0, sizeof(params)); 793 794 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 795 ath11k_hal_srng_get_params(ab, srng, ¶ms); 796 entry = (u8 *)params.ring_base_vaddr; 797 798 for (i = 0; i < params.num_entries; i++) { 799 tlv = (struct hal_tlv_hdr *)entry; 800 desc = (struct hal_reo_get_queue_stats *)tlv->value; 801 desc->cmd.info0 = 802 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++); 803 entry += entry_size; 804 } 805} 806 807#define HAL_MAX_UL_MU_USERS 37 808static inline void 809ath11k_hal_rx_handle_ofdma_info(void *rx_tlv, 810 struct hal_rx_user_status *rx_user_status) 811{ 812 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = 813 (struct hal_rx_ppdu_end_user_stats *)rx_tlv; 814 815 rx_user_status->ul_ofdma_user_v0_word0 = __le32_to_cpu(ppdu_end_user->info6); 816 817 rx_user_status->ul_ofdma_user_v0_word1 = __le32_to_cpu(ppdu_end_user->rsvd2[10]); 818} 819 820static inline void 821ath11k_hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 822 struct hal_rx_user_status *rx_user_status) 823{ 824 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = 825 (struct hal_rx_ppdu_end_user_stats *)rx_tlv; 826 827 rx_user_status->mpdu_ok_byte_count = 828 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_6_MPDU_OK_BYTE_COUNT, 829 __le32_to_cpu(ppdu_end_user->rsvd2[6])); 830 rx_user_status->mpdu_err_byte_count = 831 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_RSVD2_8_MPDU_ERR_BYTE_COUNT, 832 __le32_to_cpu(ppdu_end_user->rsvd2[8])); 833} 834 835static inline void 836ath11k_hal_rx_populate_mu_user_info(void *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info, 837 struct hal_rx_user_status *rx_user_status) 838{ 839 rx_user_status->ast_index = ppdu_info->ast_index; 840 rx_user_status->tid = ppdu_info->tid; 841 rx_user_status->tcp_msdu_count = 842 ppdu_info->tcp_msdu_count; 843 rx_user_status->udp_msdu_count = 844 ppdu_info->udp_msdu_count; 845 rx_user_status->other_msdu_count = 846 ppdu_info->other_msdu_count; 847 rx_user_status->frame_control = ppdu_info->frame_control; 848 rx_user_status->frame_control_info_valid = 849 ppdu_info->frame_control_info_valid; 850 rx_user_status->data_sequence_control_info_valid = 851 ppdu_info->data_sequence_control_info_valid; 852 rx_user_status->first_data_seq_ctrl = 853 ppdu_info->first_data_seq_ctrl; 854 rx_user_status->preamble_type = ppdu_info->preamble_type; 855 rx_user_status->ht_flags = ppdu_info->ht_flags; 856 rx_user_status->vht_flags = ppdu_info->vht_flags; 857 rx_user_status->he_flags = ppdu_info->he_flags; 858 rx_user_status->rs_flags = ppdu_info->rs_flags; 859 860 rx_user_status->mpdu_cnt_fcs_ok = 861 ppdu_info->num_mpdu_fcs_ok; 862 rx_user_status->mpdu_cnt_fcs_err = 863 ppdu_info->num_mpdu_fcs_err; 864 865 ath11k_hal_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); 866} 867 868static u16 ath11k_hal_rx_mpduinfo_get_peerid(struct ath11k_base *ab, 869 struct hal_rx_mpdu_info *mpdu_info) 870{ 871 return ab->hw_params.hw_ops->mpdu_info_get_peerid(mpdu_info); 872} 873 874static enum hal_rx_mon_status 875ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab, 876 struct hal_rx_mon_ppdu_info *ppdu_info, 877 u32 tlv_tag, u8 *tlv_data, u32 userid) 878{ 879 u32 info0, info1, value; 880 u8 he_dcm = 0, he_stbc = 0; 881 u16 he_gi = 0, he_ltf = 0; 882 883 switch (tlv_tag) { 884 case HAL_RX_PPDU_START: { 885 struct hal_rx_ppdu_start *ppdu_start = 886 (struct hal_rx_ppdu_start *)tlv_data; 887 888 ppdu_info->ppdu_id = 889 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID, 890 __le32_to_cpu(ppdu_start->info0)); 891 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num); 892 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts); 893 break; 894 } 895 case HAL_RX_PPDU_END_USER_STATS: { 896 struct hal_rx_ppdu_end_user_stats *eu_stats = 897 (struct hal_rx_ppdu_end_user_stats *)tlv_data; 898 899 info0 = __le32_to_cpu(eu_stats->info0); 900 info1 = __le32_to_cpu(eu_stats->info1); 901 902 ppdu_info->ast_index = 903 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX, 904 __le32_to_cpu(eu_stats->info2)); 905 ppdu_info->tid = 906 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP, 907 __le32_to_cpu(eu_stats->info6))) - 1; 908 ppdu_info->tcp_msdu_count = 909 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT, 910 __le32_to_cpu(eu_stats->info4)); 911 ppdu_info->udp_msdu_count = 912 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT, 913 __le32_to_cpu(eu_stats->info4)); 914 ppdu_info->other_msdu_count = 915 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT, 916 __le32_to_cpu(eu_stats->info5)); 917 ppdu_info->tcp_ack_msdu_count = 918 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT, 919 __le32_to_cpu(eu_stats->info5)); 920 ppdu_info->preamble_type = 921 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1); 922 ppdu_info->num_mpdu_fcs_ok = 923 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK, 924 info1); 925 ppdu_info->num_mpdu_fcs_err = 926 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR, 927 info0); 928 switch (ppdu_info->preamble_type) { 929 case HAL_RX_PREAMBLE_11N: 930 ppdu_info->ht_flags = 1; 931 break; 932 case HAL_RX_PREAMBLE_11AC: 933 ppdu_info->vht_flags = 1; 934 break; 935 case HAL_RX_PREAMBLE_11AX: 936 ppdu_info->he_flags = 1; 937 break; 938 default: 939 break; 940 } 941 942 if (userid < HAL_MAX_UL_MU_USERS) { 943 struct hal_rx_user_status *rxuser_stats = 944 &ppdu_info->userstats; 945 946 ath11k_hal_rx_handle_ofdma_info(tlv_data, rxuser_stats); 947 ath11k_hal_rx_populate_mu_user_info(tlv_data, ppdu_info, 948 rxuser_stats); 949 } 950 ppdu_info->userstats.mpdu_fcs_ok_bitmap[0] = 951 __le32_to_cpu(eu_stats->rsvd1[0]); 952 ppdu_info->userstats.mpdu_fcs_ok_bitmap[1] = 953 __le32_to_cpu(eu_stats->rsvd1[1]); 954 955 break; 956 } 957 case HAL_RX_PPDU_END_USER_STATS_EXT: { 958 struct hal_rx_ppdu_end_user_stats_ext *eu_stats = 959 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data; 960 ppdu_info->userstats.mpdu_fcs_ok_bitmap[2] = eu_stats->info1; 961 ppdu_info->userstats.mpdu_fcs_ok_bitmap[3] = eu_stats->info2; 962 ppdu_info->userstats.mpdu_fcs_ok_bitmap[4] = eu_stats->info3; 963 ppdu_info->userstats.mpdu_fcs_ok_bitmap[5] = eu_stats->info4; 964 ppdu_info->userstats.mpdu_fcs_ok_bitmap[6] = eu_stats->info5; 965 ppdu_info->userstats.mpdu_fcs_ok_bitmap[7] = eu_stats->info6; 966 break; 967 } 968 case HAL_PHYRX_HT_SIG: { 969 struct hal_rx_ht_sig_info *ht_sig = 970 (struct hal_rx_ht_sig_info *)tlv_data; 971 972 info0 = __le32_to_cpu(ht_sig->info0); 973 info1 = __le32_to_cpu(ht_sig->info1); 974 975 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0); 976 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0); 977 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC, 978 info1); 979 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1); 980 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI; 981 982 switch (ppdu_info->mcs) { 983 case 0 ... 7: 984 ppdu_info->nss = 1; 985 break; 986 case 8 ... 15: 987 ppdu_info->nss = 2; 988 break; 989 case 16 ... 23: 990 ppdu_info->nss = 3; 991 break; 992 case 24 ... 31: 993 ppdu_info->nss = 4; 994 break; 995 } 996 997 if (ppdu_info->nss > 1) 998 ppdu_info->mcs = ppdu_info->mcs % 8; 999 1000 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1001 break; 1002 } 1003 case HAL_PHYRX_L_SIG_B: { 1004 struct hal_rx_lsig_b_info *lsigb = 1005 (struct hal_rx_lsig_b_info *)tlv_data; 1006 1007 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE, 1008 __le32_to_cpu(lsigb->info0)); 1009 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1010 break; 1011 } 1012 case HAL_PHYRX_L_SIG_A: { 1013 struct hal_rx_lsig_a_info *lsiga = 1014 (struct hal_rx_lsig_a_info *)tlv_data; 1015 1016 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE, 1017 __le32_to_cpu(lsiga->info0)); 1018 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1019 break; 1020 } 1021 case HAL_PHYRX_VHT_SIG_A: { 1022 struct hal_rx_vht_sig_a_info *vht_sig = 1023 (struct hal_rx_vht_sig_a_info *)tlv_data; 1024 u32 nsts; 1025 u32 group_id; 1026 u8 gi_setting; 1027 1028 info0 = __le32_to_cpu(vht_sig->info0); 1029 info1 = __le32_to_cpu(vht_sig->info1); 1030 1031 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, 1032 info1); 1033 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS, 1034 info1); 1035 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING, 1036 info1); 1037 switch (gi_setting) { 1038 case HAL_RX_VHT_SIG_A_NORMAL_GI: 1039 ppdu_info->gi = HAL_RX_GI_0_8_US; 1040 break; 1041 case HAL_RX_VHT_SIG_A_SHORT_GI: 1042 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 1043 ppdu_info->gi = HAL_RX_GI_0_4_US; 1044 break; 1045 } 1046 1047 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC; 1048 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0); 1049 if (ppdu_info->is_stbc && nsts > 0) 1050 nsts = ((nsts + 1) >> 1) - 1; 1051 1052 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1; 1053 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW, 1054 info0); 1055 ppdu_info->beamformed = info1 & 1056 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED; 1057 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID, 1058 info0); 1059 if (group_id == 0 || group_id == 63) 1060 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1061 else 1062 ppdu_info->reception_type = 1063 HAL_RX_RECEPTION_TYPE_MU_MIMO; 1064 ppdu_info->vht_flag_values5 = group_id; 1065 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | 1066 ppdu_info->nss); 1067 ppdu_info->vht_flag_values2 = ppdu_info->bw; 1068 ppdu_info->vht_flag_values4 = 1069 FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING, info1); 1070 break; 1071 } 1072 case HAL_PHYRX_HE_SIG_A_SU: { 1073 struct hal_rx_he_sig_a_su_info *he_sig_a = 1074 (struct hal_rx_he_sig_a_su_info *)tlv_data; 1075 1076 ppdu_info->he_flags = 1; 1077 info0 = __le32_to_cpu(he_sig_a->info0); 1078 info1 = __le32_to_cpu(he_sig_a->info1); 1079 1080 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND, info0); 1081 1082 if (value == 0) 1083 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG; 1084 else 1085 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU; 1086 1087 ppdu_info->he_data1 |= 1088 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 1089 IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN | 1090 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN | 1091 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1092 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN | 1093 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 1094 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN | 1095 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 1096 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN | 1097 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN; 1098 1099 ppdu_info->he_data2 |= 1100 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN | 1101 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN | 1102 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN | 1103 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN | 1104 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN | 1105 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN | 1106 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN; 1107 1108 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR, info0); 1109 ppdu_info->he_data3 = 1110 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value); 1111 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE, info0); 1112 ppdu_info->he_data3 |= 1113 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE, value); 1114 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG, info0); 1115 ppdu_info->he_data3 |= 1116 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value); 1117 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS, info0); 1118 ppdu_info->mcs = value; 1119 ppdu_info->he_data3 |= 1120 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, value); 1121 1122 he_dcm = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM, info0); 1123 ppdu_info->dcm = he_dcm; 1124 ppdu_info->he_data3 |= 1125 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, he_dcm); 1126 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info1); 1127 ppdu_info->ldpc = (value == HAL_RX_SU_MU_CODING_LDPC) ? 1 : 0; 1128 ppdu_info->he_data3 |= 1129 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value); 1130 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA, info1); 1131 ppdu_info->he_data3 |= 1132 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value); 1133 he_stbc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC, info1); 1134 ppdu_info->is_stbc = he_stbc; 1135 ppdu_info->he_data3 |= 1136 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, he_stbc); 1137 1138 /* data4 */ 1139 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE, info0); 1140 ppdu_info->he_data4 = 1141 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value); 1142 1143 /* data5 */ 1144 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW, info0); 1145 ppdu_info->bw = value; 1146 ppdu_info->he_data5 = 1147 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value); 1148 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE, info0); 1149 switch (value) { 1150 case 0: 1151 he_gi = HE_GI_0_8; 1152 he_ltf = HE_LTF_1_X; 1153 break; 1154 case 1: 1155 he_gi = HE_GI_0_8; 1156 he_ltf = HE_LTF_2_X; 1157 break; 1158 case 2: 1159 he_gi = HE_GI_1_6; 1160 he_ltf = HE_LTF_2_X; 1161 break; 1162 case 3: 1163 if (he_dcm && he_stbc) { 1164 he_gi = HE_GI_0_8; 1165 he_ltf = HE_LTF_4_X; 1166 } else { 1167 he_gi = HE_GI_3_2; 1168 he_ltf = HE_LTF_4_X; 1169 } 1170 break; 1171 } 1172 ppdu_info->gi = he_gi; 1173 he_gi = (he_gi != 0) ? he_gi - 1 : 0; 1174 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi); 1175 ppdu_info->ltf_size = he_ltf; 1176 ppdu_info->he_data5 |= 1177 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE, 1178 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf); 1179 1180 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0); 1181 ppdu_info->he_data5 |= 1182 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value); 1183 1184 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR, info1); 1185 ppdu_info->he_data5 |= 1186 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value); 1187 1188 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF, info1); 1189 ppdu_info->beamformed = value; 1190 ppdu_info->he_data5 |= 1191 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_TXBF, value); 1192 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM, info1); 1193 ppdu_info->he_data5 |= 1194 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value); 1195 1196 /* data6 */ 1197 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0); 1198 value++; 1199 ppdu_info->nss = value; 1200 ppdu_info->he_data6 = 1201 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_NSTS, value); 1202 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND, info1); 1203 ppdu_info->he_data6 |= 1204 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value); 1205 value = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION, info1); 1206 ppdu_info->he_data6 |= 1207 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value); 1208 1209 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 1210 break; 1211 } 1212 case HAL_PHYRX_HE_SIG_A_MU_DL: { 1213 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl = 1214 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data; 1215 1216 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 1217 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 1218 1219 ppdu_info->he_mu_flags = 1; 1220 1221 ppdu_info->he_data1 = IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU; 1222 ppdu_info->he_data1 |= 1223 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 1224 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN | 1225 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN | 1226 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 1227 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN | 1228 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN; 1229 1230 ppdu_info->he_data2 = 1231 IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN | 1232 IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN | 1233 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN | 1234 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN | 1235 IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN | 1236 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN; 1237 1238 /*data3*/ 1239 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR, info0); 1240 ppdu_info->he_data3 = 1241 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR, value); 1242 1243 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG, info0); 1244 ppdu_info->he_data3 |= 1245 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_UL_DL, value); 1246 1247 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA, info1); 1248 ppdu_info->he_data3 |= 1249 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG, value); 1250 1251 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC, info1); 1252 he_stbc = value; 1253 ppdu_info->he_data3 |= 1254 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_STBC, value); 1255 1256 /*data4*/ 1257 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE, info0); 1258 ppdu_info->he_data4 = 1259 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE, value); 1260 1261 /*data5*/ 1262 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0); 1263 ppdu_info->bw = value; 1264 ppdu_info->he_data5 = 1265 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC, value); 1266 1267 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE, info0); 1268 switch (value) { 1269 case 0: 1270 he_gi = HE_GI_0_8; 1271 he_ltf = HE_LTF_4_X; 1272 break; 1273 case 1: 1274 he_gi = HE_GI_0_8; 1275 he_ltf = HE_LTF_2_X; 1276 break; 1277 case 2: 1278 he_gi = HE_GI_1_6; 1279 he_ltf = HE_LTF_2_X; 1280 break; 1281 case 3: 1282 he_gi = HE_GI_3_2; 1283 he_ltf = HE_LTF_4_X; 1284 break; 1285 } 1286 ppdu_info->gi = he_gi; 1287 he_gi = (he_gi != 0) ? he_gi - 1 : 0; 1288 ppdu_info->he_data5 |= FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_GI, he_gi); 1289 ppdu_info->ltf_size = he_ltf; 1290 ppdu_info->he_data5 |= 1291 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE, 1292 (he_ltf == HE_LTF_4_X) ? he_ltf - 1 : he_ltf); 1293 1294 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB, info1); 1295 ppdu_info->he_data5 |= 1296 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS, value); 1297 1298 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR, 1299 info1); 1300 ppdu_info->he_data5 |= 1301 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD, value); 1302 1303 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM, 1304 info1); 1305 ppdu_info->he_data5 |= 1306 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG, value); 1307 1308 /*data6*/ 1309 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION, 1310 info0); 1311 ppdu_info->he_data6 |= 1312 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_DOPPLER, value); 1313 1314 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION, info1); 1315 ppdu_info->he_data6 |= 1316 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA6_TXOP, value); 1317 1318 /* HE-MU Flags */ 1319 /* HE-MU-flags1 */ 1320 ppdu_info->he_flags1 = 1321 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN | 1322 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN | 1323 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN | 1324 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN | 1325 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN; 1326 1327 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB, info0); 1328 ppdu_info->he_flags1 |= 1329 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN, 1330 value); 1331 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB, info0); 1332 ppdu_info->he_flags1 |= 1333 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN, 1334 value); 1335 1336 /* HE-MU-flags2 */ 1337 ppdu_info->he_flags2 = 1338 IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN; 1339 1340 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW, info0); 1341 ppdu_info->he_flags2 |= 1342 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW, 1343 value); 1344 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB, info0); 1345 ppdu_info->he_flags2 |= 1346 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP, value); 1347 value = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB, info0); 1348 value = value - 1; 1349 ppdu_info->he_flags2 |= 1350 FIELD_PREP(IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS, 1351 value); 1352 1353 ppdu_info->is_stbc = info1 & 1354 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC; 1355 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 1356 break; 1357 } 1358 case HAL_PHYRX_HE_SIG_B1_MU: { 1359 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu = 1360 (struct hal_rx_he_sig_b1_mu_info *)tlv_data; 1361 u16 ru_tones; 1362 1363 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 1364 1365 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION, 1366 info0); 1367 ppdu_info->ru_alloc = 1368 ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(ru_tones); 1369 ppdu_info->he_RU[0] = ru_tones; 1370 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 1371 break; 1372 } 1373 case HAL_PHYRX_HE_SIG_B2_MU: { 1374 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu = 1375 (struct hal_rx_he_sig_b2_mu_info *)tlv_data; 1376 1377 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 1378 1379 ppdu_info->he_data1 |= IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1380 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN; 1381 1382 ppdu_info->mcs = 1383 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS, info0); 1384 ppdu_info->he_data3 |= 1385 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs); 1386 1387 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING, info0); 1388 ppdu_info->ldpc = value; 1389 ppdu_info->he_data3 |= 1390 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value); 1391 1392 value = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID, info0); 1393 ppdu_info->he_data4 |= 1394 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value); 1395 1396 ppdu_info->nss = 1397 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS, info0) + 1; 1398 break; 1399 } 1400 case HAL_PHYRX_HE_SIG_B2_OFDMA: { 1401 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma = 1402 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data; 1403 1404 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0); 1405 1406 ppdu_info->he_data1 |= 1407 IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1408 IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN | 1409 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN; 1410 1411 /* HE-data2 */ 1412 ppdu_info->he_data2 |= IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN; 1413 1414 ppdu_info->mcs = 1415 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS, 1416 info0); 1417 ppdu_info->he_data3 |= 1418 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS, ppdu_info->mcs); 1419 1420 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM, info0); 1421 he_dcm = value; 1422 ppdu_info->he_data3 |= 1423 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM, value); 1424 1425 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING, info0); 1426 ppdu_info->ldpc = value; 1427 ppdu_info->he_data3 |= 1428 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA3_CODING, value); 1429 1430 /* HE-data4 */ 1431 value = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID, info0); 1432 ppdu_info->he_data4 |= 1433 FIELD_PREP(IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID, value); 1434 1435 ppdu_info->nss = 1436 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS, 1437 info0) + 1; 1438 ppdu_info->beamformed = 1439 info0 & HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF; 1440 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 1441 break; 1442 } 1443 case HAL_PHYRX_RSSI_LEGACY: { 1444 int i; 1445 bool db2dbm = test_bit(WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT, 1446 ab->wmi_ab.svc_map); 1447 struct hal_rx_phyrx_rssi_legacy_info *rssi = 1448 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data; 1449 1450 /* TODO: Please note that the combined rssi will not be accurate 1451 * in MU case. Rssi in MU needs to be retrieved from 1452 * PHYRX_OTHER_RECEIVE_INFO TLV. 1453 */ 1454 ppdu_info->rssi_comb = 1455 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB, 1456 __le32_to_cpu(rssi->info0)); 1457 1458 if (db2dbm) { 1459 for (i = 0; i < ARRAY_SIZE(rssi->preamble); i++) { 1460 ppdu_info->rssi_chain_pri20[i] = 1461 le32_get_bits(rssi->preamble[i].rssi_2040, 1462 HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20); 1463 } 1464 } 1465 break; 1466 } 1467 case HAL_RX_MPDU_START: { 1468 struct hal_rx_mpdu_info *mpdu_info = 1469 (struct hal_rx_mpdu_info *)tlv_data; 1470 u16 peer_id; 1471 1472 peer_id = ath11k_hal_rx_mpduinfo_get_peerid(ab, mpdu_info); 1473 if (peer_id) 1474 ppdu_info->peer_id = peer_id; 1475 break; 1476 } 1477 case HAL_RXPCU_PPDU_END_INFO: { 1478 struct hal_rx_ppdu_end_duration *ppdu_rx_duration = 1479 (struct hal_rx_ppdu_end_duration *)tlv_data; 1480 ppdu_info->rx_duration = 1481 FIELD_GET(HAL_RX_PPDU_END_DURATION, 1482 __le32_to_cpu(ppdu_rx_duration->info0)); 1483 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]); 1484 ppdu_info->tsft = (ppdu_info->tsft << 32) | 1485 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]); 1486 break; 1487 } 1488 case HAL_DUMMY: 1489 return HAL_RX_MON_STATUS_BUF_DONE; 1490 case HAL_RX_PPDU_END_STATUS_DONE: 1491 case 0: 1492 return HAL_RX_MON_STATUS_PPDU_DONE; 1493 default: 1494 break; 1495 } 1496 1497 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 1498} 1499 1500enum hal_rx_mon_status 1501ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab, 1502 struct hal_rx_mon_ppdu_info *ppdu_info, 1503 struct sk_buff *skb) 1504{ 1505 struct hal_tlv_hdr *tlv; 1506 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; 1507 u16 tlv_tag; 1508 u16 tlv_len; 1509 u32 tlv_userid = 0; 1510 u8 *ptr = skb->data; 1511 1512 do { 1513 tlv = (struct hal_tlv_hdr *)ptr; 1514 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl); 1515 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl); 1516 tlv_userid = FIELD_GET(HAL_TLV_USR_ID, tlv->tl); 1517 ptr += sizeof(*tlv); 1518 1519 /* The actual length of PPDU_END is the combined length of many PHY 1520 * TLVs that follow. Skip the TLV header and 1521 * rx_rxpcu_classification_overview that follows the header to get to 1522 * next TLV. 1523 */ 1524 if (tlv_tag == HAL_RX_PPDU_END) 1525 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 1526 1527 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info, 1528 tlv_tag, ptr, tlv_userid); 1529 ptr += tlv_len; 1530 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 1531 1532 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) 1533 break; 1534 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); 1535 1536 return hal_status; 1537} 1538 1539void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, 1540 u32 *sw_cookie, void **pp_buf_addr, 1541 u8 *rbm, u32 *msdu_cnt) 1542{ 1543 struct hal_reo_entrance_ring *reo_ent_ring = 1544 (struct hal_reo_entrance_ring *)rx_desc; 1545 struct ath11k_buffer_addr *buf_addr_info; 1546 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 1547 1548 rx_mpdu_desc_info_details = 1549 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info; 1550 1551 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1552 rx_mpdu_desc_info_details->info0); 1553 1554 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info; 1555 1556 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1557 buf_addr_info->info1)) << 32) | 1558 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1559 buf_addr_info->info0); 1560 1561 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1562 buf_addr_info->info1); 1563 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, 1564 buf_addr_info->info1); 1565 1566 *pp_buf_addr = (void *)buf_addr_info; 1567} 1568 1569void 1570ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc, 1571 struct hal_sw_mon_ring_entries *sw_mon_entries) 1572{ 1573 struct hal_sw_monitor_ring *sw_mon_ring = rx_desc; 1574 struct ath11k_buffer_addr *buf_addr_info; 1575 struct ath11k_buffer_addr *status_buf_addr_info; 1576 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 1577 1578 rx_mpdu_desc_info_details = &sw_mon_ring->rx_mpdu_info; 1579 1580 sw_mon_entries->msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT, 1581 rx_mpdu_desc_info_details->info0); 1582 1583 buf_addr_info = &sw_mon_ring->buf_addr_info; 1584 status_buf_addr_info = &sw_mon_ring->status_buf_addr_info; 1585 1586 sw_mon_entries->mon_dst_paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1587 buf_addr_info->info1)) << 32) | 1588 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1589 buf_addr_info->info0); 1590 1591 sw_mon_entries->mon_status_paddr = 1592 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, 1593 status_buf_addr_info->info1)) << 32) | 1594 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, 1595 status_buf_addr_info->info0); 1596 1597 sw_mon_entries->mon_dst_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1598 buf_addr_info->info1); 1599 1600 sw_mon_entries->mon_status_sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 1601 status_buf_addr_info->info1); 1602 1603 sw_mon_entries->status_buf_count = FIELD_GET(HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT, 1604 sw_mon_ring->info0); 1605 1606 sw_mon_entries->dst_buf_addr_info = buf_addr_info; 1607 sw_mon_entries->status_buf_addr_info = status_buf_addr_info; 1608 1609 sw_mon_entries->ppdu_id = 1610 FIELD_GET(HAL_SW_MON_RING_INFO1_PHY_PPDU_ID, sw_mon_ring->info1); 1611} 1612