1/*-
2********************************************************************************
3Copyright (C) 2015 Annapurna Labs Ltd.
4
5This file may be licensed under the terms of the Annapurna Labs Commercial
6License Agreement.
7
8Alternatively, this file can be distributed under the terms of the GNU General
9Public License V2 as published by the Free Software Foundation and can be
10found at http://www.gnu.org/licenses/gpl-2.0.html
11
12Alternatively, redistribution and use in source and binary forms, with or
13without modification, are permitted provided that the following conditions are
14met:
15
16    *     Redistributions of source code must retain the above copyright notice,
17this list of conditions and the following disclaimer.
18
19    *     Redistributions in binary form must reproduce the above copyright
20notice, this list of conditions and the following disclaimer in
21the documentation and/or other materials provided with the
22distribution.
23
24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34
35*******************************************************************************/
36
37/**
38 * @defgroup group_common HAL Common Layer
39 *  @{
40 * @file   al_hal_reg_utils.h
41 *
42 * @brief  Register utilities used by HALs and platform layer
43 *
44 *
45 */
46
47#ifndef __AL_HAL_REG_UTILS_H__
48#define __AL_HAL_REG_UTILS_H__
49
50#include "al_hal_plat_types.h"
51#include "al_hal_plat_services.h"
52
53/* *INDENT-OFF* */
54#ifdef __cplusplus
55extern "C" {
56#endif
57/* *INDENT-ON* */
58
59#define AL_BIT(b)	(1UL << (b))
60#define AL_BIT_64(b)	(1ULL << (b))
61
62#define AL_ADDR_LOW(x)	((uint32_t)((al_phys_addr_t)(x)))
63#define AL_ADDR_HIGH(x)	((uint32_t)((((al_phys_addr_t)(x)) >> 16) >> 16))
64
65/** get field out of 32 bit register */
66#define AL_REG_FIELD_GET(reg, mask, shift)  (((reg) & (mask)) >> (shift))
67
68/** set field of 32 bit register */
69#define AL_REG_FIELD_SET(reg, mask, shift, val)			\
70	(reg) =							\
71		(((reg) & (~(mask))) |				\
72		((((unsigned)(val)) << (shift)) & (mask)))
73
74/** set field of 64 bit register */
75#define AL_REG_FIELD_SET_64(reg, mask, shift, val)		\
76	((reg) =						\
77		(((reg) & (~(mask))) |				\
78		((((uint64_t)(val)) << (shift)) & (mask))))
79
80/** get single bit out of 32 bit register */
81#define AL_REG_BIT_GET(reg, shift)				\
82	AL_REG_FIELD_GET(reg, AL_BIT(shift), shift)
83
84#define AL_REG_BITS_FIELD(shift, val)				\
85		(((unsigned)(val)) << (shift))
86
87/** set single bit field of 32 bit register to a given value */
88#define AL_REG_BIT_VAL_SET(reg, shift, val)				\
89	AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val)
90
91/** set single bit of 32 bit register to 1 */
92#define AL_REG_BIT_SET(reg, shift)				\
93	AL_REG_BIT_VAL_SET(reg, shift, 1)
94
95/** clear single bit of 32 bit register */
96#define AL_REG_BIT_CLEAR(reg, shift)				\
97	AL_REG_BIT_VAL_SET(reg, shift, 0)
98
99
100#define AL_BIT_MASK(n)						\
101	(AL_BIT(n) - 1)
102
103#define AL_FIELD_MASK(msb, lsb)					\
104	(AL_BIT(msb) + AL_BIT_MASK(msb) - AL_BIT_MASK(lsb))
105
106/** clear bits specified by clear_mask */
107#define AL_REG_MASK_CLEAR(reg, clear_mask)			\
108	((reg) = (((reg) & (~(clear_mask)))))
109
110/** set bits specified by clear_mask */
111#define AL_REG_MASK_SET(reg, clear_mask)			\
112	((reg) = (((reg) | (clear_mask))))
113
114
115/** clear bits specified by clear_mask, and set bits specified by set_mask */
116#define AL_REG_CLEAR_AND_SET(reg, clear_mask, set_mask)			\
117	(reg) =	(((reg) & (~(clear_mask))) | (set_mask))
118
119#define AL_ALIGN_UP(val, size)					\
120	((size) * (((val) + (size) - 1) / (size)))
121
122/** take bits selected by mask from one data, the rest from background */
123#define AL_MASK_VAL(mask, data, background)		\
124	(((mask) & (data)) | ((~mask) & (background)))
125
126/**
127 * 8 bits register masked write
128 *
129 * @param	reg
130 *	register address
131 * @param	mask
132 *	bits not selected (1) by mask will be left unchanged
133 * @param	data
134 *	data to write. bits not selected by mask ignored.
135 */
136static inline void
137al_reg_write8_masked(uint8_t __iomem *reg, uint8_t mask, uint8_t data)
138{
139	uint8_t temp;
140	temp = al_reg_read8(reg);
141	al_reg_write8(reg, AL_MASK_VAL(mask, data, temp));
142}
143
144
145/**
146 * 16 bits register masked write
147 *
148 * @param	reg
149 *	register address
150 * @param	mask
151 *	bits not selected (1) by mask will be left unchanged
152 * @param	data
153 *	data to write. bits not selected by mask ignored.
154 */
155static inline void
156al_reg_write16_masked(uint16_t __iomem *reg, uint16_t mask, uint16_t data)
157{
158	uint16_t temp;
159	temp = al_reg_read16(reg);
160	al_reg_write16(reg, AL_MASK_VAL(mask, data, temp));
161}
162
163
164/**
165 * 32 bits register masked write
166 *
167 * @param	reg
168 *	register address
169 * @param	mask
170 *	bits not selected (1) by mask will be left unchanged
171 * @param	data
172 *	data to write. bits not selected by mask ignored.
173 */
174static inline void
175al_reg_write32_masked(uint32_t __iomem *reg, uint32_t mask, uint32_t data)
176{
177	uint32_t temp;
178	temp = al_reg_read32(reg);
179	al_reg_write32(reg, AL_MASK_VAL(mask, data, temp));
180}
181
182/* *INDENT-OFF* */
183#ifdef __cplusplus
184}
185#endif
186/* *INDENT-ON* */
187/** @} end of Common group */
188#endif
189
190