1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014-2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 36 */ 37 38#ifdef __arm__ 39#include <arm/cpu.h> 40#else /* !__arm__ */ 41 42#ifndef _MACHINE_CPU_H_ 43#define _MACHINE_CPU_H_ 44 45#if !defined(__ASSEMBLER__) 46#include <machine/atomic.h> 47#include <machine/frame.h> 48#endif 49#include <machine/armreg.h> 50 51#define TRAPF_PC(tfp) ((tfp)->tf_elr) 52#define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) 53 54#define cpu_getstack(td) ((td)->td_frame->tf_sp) 55#define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 56#define cpu_spinwait() __asm __volatile("yield" ::: "memory") 57#define cpu_lock_delay() DELAY(1) 58 59/* Extract CPU affinity levels 0-3 */ 60#define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 61#define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 62#define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 63#define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 64#define CPU_AFF0_MASK 0xffUL 65#define CPU_AFF1_MASK 0xff00UL 66#define CPU_AFF2_MASK 0xff0000UL 67#define CPU_AFF3_MASK 0xff00000000UL 68#define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 69 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 70 71#ifdef _KERNEL 72 73#define CPU_IMPL_ARM 0x41 74#define CPU_IMPL_BROADCOM 0x42 75#define CPU_IMPL_CAVIUM 0x43 76#define CPU_IMPL_DEC 0x44 77#define CPU_IMPL_FUJITSU 0x46 78#define CPU_IMPL_INFINEON 0x49 79#define CPU_IMPL_FREESCALE 0x4D 80#define CPU_IMPL_NVIDIA 0x4E 81#define CPU_IMPL_APM 0x50 82#define CPU_IMPL_QUALCOMM 0x51 83#define CPU_IMPL_MARVELL 0x56 84#define CPU_IMPL_APPLE 0x61 85#define CPU_IMPL_INTEL 0x69 86#define CPU_IMPL_AMPERE 0xC0 87 88/* ARM Part numbers */ 89#define CPU_PART_FOUNDATION 0xD00 90#define CPU_PART_CORTEX_A34 0xD02 91#define CPU_PART_CORTEX_A53 0xD03 92#define CPU_PART_CORTEX_A35 0xD04 93#define CPU_PART_CORTEX_A55 0xD05 94#define CPU_PART_CORTEX_A65 0xD06 95#define CPU_PART_CORTEX_A57 0xD07 96#define CPU_PART_CORTEX_A72 0xD08 97#define CPU_PART_CORTEX_A73 0xD09 98#define CPU_PART_CORTEX_A75 0xD0A 99#define CPU_PART_CORTEX_A76 0xD0B 100#define CPU_PART_NEOVERSE_N1 0xD0C 101#define CPU_PART_CORTEX_A77 0xD0D 102#define CPU_PART_CORTEX_A76AE 0xD0E 103#define CPU_PART_AEM_V8 0xD0F 104#define CPU_PART_NEOVERSE_V1 0xD40 105#define CPU_PART_CORTEX_A78 0xD41 106#define CPU_PART_CORTEX_A65AE 0xD43 107#define CPU_PART_CORTEX_X1 0xD44 108#define CPU_PART_CORTEX_A510 0xD46 109#define CPU_PART_CORTEX_A710 0xD47 110#define CPU_PART_CORTEX_X2 0xD48 111#define CPU_PART_NEOVERSE_N2 0xD49 112#define CPU_PART_NEOVERSE_E1 0xD4A 113#define CPU_PART_CORTEX_A78C 0xD4B 114#define CPU_PART_CORTEX_X1C 0xD4C 115#define CPU_PART_CORTEX_A715 0xD4D 116#define CPU_PART_CORTEX_X3 0xD4E 117#define CPU_PART_NEOVERSE_V2 0xD4F 118 119/* Cavium Part numbers */ 120#define CPU_PART_THUNDERX 0x0A1 121#define CPU_PART_THUNDERX_81XX 0x0A2 122#define CPU_PART_THUNDERX_83XX 0x0A3 123#define CPU_PART_THUNDERX2 0x0AF 124 125#define CPU_REV_THUNDERX_1_0 0x00 126#define CPU_REV_THUNDERX_1_1 0x01 127 128#define CPU_REV_THUNDERX2_0 0x00 129 130/* APM / Ampere Part Number */ 131#define CPU_PART_EMAG8180 0x000 132 133/* Qualcomm */ 134#define CPU_PART_KRYO400_GOLD 0x804 135#define CPU_PART_KRYO400_SILVER 0x805 136 137/* Apple part numbers */ 138#define CPU_PART_M1_ICESTORM 0x022 139#define CPU_PART_M1_FIRESTORM 0x023 140#define CPU_PART_M1_ICESTORM_PRO 0x024 141#define CPU_PART_M1_FIRESTORM_PRO 0x025 142#define CPU_PART_M1_ICESTORM_MAX 0x028 143#define CPU_PART_M1_FIRESTORM_MAX 0x029 144#define CPU_PART_M2_BLIZZARD 0x032 145#define CPU_PART_M2_AVALANCHE 0x033 146#define CPU_PART_M2_BLIZZARD_PRO 0x034 147#define CPU_PART_M2_AVALANCHE_PRO 0x035 148#define CPU_PART_M2_BLIZZARD_MAX 0x038 149#define CPU_PART_M2_AVALANCHE_MAX 0x039 150 151#define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 152#define CPU_PART(midr) (((midr) >> 4) & 0xfff) 153#define CPU_VAR(midr) (((midr) >> 20) & 0xf) 154#define CPU_ARCH(midr) (((midr) >> 16) & 0xf) 155#define CPU_REV(midr) (((midr) >> 0) & 0xf) 156 157#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 158#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 159#define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 160#define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16) 161#define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 162 163#define CPU_IMPL_MASK (0xff << 24) 164#define CPU_PART_MASK (0xfff << 4) 165#define CPU_VAR_MASK (0xf << 20) 166#define CPU_ARCH_MASK (0xf << 16) 167#define CPU_REV_MASK (0xf << 0) 168 169#define CPU_ID_RAW(impl, part, var, rev) \ 170 (CPU_IMPL_TO_MIDR((impl)) | \ 171 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 172 CPU_REV_TO_MIDR((rev))) 173 174#define CPU_MATCH(mask, impl, part, var, rev) \ 175 (((mask) & PCPU_GET(midr)) == \ 176 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 177 178#define CPU_MATCH_RAW(mask, devid) \ 179 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 180 181/* 182 * Chip-specific errata. This defines are intended to be 183 * booleans used within if statements. When an appropriate 184 * kernel option is disabled, these defines must be defined 185 * as 0 to allow the compiler to remove a dead code thus 186 * produce better optimized kernel image. 187 */ 188/* 189 * Vendor: Cavium 190 * Chip: ThunderX 191 * Revision(s): Pass 1.0, Pass 1.1 192 */ 193#ifdef THUNDERX_PASS_1_1_ERRATA 194#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ 195 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 196 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ 197 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 198 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) 199#else 200#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 201#endif 202 203#if !defined(__ASSEMBLER__) 204extern char btext[]; 205extern char etext[]; 206 207extern uint64_t __cpu_affinity[]; 208 209struct arm64_addr_mask; 210extern struct arm64_addr_mask elf64_addr_mask; 211 212typedef void (*cpu_reset_hook_t)(void); 213extern cpu_reset_hook_t cpu_reset_hook; 214 215void cpu_halt(void) __dead2; 216void cpu_reset(void) __dead2; 217void fork_trampoline(void); 218void identify_cache(uint64_t); 219void identify_cpu(u_int); 220void install_cpu_errata(void); 221 222/* Pointer Authentication Code (PAC) support */ 223void ptrauth_init(void); 224void ptrauth_fork(struct thread *, struct thread *); 225void ptrauth_exec(struct thread *); 226void ptrauth_copy_thread(struct thread *, struct thread *); 227void ptrauth_thread_alloc(struct thread *); 228void ptrauth_thread0(struct thread *); 229#ifdef SMP 230void ptrauth_mp_start(uint64_t); 231#endif 232 233/* Functions to read the sanitised view of the special registers */ 234void update_special_regs(u_int); 235bool extract_user_id_field(u_int, u_int, uint8_t *); 236bool get_kernel_reg(u_int, uint64_t *); 237bool get_kernel_reg_masked(u_int, uint64_t *, uint64_t); 238 239void cpu_desc_init(void); 240 241#define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 242#define CPU_CURRENT_SOCKET \ 243 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) 244 245static __inline uint64_t 246get_cyclecount(void) 247{ 248 uint64_t ret; 249 250 ret = READ_SPECIALREG(cntvct_el0); 251 252 return (ret); 253} 254 255#define ADDRESS_TRANSLATE_FUNC(stage) \ 256static inline uint64_t \ 257arm64_address_translate_ ##stage (uint64_t addr) \ 258{ \ 259 uint64_t ret; \ 260 \ 261 __asm __volatile( \ 262 "at " __STRING(stage) ", %1 \n" \ 263 "isb \n" \ 264 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 265 \ 266 return (ret); \ 267} 268 269ADDRESS_TRANSLATE_FUNC(s1e0r) 270ADDRESS_TRANSLATE_FUNC(s1e0w) 271ADDRESS_TRANSLATE_FUNC(s1e1r) 272ADDRESS_TRANSLATE_FUNC(s1e1w) 273 274#endif /* !__ASSEMBLER__ */ 275#endif 276 277#endif /* !_MACHINE_CPU_H_ */ 278 279#endif /* !__arm__ */ 280