1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015,2021 The FreeBSD Foundation 4 * 5 * Portions of this software were developed by Andrew Turner 6 * under sponsorship from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#ifdef __arm__ 31#include <arm/armreg.h> 32#else /* !__arm__ */ 33 34#ifndef _MACHINE_ARMREG_H_ 35#define _MACHINE_ARMREG_H_ 36 37#define INSN_SIZE 4 38 39#define MRS_MASK 0xfff00000 40#define MRS_VALUE 0xd5300000 41#define MRS_SPECIAL(insn) ((insn) & 0x000fffe0) 42#define MRS_REGISTER(insn) ((insn) & 0x0000001f) 43#define MRS_Op0_SHIFT 19 44#define MRS_Op0_MASK 0x00080000 45#define MRS_Op1_SHIFT 16 46#define MRS_Op1_MASK 0x00070000 47#define MRS_CRn_SHIFT 12 48#define MRS_CRn_MASK 0x0000f000 49#define MRS_CRm_SHIFT 8 50#define MRS_CRm_MASK 0x00000f00 51#define MRS_Op2_SHIFT 5 52#define MRS_Op2_MASK 0x000000e0 53#define MRS_Rt_SHIFT 0 54#define MRS_Rt_MASK 0x0000001f 55#define __MRS_REG(op0, op1, crn, crm, op2) \ 56 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \ 57 ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) | \ 58 ((op2) << MRS_Op2_SHIFT)) 59#define MRS_REG(reg) \ 60 __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 61 62#define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 63 S##op0##_##op1##_C##crn##_C##crm##_##op2 64#define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ 65 __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) 66#define MRS_REG_ALT_NAME(reg) \ 67 _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) 68 69 70#define READ_SPECIALREG(reg) \ 71({ uint64_t _val; \ 72 __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ 73 _val; \ 74}) 75#define WRITE_SPECIALREG(reg, _val) \ 76 __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) 77 78#define UL(x) UINT64_C(x) 79 80/* APDAKeyHi_EL1 */ 81#define APDAKeyHi_EL1_REG MRS_REG_ALT_NAME(APDAKeyHi_EL1) 82#define APDAKeyHi_EL1_op0 3 83#define APDAKeyHi_EL1_op1 0 84#define APDAKeyHi_EL1_CRn 2 85#define APDAKeyHi_EL1_CRm 2 86#define APDAKeyHi_EL1_op2 1 87 88/* APDAKeyLo_EL1 */ 89#define APDAKeyLo_EL1_REG MRS_REG_ALT_NAME(APDAKeyLo_EL1) 90#define APDAKeyLo_EL1_op0 3 91#define APDAKeyLo_EL1_op1 0 92#define APDAKeyLo_EL1_CRn 2 93#define APDAKeyLo_EL1_CRm 2 94#define APDAKeyLo_EL1_op2 0 95 96/* APDBKeyHi_EL1 */ 97#define APDBKeyHi_EL1_REG MRS_REG_ALT_NAME(APDBKeyHi_EL1) 98#define APDBKeyHi_EL1_op0 3 99#define APDBKeyHi_EL1_op1 0 100#define APDBKeyHi_EL1_CRn 2 101#define APDBKeyHi_EL1_CRm 2 102#define APDBKeyHi_EL1_op2 3 103 104/* APDBKeyLo_EL1 */ 105#define APDBKeyLo_EL1_REG MRS_REG_ALT_NAME(APDBKeyLo_EL1) 106#define APDBKeyLo_EL1_op0 3 107#define APDBKeyLo_EL1_op1 0 108#define APDBKeyLo_EL1_CRn 2 109#define APDBKeyLo_EL1_CRm 2 110#define APDBKeyLo_EL1_op2 2 111 112/* APGAKeyHi_EL1 */ 113#define APGAKeyHi_EL1_REG MRS_REG_ALT_NAME(APGAKeyHi_EL1) 114#define APGAKeyHi_EL1_op0 3 115#define APGAKeyHi_EL1_op1 0 116#define APGAKeyHi_EL1_CRn 2 117#define APGAKeyHi_EL1_CRm 3 118#define APGAKeyHi_EL1_op2 1 119 120/* APGAKeyLo_EL1 */ 121#define APGAKeyLo_EL1_REG MRS_REG_ALT_NAME(APGAKeyLo_EL1) 122#define APGAKeyLo_EL1_op0 3 123#define APGAKeyLo_EL1_op1 0 124#define APGAKeyLo_EL1_CRn 2 125#define APGAKeyLo_EL1_CRm 3 126#define APGAKeyLo_EL1_op2 0 127 128/* APIAKeyHi_EL1 */ 129#define APIAKeyHi_EL1_REG MRS_REG_ALT_NAME(APIAKeyHi_EL1) 130#define APIAKeyHi_EL1_op0 3 131#define APIAKeyHi_EL1_op1 0 132#define APIAKeyHi_EL1_CRn 2 133#define APIAKeyHi_EL1_CRm 1 134#define APIAKeyHi_EL1_op2 1 135 136/* APIAKeyLo_EL1 */ 137#define APIAKeyLo_EL1_REG MRS_REG_ALT_NAME(APIAKeyLo_EL1) 138#define APIAKeyLo_EL1_op0 3 139#define APIAKeyLo_EL1_op1 0 140#define APIAKeyLo_EL1_CRn 2 141#define APIAKeyLo_EL1_CRm 1 142#define APIAKeyLo_EL1_op2 0 143 144/* APIBKeyHi_EL1 */ 145#define APIBKeyHi_EL1_REG MRS_REG_ALT_NAME(APIBKeyHi_EL1) 146#define APIBKeyHi_EL1_op0 3 147#define APIBKeyHi_EL1_op1 0 148#define APIBKeyHi_EL1_CRn 2 149#define APIBKeyHi_EL1_CRm 1 150#define APIBKeyHi_EL1_op2 3 151 152/* APIBKeyLo_EL1 */ 153#define APIBKeyLo_EL1_REG MRS_REG_ALT_NAME(APIBKeyLo_EL1) 154#define APIBKeyLo_EL1_op0 3 155#define APIBKeyLo_EL1_op1 0 156#define APIBKeyLo_EL1_CRn 2 157#define APIBKeyLo_EL1_CRm 1 158#define APIBKeyLo_EL1_op2 2 159 160/* CCSIDR_EL1 - Cache Size ID Register */ 161#define CCSIDR_NumSets_MASK 0x0FFFE000 162#define CCSIDR_NumSets64_MASK 0x00FFFFFF00000000 163#define CCSIDR_NumSets_SHIFT 13 164#define CCSIDR_NumSets64_SHIFT 32 165#define CCSIDR_Assoc_MASK 0x00001FF8 166#define CCSIDR_Assoc64_MASK 0x0000000000FFFFF8 167#define CCSIDR_Assoc_SHIFT 3 168#define CCSIDR_Assoc64_SHIFT 3 169#define CCSIDR_LineSize_MASK 0x7 170#define CCSIDR_NSETS(idr) \ 171 (((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT) 172#define CCSIDR_ASSOC(idr) \ 173 (((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT) 174#define CCSIDR_NSETS_64(idr) \ 175 (((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT) 176#define CCSIDR_ASSOC_64(idr) \ 177 (((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT) 178 179/* CLIDR_EL1 - Cache level ID register */ 180#define CLIDR_CTYPE_MASK 0x7 /* Cache type mask bits */ 181#define CLIDR_CTYPE_IO 0x1 /* Instruction only */ 182#define CLIDR_CTYPE_DO 0x2 /* Data only */ 183#define CLIDR_CTYPE_ID 0x3 /* Split instruction and data */ 184#define CLIDR_CTYPE_UNIFIED 0x4 /* Unified */ 185 186/* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */ 187#define CNTP_CTL_EL0 MRS_REG(CNTP_CTL_EL0) 188#define CNTP_CTL_EL0_op0 3 189#define CNTP_CTL_EL0_op1 3 190#define CNTP_CTL_EL0_CRn 14 191#define CNTP_CTL_EL0_CRm 2 192#define CNTP_CTL_EL0_op2 1 193#define CNTP_CTL_ENABLE (1 << 0) 194#define CNTP_CTL_IMASK (1 << 1) 195#define CNTP_CTL_ISTATUS (1 << 2) 196 197/* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */ 198#define CNTP_CVAL_EL0 MRS_REG(CNTP_CVAL_EL0) 199#define CNTP_CVAL_EL0_op0 3 200#define CNTP_CVAL_EL0_op1 3 201#define CNTP_CVAL_EL0_CRn 14 202#define CNTP_CVAL_EL0_CRm 2 203#define CNTP_CVAL_EL0_op2 2 204 205/* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */ 206#define CNTP_TVAL_EL0 MRS_REG(CNTP_TVAL_EL0) 207#define CNTP_TVAL_EL0_op0 3 208#define CNTP_TVAL_EL0_op1 3 209#define CNTP_TVAL_EL0_CRn 14 210#define CNTP_TVAL_EL0_CRm 2 211#define CNTP_TVAL_EL0_op2 0 212 213/* CNTPCT_EL0 - Counter-timer Physical Count register */ 214#define CNTPCT_EL0 MRS_REG(CNTPCT_EL0) 215#define CNTPCT_EL0_op0 3 216#define CNTPCT_EL0_op1 3 217#define CNTPCT_EL0_CRn 14 218#define CNTPCT_EL0_CRm 0 219#define CNTPCT_EL0_op2 1 220 221/* CONTEXTIDR_EL1 - Context ID register */ 222#define CONTEXTIDR_EL1 MRS_REG(CONTEXTIDR_EL1) 223#define CONTEXTIDR_EL1_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL1) 224#define CONTEXTIDR_EL1_op0 3 225#define CONTEXTIDR_EL1_op1 0 226#define CONTEXTIDR_EL1_CRn 13 227#define CONTEXTIDR_EL1_CRm 0 228#define CONTEXTIDR_EL1_op2 1 229 230/* CPACR_EL1 */ 231#define CPACR_ZEN_MASK (0x3 << 16) 232#define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */ 233#define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */ 234#define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */ 235#define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */ 236#define CPACR_FPEN_MASK (0x3 << 20) 237#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 238#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 239#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 240#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 241#define CPACR_TTA (0x1 << 28) 242 243/* CSSELR_EL1 - Cache size selection register */ 244#define CSSELR_Level(i) (i << 1) 245#define CSSELR_InD 0x00000001 246 247/* CTR_EL0 - Cache Type Register */ 248#define CTR_RES1 (1 << 31) 249#define CTR_TminLine_SHIFT 32 250#define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) 251#define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) 252#define CTR_DIC_SHIFT 29 253#define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) 254#define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) 255#define CTR_IDC_SHIFT 28 256#define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) 257#define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) 258#define CTR_CWG_SHIFT 24 259#define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) 260#define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) 261#define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) 262#define CTR_ERG_SHIFT 20 263#define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) 264#define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) 265#define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) 266#define CTR_DLINE_SHIFT 16 267#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 268#define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) 269#define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) 270#define CTR_L1IP_SHIFT 14 271#define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) 272#define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) 273#define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) 274#define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) 275#define CTR_L1IP_VIPT (2 << CTR_L1IP_SHIFT) 276#define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) 277#define CTR_ILINE_SHIFT 0 278#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 279#define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) 280#define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) 281 282/* CurrentEL - Current Exception Level */ 283#define CURRENTEL_EL_SHIFT 2 284#define CURRENTEL_EL_MASK (0x3 << CURRENTEL_EL_SHIFT) 285#define CURRENTEL_EL_EL0 (0x0 << CURRENTEL_EL_SHIFT) 286#define CURRENTEL_EL_EL1 (0x1 << CURRENTEL_EL_SHIFT) 287#define CURRENTEL_EL_EL2 (0x2 << CURRENTEL_EL_SHIFT) 288#define CURRENTEL_EL_EL3 (0x3 << CURRENTEL_EL_SHIFT) 289 290/* DAIFSet/DAIFClear */ 291#define DAIF_D (1 << 3) 292#define DAIF_A (1 << 2) 293#define DAIF_I (1 << 1) 294#define DAIF_F (1 << 0) 295#define DAIF_ALL (DAIF_D | DAIF_A | DAIF_I | DAIF_F) 296#define DAIF_INTR (DAIF_I) /* All exceptions that pass */ 297 /* through the intr framework */ 298 299/* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */ 300#define DBGBCR_EL1_op0 2 301#define DBGBCR_EL1_op1 0 302#define DBGBCR_EL1_CRn 0 303/* DBGBCR_EL1_CRm indicates which watchpoint this register is for */ 304#define DBGBCR_EL1_op2 5 305#define DBGBCR_EN 0x1 306#define DBGBCR_PMC_SHIFT 1 307#define DBGBCR_PMC (0x3 << DBGBCR_PMC_SHIFT) 308#define DBGBCR_PMC_EL1 (0x1 << DBGBCR_PMC_SHIFT) 309#define DBGBCR_PMC_EL0 (0x2 << DBGBCR_PMC_SHIFT) 310#define DBGBCR_BAS_SHIFT 5 311#define DBGBCR_BAS (0xf << DBGBCR_BAS_SHIFT) 312#define DBGBCR_HMC_SHIFT 13 313#define DBGBCR_HMC (0x1 << DBGBCR_HMC_SHIFT) 314#define DBGBCR_SSC_SHIFT 14 315#define DBGBCR_SSC (0x3 << DBGBCR_SSC_SHIFT) 316#define DBGBCR_LBN_SHIFT 16 317#define DBGBCR_LBN (0xf << DBGBCR_LBN_SHIFT) 318#define DBGBCR_BT_SHIFT 20 319#define DBGBCR_BT (0xf << DBGBCR_BT_SHIFT) 320 321/* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */ 322#define DBGBVR_EL1_op0 2 323#define DBGBVR_EL1_op1 0 324#define DBGBVR_EL1_CRn 0 325/* DBGBVR_EL1_CRm indicates which watchpoint this register is for */ 326#define DBGBVR_EL1_op2 4 327 328/* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */ 329#define DBGWCR_EL1_op0 2 330#define DBGWCR_EL1_op1 0 331#define DBGWCR_EL1_CRn 0 332/* DBGWCR_EL1_CRm indicates which watchpoint this register is for */ 333#define DBGWCR_EL1_op2 7 334#define DBGWCR_EN 0x1 335#define DBGWCR_PAC_SHIFT 1 336#define DBGWCR_PAC (0x3 << DBGWCR_PAC_SHIFT) 337#define DBGWCR_PAC_EL1 (0x1 << DBGWCR_PAC_SHIFT) 338#define DBGWCR_PAC_EL0 (0x2 << DBGWCR_PAC_SHIFT) 339#define DBGWCR_LSC_SHIFT 3 340#define DBGWCR_LSC (0x3 << DBGWCR_LSC_SHIFT) 341#define DBGWCR_BAS_SHIFT 5 342#define DBGWCR_BAS (0xff << DBGWCR_BAS_SHIFT) 343#define DBGWCR_HMC_SHIFT 13 344#define DBGWCR_HMC (0x1 << DBGWCR_HMC_SHIFT) 345#define DBGWCR_SSC_SHIFT 14 346#define DBGWCR_SSC (0x3 << DBGWCR_SSC_SHIFT) 347#define DBGWCR_LBN_SHIFT 16 348#define DBGWCR_LBN (0xf << DBGWCR_LBN_SHIFT) 349#define DBGWCR_WT_SHIFT 20 350#define DBGWCR_WT (0x1 << DBGWCR_WT_SHIFT) 351#define DBGWCR_MASK_SHIFT 24 352#define DBGWCR_MASK (0x1f << DBGWCR_MASK_SHIFT) 353 354/* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */ 355#define DBGWVR_EL1_op0 2 356#define DBGWVR_EL1_op1 0 357#define DBGWVR_EL1_CRn 0 358/* DBGWVR_EL1_CRm indicates which watchpoint this register is for */ 359#define DBGWVR_EL1_op2 6 360 361/* DCZID_EL0 - Data Cache Zero ID register */ 362#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 363#define DCZID_BS_SHIFT 0 364#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 365#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 366 367/* DBGAUTHSTATUS_EL1 */ 368#define DBGAUTHSTATUS_EL1 MRS_REG(DBGAUTHSTATUS_EL1) 369#define DBGAUTHSTATUS_EL1_op0 2 370#define DBGAUTHSTATUS_EL1_op1 0 371#define DBGAUTHSTATUS_EL1_CRn 7 372#define DBGAUTHSTATUS_EL1_CRm 14 373#define DBGAUTHSTATUS_EL1_op2 6 374 375/* DBGCLAIMCLR_EL1 */ 376#define DBGCLAIMCLR_EL1 MRS_REG(DBGCLAIMCLR_EL1) 377#define DBGCLAIMCLR_EL1_op0 2 378#define DBGCLAIMCLR_EL1_op1 0 379#define DBGCLAIMCLR_EL1_CRn 7 380#define DBGCLAIMCLR_EL1_CRm 9 381#define DBGCLAIMCLR_EL1_op2 6 382 383/* DBGCLAIMSET_EL1 */ 384#define DBGCLAIMSET_EL1 MRS_REG(DBGCLAIMSET_EL1) 385#define DBGCLAIMSET_EL1_op0 2 386#define DBGCLAIMSET_EL1_op1 0 387#define DBGCLAIMSET_EL1_CRn 7 388#define DBGCLAIMSET_EL1_CRm 8 389#define DBGCLAIMSET_EL1_op2 6 390 391/* DBGPRCR_EL1 */ 392#define DBGPRCR_EL1 MRS_REG(DBGPRCR_EL1) 393#define DBGPRCR_EL1_op0 2 394#define DBGPRCR_EL1_op1 0 395#define DBGPRCR_EL1_CRn 1 396#define DBGPRCR_EL1_CRm 4 397#define DBGPRCR_EL1_op2 4 398 399/* ESR_ELx */ 400#define ESR_ELx_ISS_MASK 0x01ffffff 401#define ISS_FP_TFV_SHIFT 23 402#define ISS_FP_TFV (0x01 << ISS_FP_TFV_SHIFT) 403#define ISS_FP_IOF 0x01 404#define ISS_FP_DZF 0x02 405#define ISS_FP_OFF 0x04 406#define ISS_FP_UFF 0x08 407#define ISS_FP_IXF 0x10 408#define ISS_FP_IDF 0x80 409#define ISS_INSN_FnV (0x01 << 10) 410#define ISS_INSN_EA (0x01 << 9) 411#define ISS_INSN_S1PTW (0x01 << 7) 412#define ISS_INSN_IFSC_MASK (0x1f << 0) 413 414#define ISS_WFx_TI_SHIFT 0 415#define ISS_WFx_TI_MASK (0x03 << ISS_WFx_TI_SHIFT) 416#define ISS_WFx_TI_WFI (0x00 << ISS_WFx_TI_SHIFT) 417#define ISS_WFx_TI_WFE (0x01 << ISS_WFx_TI_SHIFT) 418#define ISS_WFx_TI_WFIT (0x02 << ISS_WFx_TI_SHIFT) 419#define ISS_WFx_TI_WFET (0x03 << ISS_WFx_TI_SHIFT) 420#define ISS_WFx_RV_SHIFT 2 421#define ISS_WFx_RV_MASK (0x01 << ISS_WFx_RV_SHIFT) 422#define ISS_WFx_RV_INVALID (0x00 << ISS_WFx_RV_SHIFT) 423#define ISS_WFx_RV_VALID (0x01 << ISS_WFx_RV_SHIFT) 424#define ISS_WFx_RN_SHIFT 5 425#define ISS_WFx_RN_MASK (0x1f << ISS_WFx_RN_SHIFT) 426#define ISS_WFx_RN(x) (((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT) 427#define ISS_WFx_COND_SHIFT 20 428#define ISS_WFx_COND_MASK (0x0f << ISS_WFx_COND_SHIFT) 429#define ISS_WFx_CV_SHIFT 24 430#define ISS_WFx_CV_MASK (0x01 << ISS_WFx_CV_SHIFT) 431#define ISS_WFx_CV_INVALID (0x00 << ISS_WFx_CV_SHIFT) 432#define ISS_WFx_CV_VALID (0x01 << ISS_WFx_CV_SHIFT) 433 434#define ISS_MSR_DIR_SHIFT 0 435#define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) 436#define ISS_MSR_Rt_SHIFT 5 437#define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) 438#define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) 439#define ISS_MSR_CRm_SHIFT 1 440#define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) 441#define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) 442#define ISS_MSR_CRn_SHIFT 10 443#define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) 444#define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) 445#define ISS_MSR_OP1_SHIFT 14 446#define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) 447#define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) 448#define ISS_MSR_OP2_SHIFT 17 449#define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) 450#define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) 451#define ISS_MSR_OP0_SHIFT 20 452#define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) 453#define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) 454#define ISS_MSR_REG_MASK \ 455 (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | \ 456 ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK) 457#define ISS_MSR_REG(reg) \ 458 (((reg ## _op0) << ISS_MSR_OP0_SHIFT) | \ 459 ((reg ## _op1) << ISS_MSR_OP1_SHIFT) | \ 460 ((reg ## _CRn) << ISS_MSR_CRn_SHIFT) | \ 461 ((reg ## _CRm) << ISS_MSR_CRm_SHIFT) | \ 462 ((reg ## _op2) << ISS_MSR_OP2_SHIFT)) 463 464#define ISS_DATA_ISV_SHIFT 24 465#define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT) 466#define ISS_DATA_SAS_SHIFT 22 467#define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT) 468#define ISS_DATA_SSE_SHIFT 21 469#define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT) 470#define ISS_DATA_SRT_SHIFT 16 471#define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT) 472#define ISS_DATA_SF (0x01 << 15) 473#define ISS_DATA_AR (0x01 << 14) 474#define ISS_DATA_FnV (0x01 << 10) 475#define ISS_DATA_EA (0x01 << 9) 476#define ISS_DATA_CM (0x01 << 8) 477#define ISS_DATA_S1PTW (0x01 << 7) 478#define ISS_DATA_WnR_SHIFT 6 479#define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT) 480#define ISS_DATA_DFSC_MASK (0x3f << 0) 481#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 482#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 483#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 484#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 485#define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 486#define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 487#define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 488#define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 489#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 490#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 491#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 492#define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 493#define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 494#define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 495#define ISS_DATA_DFSC_EXT (0x10 << 0) 496#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 497#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 498#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 499#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 500#define ISS_DATA_DFSC_ECC (0x18 << 0) 501#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 502#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 503#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 504#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 505#define ISS_DATA_DFSC_ALIGN (0x21 << 0) 506#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 507#define ESR_ELx_IL (0x01 << 25) 508#define ESR_ELx_EC_SHIFT 26 509#define ESR_ELx_EC_MASK (0x3f << 26) 510#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 511#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 512#define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ 513#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ 514#define EXCP_BTI 0x0d /* Branch Target Exception */ 515#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 516#define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ 517#define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ 518#define EXCP_HVC 0x16 /* HVC trap */ 519#define EXCP_MSR 0x18 /* MSR/MRS trap */ 520#define EXCP_SVE 0x19 /* SVE trap */ 521#define EXCP_FPAC 0x1c /* Faulting PAC trap */ 522#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 523#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 524#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 525#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 526#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 527#define EXCP_SP_ALIGN 0x26 /* SP slignment fault */ 528#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 529#define EXCP_SERROR 0x2f /* SError interrupt */ 530#define EXCP_BRKPT_EL0 0x30 /* Hardware breakpoint, from same EL */ 531#define EXCP_BRKPT_EL1 0x31 /* Hardware breakpoint, from same EL */ 532#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 533#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 534#define EXCP_WATCHPT_EL0 0x34 /* Watchpoint, from lower EL */ 535#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 536#define EXCP_BRKPT_32 0x38 /* 32bits breakpoint */ 537#define EXCP_BRK 0x3c /* Breakpoint */ 538 539/* ICC_CTLR_EL1 */ 540#define ICC_CTLR_EL1_EOIMODE (1U << 1) 541 542/* ICC_IAR1_EL1 */ 543#define ICC_IAR1_EL1_SPUR (0x03ff) 544 545/* ICC_IGRPEN0_EL1 */ 546#define ICC_IGRPEN0_EL1_EN (1U << 0) 547 548/* ICC_PMR_EL1 */ 549#define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 550 551/* ICC_SGI1R_EL1 */ 552#define ICC_SGI1R_EL1 MRS_REG(ICC_SGI1R_EL1) 553#define ICC_SGI1R_EL1_op0 3 554#define ICC_SGI1R_EL1_op1 0 555#define ICC_SGI1R_EL1_CRn 12 556#define ICC_SGI1R_EL1_CRm 11 557#define ICC_SGI1R_EL1_op2 5 558#define ICC_SGI1R_EL1_TL_SHIFT 0 559#define ICC_SGI1R_EL1_TL_MASK (0xffffUL << ICC_SGI1R_EL1_TL_SHIFT) 560#define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) 561#define ICC_SGI1R_EL1_AFF1_SHIFT 16 562#define ICC_SGI1R_EL1_AFF1_MASK (0xfful << ICC_SGI1R_EL1_AFF1_SHIFT) 563#define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) 564#define ICC_SGI1R_EL1_SGIID_SHIFT 24 565#define ICC_SGI1R_EL1_SGIID_MASK (0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT) 566#define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) 567#define ICC_SGI1R_EL1_AFF2_SHIFT 32 568#define ICC_SGI1R_EL1_AFF2_MASK (0xfful << ICC_SGI1R_EL1_AFF2_SHIFT) 569#define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) 570#define ICC_SGI1R_EL1_RS_SHIFT 44 571#define ICC_SGI1R_EL1_RS_MASK (0xful << ICC_SGI1R_EL1_RS_SHIFT) 572#define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) 573#define ICC_SGI1R_EL1_AFF3_SHIFT 48 574#define ICC_SGI1R_EL1_AFF3_MASK (0xfful << ICC_SGI1R_EL1_AFF3_SHIFT) 575#define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) 576#define ICC_SGI1R_EL1_IRM (0x1UL << 40) 577 578/* ICC_SRE_EL1 */ 579#define ICC_SRE_EL1_SRE (1U << 0) 580 581/* ID_AA64AFR0_EL1 */ 582#define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) 583#define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1) 584#define ID_AA64AFR0_EL1_op0 3 585#define ID_AA64AFR0_EL1_op1 0 586#define ID_AA64AFR0_EL1_CRn 0 587#define ID_AA64AFR0_EL1_CRm 5 588#define ID_AA64AFR0_EL1_op2 4 589 590/* ID_AA64AFR1_EL1 */ 591#define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) 592#define ID_AA64AFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR1_EL1) 593#define ID_AA64AFR1_EL1_op0 3 594#define ID_AA64AFR1_EL1_op1 0 595#define ID_AA64AFR1_EL1_CRn 0 596#define ID_AA64AFR1_EL1_CRm 5 597#define ID_AA64AFR1_EL1_op2 5 598 599/* ID_AA64DFR0_EL1 */ 600#define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) 601#define ID_AA64DFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR0_EL1) 602#define ID_AA64DFR0_EL1_op0 3 603#define ID_AA64DFR0_EL1_op1 0 604#define ID_AA64DFR0_EL1_CRn 0 605#define ID_AA64DFR0_EL1_CRm 5 606#define ID_AA64DFR0_EL1_op2 0 607#define ID_AA64DFR0_DebugVer_SHIFT 0 608#define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT) 609#define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) 610#define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT) 611#define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT) 612#define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT) 613#define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT) 614#define ID_AA64DFR0_DebugVer_8_8 (UL(0xa) << ID_AA64DFR0_DebugVer_SHIFT) 615#define ID_AA64DFR0_TraceVer_SHIFT 4 616#define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT) 617#define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) 618#define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT) 619#define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT) 620#define ID_AA64DFR0_PMUVer_SHIFT 8 621#define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 622#define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) 623#define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT) 624#define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT) 625#define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT) 626#define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT) 627#define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT) 628#define ID_AA64DFR0_PMUVer_3_7 (UL(0x7) << ID_AA64DFR0_PMUVer_SHIFT) 629#define ID_AA64DFR0_PMUVer_3_8 (UL(0x8) << ID_AA64DFR0_PMUVer_SHIFT) 630#define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT) 631#define ID_AA64DFR0_BRPs_SHIFT 12 632#define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT) 633#define ID_AA64DFR0_BRPs_VAL(x) \ 634 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1) 635#define ID_AA64DFR0_PMSS_SHIFT 16 636#define ID_AA64DFR0_PMSS_MASK (UL(0xf) << ID_AA64DFR0_PMSS_SHIFT) 637#define ID_AA64DFR0_PMSS_VAL(x) ((x) & ID_AA64DFR0_PMSS_MASK) 638#define ID_AA64DFR0_PMSS_NONE (UL(0x0) << ID_AA64DFR0_PMSS_SHIFT) 639#define ID_AA64DFR0_PMSS_IMPL (UL(0x1) << ID_AA64DFR0_PMSS_SHIFT) 640#define ID_AA64DFR0_WRPs_SHIFT 20 641#define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) 642#define ID_AA64DFR0_WRPs_VAL(x) \ 643 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) 644#define ID_AA64DFR0_CTX_CMPs_SHIFT 28 645#define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) 646#define ID_AA64DFR0_CTX_CMPs_VAL(x) \ 647 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1) 648#define ID_AA64DFR0_PMSVer_SHIFT 32 649#define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT) 650#define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) 651#define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT) 652#define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT) 653#define ID_AA64DFR0_PMSVer_SPE_1_1 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT) 654#define ID_AA64DFR0_PMSVer_SPE_1_2 (UL(0x3) << ID_AA64DFR0_PMSVer_SHIFT) 655#define ID_AA64DFR0_PMSVer_SPE_1_3 (UL(0x4) << ID_AA64DFR0_PMSVer_SHIFT) 656#define ID_AA64DFR0_DoubleLock_SHIFT 36 657#define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 658#define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) 659#define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT) 660#define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT) 661#define ID_AA64DFR0_TraceFilt_SHIFT 40 662#define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT) 663#define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) 664#define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT) 665#define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT) 666#define ID_AA64DFR0_TraceBuffer_SHIFT 44 667#define ID_AA64DFR0_TraceBuffer_MASK (UL(0xf) << ID_AA64DFR0_TraceBuffer_SHIFT) 668#define ID_AA64DFR0_TraceBuffer_VAL(x) ((x) & ID_AA64DFR0_TraceBuffer_MASK) 669#define ID_AA64DFR0_TraceBuffer_NONE (UL(0x0) << ID_AA64DFR0_TraceBuffer_SHIFT) 670#define ID_AA64DFR0_TraceBuffer_IMPL (UL(0x1) << ID_AA64DFR0_TraceBuffer_SHIFT) 671#define ID_AA64DFR0_MTPMU_SHIFT 48 672#define ID_AA64DFR0_MTPMU_MASK (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT) 673#define ID_AA64DFR0_MTPMU_VAL(x) ((x) & ID_AA64DFR0_MTPMU_MASK) 674#define ID_AA64DFR0_MTPMU_NONE (UL(0x0) << ID_AA64DFR0_MTPMU_SHIFT) 675#define ID_AA64DFR0_MTPMU_IMPL (UL(0x1) << ID_AA64DFR0_MTPMU_SHIFT) 676#define ID_AA64DFR0_MTPMU_NONE_MT_RES0 (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT) 677#define ID_AA64DFR0_BRBE_SHIFT 52 678#define ID_AA64DFR0_BRBE_MASK (UL(0xf) << ID_AA64DFR0_BRBE_SHIFT) 679#define ID_AA64DFR0_BRBE_VAL(x) ((x) & ID_AA64DFR0_BRBE_MASK) 680#define ID_AA64DFR0_BRBE_NONE (UL(0x0) << ID_AA64DFR0_BRBE_SHIFT) 681#define ID_AA64DFR0_BRBE_IMPL (UL(0x1) << ID_AA64DFR0_BRBE_SHIFT) 682#define ID_AA64DFR0_BRBE_EL3 (UL(0x2) << ID_AA64DFR0_BRBE_SHIFT) 683#define ID_AA64DFR0_HPMN0_SHIFT 60 684#define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT) 685#define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK) 686#define ID_AA64DFR0_HPMN0_CONSTR (UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT) 687#define ID_AA64DFR0_HPMN0_DEFINED (UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT) 688 689/* ID_AA64DFR1_EL1 */ 690#define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1) 691#define ID_AA64DFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR1_EL1) 692#define ID_AA64DFR1_EL1_op0 3 693#define ID_AA64DFR1_EL1_op1 0 694#define ID_AA64DFR1_EL1_CRn 0 695#define ID_AA64DFR1_EL1_CRm 5 696#define ID_AA64DFR1_EL1_op2 1 697 698/* ID_AA64ISAR0_EL1 */ 699#define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) 700#define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1) 701#define ID_AA64ISAR0_EL1_op0 3 702#define ID_AA64ISAR0_EL1_op1 0 703#define ID_AA64ISAR0_EL1_CRn 0 704#define ID_AA64ISAR0_EL1_CRm 6 705#define ID_AA64ISAR0_EL1_op2 0 706#define ID_AA64ISAR0_AES_SHIFT 4 707#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT) 708#define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) 709#define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT) 710#define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT) 711#define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT) 712#define ID_AA64ISAR0_SHA1_SHIFT 8 713#define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT) 714#define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 715#define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT) 716#define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT) 717#define ID_AA64ISAR0_SHA2_SHIFT 12 718#define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT) 719#define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 720#define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT) 721#define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT) 722#define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT) 723#define ID_AA64ISAR0_CRC32_SHIFT 16 724#define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT) 725#define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 726#define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT) 727#define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT) 728#define ID_AA64ISAR0_Atomic_SHIFT 20 729#define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT) 730#define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) 731#define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT) 732#define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT) 733#define ID_AA64ISAR0_TME_SHIFT 24 734#define ID_AA64ISAR0_TME_MASK (UL(0xf) << ID_AA64ISAR0_TME_SHIFT) 735#define ID_AA64ISAR0_TME_NONE (UL(0x0) << ID_AA64ISAR0_TME_SHIFT) 736#define ID_AA64ISAR0_TME_IMPL (UL(0x1) << ID_AA64ISAR0_TME_SHIFT) 737#define ID_AA64ISAR0_RDM_SHIFT 28 738#define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT) 739#define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) 740#define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT) 741#define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT) 742#define ID_AA64ISAR0_SHA3_SHIFT 32 743#define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT) 744#define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 745#define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT) 746#define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT) 747#define ID_AA64ISAR0_SM3_SHIFT 36 748#define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT) 749#define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) 750#define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT) 751#define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT) 752#define ID_AA64ISAR0_SM4_SHIFT 40 753#define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT) 754#define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) 755#define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT) 756#define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT) 757#define ID_AA64ISAR0_DP_SHIFT 44 758#define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT) 759#define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) 760#define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT) 761#define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT) 762#define ID_AA64ISAR0_FHM_SHIFT 48 763#define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT) 764#define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) 765#define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT) 766#define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT) 767#define ID_AA64ISAR0_TS_SHIFT 52 768#define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT) 769#define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) 770#define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT) 771#define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT) 772#define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT) 773#define ID_AA64ISAR0_TLB_SHIFT 56 774#define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT) 775#define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) 776#define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT) 777#define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT) 778#define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT) 779#define ID_AA64ISAR0_RNDR_SHIFT 60 780#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT) 781#define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 782#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT) 783#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT) 784 785/* ID_AA64ISAR1_EL1 */ 786#define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) 787#define ID_AA64ISAR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1) 788#define ID_AA64ISAR1_EL1_op0 3 789#define ID_AA64ISAR1_EL1_op1 0 790#define ID_AA64ISAR1_EL1_CRn 0 791#define ID_AA64ISAR1_EL1_CRm 6 792#define ID_AA64ISAR1_EL1_op2 1 793#define ID_AA64ISAR1_DPB_SHIFT 0 794#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT) 795#define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) 796#define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT) 797#define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT) 798#define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT) 799#define ID_AA64ISAR1_APA_SHIFT 4 800#define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT) 801#define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) 802#define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT) 803#define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT) 804#define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT) 805#define ID_AA64ISAR1_APA_EPAC2 (UL(0x3) << ID_AA64ISAR1_APA_SHIFT) 806#define ID_AA64ISAR1_APA_FPAC (UL(0x4) << ID_AA64ISAR1_APA_SHIFT) 807#define ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT) 808#define ID_AA64ISAR1_API_SHIFT 8 809#define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT) 810#define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) 811#define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT) 812#define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT) 813#define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT) 814#define ID_AA64ISAR1_API_EPAC2 (UL(0x3) << ID_AA64ISAR1_API_SHIFT) 815#define ID_AA64ISAR1_API_FPAC (UL(0x4) << ID_AA64ISAR1_API_SHIFT) 816#define ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT) 817#define ID_AA64ISAR1_JSCVT_SHIFT 12 818#define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT) 819#define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 820#define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT) 821#define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT) 822#define ID_AA64ISAR1_FCMA_SHIFT 16 823#define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT) 824#define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 825#define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT) 826#define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT) 827#define ID_AA64ISAR1_LRCPC_SHIFT 20 828#define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT) 829#define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 830#define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT) 831#define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT) 832#define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT) 833#define ID_AA64ISAR1_GPA_SHIFT 24 834#define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT) 835#define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) 836#define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT) 837#define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT) 838#define ID_AA64ISAR1_GPI_SHIFT 28 839#define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT) 840#define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) 841#define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT) 842#define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT) 843#define ID_AA64ISAR1_FRINTTS_SHIFT 32 844#define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT) 845#define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 846#define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT) 847#define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT) 848#define ID_AA64ISAR1_SB_SHIFT 36 849#define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT) 850#define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) 851#define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT) 852#define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT) 853#define ID_AA64ISAR1_SPECRES_SHIFT 40 854#define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT) 855#define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 856#define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT) 857#define ID_AA64ISAR1_SPECRES_IMPL (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT) 858#define ID_AA64ISAR1_BF16_SHIFT 44 859#define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT) 860#define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) 861#define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT) 862#define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT) 863#define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT) 864#define ID_AA64ISAR1_DGH_SHIFT 48 865#define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT) 866#define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) 867#define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT) 868#define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT) 869#define ID_AA64ISAR1_I8MM_SHIFT 52 870#define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT) 871#define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 872#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT) 873#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT) 874#define ID_AA64ISAR1_XS_SHIFT 56 875#define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT) 876#define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) 877#define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT) 878#define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT) 879#define ID_AA64ISAR1_LS64_SHIFT 60 880#define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT) 881#define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) 882#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT) 883#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT) 884#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT) 885#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT) 886 887/* ID_AA64ISAR2_EL1 */ 888#define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) 889#define ID_AA64ISAR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1) 890#define ID_AA64ISAR2_EL1_op0 3 891#define ID_AA64ISAR2_EL1_op1 0 892#define ID_AA64ISAR2_EL1_CRn 0 893#define ID_AA64ISAR2_EL1_CRm 6 894#define ID_AA64ISAR2_EL1_op2 2 895#define ID_AA64ISAR2_WFxT_SHIFT 0 896#define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT) 897#define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) 898#define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT) 899#define ID_AA64ISAR2_WFxT_IMPL (UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT) 900#define ID_AA64ISAR2_RPRES_SHIFT 4 901#define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT) 902#define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) 903#define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT) 904#define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT) 905#define ID_AA64ISAR2_GPA3_SHIFT 8 906#define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT) 907#define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) 908#define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT) 909#define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT) 910#define ID_AA64ISAR2_APA3_SHIFT 12 911#define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT) 912#define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) 913#define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT) 914#define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT) 915#define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT) 916#define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT) 917#define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT) 918#define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT) 919#define ID_AA64ISAR2_MOPS_SHIFT 16 920#define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT) 921#define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) 922#define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT) 923#define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT) 924#define ID_AA64ISAR2_BC_SHIFT 20 925#define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT) 926#define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) 927#define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT) 928#define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT) 929#define ID_AA64ISAR2_PAC_frac_SHIFT 28 930#define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT) 931#define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) 932#define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT) 933#define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT) 934 935/* ID_AA64MMFR0_EL1 */ 936#define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) 937#define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1) 938#define ID_AA64MMFR0_EL1_op0 3 939#define ID_AA64MMFR0_EL1_op1 0 940#define ID_AA64MMFR0_EL1_CRn 0 941#define ID_AA64MMFR0_EL1_CRm 7 942#define ID_AA64MMFR0_EL1_op2 0 943#define ID_AA64MMFR0_PARange_SHIFT 0 944#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT) 945#define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) 946#define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT) 947#define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT) 948#define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT) 949#define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT) 950#define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT) 951#define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT) 952#define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT) 953#define ID_AA64MMFR0_ASIDBits_SHIFT 4 954#define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT) 955#define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) 956#define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT) 957#define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT) 958#define ID_AA64MMFR0_BigEnd_SHIFT 8 959#define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT) 960#define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) 961#define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT) 962#define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT) 963#define ID_AA64MMFR0_SNSMem_SHIFT 12 964#define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT) 965#define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) 966#define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT) 967#define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT) 968#define ID_AA64MMFR0_BigEndEL0_SHIFT 16 969#define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT) 970#define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) 971#define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT) 972#define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT) 973#define ID_AA64MMFR0_TGran16_SHIFT 20 974#define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT) 975#define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) 976#define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT) 977#define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT) 978#define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT) 979#define ID_AA64MMFR0_TGran64_SHIFT 24 980#define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 981#define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) 982#define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT) 983#define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT) 984#define ID_AA64MMFR0_TGran4_SHIFT 28 985#define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 986#define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) 987#define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT) 988#define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT) 989#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT) 990#define ID_AA64MMFR0_TGran16_2_SHIFT 32 991#define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT) 992#define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) 993#define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT) 994#define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT) 995#define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT) 996#define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT) 997#define ID_AA64MMFR0_TGran64_2_SHIFT 36 998#define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT) 999#define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) 1000#define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT) 1001#define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT) 1002#define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT) 1003#define ID_AA64MMFR0_TGran4_2_SHIFT 40 1004#define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT) 1005#define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) 1006#define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT) 1007#define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT) 1008#define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT) 1009#define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT) 1010#define ID_AA64MMFR0_ExS_SHIFT 44 1011#define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT) 1012#define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) 1013#define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT) 1014#define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT) 1015#define ID_AA64MMFR0_FGT_SHIFT 56 1016#define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT) 1017#define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK) 1018#define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT) 1019#define ID_AA64MMFR0_FGT_IMPL (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT) 1020#define ID_AA64MMFR0_ECV_SHIFT 60 1021#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT) 1022#define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK) 1023#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT) 1024#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT) 1025#define ID_AA64MMFR0_ECV_CNTHCTL (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT) 1026 1027/* ID_AA64MMFR1_EL1 */ 1028#define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) 1029#define ID_AA64MMFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1) 1030#define ID_AA64MMFR1_EL1_op0 3 1031#define ID_AA64MMFR1_EL1_op1 0 1032#define ID_AA64MMFR1_EL1_CRn 0 1033#define ID_AA64MMFR1_EL1_CRm 7 1034#define ID_AA64MMFR1_EL1_op2 1 1035#define ID_AA64MMFR1_HAFDBS_SHIFT 0 1036#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT) 1037#define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 1038#define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT) 1039#define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT) 1040#define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT) 1041#define ID_AA64MMFR1_VMIDBits_SHIFT 4 1042#define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT) 1043#define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) 1044#define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT) 1045#define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT) 1046#define ID_AA64MMFR1_VH_SHIFT 8 1047#define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT) 1048#define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) 1049#define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT) 1050#define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT) 1051#define ID_AA64MMFR1_HPDS_SHIFT 12 1052#define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT) 1053#define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 1054#define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT) 1055#define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT) 1056#define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT) 1057#define ID_AA64MMFR1_LO_SHIFT 16 1058#define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT) 1059#define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) 1060#define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT) 1061#define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT) 1062#define ID_AA64MMFR1_PAN_SHIFT 20 1063#define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT) 1064#define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) 1065#define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT) 1066#define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT) 1067#define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 1068#define ID_AA64MMFR1_PAN_EPAN (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT) 1069#define ID_AA64MMFR1_SpecSEI_SHIFT 24 1070#define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT) 1071#define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) 1072#define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT) 1073#define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT) 1074#define ID_AA64MMFR1_XNX_SHIFT 28 1075#define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT) 1076#define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) 1077#define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT) 1078#define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT) 1079#define ID_AA64MMFR1_TWED_SHIFT 32 1080#define ID_AA64MMFR1_TWED_MASK (UL(0xf) << ID_AA64MMFR1_TWED_SHIFT) 1081#define ID_AA64MMFR1_TWED_VAL(x) ((x) & ID_AA64MMFR1_TWED_MASK) 1082#define ID_AA64MMFR1_TWED_NONE (UL(0x0) << ID_AA64MMFR1_TWED_SHIFT) 1083#define ID_AA64MMFR1_TWED_IMPL (UL(0x1) << ID_AA64MMFR1_TWED_SHIFT) 1084#define ID_AA64MMFR1_ETS_SHIFT 36 1085#define ID_AA64MMFR1_ETS_MASK (UL(0xf) << ID_AA64MMFR1_ETS_SHIFT) 1086#define ID_AA64MMFR1_ETS_VAL(x) ((x) & ID_AA64MMFR1_ETS_MASK) 1087#define ID_AA64MMFR1_ETS_NONE (UL(0x0) << ID_AA64MMFR1_ETS_SHIFT) 1088#define ID_AA64MMFR1_ETS_IMPL (UL(0x1) << ID_AA64MMFR1_ETS_SHIFT) 1089#define ID_AA64MMFR1_HCX_SHIFT 40 1090#define ID_AA64MMFR1_HCX_MASK (UL(0xf) << ID_AA64MMFR1_HCX_SHIFT) 1091#define ID_AA64MMFR1_HCX_VAL(x) ((x) & ID_AA64MMFR1_HCX_MASK) 1092#define ID_AA64MMFR1_HCX_NONE (UL(0x0) << ID_AA64MMFR1_HCX_SHIFT) 1093#define ID_AA64MMFR1_HCX_IMPL (UL(0x1) << ID_AA64MMFR1_HCX_SHIFT) 1094#define ID_AA64MMFR1_AFP_SHIFT 44 1095#define ID_AA64MMFR1_AFP_MASK (UL(0xf) << ID_AA64MMFR1_AFP_SHIFT) 1096#define ID_AA64MMFR1_AFP_VAL(x) ((x) & ID_AA64MMFR1_AFP_MASK) 1097#define ID_AA64MMFR1_AFP_NONE (UL(0x0) << ID_AA64MMFR1_AFP_SHIFT) 1098#define ID_AA64MMFR1_AFP_IMPL (UL(0x1) << ID_AA64MMFR1_AFP_SHIFT) 1099#define ID_AA64MMFR1_nTLBPA_SHIFT 48 1100#define ID_AA64MMFR1_nTLBPA_MASK (UL(0xf) << ID_AA64MMFR1_nTLBPA_SHIFT) 1101#define ID_AA64MMFR1_nTLBPA_VAL(x) ((x) & ID_AA64MMFR1_nTLBPA_MASK) 1102#define ID_AA64MMFR1_nTLBPA_NONE (UL(0x0) << ID_AA64MMFR1_nTLBPA_SHIFT) 1103#define ID_AA64MMFR1_nTLBPA_IMPL (UL(0x1) << ID_AA64MMFR1_nTLBPA_SHIFT) 1104#define ID_AA64MMFR1_TIDCP1_SHIFT 52 1105#define ID_AA64MMFR1_TIDCP1_MASK (UL(0xf) << ID_AA64MMFR1_TIDCP1_SHIFT) 1106#define ID_AA64MMFR1_TIDCP1_VAL(x) ((x) & ID_AA64MMFR1_TIDCP1_MASK) 1107#define ID_AA64MMFR1_TIDCP1_NONE (UL(0x0) << ID_AA64MMFR1_TIDCP1_SHIFT) 1108#define ID_AA64MMFR1_TIDCP1_IMPL (UL(0x1) << ID_AA64MMFR1_TIDCP1_SHIFT) 1109#define ID_AA64MMFR1_CMOVW_SHIFT 56 1110#define ID_AA64MMFR1_CMOVW_MASK (UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT) 1111#define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK) 1112#define ID_AA64MMFR1_CMOVW_NONE (UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT) 1113#define ID_AA64MMFR1_CMOVW_IMPL (UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT) 1114 1115/* ID_AA64MMFR2_EL1 */ 1116#define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) 1117#define ID_AA64MMFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1) 1118#define ID_AA64MMFR2_EL1_op0 3 1119#define ID_AA64MMFR2_EL1_op1 0 1120#define ID_AA64MMFR2_EL1_CRn 0 1121#define ID_AA64MMFR2_EL1_CRm 7 1122#define ID_AA64MMFR2_EL1_op2 2 1123#define ID_AA64MMFR2_CnP_SHIFT 0 1124#define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT) 1125#define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) 1126#define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT) 1127#define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT) 1128#define ID_AA64MMFR2_UAO_SHIFT 4 1129#define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT) 1130#define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) 1131#define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT) 1132#define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT) 1133#define ID_AA64MMFR2_LSM_SHIFT 8 1134#define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT) 1135#define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) 1136#define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT) 1137#define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT) 1138#define ID_AA64MMFR2_IESB_SHIFT 12 1139#define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT) 1140#define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) 1141#define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT) 1142#define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT) 1143#define ID_AA64MMFR2_VARange_SHIFT 16 1144#define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT) 1145#define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) 1146#define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT) 1147#define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT) 1148#define ID_AA64MMFR2_CCIDX_SHIFT 20 1149#define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT) 1150#define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 1151#define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT) 1152#define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT) 1153#define ID_AA64MMFR2_NV_SHIFT 24 1154#define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT) 1155#define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) 1156#define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT) 1157#define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT) 1158#define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT) 1159#define ID_AA64MMFR2_ST_SHIFT 28 1160#define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT) 1161#define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) 1162#define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT) 1163#define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT) 1164#define ID_AA64MMFR2_AT_SHIFT 32 1165#define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT) 1166#define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) 1167#define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT) 1168#define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT) 1169#define ID_AA64MMFR2_IDS_SHIFT 36 1170#define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT) 1171#define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) 1172#define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT) 1173#define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT) 1174#define ID_AA64MMFR2_FWB_SHIFT 40 1175#define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT) 1176#define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) 1177#define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT) 1178#define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT) 1179#define ID_AA64MMFR2_TTL_SHIFT 48 1180#define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT) 1181#define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) 1182#define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT) 1183#define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT) 1184#define ID_AA64MMFR2_BBM_SHIFT 52 1185#define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT) 1186#define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) 1187#define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT) 1188#define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT) 1189#define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT) 1190#define ID_AA64MMFR2_EVT_SHIFT 56 1191#define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT) 1192#define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) 1193#define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT) 1194#define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT) 1195#define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT) 1196#define ID_AA64MMFR2_E0PD_SHIFT 60 1197#define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT) 1198#define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) 1199#define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) 1200#define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) 1201 1202/* ID_AA64MMFR3_EL1 */ 1203#define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1) 1204#define ID_AA64MMFR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1) 1205#define ID_AA64MMFR3_EL1_op0 3 1206#define ID_AA64MMFR3_EL1_op1 0 1207#define ID_AA64MMFR3_EL1_CRn 0 1208#define ID_AA64MMFR3_EL1_CRm 7 1209#define ID_AA64MMFR3_EL1_op2 3 1210#define ID_AA64MMFR3_TCRX_SHIFT 0 1211#define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT) 1212#define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK) 1213#define ID_AA64MMFR3_TCRX_NONE (UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT) 1214#define ID_AA64MMFR3_TCRX_IMPL (UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT) 1215#define ID_AA64MMFR3_SCTLRX_SHIFT 4 1216#define ID_AA64MMFR3_SCTLRX_MASK (UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT) 1217#define ID_AA64MMFR3_SCTLRX_VAL(x) ((x) & ID_AA64MMFR3_SCTLRX_MASK) 1218#define ID_AA64MMFR3_SCTLRX_NONE (UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT) 1219#define ID_AA64MMFR3_SCTLRX_IMPL (UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT) 1220#define ID_AA64MMFR3_MEC_SHIFT 28 1221#define ID_AA64MMFR3_MEC_MASK (UL(0xf) << ID_AA64MMFR3_MEC_SHIFT) 1222#define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) 1223#define ID_AA64MMFR3_MEC_NONE (UL(0x0) << ID_AA64MMFR3_MEC_SHIFT) 1224#define ID_AA64MMFR3_MEC_IMPL (UL(0x1) << ID_AA64MMFR3_MEC_SHIFT) 1225#define ID_AA64MMFR3_Spec_FPACC_SHIFT 60 1226#define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT) 1227#define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK) 1228#define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT) 1229#define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT) 1230 1231/* ID_AA64MMFR4_EL1 */ 1232#define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1) 1233#define ID_AA64MMFR4_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1) 1234#define ID_AA64MMFR4_EL1_op0 3 1235#define ID_AA64MMFR4_EL1_op1 0 1236#define ID_AA64MMFR4_EL1_CRn 0 1237#define ID_AA64MMFR4_EL1_CRm 7 1238#define ID_AA64MMFR4_EL1_op2 4 1239 1240/* ID_AA64PFR0_EL1 */ 1241#define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) 1242#define ID_AA64PFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR0_EL1) 1243#define ID_AA64PFR0_EL1_op0 3 1244#define ID_AA64PFR0_EL1_op1 0 1245#define ID_AA64PFR0_EL1_CRn 0 1246#define ID_AA64PFR0_EL1_CRm 4 1247#define ID_AA64PFR0_EL1_op2 0 1248#define ID_AA64PFR0_EL0_SHIFT 0 1249#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT) 1250#define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) 1251#define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT) 1252#define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT) 1253#define ID_AA64PFR0_EL1_SHIFT 4 1254#define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT) 1255#define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) 1256#define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT) 1257#define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT) 1258#define ID_AA64PFR0_EL2_SHIFT 8 1259#define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT) 1260#define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) 1261#define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT) 1262#define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT) 1263#define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT) 1264#define ID_AA64PFR0_EL3_SHIFT 12 1265#define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT) 1266#define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) 1267#define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT) 1268#define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT) 1269#define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT) 1270#define ID_AA64PFR0_FP_SHIFT 16 1271#define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 1272#define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) 1273#define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT) 1274#define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT) 1275#define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT) 1276#define ID_AA64PFR0_AdvSIMD_SHIFT 20 1277#define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 1278#define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) 1279#define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT) 1280#define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT) 1281#define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT) 1282#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 1283#define ID_AA64PFR0_GIC_SHIFT 24 1284#define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT) 1285#define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) 1286#define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) 1287#define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) 1288#define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT) 1289#define ID_AA64PFR0_RAS_SHIFT 28 1290#define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) 1291#define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) 1292#define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT) 1293#define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT) 1294#define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT) 1295#define ID_AA64PFR0_SVE_SHIFT 32 1296#define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT) 1297#define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) 1298#define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT) 1299#define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT) 1300#define ID_AA64PFR0_SEL2_SHIFT 36 1301#define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT) 1302#define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) 1303#define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT) 1304#define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT) 1305#define ID_AA64PFR0_MPAM_SHIFT 40 1306#define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT) 1307#define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) 1308#define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT) 1309#define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT) 1310#define ID_AA64PFR0_AMU_SHIFT 44 1311#define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT) 1312#define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) 1313#define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT) 1314#define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT) 1315#define ID_AA64PFR0_AMU_V1_1 (UL(0x2) << ID_AA64PFR0_AMU_SHIFT) 1316#define ID_AA64PFR0_DIT_SHIFT 48 1317#define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT) 1318#define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) 1319#define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT) 1320#define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT) 1321#define ID_AA64PFR0_RME_SHIFT 52 1322#define ID_AA64PFR0_RME_MASK (UL(0xf) << ID_AA64PFR0_RME_SHIFT) 1323#define ID_AA64PFR0_RME_VAL(x) ((x) & ID_AA64PFR0_RME_MASK) 1324#define ID_AA64PFR0_RME_NONE (UL(0x0) << ID_AA64PFR0_RME_SHIFT) 1325#define ID_AA64PFR0_RME_IMPL (UL(0x1) << ID_AA64PFR0_RME_SHIFT) 1326#define ID_AA64PFR0_CSV2_SHIFT 56 1327#define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT) 1328#define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) 1329#define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT) 1330#define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT) 1331#define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT) 1332#define ID_AA64PFR0_CSV2_3 (UL(0x3) << ID_AA64PFR0_CSV2_SHIFT) 1333#define ID_AA64PFR0_CSV3_SHIFT 60 1334#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT) 1335#define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) 1336#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT) 1337#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT) 1338 1339/* ID_AA64PFR1_EL1 */ 1340#define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) 1341#define ID_AA64PFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR1_EL1) 1342#define ID_AA64PFR1_EL1_op0 3 1343#define ID_AA64PFR1_EL1_op1 0 1344#define ID_AA64PFR1_EL1_CRn 0 1345#define ID_AA64PFR1_EL1_CRm 4 1346#define ID_AA64PFR1_EL1_op2 1 1347#define ID_AA64PFR1_BT_SHIFT 0 1348#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT) 1349#define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) 1350#define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT) 1351#define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT) 1352#define ID_AA64PFR1_SSBS_SHIFT 4 1353#define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT) 1354#define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) 1355#define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT) 1356#define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT) 1357#define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT) 1358#define ID_AA64PFR1_MTE_SHIFT 8 1359#define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT) 1360#define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) 1361#define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT) 1362#define ID_AA64PFR1_MTE_MTE (UL(0x1) << ID_AA64PFR1_MTE_SHIFT) 1363#define ID_AA64PFR1_MTE_MTE2 (UL(0x2) << ID_AA64PFR1_MTE_SHIFT) 1364#define ID_AA64PFR1_MTE_MTE3 (UL(0x3) << ID_AA64PFR1_MTE_SHIFT) 1365#define ID_AA64PFR1_RAS_frac_SHIFT 12 1366#define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT) 1367#define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) 1368#define ID_AA64PFR1_RAS_frac_p0 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT) 1369#define ID_AA64PFR1_RAS_frac_p1 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT) 1370#define ID_AA64PFR1_MPAM_frac_SHIFT 16 1371#define ID_AA64PFR1_MPAM_frac_MASK (UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT) 1372#define ID_AA64PFR1_MPAM_frac_VAL(x) ((x) & ID_AA64PFR1_MPAM_frac_MASK) 1373#define ID_AA64PFR1_MPAM_frac_p0 (UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT) 1374#define ID_AA64PFR1_MPAM_frac_p1 (UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT) 1375#define ID_AA64PFR1_SME_SHIFT 24 1376#define ID_AA64PFR1_SME_MASK (UL(0xf) << ID_AA64PFR1_SME_SHIFT) 1377#define ID_AA64PFR1_SME_VAL(x) ((x) & ID_AA64PFR1_SME_MASK) 1378#define ID_AA64PFR1_SME_NONE (UL(0x0) << ID_AA64PFR1_SME_SHIFT) 1379#define ID_AA64PFR1_SME_SME (UL(0x1) << ID_AA64PFR1_SME_SHIFT) 1380#define ID_AA64PFR1_SME_SME2 (UL(0x2) << ID_AA64PFR1_SME_SHIFT) 1381#define ID_AA64PFR1_RNDR_trap_SHIFT 28 1382#define ID_AA64PFR1_RNDR_trap_MASK (UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT) 1383#define ID_AA64PFR1_RNDR_trap_VAL(x) ((x) & ID_AA64PFR1_RNDR_trap_MASK) 1384#define ID_AA64PFR1_RNDR_trap_NONE (UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT) 1385#define ID_AA64PFR1_RNDR_trap_IMPL (UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT) 1386#define ID_AA64PFR1_CSV2_frac_SHIFT 32 1387#define ID_AA64PFR1_CSV2_frac_MASK (UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT) 1388#define ID_AA64PFR1_CSV2_frac_VAL(x) ((x) & ID_AA64PFR1_CSV2_frac_MASK) 1389#define ID_AA64PFR1_CSV2_frac_p0 (UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT) 1390#define ID_AA64PFR1_CSV2_frac_p1 (UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT) 1391#define ID_AA64PFR1_CSV2_frac_p2 (UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT) 1392#define ID_AA64PFR1_NMI_SHIFT 36 1393#define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT) 1394#define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK) 1395#define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT) 1396#define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT) 1397 1398/* ID_AA64PFR2_EL1 */ 1399#define ID_AA64PFR2_EL1 MRS_REG(ID_AA64PFR2_EL1) 1400#define ID_AA64PFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR2_EL1) 1401#define ID_AA64PFR2_EL1_op0 3 1402#define ID_AA64PFR2_EL1_op1 0 1403#define ID_AA64PFR2_EL1_CRn 0 1404#define ID_AA64PFR2_EL1_CRm 4 1405#define ID_AA64PFR2_EL1_op2 2 1406 1407/* ID_AA64ZFR0_EL1 */ 1408#define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) 1409#define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) 1410#define ID_AA64ZFR0_EL1_op0 3 1411#define ID_AA64ZFR0_EL1_op1 0 1412#define ID_AA64ZFR0_EL1_CRn 0 1413#define ID_AA64ZFR0_EL1_CRm 4 1414#define ID_AA64ZFR0_EL1_op2 4 1415#define ID_AA64ZFR0_SVEver_SHIFT 0 1416#define ID_AA64ZFR0_SVEver_MASK (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT) 1417#define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK 1418#define ID_AA64ZFR0_SVEver_SVE1 (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT) 1419#define ID_AA64ZFR0_SVEver_SVE2 (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT) 1420#define ID_AA64ZFR0_AES_SHIFT 4 1421#define ID_AA64ZFR0_AES_MASK (UL(0xf) << ID_AA64ZFR0_AES_SHIFT) 1422#define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK 1423#define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT) 1424#define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT) 1425#define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT) 1426#define ID_AA64ZFR0_BitPerm_SHIFT 16 1427#define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT) 1428#define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK 1429#define ID_AA64ZFR0_BitPerm_NONE (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT) 1430#define ID_AA64ZFR0_BitPerm_IMPL (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT) 1431#define ID_AA64ZFR0_BF16_SHIFT 20 1432#define ID_AA64ZFR0_BF16_MASK (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT) 1433#define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK 1434#define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT) 1435#define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) 1436#define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) 1437#define ID_AA64ZFR0_SHA3_SHIFT 32 1438#define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT) 1439#define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK 1440#define ID_AA64ZFR0_SHA3_NONE (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT) 1441#define ID_AA64ZFR0_SHA3_IMPL (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT) 1442#define ID_AA64ZFR0_SM4_SHIFT 40 1443#define ID_AA64ZFR0_SM4_MASK (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT) 1444#define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK 1445#define ID_AA64ZFR0_SM4_NONE (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT) 1446#define ID_AA64ZFR0_SM4_IMPL (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT) 1447#define ID_AA64ZFR0_I8MM_SHIFT 44 1448#define ID_AA64ZFR0_I8MM_MASK (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT) 1449#define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK 1450#define ID_AA64ZFR0_I8MM_NONE (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT) 1451#define ID_AA64ZFR0_I8MM_IMPL (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT) 1452#define ID_AA64ZFR0_F32MM_SHIFT 52 1453#define ID_AA64ZFR0_F32MM_MASK (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT) 1454#define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK 1455#define ID_AA64ZFR0_F32MM_NONE (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT) 1456#define ID_AA64ZFR0_F32MM_IMPL (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT) 1457#define ID_AA64ZFR0_F64MM_SHIFT 56 1458#define ID_AA64ZFR0_F64MM_MASK (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT) 1459#define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK 1460#define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT) 1461#define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT) 1462 1463/* ID_ISAR5_EL1 */ 1464#define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) 1465#define ID_ISAR5_EL1_op0 0x3 1466#define ID_ISAR5_EL1_op1 0x0 1467#define ID_ISAR5_EL1_CRn 0x0 1468#define ID_ISAR5_EL1_CRm 0x2 1469#define ID_ISAR5_EL1_op2 0x5 1470#define ID_ISAR5_SEVL_SHIFT 0 1471#define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT) 1472#define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) 1473#define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT) 1474#define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT) 1475#define ID_ISAR5_AES_SHIFT 4 1476#define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT) 1477#define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) 1478#define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT) 1479#define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT) 1480#define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT) 1481#define ID_ISAR5_SHA1_SHIFT 8 1482#define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT) 1483#define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) 1484#define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT) 1485#define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT) 1486#define ID_ISAR5_SHA2_SHIFT 12 1487#define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT) 1488#define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) 1489#define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT) 1490#define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT) 1491#define ID_ISAR5_CRC32_SHIFT 16 1492#define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT) 1493#define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) 1494#define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT) 1495#define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT) 1496#define ID_ISAR5_RDM_SHIFT 24 1497#define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT) 1498#define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) 1499#define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT) 1500#define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT) 1501#define ID_ISAR5_VCMA_SHIFT 28 1502#define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT) 1503#define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) 1504#define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT) 1505#define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT) 1506 1507/* MAIR_EL1 - Memory Attribute Indirection Register */ 1508#define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8)) 1509#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 1510#define MAIR_DEVICE_nGnRnE UL(0x00) 1511#define MAIR_DEVICE_nGnRE UL(0x04) 1512#define MAIR_NORMAL_NC UL(0x44) 1513#define MAIR_NORMAL_WT UL(0xbb) 1514#define MAIR_NORMAL_WB UL(0xff) 1515 1516/* MDCCINT_EL1 */ 1517#define MDCCINT_EL1 MRS_REG(MDCCINT_EL1) 1518#define MDCCINT_EL1_op0 2 1519#define MDCCINT_EL1_op1 0 1520#define MDCCINT_EL1_CRn 0 1521#define MDCCINT_EL1_CRm 2 1522#define MDCCINT_EL1_op2 0 1523 1524/* MDCCSR_EL0 */ 1525#define MDCCSR_EL0 MRS_REG(MDCCSR_EL0) 1526#define MDCCSR_EL0_op0 2 1527#define MDCCSR_EL0_op1 3 1528#define MDCCSR_EL0_CRn 0 1529#define MDCCSR_EL0_CRm 1 1530#define MDCCSR_EL0_op2 0 1531 1532/* MDSCR_EL1 - Monitor Debug System Control Register */ 1533#define MDSCR_EL1 MRS_REG(MDSCR_EL1) 1534#define MDSCR_EL1_op0 2 1535#define MDSCR_EL1_op1 0 1536#define MDSCR_EL1_CRn 0 1537#define MDSCR_EL1_CRm 2 1538#define MDSCR_EL1_op2 2 1539#define MDSCR_SS_SHIFT 0 1540#define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT) 1541#define MDSCR_KDE_SHIFT 13 1542#define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT) 1543#define MDSCR_MDE_SHIFT 15 1544#define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT) 1545 1546/* MIDR_EL1 - Main ID Register */ 1547#define MIDR_EL1 MRS_REG(MIDR_EL1) 1548#define MIDR_EL1_op0 3 1549#define MIDR_EL1_op1 0 1550#define MIDR_EL1_CRn 0 1551#define MIDR_EL1_CRm 0 1552#define MIDR_EL1_op2 0 1553 1554/* MPIDR_EL1 - Multiprocessor Affinity Register */ 1555#define MPIDR_EL1 MRS_REG(MPIDR_EL1) 1556#define MPIDR_EL1_op0 3 1557#define MPIDR_EL1_op1 0 1558#define MPIDR_EL1_CRn 0 1559#define MPIDR_EL1_CRm 0 1560#define MPIDR_EL1_op2 5 1561#define MPIDR_AFF0_SHIFT 0 1562#define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT) 1563#define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) 1564#define MPIDR_AFF1_SHIFT 8 1565#define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT) 1566#define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) 1567#define MPIDR_AFF2_SHIFT 16 1568#define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT) 1569#define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) 1570#define MPIDR_MT_SHIFT 24 1571#define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT) 1572#define MPIDR_U_SHIFT 30 1573#define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT) 1574#define MPIDR_AFF3_SHIFT 32 1575#define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT) 1576#define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) 1577 1578/* MVFR0_EL1 */ 1579#define MVFR0_EL1 MRS_REG(MVFR0_EL1) 1580#define MVFR0_EL1_op0 0x3 1581#define MVFR0_EL1_op1 0x0 1582#define MVFR0_EL1_CRn 0x0 1583#define MVFR0_EL1_CRm 0x3 1584#define MVFR0_EL1_op2 0x0 1585#define MVFR0_SIMDReg_SHIFT 0 1586#define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT) 1587#define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) 1588#define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT) 1589#define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT) 1590#define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT) 1591#define MVFR0_FPSP_SHIFT 4 1592#define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT) 1593#define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) 1594#define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT) 1595#define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT) 1596#define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT) 1597#define MVFR0_FPDP_SHIFT 8 1598#define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT) 1599#define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) 1600#define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT) 1601#define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT) 1602#define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT) 1603#define MVFR0_FPTrap_SHIFT 12 1604#define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT) 1605#define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) 1606#define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT) 1607#define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT) 1608#define MVFR0_FPDivide_SHIFT 16 1609#define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT) 1610#define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) 1611#define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT) 1612#define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT) 1613#define MVFR0_FPSqrt_SHIFT 20 1614#define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT) 1615#define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) 1616#define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT) 1617#define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT) 1618#define MVFR0_FPShVec_SHIFT 24 1619#define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT) 1620#define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) 1621#define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT) 1622#define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT) 1623#define MVFR0_FPRound_SHIFT 28 1624#define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT) 1625#define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) 1626#define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT) 1627#define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT) 1628 1629/* MVFR1_EL1 */ 1630#define MVFR1_EL1 MRS_REG(MVFR1_EL1) 1631#define MVFR1_EL1_op0 0x3 1632#define MVFR1_EL1_op1 0x0 1633#define MVFR1_EL1_CRn 0x0 1634#define MVFR1_EL1_CRm 0x3 1635#define MVFR1_EL1_op2 0x1 1636#define MVFR1_FPFtZ_SHIFT 0 1637#define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT) 1638#define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) 1639#define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT) 1640#define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT) 1641#define MVFR1_FPDNaN_SHIFT 4 1642#define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT) 1643#define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) 1644#define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT) 1645#define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT) 1646#define MVFR1_SIMDLS_SHIFT 8 1647#define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT) 1648#define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) 1649#define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT) 1650#define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT) 1651#define MVFR1_SIMDInt_SHIFT 12 1652#define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT) 1653#define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) 1654#define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT) 1655#define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT) 1656#define MVFR1_SIMDSP_SHIFT 16 1657#define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT) 1658#define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) 1659#define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT) 1660#define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT) 1661#define MVFR1_SIMDHP_SHIFT 20 1662#define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT) 1663#define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) 1664#define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT) 1665#define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT) 1666#define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT) 1667#define MVFR1_FPHP_SHIFT 24 1668#define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT) 1669#define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) 1670#define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT) 1671#define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT) 1672#define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT) 1673#define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT) 1674#define MVFR1_SIMDFMAC_SHIFT 28 1675#define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT) 1676#define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) 1677#define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT) 1678#define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT) 1679 1680/* OSDLR_EL1 */ 1681#define OSDLR_EL1 MRS_REG(OSDLR_EL1) 1682#define OSDLR_EL1_op0 2 1683#define OSDLR_EL1_op1 0 1684#define OSDLR_EL1_CRn 1 1685#define OSDLR_EL1_CRm 3 1686#define OSDLR_EL1_op2 4 1687 1688/* OSLAR_EL1 */ 1689#define OSLAR_EL1 MRS_REG(OSLAR_EL1) 1690#define OSLAR_EL1_op0 2 1691#define OSLAR_EL1_op1 0 1692#define OSLAR_EL1_CRn 1 1693#define OSLAR_EL1_CRm 0 1694#define OSLAR_EL1_op2 4 1695 1696/* OSLSR_EL1 */ 1697#define OSLSR_EL1 MRS_REG(OSLSR_EL1) 1698#define OSLSR_EL1_op0 2 1699#define OSLSR_EL1_op1 0 1700#define OSLSR_EL1_CRn 1 1701#define OSLSR_EL1_CRm 1 1702#define OSLSR_EL1_op2 4 1703 1704/* PAR_EL1 - Physical Address Register */ 1705#define PAR_F_SHIFT 0 1706#define PAR_F (0x1 << PAR_F_SHIFT) 1707#define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 1708/* When PAR_F == 0 (success) */ 1709#define PAR_LOW_MASK 0xfff 1710#define PAR_SH_SHIFT 7 1711#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 1712#define PAR_NS_SHIFT 9 1713#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 1714#define PAR_PA_SHIFT 12 1715#define PAR_PA_MASK 0x0000fffffffff000 1716#define PAR_ATTR_SHIFT 56 1717#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 1718/* When PAR_F == 1 (aborted) */ 1719#define PAR_FST_SHIFT 1 1720#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 1721#define PAR_PTW_SHIFT 8 1722#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 1723#define PAR_S_SHIFT 9 1724#define PAR_S_MASK (0x1 << PAR_S_SHIFT) 1725 1726/* PMBIDR_EL1 */ 1727#define PMBIDR_EL1 MRS_REG(PMBIDR_EL1) 1728#define PMBIDR_EL1_REG MRS_REG_ALT_NAME(PMBIDR_EL1) 1729#define PMBIDR_EL1_op0 3 1730#define PMBIDR_EL1_op1 0 1731#define PMBIDR_EL1_CRn 9 1732#define PMBIDR_EL1_CRm 10 1733#define PMBIDR_EL1_op2 7 1734#define PMBIDR_Align_SHIFT 0 1735#define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT) 1736#define PMBIDR_P_SHIFT 4 1737#define PMBIDR_P (UL(0x1) << PMBIDR_P_SHIFT) 1738#define PMBIDR_F_SHIFT 5 1739#define PMBIDR_F (UL(0x1) << PMBIDR_F_SHIFT) 1740 1741/* PMBLIMITR_EL1 */ 1742#define PMBLIMITR_EL1 MRS_REG(PMBLIMITR_EL1) 1743#define PMBLIMITR_EL1_REG MRS_REG_ALT_NAME(PMBLIMITR_EL1) 1744#define PMBLIMITR_EL1_op0 3 1745#define PMBLIMITR_EL1_op1 0 1746#define PMBLIMITR_EL1_CRn 9 1747#define PMBLIMITR_EL1_CRm 10 1748#define PMBLIMITR_EL1_op2 0 1749#define PMBLIMITR_E_SHIFT 0 1750#define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT) 1751#define PMBLIMITR_FM_SHIFT 1 1752#define PMBLIMITR_FM_MASK (UL(0x3) << PMBLIMITR_FM_SHIFT) 1753#define PMBLIMITR_PMFZ_SHIFT 5 1754#define PMBLIMITR_PMFZ (UL(0x1) << PMBLIMITR_PMFZ_SHIFT) 1755#define PMBLIMITR_LIMIT_SHIFT 12 1756#define PMBLIMITR_LIMIT_MASK \ 1757 (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT) 1758 1759/* PMBPTR_EL1 */ 1760#define PMBPTR_EL1 MRS_REG(PMBPTR_EL1) 1761#define PMBPTR_EL1_REG MRS_REG_ALT_NAME(PMBPTR_EL1) 1762#define PMBPTR_EL1_op0 3 1763#define PMBPTR_EL1_op1 0 1764#define PMBPTR_EL1_CRn 9 1765#define PMBPTR_EL1_CRm 10 1766#define PMBPTR_EL1_op2 1 1767#define PMBPTR_PTR_SHIFT 0 1768#define PMBPTR_PTR_MASK \ 1769 (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT) 1770 1771/* PMBSR_EL1 */ 1772#define PMBSR_EL1 MRS_REG(PMBSR_EL1) 1773#define PMBSR_EL1_REG MRS_REG_ALT_NAME(PMBSR_EL1) 1774#define PMBSR_EL1_op0 3 1775#define PMBSR_EL1_op1 0 1776#define PMBSR_EL1_CRn 9 1777#define PMBSR_EL1_CRm 10 1778#define PMBSR_EL1_op2 3 1779#define PMBSR_MSS_SHIFT 0 1780#define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) 1781#define PMBSR_MSS_BSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) 1782#define PMBSR_MSS_FSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) 1783#define PMBSR_COLL_SHIFT 16 1784#define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT) 1785#define PMBSR_S_SHIFT 17 1786#define PMBSR_S (UL(0x1) << PMBSR_S_SHIFT) 1787#define PMBSR_EA_SHIFT 18 1788#define PMBSR_EA (UL(0x1) << PMBSR_EA_SHIFT) 1789#define PMBSR_DL_SHIFT 19 1790#define PMBSR_DL (UL(0x1) << PMBSR_DL_SHIFT) 1791#define PMBSR_EC_SHIFT 26 1792#define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) 1793 1794/* PMCCFILTR_EL0 */ 1795#define PMCCFILTR_EL0 MRS_REG(PMCCFILTR_EL0) 1796#define PMCCFILTR_EL0_op0 3 1797#define PMCCFILTR_EL0_op1 3 1798#define PMCCFILTR_EL0_CRn 14 1799#define PMCCFILTR_EL0_CRm 15 1800#define PMCCFILTR_EL0_op2 7 1801 1802/* PMCCNTR_EL0 */ 1803#define PMCCNTR_EL0 MRS_REG(PMCCNTR_EL0) 1804#define PMCCNTR_EL0_op0 3 1805#define PMCCNTR_EL0_op1 3 1806#define PMCCNTR_EL0_CRn 9 1807#define PMCCNTR_EL0_CRm 13 1808#define PMCCNTR_EL0_op2 0 1809 1810/* PMCEID0_EL0 */ 1811#define PMCEID0_EL0 MRS_REG(PMCEID0_EL0) 1812#define PMCEID0_EL0_op0 3 1813#define PMCEID0_EL0_op1 3 1814#define PMCEID0_EL0_CRn 9 1815#define PMCEID0_EL0_CRm 12 1816#define PMCEID0_EL0_op2 6 1817 1818/* PMCEID1_EL0 */ 1819#define PMCEID1_EL0 MRS_REG(PMCEID1_EL0) 1820#define PMCEID1_EL0_op0 3 1821#define PMCEID1_EL0_op1 3 1822#define PMCEID1_EL0_CRn 9 1823#define PMCEID1_EL0_CRm 12 1824#define PMCEID1_EL0_op2 7 1825 1826/* PMCNTENCLR_EL0 */ 1827#define PMCNTENCLR_EL0 MRS_REG(PMCNTENCLR_EL0) 1828#define PMCNTENCLR_EL0_op0 3 1829#define PMCNTENCLR_EL0_op1 3 1830#define PMCNTENCLR_EL0_CRn 9 1831#define PMCNTENCLR_EL0_CRm 12 1832#define PMCNTENCLR_EL0_op2 2 1833 1834/* PMCNTENSET_EL0 */ 1835#define PMCNTENSET_EL0 MRS_REG(PMCNTENSET_EL0) 1836#define PMCNTENSET_EL0_op0 3 1837#define PMCNTENSET_EL0_op1 3 1838#define PMCNTENSET_EL0_CRn 9 1839#define PMCNTENSET_EL0_CRm 12 1840#define PMCNTENSET_EL0_op2 1 1841 1842/* PMCR_EL0 - Perfomance Monitoring Counters */ 1843#define PMCR_EL0 MRS_REG(PMCR_EL0) 1844#define PMCR_EL0_op0 3 1845#define PMCR_EL0_op1 3 1846#define PMCR_EL0_CRn 9 1847#define PMCR_EL0_CRm 12 1848#define PMCR_EL0_op2 0 1849#define PMCR_E (1 << 0) /* Enable all counters */ 1850#define PMCR_P (1 << 1) /* Reset all counters */ 1851#define PMCR_C (1 << 2) /* Clock counter reset */ 1852#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 1853#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 1854#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 1855#define PMCR_LC (1 << 6) /* Long cycle count enable */ 1856#define PMCR_IMP_SHIFT 24 /* Implementer code */ 1857#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 1858#define PMCR_IMP_ARM 0x41 1859#define PMCR_IDCODE_SHIFT 16 /* Identification code */ 1860#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 1861#define PMCR_IDCODE_CORTEX_A57 0x01 1862#define PMCR_IDCODE_CORTEX_A72 0x02 1863#define PMCR_IDCODE_CORTEX_A53 0x03 1864#define PMCR_IDCODE_CORTEX_A73 0x04 1865#define PMCR_IDCODE_CORTEX_A35 0x0a 1866#define PMCR_IDCODE_CORTEX_A76 0x0b 1867#define PMCR_IDCODE_NEOVERSE_N1 0x0c 1868#define PMCR_IDCODE_CORTEX_A77 0x10 1869#define PMCR_IDCODE_CORTEX_A55 0x45 1870#define PMCR_IDCODE_NEOVERSE_E1 0x46 1871#define PMCR_IDCODE_CORTEX_A75 0x4a 1872#define PMCR_N_SHIFT 11 /* Number of counters implemented */ 1873#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 1874 1875/* PMEVCNTR<n>_EL0 */ 1876#define PMEVCNTR_EL0_op0 3 1877#define PMEVCNTR_EL0_op1 3 1878#define PMEVCNTR_EL0_CRn 14 1879#define PMEVCNTR_EL0_CRm 8 1880/* 1881 * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n' 1882 * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n' 1883 */ 1884 1885/* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */ 1886#define PMEVTYPER_EL0_op0 3 1887#define PMEVTYPER_EL0_op1 3 1888#define PMEVTYPER_EL0_CRn 14 1889#define PMEVTYPER_EL0_CRm 12 1890/* 1891 * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n' 1892 * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n' 1893 */ 1894#define PMEVTYPER_EVTCOUNT_MASK 0x000003ff /* ARMv8.0 */ 1895#define PMEVTYPER_EVTCOUNT_8_1_MASK 0x0000ffff /* ARMv8.1+ */ 1896#define PMEVTYPER_MT (1 << 25) /* Multithreading */ 1897#define PMEVTYPER_M (1 << 26) /* Secure EL3 filtering */ 1898#define PMEVTYPER_NSH (1 << 27) /* Non-secure hypervisor filtering */ 1899#define PMEVTYPER_NSU (1 << 28) /* Non-secure user filtering */ 1900#define PMEVTYPER_NSK (1 << 29) /* Non-secure kernel filtering */ 1901#define PMEVTYPER_U (1 << 30) /* User filtering */ 1902#define PMEVTYPER_P (1 << 31) /* Privileged filtering */ 1903 1904/* PMINTENCLR_EL1 */ 1905#define PMINTENCLR_EL1 MRS_REG(PMINTENCLR_EL1) 1906#define PMINTENCLR_EL1_op0 3 1907#define PMINTENCLR_EL1_op1 0 1908#define PMINTENCLR_EL1_CRn 9 1909#define PMINTENCLR_EL1_CRm 14 1910#define PMINTENCLR_EL1_op2 2 1911 1912/* PMINTENSET_EL1 */ 1913#define PMINTENSET_EL1 MRS_REG(PMINTENSET_EL1) 1914#define PMINTENSET_EL1_op0 3 1915#define PMINTENSET_EL1_op1 0 1916#define PMINTENSET_EL1_CRn 9 1917#define PMINTENSET_EL1_CRm 14 1918#define PMINTENSET_EL1_op2 1 1919 1920/* PMMIR_EL1 */ 1921#define PMMIR_EL1 MRS_REG(PMMIR_EL1) 1922#define PMMIR_EL1_op0 3 1923#define PMMIR_EL1_op1 0 1924#define PMMIR_EL1_CRn 9 1925#define PMMIR_EL1_CRm 14 1926#define PMMIR_EL1_op2 6 1927 1928/* PMOVSCLR_EL0 */ 1929#define PMOVSCLR_EL0 MRS_REG(PMOVSCLR_EL0) 1930#define PMOVSCLR_EL0_op0 3 1931#define PMOVSCLR_EL0_op1 3 1932#define PMOVSCLR_EL0_CRn 9 1933#define PMOVSCLR_EL0_CRm 12 1934#define PMOVSCLR_EL0_op2 3 1935 1936/* PMOVSSET_EL0 */ 1937#define PMOVSSET_EL0 MRS_REG(PMOVSSET_EL0) 1938#define PMOVSSET_EL0_op0 3 1939#define PMOVSSET_EL0_op1 3 1940#define PMOVSSET_EL0_CRn 9 1941#define PMOVSSET_EL0_CRm 14 1942#define PMOVSSET_EL0_op2 3 1943 1944/* PMSCR_EL1 */ 1945#define PMSCR_EL1 MRS_REG(PMSCR_EL1) 1946#define PMSCR_EL1_REG MRS_REG_ALT_NAME(PMSCR_EL1) 1947#define PMSCR_EL1_op0 3 1948#define PMSCR_EL1_op1 0 1949#define PMSCR_EL1_CRn 9 1950#define PMSCR_EL1_CRm 9 1951#define PMSCR_EL1_op2 0 1952#define PMSCR_E0SPE_SHIFT 0 1953#define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT) 1954#define PMSCR_E1SPE_SHIFT 1 1955#define PMSCR_E1SPE (UL(0x1) << PMSCR_E1SPE_SHIFT) 1956#define PMSCR_CX_SHIFT 3 1957#define PMSCR_CX (UL(0x1) << PMSCR_CX_SHIFT) 1958#define PMSCR_PA_SHIFT 4 1959#define PMSCR_PA (UL(0x1) << PMSCR_PA_SHIFT) 1960#define PMSCR_TS_SHIFT 5 1961#define PMSCR_TS (UL(0x1) << PMSCR_TS_SHIFT) 1962#define PMSCR_PCT_SHIFT 6 1963#define PMSCR_PCT_MASK (UL(0x3) << PMSCR_PCT_SHIFT) 1964 1965/* PMSELR_EL0 */ 1966#define PMSELR_EL0 MRS_REG(PMSELR_EL0) 1967#define PMSELR_EL0_op0 3 1968#define PMSELR_EL0_op1 3 1969#define PMSELR_EL0_CRn 9 1970#define PMSELR_EL0_CRm 12 1971#define PMSELR_EL0_op2 5 1972#define PMSELR_SEL_MASK 0x1f 1973 1974/* PMSEVFR_EL1 */ 1975#define PMSEVFR_EL1 MRS_REG(PMSEVFR_EL1) 1976#define PMSEVFR_EL1_REG MRS_REG_ALT_NAME(PMSEVFR_EL1) 1977#define PMSEVFR_EL1_op0 3 1978#define PMSEVFR_EL1_op1 0 1979#define PMSEVFR_EL1_CRn 9 1980#define PMSEVFR_EL1_CRm 9 1981#define PMSEVFR_EL1_op2 5 1982 1983/* PMSFCR_EL1 */ 1984#define PMSFCR_EL1 MRS_REG(PMSFCR_EL1) 1985#define PMSFCR_EL1_REG MRS_REG_ALT_NAME(PMSFCR_EL1) 1986#define PMSFCR_EL1_op0 3 1987#define PMSFCR_EL1_op1 0 1988#define PMSFCR_EL1_CRn 9 1989#define PMSFCR_EL1_CRm 9 1990#define PMSFCR_EL1_op2 4 1991#define PMSFCR_FE_SHIFT 0 1992#define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT) 1993#define PMSFCR_FT_SHIFT 1 1994#define PMSFCR_FT (UL(0x1) << PMSFCR_FT_SHIFT) 1995#define PMSFCR_FL_SHIFT 2 1996#define PMSFCR_FL (UL(0x1) << PMSFCR_FL_SHIFT) 1997#define PMSFCR_FnE_SHIFT 3 1998#define PMSFCR_FnE (UL(0x1) << PMSFCR_FnE_SHIFT) 1999#define PMSFCR_B_SHIFT 16 2000#define PMSFCR_B (UL(0x1) << PMSFCR_B_SHIFT) 2001#define PMSFCR_LD_SHIFT 17 2002#define PMSFCR_LD (UL(0x1) << PMSFCR_LD_SHIFT) 2003#define PMSFCR_ST_SHIFT 18 2004#define PMSFCR_ST (UL(0x1) << PMSFCR_ST_SHIFT) 2005 2006/* PMSICR_EL1 */ 2007#define PMSICR_EL1 MRS_REG(PMSICR_EL1) 2008#define PMSICR_EL1_REG MRS_REG_ALT_NAME(PMSICR_EL1) 2009#define PMSICR_EL1_op0 3 2010#define PMSICR_EL1_op1 0 2011#define PMSICR_EL1_CRn 9 2012#define PMSICR_EL1_CRm 9 2013#define PMSICR_EL1_op2 2 2014#define PMSICR_COUNT_SHIFT 0 2015#define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT) 2016#define PMSICR_ECOUNT_SHIFT 56 2017#define PMSICR_ECOUNT_MASK (UL(0xff) << PMSICR_ECOUNT_SHIFT) 2018 2019/* PMSIDR_EL1 */ 2020#define PMSIDR_EL1 MRS_REG(PMSIDR_EL1) 2021#define PMSIDR_EL1_REG MRS_REG_ALT_NAME(PMSIDR_EL1) 2022#define PMSIDR_EL1_op0 3 2023#define PMSIDR_EL1_op1 0 2024#define PMSIDR_EL1_CRn 9 2025#define PMSIDR_EL1_CRm 9 2026#define PMSIDR_EL1_op2 7 2027#define PMSIDR_FE_SHIFT 0 2028#define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT) 2029#define PMSIDR_FT_SHIFT 1 2030#define PMSIDR_FT (UL(0x1) << PMSIDR_FT_SHIFT) 2031#define PMSIDR_FL_SHIFT 2 2032#define PMSIDR_FL (UL(0x1) << PMSIDR_FL_SHIFT) 2033#define PMSIDR_ArchInst_SHIFT 3 2034#define PMSIDR_ArchInst (UL(0x1) << PMSIDR_ArchInst_SHIFT) 2035#define PMSIDR_LDS_SHIFT 4 2036#define PMSIDR_LDS (UL(0x1) << PMSIDR_LDS_SHIFT) 2037#define PMSIDR_ERnd_SHIFT 5 2038#define PMSIDR_ERnd (UL(0x1) << PMSIDR_ERnd_SHIFT) 2039#define PMSIDR_FnE_SHIFT 6 2040#define PMSIDR_FnE (UL(0x1) << PMSIDR_FnE_SHIFT) 2041#define PMSIDR_Interval_SHIFT 8 2042#define PMSIDR_Interval_MASK (UL(0xf) << PMSIDR_Interval_SHIFT) 2043#define PMSIDR_MaxSize_SHIFT 12 2044#define PMSIDR_MaxSize_MASK (UL(0xf) << PMSIDR_MaxSize_SHIFT) 2045#define PMSIDR_CountSize_SHIFT 16 2046#define PMSIDR_CountSize_MASK (UL(0xf) << PMSIDR_CountSize_SHIFT) 2047#define PMSIDR_Format_SHIFT 20 2048#define PMSIDR_Format_MASK (UL(0xf) << PMSIDR_Format_SHIFT) 2049#define PMSIDR_PBT_SHIFT 24 2050#define PMSIDR_PBT (UL(0x1) << PMSIDR_PBT_SHIFT) 2051 2052/* PMSIRR_EL1 */ 2053#define PMSIRR_EL1 MRS_REG(PMSIRR_EL1) 2054#define PMSIRR_EL1_REG MRS_REG_ALT_NAME(PMSIRR_EL1) 2055#define PMSIRR_EL1_op0 3 2056#define PMSIRR_EL1_op1 0 2057#define PMSIRR_EL1_CRn 9 2058#define PMSIRR_EL1_CRm 9 2059#define PMSIRR_EL1_op2 3 2060#define PMSIRR_RND_SHIFT 0 2061#define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT) 2062#define PMSIRR_INTERVAL_SHIFT 8 2063#define PMSIRR_INTERVAL_MASK (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT) 2064 2065/* PMSLATFR_EL1 */ 2066#define PMSLATFR_EL1 MRS_REG(PMSLATFR_EL1) 2067#define PMSLATFR_EL1_REG MRS_REG_ALT_NAME(PMSLATFR_EL1) 2068#define PMSLATFR_EL1_op0 3 2069#define PMSLATFR_EL1_op1 0 2070#define PMSLATFR_EL1_CRn 9 2071#define PMSLATFR_EL1_CRm 9 2072#define PMSLATFR_EL1_op2 6 2073#define PMSLATFR_MINLAT_SHIFT 0 2074#define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT) 2075 2076/* PMSNEVFR_EL1 */ 2077#define PMSNEVFR_EL1 MRS_REG(PMSNEVFR_EL1) 2078#define PMSNEVFR_EL1_REG MRS_REG_ALT_NAME(PMSNEVFR_EL1) 2079#define PMSNEVFR_EL1_op0 3 2080#define PMSNEVFR_EL1_op1 0 2081#define PMSNEVFR_EL1_CRn 9 2082#define PMSNEVFR_EL1_CRm 9 2083#define PMSNEVFR_EL1_op2 1 2084 2085/* PMSWINC_EL0 */ 2086#define PMSWINC_EL0 MRS_REG(PMSWINC_EL0) 2087#define PMSWINC_EL0_op0 3 2088#define PMSWINC_EL0_op1 3 2089#define PMSWINC_EL0_CRn 9 2090#define PMSWINC_EL0_CRm 12 2091#define PMSWINC_EL0_op2 4 2092 2093/* PMUSERENR_EL0 */ 2094#define PMUSERENR_EL0 MRS_REG(PMUSERENR_EL0) 2095#define PMUSERENR_EL0_op0 3 2096#define PMUSERENR_EL0_op1 3 2097#define PMUSERENR_EL0_CRn 9 2098#define PMUSERENR_EL0_CRm 14 2099#define PMUSERENR_EL0_op2 0 2100 2101/* PMXEVCNTR_EL0 */ 2102#define PMXEVCNTR_EL0 MRS_REG(PMXEVCNTR_EL0) 2103#define PMXEVCNTR_EL0_op0 3 2104#define PMXEVCNTR_EL0_op1 3 2105#define PMXEVCNTR_EL0_CRn 9 2106#define PMXEVCNTR_EL0_CRm 13 2107#define PMXEVCNTR_EL0_op2 2 2108 2109/* PMXEVTYPER_EL0 */ 2110#define PMXEVTYPER_EL0 MRS_REG(PMXEVTYPER_EL0) 2111#define PMXEVTYPER_EL0_op0 3 2112#define PMXEVTYPER_EL0_op1 3 2113#define PMXEVTYPER_EL0_CRn 9 2114#define PMXEVTYPER_EL0_CRm 13 2115#define PMXEVTYPER_EL0_op2 1 2116 2117/* RNDRRS */ 2118#define RNDRRS MRS_REG(RNDRRS) 2119#define RNDRRS_REG MRS_REG_ALT_NAME(RNDRRS) 2120#define RNDRRS_op0 3 2121#define RNDRRS_op1 3 2122#define RNDRRS_CRn 2 2123#define RNDRRS_CRm 4 2124#define RNDRRS_op2 1 2125 2126/* SCTLR_EL1 - System Control Register */ 2127#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ 2128#define SCTLR_M (UL(0x1) << 0) 2129#define SCTLR_A (UL(0x1) << 1) 2130#define SCTLR_C (UL(0x1) << 2) 2131#define SCTLR_SA (UL(0x1) << 3) 2132#define SCTLR_SA0 (UL(0x1) << 4) 2133#define SCTLR_CP15BEN (UL(0x1) << 5) 2134#define SCTLR_nAA (UL(0x1) << 6) 2135#define SCTLR_ITD (UL(0x1) << 7) 2136#define SCTLR_SED (UL(0x1) << 8) 2137#define SCTLR_UMA (UL(0x1) << 9) 2138#define SCTLR_EnRCTX (UL(0x1) << 10) 2139#define SCTLR_EOS (UL(0x1) << 11) 2140#define SCTLR_I (UL(0x1) << 12) 2141#define SCTLR_EnDB (UL(0x1) << 13) 2142#define SCTLR_DZE (UL(0x1) << 14) 2143#define SCTLR_UCT (UL(0x1) << 15) 2144#define SCTLR_nTWI (UL(0x1) << 16) 2145/* Bit 17 is reserved */ 2146#define SCTLR_nTWE (UL(0x1) << 18) 2147#define SCTLR_WXN (UL(0x1) << 19) 2148#define SCTLR_TSCXT (UL(0x1) << 20) 2149#define SCTLR_IESB (UL(0x1) << 21) 2150#define SCTLR_EIS (UL(0x1) << 22) 2151#define SCTLR_SPAN (UL(0x1) << 23) 2152#define SCTLR_E0E (UL(0x1) << 24) 2153#define SCTLR_EE (UL(0x1) << 25) 2154#define SCTLR_UCI (UL(0x1) << 26) 2155#define SCTLR_EnDA (UL(0x1) << 27) 2156#define SCTLR_nTLSMD (UL(0x1) << 28) 2157#define SCTLR_LSMAOE (UL(0x1) << 29) 2158#define SCTLR_EnIB (UL(0x1) << 30) 2159#define SCTLR_EnIA (UL(0x1) << 31) 2160/* Bits 34:32 are reserved */ 2161#define SCTLR_BT0 (UL(0x1) << 35) 2162#define SCTLR_BT1 (UL(0x1) << 36) 2163#define SCTLR_ITFSB (UL(0x1) << 37) 2164#define SCTLR_TCF0_MASK (UL(0x3) << 38) 2165#define SCTLR_TCF_MASK (UL(0x3) << 40) 2166#define SCTLR_ATA0 (UL(0x1) << 42) 2167#define SCTLR_ATA (UL(0x1) << 43) 2168#define SCTLR_DSSBS (UL(0x1) << 44) 2169#define SCTLR_TWEDEn (UL(0x1) << 45) 2170#define SCTLR_TWEDEL_MASK (UL(0xf) << 46) 2171/* Bits 53:50 are reserved */ 2172#define SCTLR_EnASR (UL(0x1) << 54) 2173#define SCTLR_EnAS0 (UL(0x1) << 55) 2174#define SCTLR_EnALS (UL(0x1) << 56) 2175#define SCTLR_EPAN (UL(0x1) << 57) 2176 2177/* SPSR_EL1 */ 2178/* 2179 * When the exception is taken in AArch64: 2180 * M[3:2] is the exception level 2181 * M[1] is unused 2182 * M[0] is the SP select: 2183 * 0: always SP0 2184 * 1: current ELs SP 2185 */ 2186#define PSR_M_EL0t 0x00000000UL 2187#define PSR_M_EL1t 0x00000004UL 2188#define PSR_M_EL1h 0x00000005UL 2189#define PSR_M_EL2t 0x00000008UL 2190#define PSR_M_EL2h 0x00000009UL 2191#define PSR_M_64 0x00000000UL 2192#define PSR_M_32 0x00000010UL 2193#define PSR_M_MASK 0x0000000fUL 2194 2195#define PSR_T 0x00000020UL 2196 2197#define PSR_AARCH32 0x00000010UL 2198#define PSR_F 0x00000040UL 2199#define PSR_I 0x00000080UL 2200#define PSR_A 0x00000100UL 2201#define PSR_D 0x00000200UL 2202#define PSR_DAIF (PSR_D | PSR_A | PSR_I | PSR_F) 2203/* The default DAIF mask. These bits are valid in spsr_el1 and daif */ 2204#define PSR_DAIF_DEFAULT (PSR_F) 2205#define PSR_BTYPE 0x00000c00UL 2206#define PSR_SSBS 0x00001000UL 2207#define PSR_ALLINT 0x00002000UL 2208#define PSR_IL 0x00100000UL 2209#define PSR_SS 0x00200000UL 2210#define PSR_PAN 0x00400000UL 2211#define PSR_UAO 0x00800000UL 2212#define PSR_DIT 0x01000000UL 2213#define PSR_TCO 0x02000000UL 2214#define PSR_V 0x10000000UL 2215#define PSR_C 0x20000000UL 2216#define PSR_Z 0x40000000UL 2217#define PSR_N 0x80000000UL 2218#define PSR_FLAGS 0xf0000000UL 2219/* PSR fields that can be set from 32-bit and 64-bit processes */ 2220#define PSR_SETTABLE_32 PSR_FLAGS 2221#define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS) 2222 2223/* REVIDR_EL1 - Revision ID Register */ 2224#define REVIDR_EL1 MRS_REG(REVIDR_EL1) 2225#define REVIDR_EL1_op0 3 2226#define REVIDR_EL1_op1 0 2227#define REVIDR_EL1_CRn 0 2228#define REVIDR_EL1_CRm 0 2229#define REVIDR_EL1_op2 6 2230 2231/* TCR_EL1 - Translation Control Register */ 2232/* Bits 63:59 are reserved */ 2233#define TCR_TCMA1_SHIFT 58 2234#define TCR_TCMA1 (UL(1) << TCR_TCMA1_SHIFT) 2235#define TCR_TCMA0_SHIFT 57 2236#define TCR_TCMA0 (UL(1) << TCR_TCMA0_SHIFT) 2237#define TCR_E0PD1_SHIFT 56 2238#define TCR_E0PD1 (UL(1) << TCR_E0PD1_SHIFT) 2239#define TCR_E0PD0_SHIFT 55 2240#define TCR_E0PD0 (UL(1) << TCR_E0PD0_SHIFT) 2241#define TCR_NFD1_SHIFT 54 2242#define TCR_NFD1 (UL(1) << TCR_NFD1_SHIFT) 2243#define TCR_NFD0_SHIFT 53 2244#define TCR_NFD0 (UL(1) << TCR_NFD0_SHIFT) 2245#define TCR_TBID1_SHIFT 52 2246#define TCR_TBID1 (UL(1) << TCR_TBID1_SHIFT) 2247#define TCR_TBID0_SHIFT 51 2248#define TCR_TBID0 (UL(1) << TCR_TBID0_SHIFT) 2249#define TCR_HWU162_SHIFT 50 2250#define TCR_HWU162 (UL(1) << TCR_HWU162_SHIFT) 2251#define TCR_HWU161_SHIFT 49 2252#define TCR_HWU161 (UL(1) << TCR_HWU161_SHIFT) 2253#define TCR_HWU160_SHIFT 48 2254#define TCR_HWU160 (UL(1) << TCR_HWU160_SHIFT) 2255#define TCR_HWU159_SHIFT 47 2256#define TCR_HWU159 (UL(1) << TCR_HWU159_SHIFT) 2257#define TCR_HWU1 \ 2258 (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162) 2259#define TCR_HWU062_SHIFT 46 2260#define TCR_HWU062 (UL(1) << TCR_HWU062_SHIFT) 2261#define TCR_HWU061_SHIFT 45 2262#define TCR_HWU061 (UL(1) << TCR_HWU061_SHIFT) 2263#define TCR_HWU060_SHIFT 44 2264#define TCR_HWU060 (UL(1) << TCR_HWU060_SHIFT) 2265#define TCR_HWU059_SHIFT 43 2266#define TCR_HWU059 (UL(1) << TCR_HWU059_SHIFT) 2267#define TCR_HWU0 \ 2268 (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062) 2269#define TCR_HPD1_SHIFT 42 2270#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT) 2271#define TCR_HPD0_SHIFT 41 2272#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT) 2273#define TCR_HD_SHIFT 40 2274#define TCR_HD (UL(1) << TCR_HD_SHIFT) 2275#define TCR_HA_SHIFT 39 2276#define TCR_HA (UL(1) << TCR_HA_SHIFT) 2277#define TCR_TBI1_SHIFT 38 2278#define TCR_TBI1 (UL(1) << TCR_TBI1_SHIFT) 2279#define TCR_TBI0_SHIFT 37 2280#define TCR_TBI0 (UL(1) << TCR_TBI0_SHIFT) 2281#define TCR_ASID_SHIFT 36 2282#define TCR_ASID_WIDTH 1 2283#define TCR_ASID_16 (UL(1) << TCR_ASID_SHIFT) 2284/* Bit 35 is reserved */ 2285#define TCR_IPS_SHIFT 32 2286#define TCR_IPS_WIDTH 3 2287#define TCR_IPS_32BIT (UL(0) << TCR_IPS_SHIFT) 2288#define TCR_IPS_36BIT (UL(1) << TCR_IPS_SHIFT) 2289#define TCR_IPS_40BIT (UL(2) << TCR_IPS_SHIFT) 2290#define TCR_IPS_42BIT (UL(3) << TCR_IPS_SHIFT) 2291#define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT) 2292#define TCR_IPS_48BIT (UL(5) << TCR_IPS_SHIFT) 2293#define TCR_TG1_SHIFT 30 2294#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT) 2295#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT) 2296#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT) 2297#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT) 2298#define TCR_SH1_SHIFT 28 2299#define TCR_SH1_IS (UL(3) << TCR_SH1_SHIFT) 2300#define TCR_ORGN1_SHIFT 26 2301#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT) 2302#define TCR_IRGN1_SHIFT 24 2303#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT) 2304#define TCR_EPD1_SHIFT 23 2305#define TCR_EPD1 (UL(1) << TCR_EPD1_SHIFT) 2306#define TCR_A1_SHIFT 22 2307#define TCR_A1 (UL(1) << TCR_A1_SHIFT) 2308#define TCR_T1SZ_SHIFT 16 2309#define TCR_T1SZ_MASK (UL(0x3f) << TCR_T1SZ_SHIFT) 2310#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 2311#define TCR_TG0_SHIFT 14 2312#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) 2313#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT) 2314#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT) 2315#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT) 2316#define TCR_SH0_SHIFT 12 2317#define TCR_SH0_IS (UL(3) << TCR_SH0_SHIFT) 2318#define TCR_ORGN0_SHIFT 10 2319#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT) 2320#define TCR_IRGN0_SHIFT 8 2321#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT) 2322#define TCR_EPD0_SHIFT 7 2323#define TCR_EPD0 (UL(1) << TCR_EPD0_SHIFT) 2324/* Bit 6 is reserved */ 2325#define TCR_T0SZ_SHIFT 0 2326#define TCR_T0SZ_MASK (UL(0x3f) << TCR_T0SZ_SHIFT) 2327#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 2328#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 2329 2330#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 2331 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 2332#ifdef SMP 2333#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 2334#else 2335#define TCR_SMP_ATTRS 0 2336#endif 2337 2338/* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */ 2339#define TTBR_ASID_SHIFT 48 2340#define TTBR_ASID_MASK (0xfffful << TTBR_ASID_SHIFT) 2341#define TTBR_BADDR 0x0000fffffffffffeul 2342#define TTBR_CnP_SHIFT 0 2343#define TTBR_CnP (1ul << TTBR_CnP_SHIFT) 2344 2345/* ZCR_EL1 - SVE Control Register */ 2346#define ZCR_LEN_SHIFT 0 2347#define ZCR_LEN_MASK (0xf << ZCR_LEN_SHIFT) 2348#define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) 2349 2350#endif /* !_MACHINE_ARMREG_H_ */ 2351 2352#endif /* !__arm__ */ 2353