1/*- 2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28#include "opt_evdev.h" 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33 34#include <sys/conf.h> 35#include <sys/kernel.h> 36#include <sys/limits.h> 37#include <sys/lock.h> 38#include <sys/module.h> 39#include <sys/mutex.h> 40#include <sys/condvar.h> 41#include <sys/resource.h> 42#include <sys/rman.h> 43#include <sys/sysctl.h> 44#include <sys/selinfo.h> 45#include <sys/poll.h> 46#include <sys/uio.h> 47 48#include <machine/bus.h> 49 50#include <dev/ofw/openfirm.h> 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53 54#ifdef EVDEV_SUPPORT 55#include <dev/evdev/input.h> 56#include <dev/evdev/evdev.h> 57#endif 58 59#include <arm/ti/ti_sysc.h> 60#include <arm/ti/ti_adcreg.h> 61#include <arm/ti/ti_adcvar.h> 62 63#undef DEBUG_TSC 64 65#define DEFAULT_CHARGE_DELAY 0x400 66#define STEPDLY_OPEN 0x98 67 68#define ORDER_XP 0 69#define ORDER_XN 1 70#define ORDER_YP 2 71#define ORDER_YN 3 72 73/* Define our 8 steps, one for each input channel. */ 74static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = { 75 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) }, 76 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) }, 77 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) }, 78 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) }, 79 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) }, 80 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) }, 81 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) }, 82 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) }, 83}; 84 85static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 }; 86 87static int ti_adc_detach(device_t dev); 88 89#ifdef EVDEV_SUPPORT 90static void 91ti_adc_ev_report(struct ti_adc_softc *sc) 92{ 93 94 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_X, sc->sc_x); 95 evdev_push_event(sc->sc_evdev, EV_ABS, ABS_Y, sc->sc_y); 96 evdev_push_event(sc->sc_evdev, EV_KEY, BTN_TOUCH, sc->sc_pen_down); 97 evdev_sync(sc->sc_evdev); 98} 99#endif /* EVDEV */ 100 101static void 102ti_adc_enable(struct ti_adc_softc *sc) 103{ 104 uint32_t reg; 105 106 TI_ADC_LOCK_ASSERT(sc); 107 108 if (sc->sc_last_state == 1) 109 return; 110 111 /* Enable the FIFO0 threshold and the end of sequence interrupt. */ 112 ADC_WRITE4(sc, ADC_IRQENABLE_SET, 113 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); 114 115 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID; 116 if (sc->sc_tsc_wires > 0) { 117 reg |= ADC_CTRL_TSC_ENABLE; 118 switch (sc->sc_tsc_wires) { 119 case 4: 120 reg |= ADC_CTRL_TSC_4WIRE; 121 break; 122 case 5: 123 reg |= ADC_CTRL_TSC_5WIRE; 124 break; 125 case 8: 126 reg |= ADC_CTRL_TSC_8WIRE; 127 break; 128 default: 129 break; 130 } 131 } 132 reg |= ADC_CTRL_ENABLE; 133 /* Enable the ADC. Run thru enabled steps, start the conversions. */ 134 ADC_WRITE4(sc, ADC_CTRL, reg); 135 136 sc->sc_last_state = 1; 137} 138 139static void 140ti_adc_disable(struct ti_adc_softc *sc) 141{ 142 int count; 143 144 TI_ADC_LOCK_ASSERT(sc); 145 146 if (sc->sc_last_state == 0) 147 return; 148 149 /* Disable all the enabled steps. */ 150 ADC_WRITE4(sc, ADC_STEPENABLE, 0); 151 152 /* Disable the ADC. */ 153 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE); 154 155 /* Disable the FIFO0 threshold and the end of sequence interrupt. */ 156 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 157 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); 158 159 /* ACK any pending interrupt. */ 160 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS)); 161 162 /* Drain the FIFO data. */ 163 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 164 while (count > 0) { 165 (void)ADC_READ4(sc, ADC_FIFO0DATA); 166 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 167 } 168 169 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 170 while (count > 0) { 171 (void)ADC_READ4(sc, ADC_FIFO1DATA); 172 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 173 } 174 175 sc->sc_last_state = 0; 176} 177 178static int 179ti_adc_setup(struct ti_adc_softc *sc) 180{ 181 int ain, i; 182 uint32_t enabled; 183 184 TI_ADC_LOCK_ASSERT(sc); 185 186 /* Check for enabled inputs. */ 187 enabled = sc->sc_tsc_enabled; 188 for (i = 0; i < sc->sc_adc_nchannels; i++) { 189 ain = sc->sc_adc_channels[i]; 190 if (ti_adc_inputs[ain].enable) 191 enabled |= (1U << (ain + 1)); 192 } 193 194 /* Set the ADC global status. */ 195 if (enabled != 0) { 196 ti_adc_enable(sc); 197 /* Update the enabled steps. */ 198 if (enabled != ADC_READ4(sc, ADC_STEPENABLE)) 199 ADC_WRITE4(sc, ADC_STEPENABLE, enabled); 200 } else 201 ti_adc_disable(sc); 202 203 return (0); 204} 205 206static void 207ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain) 208{ 209 struct ti_adc_input *input; 210 uint32_t reg, val; 211 212 TI_ADC_LOCK_ASSERT(sc); 213 214 input = &ti_adc_inputs[ain]; 215 reg = input->stepconfig; 216 val = ADC_READ4(sc, reg); 217 218 /* Set single ended operation. */ 219 val &= ~ADC_STEP_DIFF_CNTRL; 220 221 /* Set the negative voltage reference. */ 222 val &= ~ADC_STEP_RFM_MSK; 223 224 /* Set the positive voltage reference. */ 225 val &= ~ADC_STEP_RFP_MSK; 226 227 /* Set the samples average. */ 228 val &= ~ADC_STEP_AVG_MSK; 229 val |= input->samples << ADC_STEP_AVG_SHIFT; 230 231 /* Select the desired input. */ 232 val &= ~ADC_STEP_INP_MSK; 233 val |= ain << ADC_STEP_INP_SHIFT; 234 235 /* Set the ADC to one-shot mode. */ 236 val &= ~ADC_STEP_MODE_MSK; 237 238 ADC_WRITE4(sc, reg, val); 239} 240 241static void 242ti_adc_reset(struct ti_adc_softc *sc) 243{ 244 int ain, i; 245 246 TI_ADC_LOCK_ASSERT(sc); 247 248 /* Disable all the inputs. */ 249 for (i = 0; i < sc->sc_adc_nchannels; i++) { 250 ain = sc->sc_adc_channels[i]; 251 ti_adc_inputs[ain].enable = 0; 252 } 253} 254 255static int 256ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS) 257{ 258 int error, reg; 259 struct ti_adc_softc *sc; 260 261 sc = (struct ti_adc_softc *)arg1; 262 263 TI_ADC_LOCK(sc); 264 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1; 265 TI_ADC_UNLOCK(sc); 266 267 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 268 if (error != 0 || req->newptr == NULL) 269 return (error); 270 271 /* 272 * The actual written value is the prescaler setting - 1. 273 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum 274 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10). 275 */ 276 reg--; 277 if (reg < 9) 278 reg = 9; 279 if (reg > USHRT_MAX) 280 reg = USHRT_MAX; 281 282 TI_ADC_LOCK(sc); 283 /* Disable the ADC. */ 284 ti_adc_disable(sc); 285 /* Update the ADC prescaler setting. */ 286 ADC_WRITE4(sc, ADC_CLKDIV, reg); 287 /* Enable the ADC again. */ 288 ti_adc_setup(sc); 289 TI_ADC_UNLOCK(sc); 290 291 return (0); 292} 293 294static int 295ti_adc_enable_proc(SYSCTL_HANDLER_ARGS) 296{ 297 int error; 298 int32_t enable; 299 struct ti_adc_softc *sc; 300 struct ti_adc_input *input; 301 302 input = (struct ti_adc_input *)arg1; 303 sc = input->sc; 304 305 enable = input->enable; 306 error = sysctl_handle_int(oidp, &enable, sizeof(enable), 307 req); 308 if (error != 0 || req->newptr == NULL) 309 return (error); 310 311 if (enable) 312 enable = 1; 313 314 TI_ADC_LOCK(sc); 315 /* Setup the ADC as needed. */ 316 if (input->enable != enable) { 317 input->enable = enable; 318 ti_adc_setup(sc); 319 if (input->enable == 0) 320 input->value = 0; 321 } 322 TI_ADC_UNLOCK(sc); 323 324 return (0); 325} 326 327static int 328ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS) 329{ 330 int error, reg; 331 struct ti_adc_softc *sc; 332 struct ti_adc_input *input; 333 334 input = (struct ti_adc_input *)arg1; 335 sc = input->sc; 336 337 TI_ADC_LOCK(sc); 338 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY; 339 TI_ADC_UNLOCK(sc); 340 341 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 342 if (error != 0 || req->newptr == NULL) 343 return (error); 344 345 if (reg < 0) 346 reg = 0; 347 348 TI_ADC_LOCK(sc); 349 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY); 350 TI_ADC_UNLOCK(sc); 351 352 return (0); 353} 354 355static int 356ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS) 357{ 358 int error, samples, i; 359 struct ti_adc_softc *sc; 360 struct ti_adc_input *input; 361 362 input = (struct ti_adc_input *)arg1; 363 sc = input->sc; 364 365 if (input->samples > nitems(ti_adc_samples)) 366 input->samples = nitems(ti_adc_samples); 367 samples = ti_adc_samples[input->samples]; 368 369 error = sysctl_handle_int(oidp, &samples, 0, req); 370 if (error != 0 || req->newptr == NULL) 371 return (error); 372 373 TI_ADC_LOCK(sc); 374 if (samples != ti_adc_samples[input->samples]) { 375 input->samples = 0; 376 for (i = 0; i < nitems(ti_adc_samples); i++) 377 if (samples >= ti_adc_samples[i]) 378 input->samples = i; 379 ti_adc_input_setup(sc, input->input); 380 } 381 TI_ADC_UNLOCK(sc); 382 383 return (error); 384} 385 386static void 387ti_adc_read_data(struct ti_adc_softc *sc) 388{ 389 int count, ain; 390 struct ti_adc_input *input; 391 uint32_t data; 392 393 TI_ADC_LOCK_ASSERT(sc); 394 395 /* Read the available data. */ 396 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 397 while (count > 0) { 398 data = ADC_READ4(sc, ADC_FIFO0DATA); 399 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT; 400 input = &ti_adc_inputs[ain]; 401 if (input->enable == 0) 402 input->value = 0; 403 else 404 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK); 405 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 406 } 407} 408 409static int 410cmp_values(const void *a, const void *b) 411{ 412 const uint32_t *v1, *v2; 413 v1 = a; 414 v2 = b; 415 if (*v1 < *v2) 416 return -1; 417 if (*v1 > *v2) 418 return 1; 419 420 return (0); 421} 422 423static void 424ti_adc_tsc_read_data(struct ti_adc_softc *sc) 425{ 426 int count; 427 uint32_t data[16]; 428 uint32_t x, y; 429 int i, start, end; 430 431 TI_ADC_LOCK_ASSERT(sc); 432 433 /* Read the available data. */ 434 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 435 if (count == 0) 436 return; 437 438 i = 0; 439 while (count > 0) { 440 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK; 441 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 442 } 443 444 if (sc->sc_coord_readouts > 3) { 445 start = 1; 446 end = sc->sc_coord_readouts - 1; 447 qsort(data, sc->sc_coord_readouts, 448 sizeof(data[0]), &cmp_values); 449 qsort(&data[sc->sc_coord_readouts + 2], 450 sc->sc_coord_readouts, 451 sizeof(data[0]), &cmp_values); 452 } 453 else { 454 start = 0; 455 end = sc->sc_coord_readouts; 456 } 457 458 x = y = 0; 459 for (i = start; i < end; i++) 460 y += data[i]; 461 y /= (end - start); 462 463 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++) 464 x += data[i]; 465 x /= (end - start); 466 467#ifdef DEBUG_TSC 468 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y); 469#endif 470 471#ifdef EVDEV_SUPPORT 472 if ((sc->sc_x != x) || (sc->sc_y != y)) { 473 sc->sc_x = x; 474 sc->sc_y = y; 475 ti_adc_ev_report(sc); 476 } 477#endif 478} 479 480static void 481ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status) 482{ 483 /* Read the available data. */ 484 if (status & ADC_IRQ_FIFO0_THRES) 485 ti_adc_read_data(sc); 486} 487 488static void 489ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status) 490{ 491 /* Read the available data. */ 492 if (status & ADC_IRQ_FIFO1_THRES) 493 ti_adc_tsc_read_data(sc); 494 495} 496 497static void 498ti_adc_intr(void *arg) 499{ 500 struct ti_adc_softc *sc; 501 uint32_t status, rawstatus; 502 503 sc = (struct ti_adc_softc *)arg; 504 505 TI_ADC_LOCK(sc); 506 507 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW); 508 status = ADC_READ4(sc, ADC_IRQSTATUS); 509 510 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) { 511 sc->sc_pen_down = 1; 512 status |= ADC_IRQ_HW_PEN_ASYNC; 513 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 514 ADC_IRQ_HW_PEN_ASYNC); 515#ifdef EVDEV_SUPPORT 516 ti_adc_ev_report(sc); 517#endif 518 } 519 520 if (rawstatus & ADC_IRQ_PEN_UP) { 521 sc->sc_pen_down = 0; 522 status |= ADC_IRQ_PEN_UP; 523#ifdef EVDEV_SUPPORT 524 ti_adc_ev_report(sc); 525#endif 526 } 527 528 if (status & ADC_IRQ_FIFO0_THRES) 529 ti_adc_intr_locked(sc, status); 530 531 if (status & ADC_IRQ_FIFO1_THRES) 532 ti_adc_tsc_intr_locked(sc, status); 533 534 if (status) { 535 /* ACK the interrupt. */ 536 ADC_WRITE4(sc, ADC_IRQSTATUS, status); 537 } 538 539 /* Start the next conversion ? */ 540 if (status & ADC_IRQ_END_OF_SEQ) 541 ti_adc_setup(sc); 542 543 TI_ADC_UNLOCK(sc); 544} 545 546static void 547ti_adc_sysctl_init(struct ti_adc_softc *sc) 548{ 549 char pinbuf[3]; 550 struct sysctl_ctx_list *ctx; 551 struct sysctl_oid *tree_node, *inp_node, *inpN_node; 552 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree; 553 int ain, i; 554 555 /* 556 * Add per-pin sysctl tree/handlers. 557 */ 558 ctx = device_get_sysctl_ctx(sc->sc_dev); 559 tree_node = device_get_sysctl_tree(sc->sc_dev); 560 tree = SYSCTL_CHILDREN(tree_node); 561 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv", 562 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, 0, 563 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler"); 564 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain", 565 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC inputs"); 566 inp_tree = SYSCTL_CHILDREN(inp_node); 567 568 for (i = 0; i < sc->sc_adc_nchannels; i++) { 569 ain = sc->sc_adc_channels[i]; 570 571 snprintf(pinbuf, sizeof(pinbuf), "%d", ain); 572 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf, 573 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ADC input"); 574 inpN_tree = SYSCTL_CHILDREN(inpN_node); 575 576 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable", 577 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 578 &ti_adc_inputs[ain], 0, 579 ti_adc_enable_proc, "IU", "Enable ADC input"); 580 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay", 581 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 582 &ti_adc_inputs[ain], 0, 583 ti_adc_open_delay_proc, "IU", "ADC open delay"); 584 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg", 585 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, 586 &ti_adc_inputs[ain], 0, 587 ti_adc_samples_avg_proc, "IU", "ADC samples average"); 588 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input", 589 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0, 590 "Converted raw value for the ADC input"); 591 } 592} 593 594static void 595ti_adc_inputs_init(struct ti_adc_softc *sc) 596{ 597 int ain, i; 598 struct ti_adc_input *input; 599 600 TI_ADC_LOCK(sc); 601 for (i = 0; i < sc->sc_adc_nchannels; i++) { 602 ain = sc->sc_adc_channels[i]; 603 input = &ti_adc_inputs[ain]; 604 input->sc = sc; 605 input->input = ain; 606 input->value = 0; 607 input->enable = 0; 608 input->samples = 0; 609 ti_adc_input_setup(sc, ain); 610 } 611 TI_ADC_UNLOCK(sc); 612} 613 614static void 615ti_adc_tsc_init(struct ti_adc_softc *sc) 616{ 617 int i, start_step, end_step; 618 uint32_t stepconfig, val; 619 620 TI_ADC_LOCK(sc); 621 622 /* X coordinates */ 623 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 624 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit; 625 if (sc->sc_tsc_wires == 4) 626 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit; 627 else if (sc->sc_tsc_wires == 5) 628 stepconfig |= ADC_STEP_INP(4) | 629 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit; 630 else if (sc->sc_tsc_wires == 8) 631 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit; 632 633 start_step = ADC_STEPS - sc->sc_coord_readouts + 1; 634 end_step = start_step + sc->sc_coord_readouts - 1; 635 for (i = start_step; i <= end_step; i++) { 636 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig); 637 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN); 638 } 639 640 /* Y coordinates */ 641 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 642 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit | 643 ADC_STEP_INM(8); 644 if (sc->sc_tsc_wires == 4) 645 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit; 646 else if (sc->sc_tsc_wires == 5) 647 stepconfig |= ADC_STEP_INP(4) | 648 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit; 649 else if (sc->sc_tsc_wires == 8) 650 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit; 651 652 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1; 653 end_step = start_step + sc->sc_coord_readouts - 1; 654 for (i = start_step; i <= end_step; i++) { 655 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig); 656 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN); 657 } 658 659 /* Charge config */ 660 val = ADC_READ4(sc, ADC_IDLECONFIG); 661 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val); 662 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay); 663 664 /* 2 steps for Z */ 665 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1; 666 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 667 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit | 668 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) | 669 ADC_STEP_INM(8); 670 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig); 671 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN); 672 start_step++; 673 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp); 674 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig); 675 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN); 676 677 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1); 678 679 sc->sc_tsc_enabled = 1; 680 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1; 681 end_step = ADC_STEPS; 682 for (i = start_step; i <= end_step; i++) { 683 sc->sc_tsc_enabled |= (1 << i); 684 } 685 686 TI_ADC_UNLOCK(sc); 687} 688 689static void 690ti_adc_idlestep_init(struct ti_adc_softc *sc) 691{ 692 uint32_t val; 693 694 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW; 695 696 ADC_WRITE4(sc, ADC_IDLECONFIG, val); 697} 698 699static int 700ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs) 701{ 702 int i; 703 int wire, ai; 704 705 for (i = 0; i < nwire_configs; i++) { 706 wire = wire_configs[i] & 0xf; 707 ai = (wire_configs[i] >> 4) & 0xf; 708 switch (wire) { 709 case ORDER_XP: 710 sc->sc_xp_bit = ADC_STEP_XPP_SW; 711 sc->sc_xp_inp = ai; 712 break; 713 case ORDER_XN: 714 sc->sc_xn_bit = ADC_STEP_XNN_SW; 715 sc->sc_xn_inp = ai; 716 break; 717 case ORDER_YP: 718 sc->sc_yp_bit = ADC_STEP_YPP_SW; 719 sc->sc_yp_inp = ai; 720 break; 721 case ORDER_YN: 722 sc->sc_yn_bit = ADC_STEP_YNN_SW; 723 sc->sc_yn_inp = ai; 724 break; 725 default: 726 device_printf(sc->sc_dev, "Invalid wire config\n"); 727 return (-1); 728 } 729 } 730 return (0); 731} 732 733static int 734ti_adc_probe(device_t dev) 735{ 736 737 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc")) 738 return (ENXIO); 739 device_set_desc(dev, "TI ADC controller"); 740 741 return (BUS_PROBE_DEFAULT); 742} 743 744static int 745ti_adc_attach(device_t dev) 746{ 747 int err, rid, i; 748 struct ti_adc_softc *sc; 749 uint32_t rev, reg; 750 phandle_t node, child; 751 pcell_t cell; 752 int *channels; 753 int nwire_configs; 754 int *wire_configs; 755 756 sc = device_get_softc(dev); 757 sc->sc_dev = dev; 758 759 node = ofw_bus_get_node(dev); 760 761 sc->sc_tsc_wires = 0; 762 sc->sc_coord_readouts = 1; 763 sc->sc_x_plate_resistance = 0; 764 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY; 765 /* Read "tsc" node properties */ 766 child = ofw_bus_find_child(node, "tsc"); 767 if (child != 0 && OF_hasprop(child, "ti,wires")) { 768 if ((OF_getencprop(child, "ti,wires", &cell, sizeof(cell))) > 0) 769 sc->sc_tsc_wires = cell; 770 if ((OF_getencprop(child, "ti,coordinate-readouts", &cell, 771 sizeof(cell))) > 0) 772 sc->sc_coord_readouts = cell; 773 if ((OF_getencprop(child, "ti,x-plate-resistance", &cell, 774 sizeof(cell))) > 0) 775 sc->sc_x_plate_resistance = cell; 776 if ((OF_getencprop(child, "ti,charge-delay", &cell, 777 sizeof(cell))) > 0) 778 sc->sc_charge_delay = cell; 779 nwire_configs = OF_getencprop_alloc_multi(child, 780 "ti,wire-config", sizeof(*wire_configs), 781 (void **)&wire_configs); 782 if (nwire_configs != sc->sc_tsc_wires) { 783 device_printf(sc->sc_dev, 784 "invalid number of ti,wire-config: %d (should be %d)\n", 785 nwire_configs, sc->sc_tsc_wires); 786 OF_prop_free(wire_configs); 787 return (EINVAL); 788 } 789 err = ti_adc_config_wires(sc, wire_configs, nwire_configs); 790 OF_prop_free(wire_configs); 791 if (err) 792 return (EINVAL); 793 } 794 795 /* Read "adc" node properties */ 796 child = ofw_bus_find_child(node, "adc"); 797 if (child != 0) { 798 sc->sc_adc_nchannels = OF_getencprop_alloc_multi(child, 799 "ti,adc-channels", sizeof(*channels), (void **)&channels); 800 if (sc->sc_adc_nchannels > 0) { 801 for (i = 0; i < sc->sc_adc_nchannels; i++) 802 sc->sc_adc_channels[i] = channels[i]; 803 OF_prop_free(channels); 804 } 805 } 806 807 /* Sanity check FDT data */ 808 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) { 809 device_printf(dev, "total number of channels (%d) is larger than %d\n", 810 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS); 811 return (ENXIO); 812 } 813 814 rid = 0; 815 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 816 RF_ACTIVE); 817 if (!sc->sc_mem_res) { 818 device_printf(dev, "cannot allocate memory window\n"); 819 return (ENXIO); 820 } 821 822 /* Activate the ADC_TSC module. */ 823 err = ti_sysc_clock_enable(device_get_parent(dev)); 824 if (err) 825 return (err); 826 827 rid = 0; 828 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 829 RF_ACTIVE); 830 if (!sc->sc_irq_res) { 831 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 832 device_printf(dev, "cannot allocate interrupt\n"); 833 return (ENXIO); 834 } 835 836 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 837 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) { 838 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 839 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 840 device_printf(dev, "Unable to setup the irq handler.\n"); 841 return (ENXIO); 842 } 843 844 /* Check the ADC revision. */ 845 rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev))); 846 device_printf(dev, 847 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", 848 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT, 849 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT, 850 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT, 851 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT, 852 rev & ADC_REV_MINOR_MSK, 853 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT); 854 855 reg = ADC_READ4(sc, ADC_CTRL); 856 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID); 857 858 /* 859 * Set the ADC prescaler to 2400 if touchscreen is not enabled 860 * and to 24 if it is. This sets the ADC clock to ~10Khz and 861 * ~1Mhz respectively (CLK_M_OSC / prescaler). 862 */ 863 if (sc->sc_tsc_wires) 864 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1); 865 else 866 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1); 867 868 TI_ADC_LOCK_INIT(sc); 869 870 ti_adc_idlestep_init(sc); 871 ti_adc_inputs_init(sc); 872 ti_adc_sysctl_init(sc); 873 ti_adc_tsc_init(sc); 874 875 TI_ADC_LOCK(sc); 876 ti_adc_setup(sc); 877 TI_ADC_UNLOCK(sc); 878 879#ifdef EVDEV_SUPPORT 880 if (sc->sc_tsc_wires > 0) { 881 sc->sc_evdev = evdev_alloc(); 882 evdev_set_name(sc->sc_evdev, device_get_desc(dev)); 883 evdev_set_phys(sc->sc_evdev, device_get_nameunit(dev)); 884 evdev_set_id(sc->sc_evdev, BUS_VIRTUAL, 0, 0, 0); 885 evdev_support_prop(sc->sc_evdev, INPUT_PROP_DIRECT); 886 evdev_support_event(sc->sc_evdev, EV_SYN); 887 evdev_support_event(sc->sc_evdev, EV_ABS); 888 evdev_support_event(sc->sc_evdev, EV_KEY); 889 890 evdev_support_abs(sc->sc_evdev, ABS_X, 0, 891 ADC_MAX_VALUE, 0, 0, 0); 892 evdev_support_abs(sc->sc_evdev, ABS_Y, 0, 893 ADC_MAX_VALUE, 0, 0, 0); 894 895 evdev_support_key(sc->sc_evdev, BTN_TOUCH); 896 897 err = evdev_register(sc->sc_evdev); 898 if (err) { 899 device_printf(dev, 900 "failed to register evdev: error=%d\n", err); 901 ti_adc_detach(dev); 902 return (err); 903 } 904 905 sc->sc_pen_down = 0; 906 sc->sc_x = -1; 907 sc->sc_y = -1; 908 } 909#endif /* EVDEV */ 910 911 return (0); 912} 913 914static int 915ti_adc_detach(device_t dev) 916{ 917 struct ti_adc_softc *sc; 918 919 sc = device_get_softc(dev); 920 921 /* Turn off the ADC. */ 922 TI_ADC_LOCK(sc); 923 ti_adc_reset(sc); 924 ti_adc_setup(sc); 925 926#ifdef EVDEV_SUPPORT 927 evdev_free(sc->sc_evdev); 928#endif 929 930 TI_ADC_UNLOCK(sc); 931 932 TI_ADC_LOCK_DESTROY(sc); 933 934 if (sc->sc_intrhand) 935 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 936 if (sc->sc_irq_res) 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 938 if (sc->sc_mem_res) 939 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 940 941 return (bus_generic_detach(dev)); 942} 943 944static device_method_t ti_adc_methods[] = { 945 DEVMETHOD(device_probe, ti_adc_probe), 946 DEVMETHOD(device_attach, ti_adc_attach), 947 DEVMETHOD(device_detach, ti_adc_detach), 948 949 DEVMETHOD_END 950}; 951 952static driver_t ti_adc_driver = { 953 "ti_adc", 954 ti_adc_methods, 955 sizeof(struct ti_adc_softc), 956}; 957 958DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, 0, 0); 959MODULE_VERSION(ti_adc, 1); 960MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1); 961MODULE_DEPEND(ti_adc, ti_sysc, 1, 1, 1); 962#ifdef EVDEV_SUPPORT 963MODULE_DEPEND(ti_adc, evdev, 1, 1, 1); 964#endif 965