1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#ifndef _MV_CP110_SYSCON_H_ 29#define _MV_CP110_SYSCON_H_ 30 31enum mv_cp110_clk_id { 32 CP110_PLL_0 = 0, 33 CP110_PPV2_CORE, 34 CP110_X2CORE, 35 CP110_CORE, 36 CP110_NAND, 37 CP110_SDIO, 38 CP110_MAX_CLOCK 39}; 40 41/* Gates */ 42#define CP110_CLOCK_GATING_OFFSET 0x220 43 44struct cp110_gate { 45 const char *name; 46 uint32_t shift; 47}; 48 49#define CCU_GATE(idx, clkname, s) \ 50 [idx] = { \ 51 .name = clkname, \ 52 .shift = s, \ 53 }, 54 55#define CP110_GATE_AUDIO 0 56#define CP110_GATE_COMM_UNIT 1 57#define CP110_GATE_NAND 2 58#define CP110_GATE_PPV2 3 59#define CP110_GATE_SDIO 4 60#define CP110_GATE_MG 5 61#define CP110_GATE_MG_CORE 6 62#define CP110_GATE_XOR1 7 63#define CP110_GATE_XOR0 8 64#define CP110_GATE_GOP_DP 9 65#define CP110_GATE_PCIE_X1_0 11 66#define CP110_GATE_PCIE_X1_1 12 67#define CP110_GATE_PCIE_X4 13 68#define CP110_GATE_PCIE_XOR 14 69#define CP110_GATE_SATA 15 70#define CP110_GATE_SATA_USB 16 71#define CP110_GATE_MAIN 17 72#define CP110_GATE_SDMMC_GOP 18 73#define CP110_GATE_SLOW_IO 21 74#define CP110_GATE_USB3H0 22 75#define CP110_GATE_USB3H1 23 76#define CP110_GATE_USB3DEV 24 77#define CP110_GATE_EIP150 25 78#define CP110_GATE_EIP197 26 79 80#endif 81