1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27/* $NetBSD: cpu.h,v 1.2 2001/02/23 21:23:52 reinoud Exp $ */ 28 29#ifndef MACHINE_CPU_H 30#define MACHINE_CPU_H 31 32#include <machine/armreg.h> 33#include <machine/frame.h> 34 35void cpu_halt(void); 36 37#ifdef _KERNEL 38#include <machine/atomic.h> 39#include <machine/cpufunc.h> 40#include <machine/cpuinfo.h> 41#include <machine/sysreg.h> 42 43/* 44 * Some kernel modules (dtrace all for example) are compiled 45 * unconditionally with -DSMP. Although it looks like a bug, 46 * handle this case here and in #elif condition in ARM_SMP_UP macro. 47 */ 48#if __ARM_ARCH <= 6 && defined(SMP) && !defined(KLD_MODULE) 49#error SMP option is not supported on ARMv6 50#endif 51 52#if __ARM_ARCH <= 6 && defined(SMP_ON_UP) 53#error SMP_ON_UP option is only supported on ARMv7+ CPUs 54#endif 55 56#if !defined(SMP) && defined(SMP_ON_UP) 57#error SMP option must be defined for SMP_ON_UP option 58#endif 59 60#define CPU_ASID_KERNEL 0 61 62#if defined(SMP_ON_UP) 63#define ARM_SMP_UP(smp_code, up_code) \ 64do { \ 65 if (cpuinfo.mp_ext != 0) { \ 66 smp_code; \ 67 } else { \ 68 up_code; \ 69 } \ 70} while (0) 71#elif defined(SMP) && __ARM_ARCH > 6 72#define ARM_SMP_UP(smp_code, up_code) \ 73do { \ 74 smp_code; \ 75} while (0) 76#else 77#define ARM_SMP_UP(smp_code, up_code) \ 78do { \ 79 up_code; \ 80} while (0) 81#endif 82 83void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */ 84vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t); 85vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t); 86 87#ifdef DEV_PMU 88#include <sys/pcpu.h> 89#define PMU_OVSR_C 0x80000000 /* Cycle Counter */ 90extern uint32_t ccnt_hi[MAXCPU]; 91extern int pmu_attched; 92#endif /* DEV_PMU */ 93 94#define sev() __asm __volatile("sev" : : : "memory") 95#define wfe() __asm __volatile("wfe" : : : "memory") 96 97/* 98 * Macros to generate CP15 (system control processor) read/write functions. 99 */ 100#define _FX(s...) #s 101 102#define _RF0(fname, aname...) \ 103static __inline uint32_t \ 104fname(void) \ 105{ \ 106 uint32_t reg; \ 107 __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \ 108 return(reg); \ 109} 110 111#define _R64F0(fname, aname) \ 112static __inline uint64_t \ 113fname(void) \ 114{ \ 115 uint64_t reg; \ 116 __asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \ 117 return(reg); \ 118} 119 120#define _WF0(fname, aname...) \ 121static __inline void \ 122fname(void) \ 123{ \ 124 __asm __volatile("mcr\t" _FX(aname)); \ 125} 126 127#define _WF1(fname, aname...) \ 128static __inline void \ 129fname(uint32_t reg) \ 130{ \ 131 __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \ 132} 133 134#define _W64F1(fname, aname...) \ 135static __inline void \ 136fname(uint64_t reg) \ 137{ \ 138 __asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \ 139} 140 141/* 142 * Raw CP15 maintenance operations 143 * !!! not for external use !!! 144 */ 145 146/* TLB */ 147 148_WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */ 149#if __ARM_ARCH >= 7 && defined(SMP) 150_WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */ 151#endif 152_WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */ 153#if __ARM_ARCH >= 7 && defined(SMP) 154_WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */ 155#endif 156_WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */ 157#if __ARM_ARCH >= 7 && defined(SMP) 158_WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */ 159#endif 160_WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */ 161 162_WF1(_CP15_TTB_SET, CP15_TTBR0(%0)) 163 164/* Cache and Branch predictor */ 165 166_WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */ 167#if __ARM_ARCH >= 7 && defined(SMP) 168_WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */ 169#endif 170_WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */ 171_WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */ 172_WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */ 173_WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */ 174#if __ARM_ARCH >= 7 175_WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */ 176#endif 177_WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */ 178_WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */ 179_WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */ 180_WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */ 181#if __ARM_ARCH >= 7 && defined(SMP) 182_WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */ 183#endif 184_WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */ 185 186/* 187 * Publicly accessible functions 188 */ 189 190/* CP14 Debug Registers */ 191_RF0(cp14_dbgdidr_get, CP14_DBGDIDR(%0)) 192_RF0(cp14_dbgprsr_get, CP14_DBGPRSR(%0)) 193_RF0(cp14_dbgoslsr_get, CP14_DBGOSLSR(%0)) 194_RF0(cp14_dbgosdlr_get, CP14_DBGOSDLR(%0)) 195_RF0(cp14_dbgdscrint_get, CP14_DBGDSCRint(%0)) 196 197_WF1(cp14_dbgdscr_v6_set, CP14_DBGDSCRext_V6(%0)) 198_WF1(cp14_dbgdscr_v7_set, CP14_DBGDSCRext_V7(%0)) 199_WF1(cp14_dbgvcr_set, CP14_DBGVCR(%0)) 200_WF1(cp14_dbgoslar_set, CP14_DBGOSLAR(%0)) 201 202/* Various control registers */ 203 204_RF0(cp15_cpacr_get, CP15_CPACR(%0)) 205_WF1(cp15_cpacr_set, CP15_CPACR(%0)) 206_RF0(cp15_dfsr_get, CP15_DFSR(%0)) 207_RF0(cp15_ifsr_get, CP15_IFSR(%0)) 208_WF1(cp15_prrr_set, CP15_PRRR(%0)) 209_WF1(cp15_nmrr_set, CP15_NMRR(%0)) 210_RF0(cp15_ttbr_get, CP15_TTBR0(%0)) 211_RF0(cp15_dfar_get, CP15_DFAR(%0)) 212#if __ARM_ARCH >= 7 213_RF0(cp15_ifar_get, CP15_IFAR(%0)) 214_RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0)) 215#endif 216_RF0(cp15_actlr_get, CP15_ACTLR(%0)) 217_WF1(cp15_actlr_set, CP15_ACTLR(%0)) 218_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0)) 219_WF1(cp15_ats1cpw_set, CP15_ATS1CPW(%0)) 220_WF1(cp15_ats1cur_set, CP15_ATS1CUR(%0)) 221_WF1(cp15_ats1cuw_set, CP15_ATS1CUW(%0)) 222_RF0(cp15_par_get, CP15_PAR(%0)) 223_RF0(cp15_sctlr_get, CP15_SCTLR(%0)) 224 225/*CPU id registers */ 226_RF0(cp15_midr_get, CP15_MIDR(%0)) 227_RF0(cp15_ctr_get, CP15_CTR(%0)) 228_RF0(cp15_tcmtr_get, CP15_TCMTR(%0)) 229_RF0(cp15_tlbtr_get, CP15_TLBTR(%0)) 230_RF0(cp15_mpidr_get, CP15_MPIDR(%0)) 231_RF0(cp15_revidr_get, CP15_REVIDR(%0)) 232_RF0(cp15_ccsidr_get, CP15_CCSIDR(%0)) 233_RF0(cp15_clidr_get, CP15_CLIDR(%0)) 234_RF0(cp15_aidr_get, CP15_AIDR(%0)) 235_WF1(cp15_csselr_set, CP15_CSSELR(%0)) 236_RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0)) 237_RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0)) 238_RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0)) 239_RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0)) 240_RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0)) 241_RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0)) 242_RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0)) 243_RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0)) 244_RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0)) 245_RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0)) 246_RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0)) 247_RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0)) 248_RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0)) 249_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0)) 250_RF0(cp15_cbar_get, CP15_CBAR(%0)) 251 252/* Performance Monitor registers */ 253 254#if __ARM_ARCH == 6 && defined(CPU_ARM1176) 255_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0)) 256_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0)) 257_RF0(cp15_pmcr_get, CP15_PMCR(%0)) 258_WF1(cp15_pmcr_set, CP15_PMCR(%0)) 259_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) 260_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) 261#elif __ARM_ARCH > 6 262_RF0(cp15_pmcr_get, CP15_PMCR(%0)) 263_WF1(cp15_pmcr_set, CP15_PMCR(%0)) 264_RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0)) 265_WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0)) 266_WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0)) 267_RF0(cp15_pmovsr_get, CP15_PMOVSR(%0)) 268_WF1(cp15_pmovsr_set, CP15_PMOVSR(%0)) 269_WF1(cp15_pmswinc_set, CP15_PMSWINC(%0)) 270_RF0(cp15_pmselr_get, CP15_PMSELR(%0)) 271_WF1(cp15_pmselr_set, CP15_PMSELR(%0)) 272_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) 273_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) 274_RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0)) 275_WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0)) 276_RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0)) 277_WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0)) 278_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0)) 279_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0)) 280_RF0(cp15_pminten_get, CP15_PMINTENSET(%0)) 281_WF1(cp15_pminten_set, CP15_PMINTENSET(%0)) 282_WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0)) 283#endif 284 285_RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0)) 286_WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0)) 287_RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0)) 288_WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0)) 289_RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0)) 290_WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0)) 291 292/* Generic Timer registers - only use when you know the hardware is available */ 293_RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0)) 294_WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0)) 295_RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0)) 296_WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0)) 297_RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0)) 298_WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0)) 299_RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0)) 300_WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0)) 301_RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0)) 302_WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0)) 303_RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0)) 304_WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0)) 305_RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0)) 306_WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0)) 307_RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0)) 308_WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0)) 309_RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0)) 310_WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0)) 311 312_R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0)) 313_R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0)) 314_R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0)) 315_W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0)) 316_R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0)) 317_W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0)) 318_R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0)) 319_W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0)) 320_R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0)) 321_W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0)) 322 323#undef _FX 324#undef _RF0 325#undef _WF0 326#undef _WF1 327 328/* 329 * TLB maintenance operations. 330 */ 331 332/* Local (i.e. not broadcasting ) operations. */ 333 334/* Flush all TLB entries (even global). */ 335static __inline void 336tlb_flush_all_local(void) 337{ 338 339 dsb(); 340 _CP15_TLBIALL(); 341 dsb(); 342} 343 344/* Flush all not global TLB entries. */ 345static __inline void 346tlb_flush_all_ng_local(void) 347{ 348 349 dsb(); 350 _CP15_TLBIASID(CPU_ASID_KERNEL); 351 dsb(); 352} 353 354/* Flush single TLB entry (even global). */ 355static __inline void 356tlb_flush_local(vm_offset_t va) 357{ 358 359 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); 360 361 dsb(); 362 _CP15_TLBIMVA(va | CPU_ASID_KERNEL); 363 dsb(); 364} 365 366/* Flush range of TLB entries (even global). */ 367static __inline void 368tlb_flush_range_local(vm_offset_t va, vm_size_t size) 369{ 370 vm_offset_t eva = va + size; 371 372 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); 373 KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__, 374 size)); 375 376 dsb(); 377 for (; va < eva; va += PAGE_SIZE) 378 _CP15_TLBIMVA(va | CPU_ASID_KERNEL); 379 dsb(); 380} 381 382/* Broadcasting operations. */ 383#if __ARM_ARCH >= 7 && defined(SMP) 384 385static __inline void 386tlb_flush_all(void) 387{ 388 389 dsb(); 390 ARM_SMP_UP( 391 _CP15_TLBIALLIS(), 392 _CP15_TLBIALL() 393 ); 394 dsb(); 395} 396 397static __inline void 398tlb_flush_all_ng(void) 399{ 400 401 dsb(); 402 ARM_SMP_UP( 403 _CP15_TLBIASIDIS(CPU_ASID_KERNEL), 404 _CP15_TLBIASID(CPU_ASID_KERNEL) 405 ); 406 dsb(); 407} 408 409static __inline void 410tlb_flush(vm_offset_t va) 411{ 412 413 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); 414 415 dsb(); 416 ARM_SMP_UP( 417 _CP15_TLBIMVAAIS(va), 418 _CP15_TLBIMVA(va | CPU_ASID_KERNEL) 419 ); 420 dsb(); 421} 422 423static __inline void 424tlb_flush_range(vm_offset_t va, vm_size_t size) 425{ 426 vm_offset_t eva = va + size; 427 428 KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); 429 KASSERT((size & PAGE_MASK) == 0, ("%s: size %#x not aligned", __func__, 430 size)); 431 432 dsb(); 433 ARM_SMP_UP( 434 { 435 for (; va < eva; va += PAGE_SIZE) 436 _CP15_TLBIMVAAIS(va); 437 }, 438 { 439 for (; va < eva; va += PAGE_SIZE) 440 _CP15_TLBIMVA(va | CPU_ASID_KERNEL); 441 } 442 ); 443 dsb(); 444} 445#else /* __ARM_ARCH < 7 */ 446 447#define tlb_flush_all() tlb_flush_all_local() 448#define tlb_flush_all_ng() tlb_flush_all_ng_local() 449#define tlb_flush(va) tlb_flush_local(va) 450#define tlb_flush_range(va, size) tlb_flush_range_local(va, size) 451 452#endif /* __ARM_ARCH < 7 */ 453 454/* 455 * Cache maintenance operations. 456 */ 457 458/* Sync I and D caches to PoU */ 459static __inline void 460icache_sync(vm_offset_t va, vm_size_t size) 461{ 462 vm_offset_t eva = va + size; 463 464 dsb(); 465 va &= ~cpuinfo.dcache_line_mask; 466 467 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 468#if __ARM_ARCH >= 7 469 _CP15_DCCMVAU(va); 470#else 471 _CP15_DCCMVAC(va); 472#endif 473 } 474 dsb(); 475 ARM_SMP_UP( 476 _CP15_ICIALLUIS(), 477 _CP15_ICIALLU() 478 ); 479 dsb(); 480 isb(); 481} 482 483/* Invalidate I cache */ 484static __inline void 485icache_inv_all(void) 486{ 487 488 ARM_SMP_UP( 489 _CP15_ICIALLUIS(), 490 _CP15_ICIALLU() 491 ); 492 dsb(); 493 isb(); 494} 495 496/* Invalidate branch predictor buffer */ 497static __inline void 498bpb_inv_all(void) 499{ 500 501 ARM_SMP_UP( 502 _CP15_BPIALLIS(), 503 _CP15_BPIALL() 504 ); 505 dsb(); 506 isb(); 507} 508 509/* Write back D-cache to PoU */ 510static __inline void 511dcache_wb_pou(vm_offset_t va, vm_size_t size) 512{ 513 vm_offset_t eva = va + size; 514 515 dsb(); 516 va &= ~cpuinfo.dcache_line_mask; 517 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 518#if __ARM_ARCH >= 7 519 _CP15_DCCMVAU(va); 520#else 521 _CP15_DCCMVAC(va); 522#endif 523 } 524 dsb(); 525} 526 527/* 528 * Invalidate D-cache to PoC 529 * 530 * Caches are invalidated from outermost to innermost as fresh cachelines 531 * flow in this direction. In given range, if there was no dirty cacheline 532 * in any cache before, no stale cacheline should remain in them after this 533 * operation finishes. 534 */ 535static __inline void 536dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 537{ 538 vm_offset_t eva = va + size; 539 540 dsb(); 541 /* invalidate L2 first */ 542 cpu_l2cache_inv_range(pa, size); 543 544 /* then L1 */ 545 va &= ~cpuinfo.dcache_line_mask; 546 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 547 _CP15_DCIMVAC(va); 548 } 549 dsb(); 550} 551 552/* 553 * Discard D-cache lines to PoC, prior to overwrite by DMA engine. 554 * 555 * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't 556 * flow into L1 while invalidating. This routine is intended to be used only 557 * when invalidating a buffer before a DMA operation loads new data into memory. 558 * The concern in this case is that dirty lines are not evicted to main memory, 559 * overwriting the DMA data. For that reason, the L1 is done first to ensure 560 * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned. 561 */ 562static __inline void 563dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 564{ 565 vm_offset_t eva = va + size; 566 567 /* invalidate L1 first */ 568 dsb(); 569 va &= ~cpuinfo.dcache_line_mask; 570 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 571 _CP15_DCIMVAC(va); 572 } 573 dsb(); 574 575 /* then L2 */ 576 cpu_l2cache_inv_range(pa, size); 577} 578 579/* 580 * Write back D-cache to PoC 581 * 582 * Caches are written back from innermost to outermost as dirty cachelines 583 * flow in this direction. In given range, no dirty cacheline should remain 584 * in any cache after this operation finishes. 585 */ 586static __inline void 587dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 588{ 589 vm_offset_t eva = va + size; 590 591 dsb(); 592 va &= ~cpuinfo.dcache_line_mask; 593 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 594 _CP15_DCCMVAC(va); 595 } 596 dsb(); 597 598 cpu_l2cache_wb_range(pa, size); 599} 600 601/* Write back and invalidate D-cache to PoC */ 602static __inline void 603dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) 604{ 605 vm_offset_t va; 606 vm_offset_t eva = sva + size; 607 608 dsb(); 609 /* write back L1 first */ 610 va = sva & ~cpuinfo.dcache_line_mask; 611 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 612 _CP15_DCCMVAC(va); 613 } 614 dsb(); 615 616 /* then write back and invalidate L2 */ 617 cpu_l2cache_wbinv_range(pa, size); 618 619 /* then invalidate L1 */ 620 va = sva & ~cpuinfo.dcache_line_mask; 621 for ( ; va < eva; va += cpuinfo.dcache_line_size) { 622 _CP15_DCIMVAC(va); 623 } 624 dsb(); 625} 626 627/* Set TTB0 register */ 628static __inline void 629cp15_ttbr_set(uint32_t reg) 630{ 631 dsb(); 632 _CP15_TTB_SET(reg); 633 dsb(); 634 _CP15_BPIALL(); 635 dsb(); 636 isb(); 637 tlb_flush_all_ng_local(); 638} 639 640/* 641 * Functions for address checking: 642 * 643 * cp15_ats1cpr_check() ... check stage 1 privileged (PL1) read access 644 * cp15_ats1cpw_check() ... check stage 1 privileged (PL1) write access 645 * cp15_ats1cur_check() ... check stage 1 unprivileged (PL0) read access 646 * cp15_ats1cuw_check() ... check stage 1 unprivileged (PL0) write access 647 * 648 * They must be called while interrupts are disabled to get consistent result. 649 */ 650static __inline int 651cp15_ats1cpr_check(vm_offset_t addr) 652{ 653 654 cp15_ats1cpr_set(addr); 655 isb(); 656 return (cp15_par_get() & 0x01 ? EFAULT : 0); 657} 658 659static __inline int 660cp15_ats1cpw_check(vm_offset_t addr) 661{ 662 663 cp15_ats1cpw_set(addr); 664 isb(); 665 return (cp15_par_get() & 0x01 ? EFAULT : 0); 666} 667 668static __inline int 669cp15_ats1cur_check(vm_offset_t addr) 670{ 671 672 cp15_ats1cur_set(addr); 673 isb(); 674 return (cp15_par_get() & 0x01 ? EFAULT : 0); 675} 676 677static __inline int 678cp15_ats1cuw_check(vm_offset_t addr) 679{ 680 681 cp15_ats1cuw_set(addr); 682 isb(); 683 return (cp15_par_get() & 0x01 ? EFAULT : 0); 684} 685 686static __inline uint64_t 687get_cyclecount(void) 688{ 689#if __ARM_ARCH > 6 || (__ARM_ARCH == 6 && defined(CPU_ARM1176)) 690#if (__ARM_ARCH > 6) && defined(DEV_PMU) 691 if (pmu_attched) { 692 u_int cpu; 693 uint64_t h, h2; 694 uint32_t l, r; 695 696 cpu = PCPU_GET(cpuid); 697 h = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]); 698 l = cp15_pmccntr_get(); 699 /* In case interrupts are disabled we need to check for overflow. */ 700 r = cp15_pmovsr_get(); 701 if (r & PMU_OVSR_C) { 702 atomic_add_32(&ccnt_hi[cpu], 1); 703 /* Clear the event. */ 704 cp15_pmovsr_set(PMU_OVSR_C); 705 } 706 /* Make sure there was no wrap-around while we read the lo half. */ 707 h2 = (uint64_t)atomic_load_acq_32(&ccnt_hi[cpu]); 708 if (h != h2) 709 l = cp15_pmccntr_get(); 710 return (h2 << 32 | l); 711 } else 712#endif 713 return cp15_pmccntr_get(); 714#else /* No performance counters, so use nanotime(9). */ 715 struct timespec tv; 716 717 nanotime(&tv); 718 return (tv.tv_sec * (uint64_t)1000000000ull + tv.tv_nsec); 719#endif 720} 721#endif 722 723#define TRAPF_USERMODE(frame) ((frame->tf_spsr & PSR_MODE) == PSR_USR32_MODE) 724 725#define TRAPF_PC(tfp) ((tfp)->tf_pc) 726 727#define cpu_getstack(td) ((td)->td_frame->tf_usr_sp) 728#define cpu_setstack(td, sp) ((td)->td_frame->tf_usr_sp = (sp)) 729#define cpu_spinwait() /* nothing */ 730#define cpu_lock_delay() DELAY(1) 731 732#define ARM_NVEC 8 733#define ARM_VEC_ALL 0xffffffff 734 735extern vm_offset_t vector_page; 736 737/* 738 * Params passed into initarm. If you change the size of this you will 739 * need to update locore.S to allocate more memory on the stack before 740 * it calls initarm. 741 */ 742struct arm_boot_params { 743 register_t abp_size; /* Size of this structure */ 744 register_t abp_r0; /* r0 from the boot loader */ 745 register_t abp_r1; /* r1 from the boot loader */ 746 register_t abp_r2; /* r2 from the boot loader */ 747 register_t abp_r3; /* r3 from the boot loader */ 748 vm_offset_t abp_physaddr; /* The kernel physical address */ 749 vm_offset_t abp_pagetable; /* The early page table */ 750}; 751 752void arm_vector_init(vm_offset_t, int); 753void fork_trampoline(void); 754void identify_arm_cpu(void); 755void *initarm(struct arm_boot_params *); 756 757extern char btext[]; 758extern char etext[]; 759int badaddr_read(void *, size_t, void *); 760#endif /* !MACHINE_CPU_H */ 761