1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2014 Juergen Weiss <weiss@uni-mainz.de>
5 * Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/bus.h>
32#include <sys/kernel.h>
33#include <sys/lock.h>
34#include <sys/mutex.h>
35#include <sys/smp.h>
36
37#include <vm/vm.h>
38#include <vm/pmap.h>
39
40#include <machine/cpu.h>
41#include <machine/smp.h>
42#include <machine/fdt.h>
43#include <machine/intr.h>
44#include <machine/platform.h>
45#include <machine/platformvar.h>
46
47#include <arm/freescale/imx/imx6_machdep.h>
48
49#define	SCU_PHYSBASE			0x00a00000
50#define	SCU_SIZE			0x00001000
51
52#define	SCU_CONTROL_REG			0x00
53#define	  SCU_CONTROL_ENABLE		  (1 << 0)
54#define	SCU_CONFIG_REG			0x04
55#define	  SCU_CONFIG_REG_NCPU_MASK	  0x03
56#define	SCU_CPUPOWER_REG		0x08
57#define	SCU_INV_TAGS_REG		0x0c
58#define	SCU_DIAG_CONTROL		0x30
59#define	  SCU_DIAG_DISABLE_MIGBIT	  (1 << 0)
60#define	SCU_FILTER_START_REG		0x40
61#define	SCU_FILTER_END_REG		0x44
62#define	SCU_SECURE_ACCESS_REG		0x50
63#define	SCU_NONSECURE_ACCESS_REG	0x54
64
65#define	SRC_PHYSBASE			0x020d8000
66#define SRC_SIZE			0x4000
67#define	SRC_CONTROL_REG			0x00
68#define	SRC_CONTROL_C1ENA_SHIFT		  22	/* Bit for Core 1 enable */
69#define	SRC_CONTROL_C1RST_SHIFT		  14	/* Bit for Core 1 reset */
70#define	SRC_GPR0_C1FUNC			0x20	/* Register for Core 1 entry func */
71#define	SRC_GPR1_C1ARG			0x24	/* Register for Core 1 entry arg */
72
73void
74imx6_mp_setmaxid(platform_t plat)
75{
76	bus_space_handle_t scu;
77	int hwcpu, ncpu;
78	uint32_t val;
79
80	/* If we've already set the global vars don't bother to do it again. */
81	if (mp_ncpus != 0)
82		return;
83
84	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
85		panic("Couldn't map the SCU\n");
86	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONFIG_REG);
87	hwcpu = (val & SCU_CONFIG_REG_NCPU_MASK) + 1;
88	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
89
90	ncpu = hwcpu;
91	TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
92	if (ncpu < 1 || ncpu > hwcpu)
93		ncpu = hwcpu;
94
95	mp_ncpus = ncpu;
96	mp_maxid = ncpu - 1;
97}
98
99void
100imx6_mp_start_ap(platform_t plat)
101{
102	bus_space_handle_t scu;
103	bus_space_handle_t src;
104
105	uint32_t val;
106	int i;
107
108	if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
109		panic("Couldn't map the SCU\n");
110	if (bus_space_map(fdtbus_bs_tag, SRC_PHYSBASE, SRC_SIZE, 0, &src) != 0)
111		panic("Couldn't map the system reset controller (SRC)\n");
112
113	/*
114	 * Invalidate SCU cache tags.  The 0x0000ffff constant invalidates all
115	 * ways on all cores 0-3.  Per the ARM docs, it's harmless to write to
116	 * the bits for cores that are not present.
117	 */
118	bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
119
120	/*
121	 * Erratum ARM/MP: 764369 (problems with cache maintenance).
122	 * Setting the "disable-migratory bit" in the undocumented SCU
123	 * Diagnostic Control Register helps work around the problem.
124	 */
125	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
126	bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL,
127	    val | SCU_DIAG_DISABLE_MIGBIT);
128
129	/*
130	 * Enable the SCU, then clean the cache on this core.  After these two
131	 * operations the cache tag ram in the SCU is coherent with the contents
132	 * of the cache on this core.  The other cores aren't running yet so
133	 * their caches can't contain valid data yet, but we've initialized
134	 * their SCU tag ram above, so they will be coherent from startup.
135	 */
136	val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
137	bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
138	    val | SCU_CONTROL_ENABLE);
139	dcache_wbinv_poc_all();
140
141	/*
142	 * For each AP core, set the entry point address and argument registers,
143	 * and set the core-enable and core-reset bits in the control register.
144	 */
145	val = bus_space_read_4(fdtbus_bs_tag, src, SRC_CONTROL_REG);
146	for (i=1; i < mp_ncpus; i++) {
147		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR0_C1FUNC + 8*i,
148		    pmap_kextract((vm_offset_t)mpentry));
149		bus_space_write_4(fdtbus_bs_tag, src, SRC_GPR1_C1ARG  + 8*i, 0);
150
151		val |= ((1 << (SRC_CONTROL_C1ENA_SHIFT - 1 + i )) |
152		    ( 1 << (SRC_CONTROL_C1RST_SHIFT - 1 + i)));
153	}
154	bus_space_write_4(fdtbus_bs_tag, src, SRC_CONTROL_REG, val);
155
156	dsb();
157	sev();
158
159	bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
160	bus_space_unmap(fdtbus_bs_tag, src, SRC_SIZE);
161}
162