1/* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1996 Mark Brinicombe. 7 * Copyright (c) 1996 Brini. 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * RiscBSD kernel project 39 * 40 * db_disasm.c 41 * 42 * Kernel disassembler 43 * 44 * Created : 10/02/96 45 * 46 * Structured after the sparc/sparc/db_disasm.c by David S. Miller & 47 * Paul Kranenburg 48 * 49 * This code is not complete. Not all instructions are disassembled. 50 */ 51 52#include <sys/param.h> 53 54#include <sys/systm.h> 55#include <machine/disassem.h> 56#include <machine/armreg.h> 57#include <ddb/ddb.h> 58 59/* 60 * General instruction format 61 * 62 * insn[cc][mod] [operands] 63 * 64 * Those fields with an uppercase format code indicate that the field 65 * follows directly after the instruction before the separator i.e. 66 * they modify the instruction rather than just being an operand to 67 * the instruction. The only exception is the writeback flag which 68 * follows a operand. 69 * 70 * 71 * 2 - print Operand 2 of a data processing instruction 72 * d - destination register (bits 12-15) 73 * n - n register (bits 16-19) 74 * s - s register (bits 8-11) 75 * o - indirect register rn (bits 16-19) (used by swap) 76 * m - m register (bits 0-3) 77 * a - address operand of ldr/str instruction 78 * l - register list for ldm/stm instruction 79 * f - 1st fp operand (register) (bits 12-14) 80 * g - 2nd fp operand (register) (bits 16-18) 81 * h - 3rd fp operand (register/immediate) (bits 0-4) 82 * b - branch address 83 * t - thumb branch address (bits 24, 0-23) 84 * k - breakpoint comment (bits 0-3, 8-19) 85 * X - block transfer type 86 * Y - block transfer type (r13 base) 87 * c - comment field bits(0-23) 88 * p - saved or current status register 89 * F - PSR transfer fields 90 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN 91 * L - co-processor transfer size 92 * S - set status flag 93 * P - fp precision 94 * Q - fp precision (for ldf/stf) 95 * R - fp rounding 96 * v - co-processor data transfer registers + addressing mode 97 * W - writeback flag 98 * x - instruction in hex 99 * # - co-processor number 100 * y - co-processor data processing registers 101 * z - co-processor register transfer registers 102 */ 103 104struct arm32_insn { 105 u_int mask; 106 u_int pattern; 107 char* name; 108 char* format; 109}; 110 111static const struct arm32_insn arm32_i[] = { 112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ 113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ 114 { 0x0f000000, 0x0f000000, "swi", "c" }, 115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ 116 { 0x0f000000, 0x0a000000, "b", "b" }, 117 { 0x0f000000, 0x0b000000, "bl", "b" }, 118 { 0x0fe000f0, 0x00000090, "mul", "Snms" }, 119 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, 120 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, 121 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, 122 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, 123 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, 124 { 0x0d700000, 0x04200000, "strt", "daW" }, 125 { 0x0d700000, 0x04300000, "ldrt", "daW" }, 126 { 0x0d700000, 0x04600000, "strbt", "daW" }, 127 { 0x0d700000, 0x04700000, "ldrbt", "daW" }, 128 { 0x0c500000, 0x04000000, "str", "daW" }, 129 { 0x0c500000, 0x04100000, "ldr", "daW" }, 130 { 0x0c500000, 0x04400000, "strb", "daW" }, 131 { 0x0c500000, 0x04500000, "ldrb", "daW" }, 132 { 0x0fff0ff0, 0x06bf0fb0, "rev16", "dm" }, 133 { 0xffffffff, 0xf57ff01f, "clrex", "c" }, 134 { 0x0ff00ff0, 0x01800f90, "strex", "dmo" }, 135 { 0x0ff00fff, 0x01900f9f, "ldrex", "do" }, 136 { 0x0ff00ff0, 0x01a00f90, "strexd", "dmo" }, 137 { 0x0ff00fff, 0x01b00f9f, "ldrexd", "do" }, 138 { 0x0ff00ff0, 0x01c00f90, "strexb", "dmo" }, 139 { 0x0ff00fff, 0x01d00f9f, "ldrexb", "do" }, 140 { 0x0ff00ff0, 0x01e00f90, "strexh", "dmo" }, 141 { 0x0ff00fff, 0x01f00f9f, "ldrexh", "do" }, 142 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ 143 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ 144 { 0x0e100000, 0x08000000, "stm", "XnWl" }, 145 { 0x0e100000, 0x08100000, "ldm", "XnWl" }, 146 { 0x0e1000f0, 0x00100090, "ldrb", "de" }, 147 { 0x0e1000f0, 0x00000090, "strb", "de" }, 148 { 0x0e1000f0, 0x001000d0, "ldrsb", "de" }, 149 { 0x0e1000f0, 0x001000b0, "ldrh", "de" }, 150 { 0x0e1000f0, 0x000000b0, "strh", "de" }, 151 { 0x0e1000f0, 0x001000f0, "ldrsh", "de" }, 152 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ 153 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ 154 { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, 155 { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, 156 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ 157 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ 158 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ 159 { 0x0ffffff0, 0x012fff10, "bx", "m" }, 160 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, 161 { 0x0ffffff0, 0x012fff30, "blx", "m" }, 162 { 0xfff000f0, 0xe1200070, "bkpt", "k" }, 163 { 0x0de00000, 0x00000000, "and", "Sdn2" }, 164 { 0x0de00000, 0x00200000, "eor", "Sdn2" }, 165 { 0x0de00000, 0x00400000, "sub", "Sdn2" }, 166 { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, 167 { 0x0de00000, 0x00800000, "add", "Sdn2" }, 168 { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, 169 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, 170 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, 171 { 0x0df00000, 0x01100000, "tst", "Dn2" }, 172 { 0x0df00000, 0x01300000, "teq", "Dn2" }, 173 { 0x0de00000, 0x01400000, "cmp", "Dn2" }, 174 { 0x0de00000, 0x01600000, "cmn", "Dn2" }, 175 { 0x0de00000, 0x01800000, "orr", "Sdn2" }, 176 { 0x0de00000, 0x01a00000, "mov", "Sd2" }, 177 { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, 178 { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, 179 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, 180 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, 181 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, 182 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, 183 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, 184 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, 185 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, 186 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, 187 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, 188 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, 189 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, 190 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, 191 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, 192 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, 193 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, 194 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, 195 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, 196 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, 197 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, 198 { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, 199 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, 200 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, 201 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, 202 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, 203 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, 204 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, 205 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, 206 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, 207 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, 208 { 0x0e100f00, 0x0c000100, "stf", "QLv" }, 209 { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, 210 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, 211 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, 212 { 0x0ff00f10, 0x0e200110, "wfs", "d" }, 213 { 0x0ff00f10, 0x0e300110, "rfs", "d" }, 214 { 0x0ff00f10, 0x0e400110, "wfc", "d" }, 215 { 0x0ff00f10, 0x0e500110, "rfc", "d" }, 216 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, 217 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, 218 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, 219 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, 220 { 0xff100010, 0xfe000010, "mcr2", "#z" }, 221 { 0x0f100010, 0x0e000010, "mcr", "#z" }, 222 { 0xff100010, 0xfe100010, "mrc2", "#z" }, 223 { 0x0f100010, 0x0e100010, "mrc", "#z" }, 224 { 0xff000010, 0xfe000000, "cdp2", "#y" }, 225 { 0x0f000010, 0x0e000000, "cdp", "#y" }, 226 { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, 227 { 0x0e100090, 0x0c100000, "ldc", "L#v" }, 228 { 0xfe100090, 0xfc000000, "stc2", "L#v" }, 229 { 0x0e100090, 0x0c000000, "stc", "L#v" }, 230 { 0x00000000, 0x00000000, NULL, NULL } 231}; 232 233static char const arm32_insn_conditions[][4] = { 234 "eq", "ne", "cs", "cc", 235 "mi", "pl", "vs", "vc", 236 "hi", "ls", "ge", "lt", 237 "gt", "le", "", "nv" 238}; 239 240static char const insn_block_transfers[][4] = { 241 "da", "ia", "db", "ib" 242}; 243 244static char const insn_stack_block_transfers[][4] = { 245 "ed", "ea", "fd", "fa" 246}; 247 248static char const op_shifts[][4] = { 249 "lsl", "lsr", "asr", "ror" 250}; 251 252static char const insn_fpa_rounding[][2] = { 253 "", "p", "m", "z" 254}; 255 256static char const insn_fpa_precision[][2] = { 257 "s", "d", "e", "p" 258}; 259 260static char const insn_fpaconstants[][8] = { 261 "0.0", "1.0", "2.0", "3.0", 262 "4.0", "5.0", "0.5", "10.0" 263}; 264 265#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] 266#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] 267#define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] 268#define op2_shift(x) op_shifts[(x >> 5) & 3] 269#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] 270#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] 271#define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] 272#define insn_fpaimm(x) insn_fpaconstants[x & 0x07] 273 274/* Local prototypes */ 275static void disasm_register_shift(const disasm_interface_t *di, u_int insn); 276static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); 277static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, 278 u_int loc); 279static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, 280 u_int loc); 281static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, 282 u_int loc); 283static u_int disassemble_readword(u_int address); 284static void disassemble_printaddr(u_int address); 285 286vm_offset_t 287disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt) 288{ 289 const struct arm32_insn *i_ptr = arm32_i; 290 291 u_int insn; 292 int matchp; 293 int branch; 294 char* f_ptr; 295 int fmt; 296 297 fmt = 0; 298 matchp = 0; 299 insn = di->di_readword(loc); 300 301/* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ 302 303 while (i_ptr->name) { 304 if ((insn & i_ptr->mask) == i_ptr->pattern) { 305 matchp = 1; 306 break; 307 } 308 i_ptr++; 309 } 310 311 if (!matchp) { 312 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); 313 return(loc + INSN_SIZE); 314 } 315 316 /* If instruction forces condition code, don't print it. */ 317 if ((i_ptr->mask & 0xf0000000) == 0xf0000000) 318 di->di_printf("%s", i_ptr->name); 319 else 320 di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); 321 322 f_ptr = i_ptr->format; 323 324 /* Insert tab if there are no instruction modifiers */ 325 326 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { 327 ++fmt; 328 di->di_printf("\t"); 329 } 330 331 while (*f_ptr) { 332 switch (*f_ptr) { 333 /* 2 - print Operand 2 of a data processing instruction */ 334 case '2': 335 if (insn & 0x02000000) { 336 int rotate= ((insn >> 7) & 0x1e); 337 338 di->di_printf("#0x%08x", 339 (insn & 0xff) << (32 - rotate) | 340 (insn & 0xff) >> rotate); 341 } else { 342 disasm_register_shift(di, insn); 343 } 344 break; 345 /* d - destination register (bits 12-15) */ 346 case 'd': 347 di->di_printf("r%d", ((insn >> 12) & 0x0f)); 348 break; 349 /* D - insert 'p' if Rd is R15 */ 350 case 'D': 351 if (((insn >> 12) & 0x0f) == 15) 352 di->di_printf("p"); 353 break; 354 /* n - n register (bits 16-19) */ 355 case 'n': 356 di->di_printf("r%d", ((insn >> 16) & 0x0f)); 357 break; 358 /* s - s register (bits 8-11) */ 359 case 's': 360 di->di_printf("r%d", ((insn >> 8) & 0x0f)); 361 break; 362 /* o - indirect register rn (bits 16-19) (used by swap) */ 363 case 'o': 364 di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); 365 break; 366 /* m - m register (bits 0-4) */ 367 case 'm': 368 di->di_printf("r%d", ((insn >> 0) & 0x0f)); 369 break; 370 /* a - address operand of ldr/str instruction */ 371 case 'a': 372 disasm_insn_ldrstr(di, insn, loc); 373 break; 374 /* e - address operand of ldrh/strh instruction */ 375 case 'e': 376 disasm_insn_ldrhstrh(di, insn, loc); 377 break; 378 /* l - register list for ldm/stm instruction */ 379 case 'l': 380 disasm_print_reglist(di, insn); 381 break; 382 /* f - 1st fp operand (register) (bits 12-14) */ 383 case 'f': 384 di->di_printf("f%d", (insn >> 12) & 7); 385 break; 386 /* g - 2nd fp operand (register) (bits 16-18) */ 387 case 'g': 388 di->di_printf("f%d", (insn >> 16) & 7); 389 break; 390 /* h - 3rd fp operand (register/immediate) (bits 0-4) */ 391 case 'h': 392 if (insn & (1 << 3)) 393 di->di_printf("#%s", insn_fpaimm(insn)); 394 else 395 di->di_printf("f%d", insn & 7); 396 break; 397 /* b - branch address */ 398 case 'b': 399 branch = ((insn << 2) & 0x03ffffff); 400 if (branch & 0x02000000) 401 branch |= 0xfc000000; 402 di->di_printaddr(loc + 8 + branch); 403 break; 404 /* t - blx address */ 405 case 't': 406 branch = ((insn << 2) & 0x03ffffff) | 407 (insn >> 23 & 0x00000002); 408 if (branch & 0x02000000) 409 branch |= 0xfc000000; 410 di->di_printaddr(loc + 8 + branch); 411 break; 412 /* X - block transfer type */ 413 case 'X': 414 di->di_printf("%s", insn_blktrans(insn)); 415 break; 416 /* Y - block transfer type (r13 base) */ 417 case 'Y': 418 di->di_printf("%s", insn_stkblktrans(insn)); 419 break; 420 /* c - comment field bits(0-23) */ 421 case 'c': 422 di->di_printf("0x%08x", (insn & 0x00ffffff)); 423 break; 424 /* k - breakpoint comment (bits 0-3, 8-19) */ 425 case 'k': 426 di->di_printf("0x%04x", 427 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); 428 break; 429 /* p - saved or current status register */ 430 case 'p': 431 if (insn & 0x00400000) 432 di->di_printf("spsr"); 433 else 434 di->di_printf("cpsr"); 435 break; 436 /* F - PSR transfer fields */ 437 case 'F': 438 di->di_printf("_"); 439 if (insn & (1 << 16)) 440 di->di_printf("c"); 441 if (insn & (1 << 17)) 442 di->di_printf("x"); 443 if (insn & (1 << 18)) 444 di->di_printf("s"); 445 if (insn & (1 << 19)) 446 di->di_printf("f"); 447 break; 448 /* B - byte transfer flag */ 449 case 'B': 450 if (insn & 0x00400000) 451 di->di_printf("b"); 452 break; 453 /* L - co-processor transfer size */ 454 case 'L': 455 if (insn & (1 << 22)) 456 di->di_printf("l"); 457 break; 458 /* S - set status flag */ 459 case 'S': 460 if (insn & 0x00100000) 461 di->di_printf("s"); 462 break; 463 /* P - fp precision */ 464 case 'P': 465 di->di_printf("%s", insn_fpaprec(insn)); 466 break; 467 /* Q - fp precision (for ldf/stf) */ 468 case 'Q': 469 break; 470 /* R - fp rounding */ 471 case 'R': 472 di->di_printf("%s", insn_fparnd(insn)); 473 break; 474 /* W - writeback flag */ 475 case 'W': 476 if (insn & (1 << 21)) 477 di->di_printf("!"); 478 break; 479 /* # - co-processor number */ 480 case '#': 481 di->di_printf("p%d", (insn >> 8) & 0x0f); 482 break; 483 /* v - co-processor data transfer registers+addressing mode */ 484 case 'v': 485 disasm_insn_ldcstc(di, insn, loc); 486 break; 487 /* x - instruction in hex */ 488 case 'x': 489 di->di_printf("0x%08x", insn); 490 break; 491 /* y - co-processor data processing registers */ 492 case 'y': 493 di->di_printf("%d, ", (insn >> 20) & 0x0f); 494 495 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, 496 (insn >> 16) & 0x0f, insn & 0x0f); 497 498 di->di_printf(", %d", (insn >> 5) & 0x07); 499 break; 500 /* z - co-processor register transfer registers */ 501 case 'z': 502 di->di_printf("%d, ", (insn >> 21) & 0x07); 503 di->di_printf("r%d, c%d, c%d, %d", 504 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, 505 insn & 0x0f, (insn >> 5) & 0x07); 506 507/* if (((insn >> 5) & 0x07) != 0) 508 di->di_printf(", %d", (insn >> 5) & 0x07);*/ 509 break; 510 default: 511 di->di_printf("[%c - unknown]", *f_ptr); 512 break; 513 } 514 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') 515 ++f_ptr; 516 else if (*(++f_ptr)) { 517 ++fmt; 518 if (fmt == 1) 519 di->di_printf("\t"); 520 else 521 di->di_printf(", "); 522 } 523 } 524 525 di->di_printf("\n"); 526 527 return(loc + INSN_SIZE); 528} 529 530static void 531disasm_register_shift(const disasm_interface_t *di, u_int insn) 532{ 533 di->di_printf("r%d", (insn & 0x0f)); 534 if ((insn & 0x00000ff0) == 0) 535 ; 536 else if ((insn & 0x00000ff0) == 0x00000060) 537 di->di_printf(", rrx"); 538 else { 539 if (insn & 0x10) 540 di->di_printf(", %s r%d", op2_shift(insn), 541 (insn >> 8) & 0x0f); 542 else 543 di->di_printf(", %s #%d", op2_shift(insn), 544 (insn >> 7) & 0x1f); 545 } 546} 547 548static void 549disasm_print_reglist(const disasm_interface_t *di, u_int insn) 550{ 551 int loop; 552 int start; 553 int comma; 554 555 di->di_printf("{"); 556 start = -1; 557 comma = 0; 558 559 for (loop = 0; loop < 17; ++loop) { 560 if (start != -1) { 561 if (loop == 16 || !(insn & (1 << loop))) { 562 if (comma) 563 di->di_printf(", "); 564 else 565 comma = 1; 566 if (start == loop - 1) 567 di->di_printf("r%d", start); 568 else 569 di->di_printf("r%d-r%d", start, loop - 1); 570 start = -1; 571 } 572 } else { 573 if (insn & (1 << loop)) 574 start = loop; 575 } 576 } 577 di->di_printf("}"); 578 579 if (insn & (1 << 22)) 580 di->di_printf("^"); 581} 582 583static void 584disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) 585{ 586 int offset; 587 588 offset = insn & 0xfff; 589 if ((insn & 0x032f0000) == 0x010f0000) { 590 /* rA = pc, immediate index */ 591 if (insn & 0x00800000) 592 loc += offset; 593 else 594 loc -= offset; 595 di->di_printaddr(loc + 8); 596 } else { 597 di->di_printf("[r%d", (insn >> 16) & 0x0f); 598 if ((insn & 0x03000fff) != 0x01000000) { 599 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 600 if (!(insn & 0x00800000)) 601 di->di_printf("-"); 602 if (insn & (1 << 25)) 603 disasm_register_shift(di, insn); 604 else 605 di->di_printf("#0x%03x", offset); 606 } 607 if (insn & (1 << 24)) 608 di->di_printf("]"); 609 } 610} 611 612static void 613disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) 614{ 615 int offset; 616 617 offset = ((insn & 0xf00) >> 4) | (insn & 0xf); 618 if ((insn & 0x004f0000) == 0x004f0000) { 619 /* rA = pc, immediate index */ 620 if (insn & 0x00800000) 621 loc += offset; 622 else 623 loc -= offset; 624 di->di_printaddr(loc + 8); 625 } else { 626 di->di_printf("[r%d", (insn >> 16) & 0x0f); 627 if ((insn & 0x01400f0f) != 0x01400000) { 628 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 629 if (!(insn & 0x00800000)) 630 di->di_printf("-"); 631 if (insn & (1 << 22)) 632 di->di_printf("#0x%02x", offset); 633 else 634 di->di_printf("r%d", (insn & 0x0f)); 635 } 636 if (insn & (1 << 24)) 637 di->di_printf("]"); 638 } 639} 640 641static void 642disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) 643{ 644 if (((insn >> 8) & 0xf) == 1) 645 di->di_printf("f%d, ", (insn >> 12) & 0x07); 646 else 647 di->di_printf("c%d, ", (insn >> 12) & 0x0f); 648 649 di->di_printf("[r%d", (insn >> 16) & 0x0f); 650 651 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 652 653 if (!(insn & (1 << 23))) 654 di->di_printf("-"); 655 656 di->di_printf("#0x%03x", (insn & 0xff) << 2); 657 658 if (insn & (1 << 24)) 659 di->di_printf("]"); 660 661 if (insn & (1 << 21)) 662 di->di_printf("!"); 663} 664 665static u_int 666disassemble_readword(u_int address) 667{ 668 return(*((u_int *)address)); 669} 670 671static void 672disassemble_printaddr(u_int address) 673{ 674 printf("0x%08x", address); 675} 676 677static const disasm_interface_t disassemble_di = { 678 disassemble_readword, disassemble_printaddr, db_printf 679}; 680 681void 682disassemble(u_int address) 683{ 684 685 (void)disasm(&disassemble_di, address, 0); 686} 687 688/* End of disassem.c */ 689