1/*- 2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31/* 32 * SOCFPGA Reset Manager. 33 * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22) 34 */ 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/malloc.h> 42#include <sys/rman.h> 43#include <sys/timeet.h> 44#include <sys/timetc.h> 45#include <sys/sysctl.h> 46 47#include <dev/ofw/openfirm.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50 51#include <machine/bus.h> 52#include <machine/fdt.h> 53#include <machine/cpu.h> 54#include <machine/intr.h> 55 56#include <arm/altera/socfpga/socfpga_common.h> 57#include <arm/altera/socfpga/socfpga_rstmgr.h> 58#include <arm/altera/socfpga/socfpga_l3regs.h> 59 60struct rstmgr_softc { 61 struct resource *res[1]; 62 bus_space_tag_t bst; 63 bus_space_handle_t bsh; 64 device_t dev; 65}; 66 67struct rstmgr_softc *rstmgr_sc; 68 69static struct resource_spec rstmgr_spec[] = { 70 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 71 { -1, 0 } 72}; 73 74enum { 75 RSTMGR_SYSCTL_FPGA2HPS, 76 RSTMGR_SYSCTL_LWHPS2FPGA, 77 RSTMGR_SYSCTL_HPS2FPGA 78}; 79 80static int 81l3remap(struct rstmgr_softc *sc, int remap, int enable) 82{ 83 uint32_t paddr; 84 bus_addr_t vaddr; 85 phandle_t node; 86 int reg; 87 88 /* 89 * Control whether bridge is visible to L3 masters or not. 90 * Register is write-only. 91 */ 92 93 reg = REMAP_MPUZERO; 94 if (enable) 95 reg |= (remap); 96 else 97 reg &= ~(remap); 98 99 node = OF_finddevice("l3regs"); 100 if (node == -1) { 101 device_printf(sc->dev, "Can't find l3regs node\n"); 102 return (1); 103 } 104 105 if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { 106 if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) { 107 bus_space_write_4(fdtbus_bs_tag, vaddr, 108 L3REGS_REMAP, reg); 109 return (0); 110 } 111 } 112 113 return (1); 114} 115 116static int 117rstmgr_sysctl(SYSCTL_HANDLER_ARGS) 118{ 119 struct rstmgr_softc *sc; 120 int enable; 121 int remap; 122 int err; 123 int reg; 124 int bit; 125 126 sc = arg1; 127 128 switch (arg2) { 129 case RSTMGR_SYSCTL_FPGA2HPS: 130 bit = BRGMODRST_FPGA2HPS; 131 remap = 0; 132 break; 133 case RSTMGR_SYSCTL_LWHPS2FPGA: 134 bit = BRGMODRST_LWHPS2FPGA; 135 remap = REMAP_LWHPS2FPGA; 136 break; 137 case RSTMGR_SYSCTL_HPS2FPGA: 138 bit = BRGMODRST_HPS2FPGA; 139 remap = REMAP_HPS2FPGA; 140 break; 141 default: 142 return (1); 143 } 144 145 reg = READ4(sc, RSTMGR_BRGMODRST); 146 enable = reg & bit ? 0 : 1; 147 148 err = sysctl_handle_int(oidp, &enable, 0, req); 149 if (err || !req->newptr) 150 return (err); 151 152 if (enable == 1) 153 reg &= ~(bit); 154 else if (enable == 0) 155 reg |= (bit); 156 else 157 return (EINVAL); 158 159 WRITE4(sc, RSTMGR_BRGMODRST, reg); 160 l3remap(sc, remap, enable); 161 162 return (0); 163} 164 165int 166rstmgr_warmreset(uint32_t reg) 167{ 168 struct rstmgr_softc *sc; 169 170 sc = rstmgr_sc; 171 if (sc == NULL) 172 return (1); 173 174 /* Request warm reset */ 175 WRITE4(sc, reg, CTRL_SWWARMRSTREQ); 176 177 return (0); 178} 179 180static int 181rstmgr_add_sysctl(struct rstmgr_softc *sc) 182{ 183 struct sysctl_oid_list *children; 184 struct sysctl_ctx_list *ctx; 185 186 ctx = device_get_sysctl_ctx(sc->dev); 187 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 188 189 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps", 190 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 191 sc, RSTMGR_SYSCTL_FPGA2HPS, 192 rstmgr_sysctl, "I", "Enable fpga2hps bridge"); 193 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga", 194 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 195 sc, RSTMGR_SYSCTL_LWHPS2FPGA, 196 rstmgr_sysctl, "I", "Enable lwhps2fpga bridge"); 197 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga", 198 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 199 sc, RSTMGR_SYSCTL_HPS2FPGA, 200 rstmgr_sysctl, "I", "Enable hps2fpga bridge"); 201 202 return (0); 203} 204 205static int 206rstmgr_probe(device_t dev) 207{ 208 209 if (!ofw_bus_status_okay(dev)) 210 return (ENXIO); 211 212 if (!ofw_bus_is_compatible(dev, "altr,rst-mgr")) 213 return (ENXIO); 214 215 device_set_desc(dev, "Reset Manager"); 216 217 return (BUS_PROBE_DEFAULT); 218} 219 220static int 221rstmgr_attach(device_t dev) 222{ 223 struct rstmgr_softc *sc; 224 225 sc = device_get_softc(dev); 226 sc->dev = dev; 227 228 if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) { 229 device_printf(dev, "could not allocate resources\n"); 230 return (ENXIO); 231 } 232 233 /* Memory interface */ 234 sc->bst = rman_get_bustag(sc->res[0]); 235 sc->bsh = rman_get_bushandle(sc->res[0]); 236 237 rstmgr_sc = sc; 238 rstmgr_add_sysctl(sc); 239 240 return (0); 241} 242 243static device_method_t rstmgr_methods[] = { 244 DEVMETHOD(device_probe, rstmgr_probe), 245 DEVMETHOD(device_attach, rstmgr_attach), 246 { 0, 0 } 247}; 248 249static driver_t rstmgr_driver = { 250 "rstmgr", 251 rstmgr_methods, 252 sizeof(struct rstmgr_softc), 253}; 254 255DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, 0, 0); 256