1/*-
2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include "opt_platform.h"
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/devmap.h>
37
38#include <vm/vm.h>
39
40#include <dev/ofw/openfirm.h>
41
42#include <machine/armreg.h>
43#include <machine/bus.h>
44#include <machine/fdt.h>
45#include <machine/machdep.h>
46#include <machine/platform.h>
47#include <machine/platformvar.h>
48
49#include <arm/altera/socfpga/socfpga_mp.h>
50#include <arm/altera/socfpga/socfpga_rstmgr.h>
51
52#include "platform_if.h"
53
54#if defined(SOC_ALTERA_CYCLONE5)
55static int
56socfpga_devmap_init(platform_t plat)
57{
58
59	/* UART */
60	devmap_add_entry(0xffc00000, 0x100000);
61
62	/*
63	 * USB OTG
64	 *
65	 * We use static device map for USB due to some bug in the Altera
66	 * which throws Translation Fault (P) exception on high load.
67	 * It might be caused due to some power save options being turned
68	 * on or something else.
69	 */
70	devmap_add_entry(0xffb00000, 0x100000);
71
72	/* dwmmc */
73	devmap_add_entry(0xff700000, 0x100000);
74
75	/* scu */
76	devmap_add_entry(0xfff00000, 0x100000);
77
78	/* FPGA memory window, 256MB */
79	devmap_add_entry(0xd0000000, 0x10000000);
80
81	return (0);
82}
83#endif
84
85#if defined(SOC_ALTERA_ARRIA10)
86static int
87socfpga_a10_devmap_init(platform_t plat)
88{
89
90	/* UART */
91	devmap_add_entry(0xffc00000, 0x100000);
92
93	/* USB OTG */
94	devmap_add_entry(0xffb00000, 0x100000);
95
96	/* dwmmc */
97	devmap_add_entry(0xff800000, 0x100000);
98
99	/* scu */
100	devmap_add_entry(0xfff00000, 0x100000);
101
102	return (0);
103}
104#endif
105
106static void
107_socfpga_cpu_reset(bus_size_t reg)
108{
109	uint32_t paddr;
110	bus_addr_t vaddr;
111	phandle_t node;
112
113	if (rstmgr_warmreset(reg) == 0)
114		goto end;
115
116	node = OF_finddevice("/soc/rstmgr");
117	if (node == -1)
118		goto end;
119
120	if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
121		if (bus_space_map(fdtbus_bs_tag, paddr, 0x8, 0, &vaddr) == 0) {
122			bus_space_write_4(fdtbus_bs_tag, vaddr,
123			    reg, CTRL_SWWARMRSTREQ);
124		}
125	}
126
127end:
128	while (1);
129}
130
131#if defined(SOC_ALTERA_CYCLONE5)
132static void
133socfpga_cpu_reset(platform_t plat)
134{
135
136	_socfpga_cpu_reset(RSTMGR_CTRL);
137}
138#endif
139
140#if defined(SOC_ALTERA_ARRIA10)
141static void
142socfpga_a10_cpu_reset(platform_t plat)
143{
144
145	_socfpga_cpu_reset(RSTMGR_A10_CTRL);
146}
147#endif
148
149#if defined(SOC_ALTERA_CYCLONE5)
150static platform_method_t socfpga_methods[] = {
151	PLATFORMMETHOD(platform_devmap_init,	socfpga_devmap_init),
152	PLATFORMMETHOD(platform_cpu_reset,	socfpga_cpu_reset),
153#ifdef SMP
154	PLATFORMMETHOD(platform_mp_setmaxid,	socfpga_mp_setmaxid),
155	PLATFORMMETHOD(platform_mp_start_ap,	socfpga_mp_start_ap),
156#endif
157	PLATFORMMETHOD_END,
158};
159FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
160#endif
161
162#if defined(SOC_ALTERA_ARRIA10)
163static platform_method_t socfpga_a10_methods[] = {
164	PLATFORMMETHOD(platform_devmap_init,	socfpga_a10_devmap_init),
165	PLATFORMMETHOD(platform_cpu_reset,	socfpga_a10_cpu_reset),
166#ifdef SMP
167	PLATFORMMETHOD(platform_mp_setmaxid,	socfpga_mp_setmaxid),
168	PLATFORMMETHOD(platform_mp_start_ap,	socfpga_a10_mp_start_ap),
169#endif
170	PLATFORMMETHOD_END,
171};
172FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);
173#endif
174