1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
5 * Copyright (c) 2013 Alexander Fedorov
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/lock.h>
36#include <sys/malloc.h>
37#include <sys/module.h>
38#include <sys/mutex.h>
39#include <sys/resource.h>
40#include <sys/rman.h>
41#include <sys/sysctl.h>
42#include <sys/queue.h>
43#include <sys/taskqueue.h>
44
45#include <machine/bus.h>
46
47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49
50#include <dev/mmc/bridge.h>
51#include <dev/mmc/mmcbrvar.h>
52#include <dev/mmc/mmc_fdt_helpers.h>
53
54#include <arm/allwinner/aw_mmc.h>
55#include <dev/clk/clk.h>
56#include <dev/hwreset/hwreset.h>
57#include <dev/regulator/regulator.h>
58
59#include "opt_mmccam.h"
60
61#ifdef MMCCAM
62#include <cam/cam.h>
63#include <cam/cam_ccb.h>
64#include <cam/cam_debug.h>
65#include <cam/cam_sim.h>
66#include <cam/cam_xpt_sim.h>
67#include <cam/mmc/mmc_sim.h>
68
69#include "mmc_sim_if.h"
70#endif
71
72#include "mmc_pwrseq_if.h"
73
74#define	AW_MMC_MEMRES		0
75#define	AW_MMC_IRQRES		1
76#define	AW_MMC_RESSZ		2
77#define	AW_MMC_DMA_SEGS		(PAGE_SIZE / sizeof(struct aw_mmc_dma_desc))
78#define	AW_MMC_DMA_DESC_SIZE	(sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS)
79#define	AW_MMC_DMA_FTRGLEVEL	0x20070008
80
81#define	AW_MMC_RESET_RETRY	1000
82
83#define	CARD_ID_FREQUENCY	400000
84
85struct aw_mmc_conf {
86	uint32_t	dma_xferlen;
87	bool		mask_data0;
88	bool		can_calibrate;
89	bool		new_timing;
90};
91
92static const struct aw_mmc_conf a10_mmc_conf = {
93	.dma_xferlen = 0x2000,
94};
95
96static const struct aw_mmc_conf a13_mmc_conf = {
97	.dma_xferlen = 0x10000,
98};
99
100static const struct aw_mmc_conf a64_mmc_conf = {
101	.dma_xferlen = 0x10000,
102	.mask_data0 = true,
103	.can_calibrate = true,
104	.new_timing = true,
105};
106
107static const struct aw_mmc_conf a64_emmc_conf = {
108	.dma_xferlen = 0x2000,
109	.can_calibrate = true,
110};
111
112static struct ofw_compat_data compat_data[] = {
113	{"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf},
114	{"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf},
115	{"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf},
116	{"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf},
117	{"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf},
118	{NULL,             0}
119};
120
121struct aw_mmc_softc {
122	device_t		aw_dev;
123	clk_t			aw_clk_ahb;
124	clk_t			aw_clk_mmc;
125	hwreset_t		aw_rst_ahb;
126	int			aw_bus_busy;
127	int			aw_resid;
128	int			aw_timeout;
129	struct callout		aw_timeoutc;
130	struct mmc_host		aw_host;
131	struct mmc_helper	mmc_helper;
132#ifdef MMCCAM
133	union ccb *		ccb;
134	struct mmc_sim		mmc_sim;
135#else
136	struct mmc_request *	aw_req;
137#endif
138	struct mtx		aw_mtx;
139	struct resource *	aw_res[AW_MMC_RESSZ];
140	struct aw_mmc_conf *	aw_mmc_conf;
141	uint32_t		aw_intr;
142	uint32_t		aw_intr_wait;
143	void *			aw_intrhand;
144	unsigned int		aw_clock;
145	device_t		child;
146
147	/* Fields required for DMA access. */
148	bus_addr_t	  	aw_dma_desc_phys;
149	bus_dmamap_t		aw_dma_map;
150	bus_dma_tag_t 		aw_dma_tag;
151	void * 			aw_dma_desc;
152	bus_dmamap_t		aw_dma_buf_map;
153	bus_dma_tag_t		aw_dma_buf_tag;
154	int			aw_dma_map_err;
155};
156
157static struct resource_spec aw_mmc_res_spec[] = {
158	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
159	{ SYS_RES_IRQ,		0,	RF_ACTIVE | RF_SHAREABLE },
160	{ -1,			0,	0 }
161};
162
163static int aw_mmc_probe(device_t);
164static int aw_mmc_attach(device_t);
165static int aw_mmc_detach(device_t);
166static int aw_mmc_setup_dma(struct aw_mmc_softc *);
167static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc);
168static int aw_mmc_reset(struct aw_mmc_softc *);
169static int aw_mmc_init(struct aw_mmc_softc *);
170static void aw_mmc_intr(void *);
171static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
172static void aw_mmc_helper_cd_handler(device_t, bool);
173
174static void aw_mmc_print_error(uint32_t);
175static int aw_mmc_update_ios(device_t, device_t);
176static int aw_mmc_request(device_t, device_t, struct mmc_request *);
177
178#ifndef MMCCAM
179static int aw_mmc_get_ro(device_t, device_t);
180static int aw_mmc_acquire_host(device_t, device_t);
181static int aw_mmc_release_host(device_t, device_t);
182#endif
183
184#define	AW_MMC_LOCK(_sc)	mtx_lock(&(_sc)->aw_mtx)
185#define	AW_MMC_UNLOCK(_sc)	mtx_unlock(&(_sc)->aw_mtx)
186#define	AW_MMC_READ_4(_sc, _reg)					\
187	bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg)
188#define	AW_MMC_WRITE_4(_sc, _reg, _value)				\
189	bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value)
190
191SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
192    "aw_mmc driver");
193
194static int aw_mmc_debug = 0;
195SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0,
196    "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands");
197#define	AW_MMC_DEBUG_CARD	0x1
198#define	AW_MMC_DEBUG_IOS	0x2
199#define	AW_MMC_DEBUG_INT	0x4
200#define	AW_MMC_DEBUG_CMD	0x8
201
202#ifdef MMCCAM
203static int
204aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
205{
206	struct aw_mmc_softc *sc;
207
208	sc = device_get_softc(dev);
209
210	cts->host_ocr = sc->aw_host.host_ocr;
211	cts->host_f_min = sc->aw_host.f_min;
212	cts->host_f_max = sc->aw_host.f_max;
213	cts->host_caps = sc->aw_host.caps;
214	cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen *
215	    AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
216	memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios));
217
218	return (0);
219}
220
221static int
222aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts)
223{
224	struct aw_mmc_softc *sc;
225	struct mmc_ios *ios;
226	struct mmc_ios *new_ios;
227
228	sc = device_get_softc(dev);
229	ios = &sc->aw_host.ios;
230	new_ios = &cts->ios;
231
232	/* Update only requested fields */
233	if (cts->ios_valid & MMC_CLK) {
234		ios->clock = new_ios->clock;
235		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
236			device_printf(sc->aw_dev, "Clock => %d\n", ios->clock);
237	}
238	if (cts->ios_valid & MMC_VDD) {
239		ios->vdd = new_ios->vdd;
240		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
241			device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd);
242	}
243	if (cts->ios_valid & MMC_CS) {
244		ios->chip_select = new_ios->chip_select;
245		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
246			device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select);
247	}
248	if (cts->ios_valid & MMC_BW) {
249		ios->bus_width = new_ios->bus_width;
250		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
251			device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width);
252	}
253	if (cts->ios_valid & MMC_PM) {
254		ios->power_mode = new_ios->power_mode;
255		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
256			device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode);
257	}
258	if (cts->ios_valid & MMC_BT) {
259		ios->timing = new_ios->timing;
260		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
261			device_printf(sc->aw_dev, "Timing => %d\n", ios->timing);
262	}
263	if (cts->ios_valid & MMC_BM) {
264		ios->bus_mode = new_ios->bus_mode;
265		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS))
266			device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode);
267	}
268
269	return (aw_mmc_update_ios(sc->aw_dev, NULL));
270}
271
272static int
273aw_mmc_cam_request(device_t dev, union ccb *ccb)
274{
275	struct aw_mmc_softc *sc;
276	struct ccb_mmcio *mmcio;
277
278	sc = device_get_softc(dev);
279	mmcio = &ccb->mmcio;
280
281	AW_MMC_LOCK(sc);
282
283	if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
284		device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
285			    mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags,
286			    mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0,
287			    mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0);
288	}
289	if (mmcio->cmd.data != NULL) {
290		if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0)
291			panic("data->len = %d, data->flags = %d -- something is b0rked",
292			      (int)mmcio->cmd.data->len, mmcio->cmd.data->flags);
293	}
294	if (sc->ccb != NULL) {
295		device_printf(sc->aw_dev, "Controller still has an active command\n");
296		return (EBUSY);
297	}
298	sc->ccb = ccb;
299	/* aw_mmc_request locks again */
300	AW_MMC_UNLOCK(sc);
301	aw_mmc_request(sc->aw_dev, NULL, NULL);
302
303	return (0);
304}
305
306static void
307aw_mmc_cam_poll(device_t dev)
308{
309	struct aw_mmc_softc *sc;
310
311	sc = device_get_softc(dev);
312	aw_mmc_intr(sc);
313}
314#endif /* MMCCAM */
315
316static void
317aw_mmc_helper_cd_handler(device_t dev, bool present)
318{
319	struct aw_mmc_softc *sc;
320
321	sc = device_get_softc(dev);
322#ifdef MMCCAM
323	mmc_cam_sim_discover(&sc->mmc_sim);
324#else
325	AW_MMC_LOCK(sc);
326	if (present) {
327		if (sc->child == NULL) {
328			if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
329				device_printf(sc->aw_dev, "Card inserted\n");
330
331			sc->child = device_add_child(sc->aw_dev, "mmc", -1);
332			AW_MMC_UNLOCK(sc);
333			if (sc->child) {
334				device_set_ivars(sc->child, sc);
335				(void)device_probe_and_attach(sc->child);
336			}
337		} else
338			AW_MMC_UNLOCK(sc);
339	} else {
340		/* Card isn't present, detach if necessary */
341		if (sc->child != NULL) {
342			if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
343				device_printf(sc->aw_dev, "Card removed\n");
344
345			AW_MMC_UNLOCK(sc);
346			device_delete_child(sc->aw_dev, sc->child);
347			sc->child = NULL;
348		} else
349			AW_MMC_UNLOCK(sc);
350	}
351#endif /* MMCCAM */
352}
353
354static int
355aw_mmc_probe(device_t dev)
356{
357
358	if (!ofw_bus_status_okay(dev))
359		return (ENXIO);
360	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
361		return (ENXIO);
362
363	device_set_desc(dev, "Allwinner Integrated MMC/SD controller");
364
365	return (BUS_PROBE_DEFAULT);
366}
367
368static int
369aw_mmc_attach(device_t dev)
370{
371	struct aw_mmc_softc *sc;
372	struct sysctl_ctx_list *ctx;
373	struct sysctl_oid_list *tree;
374	int error;
375
376	sc = device_get_softc(dev);
377	sc->aw_dev = dev;
378
379	sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
380
381#ifndef MMCCAM
382	sc->aw_req = NULL;
383#endif
384	if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) {
385		device_printf(dev, "cannot allocate device resources\n");
386		return (ENXIO);
387	}
388	if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES],
389	    INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc,
390	    &sc->aw_intrhand)) {
391		bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
392		device_printf(dev, "cannot setup interrupt handler\n");
393		return (ENXIO);
394	}
395	mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc",
396	    MTX_DEF);
397	callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0);
398
399	/* De-assert reset */
400	if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) {
401		error = hwreset_deassert(sc->aw_rst_ahb);
402		if (error != 0) {
403			device_printf(dev, "cannot de-assert reset\n");
404			goto fail;
405		}
406	}
407
408	/* Activate the module clock. */
409	error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb);
410	if (error != 0) {
411		device_printf(dev, "cannot get ahb clock\n");
412		goto fail;
413	}
414	error = clk_enable(sc->aw_clk_ahb);
415	if (error != 0) {
416		device_printf(dev, "cannot enable ahb clock\n");
417		goto fail;
418	}
419	error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc);
420	if (error != 0) {
421		device_printf(dev, "cannot get mmc clock\n");
422		goto fail;
423	}
424	error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY,
425	    CLK_SET_ROUND_DOWN);
426	if (error != 0) {
427		device_printf(dev, "cannot init mmc clock\n");
428		goto fail;
429	}
430	error = clk_enable(sc->aw_clk_mmc);
431	if (error != 0) {
432		device_printf(dev, "cannot enable mmc clock\n");
433		goto fail;
434	}
435
436	sc->aw_timeout = 10;
437	ctx = device_get_sysctl_ctx(dev);
438	tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
439	SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
440	    &sc->aw_timeout, 0, "Request timeout in seconds");
441
442	/* Soft Reset controller. */
443	if (aw_mmc_reset(sc) != 0) {
444		device_printf(dev, "cannot reset the controller\n");
445		goto fail;
446	}
447
448	if (aw_mmc_setup_dma(sc) != 0) {
449		device_printf(sc->aw_dev, "Couldn't setup DMA!\n");
450		goto fail;
451	}
452
453	/* Set some defaults for freq and supported mode */
454	sc->aw_host.f_min = 400000;
455	sc->aw_host.f_max = 52000000;
456	sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
457	sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330;
458	mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host);
459	mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler);
460
461#ifdef MMCCAM
462	sc->ccb = NULL;
463
464	if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) {
465		device_printf(dev, "cannot alloc cam sim\n");
466		goto fail;
467	}
468#endif /* MMCCAM */
469
470	return (0);
471
472fail:
473	callout_drain(&sc->aw_timeoutc);
474	mtx_destroy(&sc->aw_mtx);
475	bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
476	bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
477
478	return (ENXIO);
479}
480
481static int
482aw_mmc_detach(device_t dev)
483{
484	struct aw_mmc_softc *sc;
485	device_t d;
486
487	sc = device_get_softc(dev);
488
489	clk_disable(sc->aw_clk_mmc);
490	clk_disable(sc->aw_clk_ahb);
491	hwreset_assert(sc->aw_rst_ahb);
492
493	mmc_fdt_gpio_teardown(&sc->mmc_helper);
494
495	callout_drain(&sc->aw_timeoutc);
496
497	AW_MMC_LOCK(sc);
498	d = sc->child;
499	sc->child = NULL;
500	AW_MMC_UNLOCK(sc);
501	if (d != NULL)
502		device_delete_child(sc->aw_dev, d);
503
504	aw_mmc_teardown_dma(sc);
505
506	mtx_destroy(&sc->aw_mtx);
507
508	bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand);
509	bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res);
510
511#ifdef MMCCAM
512	mmc_cam_sim_free(&sc->mmc_sim);
513#endif
514
515	return (0);
516}
517
518static void
519aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
520{
521	struct aw_mmc_softc *sc;
522
523	sc = (struct aw_mmc_softc *)arg;
524	if (err) {
525		sc->aw_dma_map_err = err;
526		return;
527	}
528	sc->aw_dma_desc_phys = segs[0].ds_addr;
529}
530
531static int
532aw_mmc_setup_dma(struct aw_mmc_softc *sc)
533{
534	int error;
535
536	/* Allocate the DMA descriptor memory. */
537	error = bus_dma_tag_create(
538	    bus_get_dma_tag(sc->aw_dev),	/* parent */
539	    AW_MMC_DMA_ALIGN, 0,		/* align, boundary */
540	    BUS_SPACE_MAXADDR_32BIT,		/* lowaddr */
541	    BUS_SPACE_MAXADDR,			/* highaddr */
542	    NULL, NULL,				/* filter, filterarg*/
543	    AW_MMC_DMA_DESC_SIZE, 1,		/* maxsize, nsegment */
544	    AW_MMC_DMA_DESC_SIZE,		/* maxsegsize */
545	    0,					/* flags */
546	    NULL, NULL,				/* lock, lockarg*/
547	    &sc->aw_dma_tag);
548	if (error)
549		return (error);
550
551	error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc,
552	    BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
553	    &sc->aw_dma_map);
554	if (error)
555		return (error);
556
557	error = bus_dmamap_load(sc->aw_dma_tag,
558	    sc->aw_dma_map,
559	    sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE,
560	    aw_dma_desc_cb, sc, 0);
561	if (error)
562		return (error);
563	if (sc->aw_dma_map_err)
564		return (sc->aw_dma_map_err);
565
566	/* Create the DMA map for data transfers. */
567	error = bus_dma_tag_create(
568	    bus_get_dma_tag(sc->aw_dev),	/* parent */
569	    AW_MMC_DMA_ALIGN, 0,		/* align, boundary */
570	    BUS_SPACE_MAXADDR_32BIT,		/* lowaddr */
571	    BUS_SPACE_MAXADDR,			/* highaddr */
572	    NULL, NULL,				/* filter, filterarg*/
573	    sc->aw_mmc_conf->dma_xferlen *
574	    AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS,	/* maxsize, nsegments */
575	    sc->aw_mmc_conf->dma_xferlen,	/* maxsegsize */
576	    BUS_DMA_ALLOCNOW,			/* flags */
577	    NULL, NULL,				/* lock, lockarg*/
578	    &sc->aw_dma_buf_tag);
579	if (error)
580		return (error);
581	error = bus_dmamap_create(sc->aw_dma_buf_tag, 0,
582	    &sc->aw_dma_buf_map);
583	if (error)
584		return (error);
585
586	return (0);
587}
588
589static void
590aw_mmc_teardown_dma(struct aw_mmc_softc *sc)
591{
592
593	bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map);
594	bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map);
595	if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0)
596		device_printf(sc->aw_dev, "Cannot destroy the dma tag\n");
597
598	bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
599	bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
600	if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0)
601		device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n");
602}
603
604static void
605aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
606{
607	int i;
608	struct aw_mmc_dma_desc *dma_desc;
609	struct aw_mmc_softc *sc;
610
611	sc = (struct aw_mmc_softc *)arg;
612	sc->aw_dma_map_err = err;
613
614	if (err)
615		return;
616
617	dma_desc = sc->aw_dma_desc;
618	for (i = 0; i < nsegs; i++) {
619		if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen)
620			dma_desc[i].buf_size = 0;		/* Size of 0 indicate max len */
621		else
622			dma_desc[i].buf_size = segs[i].ds_len;
623		dma_desc[i].buf_addr = segs[i].ds_addr;
624		dma_desc[i].config = AW_MMC_DMA_CONFIG_CH |
625			AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC;
626
627		dma_desc[i].next = sc->aw_dma_desc_phys +
628			((i + 1) * sizeof(struct aw_mmc_dma_desc));
629	}
630
631	dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD;
632	dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD |
633		AW_MMC_DMA_CONFIG_ER;
634	dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC;
635	dma_desc[nsegs - 1].next = 0;
636}
637
638static int
639aw_mmc_prepare_dma(struct aw_mmc_softc *sc)
640{
641	bus_dmasync_op_t sync_op;
642	int error;
643	struct mmc_command *cmd;
644	uint32_t val;
645
646#ifdef MMCCAM
647	cmd = &sc->ccb->mmcio.cmd;
648#else
649	cmd = sc->aw_req->cmd;
650#endif
651	if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS))
652		return (EFBIG);
653	error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
654	    cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0);
655	if (error)
656		return (error);
657	if (sc->aw_dma_map_err)
658		return (sc->aw_dma_map_err);
659
660	if (cmd->data->flags & MMC_DATA_WRITE)
661		sync_op = BUS_DMASYNC_PREWRITE;
662	else
663		sync_op = BUS_DMASYNC_PREREAD;
664	bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op);
665	bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE);
666
667	/* Enable DMA */
668	val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
669	val &= ~AW_MMC_GCTL_FIFO_AC_MOD;
670	val |= AW_MMC_GCTL_DMA_ENB;
671	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
672
673	/* Reset DMA */
674	val |= AW_MMC_GCTL_DMA_RST;
675	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val);
676
677	AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST);
678	AW_MMC_WRITE_4(sc, AW_MMC_DMAC,
679	    AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST);
680
681	/* Enable RX or TX DMA interrupt */
682	val = AW_MMC_READ_4(sc, AW_MMC_IDIE);
683	if (cmd->data->flags & MMC_DATA_WRITE)
684		val |= AW_MMC_IDST_TX_INT;
685	else
686		val |= AW_MMC_IDST_RX_INT;
687	AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val);
688
689	/* Set DMA descritptor list address */
690	AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys);
691
692	/* FIFO trigger level */
693	AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL);
694
695	return (0);
696}
697
698static int
699aw_mmc_reset(struct aw_mmc_softc *sc)
700{
701	uint32_t reg;
702	int timeout;
703
704	reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
705	reg |= AW_MMC_GCTL_RESET;
706	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
707	timeout = AW_MMC_RESET_RETRY;
708	while (--timeout > 0) {
709		if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0)
710			break;
711		DELAY(100);
712	}
713	if (timeout == 0)
714		return (ETIMEDOUT);
715
716	return (0);
717}
718
719static int
720aw_mmc_init(struct aw_mmc_softc *sc)
721{
722	uint32_t reg;
723	int ret;
724
725	ret = aw_mmc_reset(sc);
726	if (ret != 0)
727		return (ret);
728
729	/* Set the timeout. */
730	AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
731	    AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
732	    AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
733
734	/* Unmask interrupts. */
735	AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0);
736
737	/* Clear pending interrupts. */
738	AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
739
740	/* Debug register, undocumented */
741	AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb);
742
743	/* Function select register */
744	AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000);
745
746	AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
747
748	/* Enable interrupts and disable AHB access. */
749	reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
750	reg |= AW_MMC_GCTL_INT_ENB;
751	reg &= ~AW_MMC_GCTL_FIFO_AC_MOD;
752	reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS;
753	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
754
755	return (0);
756}
757
758static void
759aw_mmc_req_done(struct aw_mmc_softc *sc)
760{
761	struct mmc_command *cmd;
762#ifdef MMCCAM
763	union ccb *ccb;
764#else
765	struct mmc_request *req;
766#endif
767	uint32_t val, mask;
768	int retry;
769
770#ifdef MMCCAM
771	ccb = sc->ccb;
772	cmd = &ccb->mmcio.cmd;
773#else
774	cmd = sc->aw_req->cmd;
775#endif
776	if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
777		device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error);
778	}
779	if (cmd->error != MMC_ERR_NONE) {
780		/* Reset the FIFO and DMA engines. */
781		mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST;
782		val = AW_MMC_READ_4(sc, AW_MMC_GCTL);
783		AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask);
784
785		retry = AW_MMC_RESET_RETRY;
786		while (--retry > 0) {
787			if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) &
788			    AW_MMC_GCTL_RESET) == 0)
789				break;
790			DELAY(100);
791		}
792		if (retry == 0)
793			device_printf(sc->aw_dev,
794			    "timeout resetting DMA/FIFO\n");
795		aw_mmc_update_clock(sc, 1);
796	}
797
798	if (!dumping)
799		callout_stop(&sc->aw_timeoutc);
800	sc->aw_intr = 0;
801	sc->aw_resid = 0;
802	sc->aw_dma_map_err = 0;
803	sc->aw_intr_wait = 0;
804#ifdef MMCCAM
805	sc->ccb = NULL;
806	ccb->ccb_h.status =
807		(ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR);
808	xpt_done(ccb);
809#else
810	req = sc->aw_req;
811	sc->aw_req = NULL;
812	req->done(req);
813#endif
814}
815
816static void
817aw_mmc_req_ok(struct aw_mmc_softc *sc)
818{
819	int timeout;
820	struct mmc_command *cmd;
821	uint32_t status;
822
823	timeout = 1000;
824	while (--timeout > 0) {
825		status = AW_MMC_READ_4(sc, AW_MMC_STAR);
826		if ((status & AW_MMC_STAR_CARD_BUSY) == 0)
827			break;
828		DELAY(1000);
829	}
830#ifdef MMCCAM
831	cmd = &sc->ccb->mmcio.cmd;
832#else
833	cmd = sc->aw_req->cmd;
834#endif
835	if (timeout == 0) {
836		cmd->error = MMC_ERR_FAILED;
837		aw_mmc_req_done(sc);
838		return;
839	}
840	if (cmd->flags & MMC_RSP_PRESENT) {
841		if (cmd->flags & MMC_RSP_136) {
842			cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3);
843			cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2);
844			cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1);
845			cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
846		} else
847			cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0);
848	}
849	/* All data has been transferred ? */
850	if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len)
851		cmd->error = MMC_ERR_FAILED;
852	aw_mmc_req_done(sc);
853}
854
855static inline void
856set_mmc_error(struct aw_mmc_softc *sc, int error_code)
857{
858#ifdef MMCCAM
859	sc->ccb->mmcio.cmd.error = error_code;
860#else
861	sc->aw_req->cmd->error = error_code;
862#endif
863}
864
865static void
866aw_mmc_timeout(void *arg)
867{
868	struct aw_mmc_softc *sc;
869
870	sc = (struct aw_mmc_softc *)arg;
871#ifdef MMCCAM
872	if (sc->ccb != NULL) {
873#else
874	if (sc->aw_req != NULL) {
875#endif
876		device_printf(sc->aw_dev, "controller timeout\n");
877		set_mmc_error(sc, MMC_ERR_TIMEOUT);
878		aw_mmc_req_done(sc);
879	} else
880		device_printf(sc->aw_dev,
881		    "Spurious timeout - no active request\n");
882}
883
884static void
885aw_mmc_print_error(uint32_t err)
886{
887	if(err & AW_MMC_INT_RESP_ERR)
888		printf("AW_MMC_INT_RESP_ERR ");
889	if (err & AW_MMC_INT_RESP_CRC_ERR)
890		printf("AW_MMC_INT_RESP_CRC_ERR ");
891	if (err & AW_MMC_INT_DATA_CRC_ERR)
892		printf("AW_MMC_INT_DATA_CRC_ERR ");
893	if (err & AW_MMC_INT_RESP_TIMEOUT)
894		printf("AW_MMC_INT_RESP_TIMEOUT ");
895	if (err & AW_MMC_INT_FIFO_RUN_ERR)
896		printf("AW_MMC_INT_FIFO_RUN_ERR ");
897	if (err & AW_MMC_INT_CMD_BUSY)
898		printf("AW_MMC_INT_CMD_BUSY ");
899	if (err & AW_MMC_INT_DATA_START_ERR)
900		printf("AW_MMC_INT_DATA_START_ERR ");
901	if (err & AW_MMC_INT_DATA_END_BIT_ERR)
902		printf("AW_MMC_INT_DATA_END_BIT_ERR");
903	printf("\n");
904}
905
906static void
907aw_mmc_intr(void *arg)
908{
909	bus_dmasync_op_t sync_op;
910	struct aw_mmc_softc *sc;
911	struct mmc_data *data;
912	uint32_t idst, imask, rint;
913
914	sc = (struct aw_mmc_softc *)arg;
915	AW_MMC_LOCK(sc);
916	rint = AW_MMC_READ_4(sc, AW_MMC_RISR);
917	idst = AW_MMC_READ_4(sc, AW_MMC_IDST);
918	imask = AW_MMC_READ_4(sc, AW_MMC_IMKR);
919	if (idst == 0 && imask == 0 && rint == 0) {
920		AW_MMC_UNLOCK(sc);
921		return;
922	}
923	if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
924		device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n",
925		    idst, imask, rint);
926	}
927#ifdef MMCCAM
928	if (sc->ccb == NULL) {
929#else
930	if (sc->aw_req == NULL) {
931#endif
932		device_printf(sc->aw_dev,
933		    "Spurious interrupt - no active request, rint: 0x%08X\n",
934		    rint);
935		aw_mmc_print_error(rint);
936		goto end;
937	}
938	if (rint & AW_MMC_INT_ERR_BIT) {
939		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) {
940			device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint);
941			aw_mmc_print_error(rint);
942		}
943		if (rint & AW_MMC_INT_RESP_TIMEOUT)
944			set_mmc_error(sc, MMC_ERR_TIMEOUT);
945		else
946			set_mmc_error(sc, MMC_ERR_FAILED);
947		aw_mmc_req_done(sc);
948		goto end;
949	}
950	if (idst & AW_MMC_IDST_ERROR) {
951		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT))
952			device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst);
953		set_mmc_error(sc, MMC_ERR_FAILED);
954		aw_mmc_req_done(sc);
955		goto end;
956	}
957
958	sc->aw_intr |= rint;
959#ifdef MMCCAM
960	data = sc->ccb->mmcio.cmd.data;
961#else
962	data = sc->aw_req->cmd->data;
963#endif
964	if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) {
965		if (data->flags & MMC_DATA_WRITE)
966			sync_op = BUS_DMASYNC_POSTWRITE;
967		else
968			sync_op = BUS_DMASYNC_POSTREAD;
969		bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map,
970		    sync_op);
971		bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map,
972		    BUS_DMASYNC_POSTWRITE);
973		bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map);
974		sc->aw_resid = data->len >> 2;
975	}
976	if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait)
977		aw_mmc_req_ok(sc);
978
979end:
980	AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst);
981	AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint);
982	AW_MMC_UNLOCK(sc);
983}
984
985static int
986aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
987{
988	int blksz;
989	struct aw_mmc_softc *sc;
990	struct mmc_command *cmd;
991	uint32_t cmdreg, imask;
992	int err;
993
994	sc = device_get_softc(bus);
995
996	AW_MMC_LOCK(sc);
997#ifdef MMCCAM
998	KASSERT(req == NULL, ("req should be NULL in MMCCAM case!"));
999	/*
1000	 * For MMCCAM, sc->ccb has been NULL-checked and populated
1001	 * by aw_mmc_cam_request() already.
1002	 */
1003	cmd = &sc->ccb->mmcio.cmd;
1004#else
1005	if (sc->aw_req) {
1006		AW_MMC_UNLOCK(sc);
1007		return (EBUSY);
1008	}
1009	sc->aw_req = req;
1010	cmd = req->cmd;
1011
1012	if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) {
1013		device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1014			      cmd->opcode, cmd->arg, cmd->flags,
1015			      cmd->data != NULL ? (unsigned int)cmd->data->len : 0,
1016			      cmd->data != NULL ? cmd->data->flags: 0);
1017	}
1018#endif
1019	cmdreg = AW_MMC_CMDR_LOAD;
1020	imask = AW_MMC_INT_ERR_BIT;
1021	sc->aw_intr_wait = 0;
1022	sc->aw_intr = 0;
1023	sc->aw_resid = 0;
1024	cmd->error = MMC_ERR_NONE;
1025
1026	if (cmd->opcode == MMC_GO_IDLE_STATE)
1027		cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
1028
1029	if (cmd->flags & MMC_RSP_PRESENT)
1030		cmdreg |= AW_MMC_CMDR_RESP_RCV;
1031	if (cmd->flags & MMC_RSP_136)
1032		cmdreg |= AW_MMC_CMDR_LONG_RESP;
1033	if (cmd->flags & MMC_RSP_CRC)
1034		cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
1035
1036	if (cmd->data) {
1037		cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
1038
1039		if (cmd->data->flags & MMC_DATA_MULTI) {
1040			cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
1041			imask |= AW_MMC_INT_AUTO_STOP_DONE;
1042			sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
1043		} else {
1044			sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
1045			imask |= AW_MMC_INT_DATA_OVER;
1046		}
1047		if (cmd->data->flags & MMC_DATA_WRITE)
1048			cmdreg |= AW_MMC_CMDR_DIR_WRITE;
1049#ifdef MMCCAM
1050		if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) {
1051			AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size);
1052			AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1053		} else
1054#endif
1055		{
1056			blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
1057			AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
1058			AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
1059		}
1060	} else {
1061		imask |= AW_MMC_INT_CMD_DONE;
1062	}
1063
1064	/* Enable the interrupts we are interested in */
1065	AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask);
1066	AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1067
1068	/* Enable auto stop if needed */
1069	AW_MMC_WRITE_4(sc, AW_MMC_A12A,
1070	    cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff);
1071
1072	/* Write the command argument */
1073	AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
1074
1075	/*
1076	 * If we don't have data start the request
1077	 * if we do prepare the dma request and start the request
1078	 */
1079	if (cmd->data == NULL) {
1080		AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1081	} else {
1082		err = aw_mmc_prepare_dma(sc);
1083		if (err != 0)
1084			device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
1085
1086		AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
1087	}
1088
1089	if (!dumping) {
1090		callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
1091		    aw_mmc_timeout, sc);
1092	}
1093	AW_MMC_UNLOCK(sc);
1094
1095	return (0);
1096}
1097
1098static int
1099aw_mmc_read_ivar(device_t bus, device_t child, int which,
1100    uintptr_t *result)
1101{
1102	struct aw_mmc_softc *sc;
1103
1104	sc = device_get_softc(bus);
1105	switch (which) {
1106	default:
1107		return (EINVAL);
1108	case MMCBR_IVAR_BUS_MODE:
1109		*(int *)result = sc->aw_host.ios.bus_mode;
1110		break;
1111	case MMCBR_IVAR_BUS_WIDTH:
1112		*(int *)result = sc->aw_host.ios.bus_width;
1113		break;
1114	case MMCBR_IVAR_CHIP_SELECT:
1115		*(int *)result = sc->aw_host.ios.chip_select;
1116		break;
1117	case MMCBR_IVAR_CLOCK:
1118		*(int *)result = sc->aw_host.ios.clock;
1119		break;
1120	case MMCBR_IVAR_F_MIN:
1121		*(int *)result = sc->aw_host.f_min;
1122		break;
1123	case MMCBR_IVAR_F_MAX:
1124		*(int *)result = sc->aw_host.f_max;
1125		break;
1126	case MMCBR_IVAR_HOST_OCR:
1127		*(int *)result = sc->aw_host.host_ocr;
1128		break;
1129	case MMCBR_IVAR_MODE:
1130		*(int *)result = sc->aw_host.mode;
1131		break;
1132	case MMCBR_IVAR_OCR:
1133		*(int *)result = sc->aw_host.ocr;
1134		break;
1135	case MMCBR_IVAR_POWER_MODE:
1136		*(int *)result = sc->aw_host.ios.power_mode;
1137		break;
1138	case MMCBR_IVAR_VDD:
1139		*(int *)result = sc->aw_host.ios.vdd;
1140		break;
1141	case MMCBR_IVAR_VCCQ:
1142		*(int *)result = sc->aw_host.ios.vccq;
1143		break;
1144	case MMCBR_IVAR_CAPS:
1145		*(int *)result = sc->aw_host.caps;
1146		break;
1147	case MMCBR_IVAR_TIMING:
1148		*(int *)result = sc->aw_host.ios.timing;
1149		break;
1150	case MMCBR_IVAR_MAX_DATA:
1151		*(int *)result = (sc->aw_mmc_conf->dma_xferlen *
1152		    AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE;
1153		break;
1154	case MMCBR_IVAR_RETUNE_REQ:
1155		*(int *)result = retune_req_none;
1156		break;
1157	}
1158
1159	return (0);
1160}
1161
1162static int
1163aw_mmc_write_ivar(device_t bus, device_t child, int which,
1164    uintptr_t value)
1165{
1166	struct aw_mmc_softc *sc;
1167
1168	sc = device_get_softc(bus);
1169	switch (which) {
1170	default:
1171		return (EINVAL);
1172	case MMCBR_IVAR_BUS_MODE:
1173		sc->aw_host.ios.bus_mode = value;
1174		break;
1175	case MMCBR_IVAR_BUS_WIDTH:
1176		sc->aw_host.ios.bus_width = value;
1177		break;
1178	case MMCBR_IVAR_CHIP_SELECT:
1179		sc->aw_host.ios.chip_select = value;
1180		break;
1181	case MMCBR_IVAR_CLOCK:
1182		sc->aw_host.ios.clock = value;
1183		break;
1184	case MMCBR_IVAR_MODE:
1185		sc->aw_host.mode = value;
1186		break;
1187	case MMCBR_IVAR_OCR:
1188		sc->aw_host.ocr = value;
1189		break;
1190	case MMCBR_IVAR_POWER_MODE:
1191		sc->aw_host.ios.power_mode = value;
1192		break;
1193	case MMCBR_IVAR_VDD:
1194		sc->aw_host.ios.vdd = value;
1195		break;
1196	case MMCBR_IVAR_VCCQ:
1197		sc->aw_host.ios.vccq = value;
1198		break;
1199	case MMCBR_IVAR_TIMING:
1200		sc->aw_host.ios.timing = value;
1201		break;
1202	/* These are read-only */
1203	case MMCBR_IVAR_CAPS:
1204	case MMCBR_IVAR_HOST_OCR:
1205	case MMCBR_IVAR_F_MIN:
1206	case MMCBR_IVAR_F_MAX:
1207	case MMCBR_IVAR_MAX_DATA:
1208		return (EINVAL);
1209	}
1210
1211	return (0);
1212}
1213
1214static int
1215aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon)
1216{
1217	uint32_t reg;
1218	int retry;
1219
1220	reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1221	reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER |
1222	    AW_MMC_CKCR_MASK_DATA0);
1223
1224	if (clkon)
1225		reg |= AW_MMC_CKCR_ENB;
1226	if (sc->aw_mmc_conf->mask_data0)
1227		reg |= AW_MMC_CKCR_MASK_DATA0;
1228
1229	AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1230
1231	reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK |
1232	    AW_MMC_CMDR_WAIT_PRE_OVER;
1233	AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg);
1234	retry = 0xfffff;
1235
1236	while (reg & AW_MMC_CMDR_LOAD && --retry > 0) {
1237		reg = AW_MMC_READ_4(sc, AW_MMC_CMDR);
1238		DELAY(10);
1239	}
1240	AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
1241
1242	if (reg & AW_MMC_CMDR_LOAD) {
1243		device_printf(sc->aw_dev, "timeout updating clock\n");
1244		return (ETIMEDOUT);
1245	}
1246
1247	if (sc->aw_mmc_conf->mask_data0) {
1248		reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1249		reg &= ~AW_MMC_CKCR_MASK_DATA0;
1250		AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1251	}
1252
1253	return (0);
1254}
1255
1256#ifndef MMCCAM
1257static int
1258aw_mmc_switch_vccq(device_t bus, device_t child)
1259{
1260	struct aw_mmc_softc *sc;
1261	int uvolt, err;
1262
1263	sc = device_get_softc(bus);
1264
1265	if (sc->mmc_helper.vqmmc_supply == NULL)
1266		return EOPNOTSUPP;
1267
1268	switch (sc->aw_host.ios.vccq) {
1269	case vccq_180:
1270		uvolt = 1800000;
1271		break;
1272	case vccq_330:
1273		uvolt = 3300000;
1274		break;
1275	default:
1276		return EINVAL;
1277	}
1278
1279	err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt);
1280	if (err != 0) {
1281		device_printf(sc->aw_dev,
1282		    "Cannot set vqmmc to %d<->%d\n",
1283		    uvolt,
1284		    uvolt);
1285		return (err);
1286	}
1287
1288	return (0);
1289}
1290#endif
1291
1292static int
1293aw_mmc_update_ios(device_t bus, device_t child)
1294{
1295	int error;
1296	struct aw_mmc_softc *sc;
1297	struct mmc_ios *ios;
1298	unsigned int clock;
1299	uint32_t reg, div = 1;
1300	int reg_status;
1301	int rv;
1302
1303	sc = device_get_softc(bus);
1304
1305	ios = &sc->aw_host.ios;
1306
1307	/* Set the bus width. */
1308	switch (ios->bus_width) {
1309	case bus_width_1:
1310		AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1);
1311		break;
1312	case bus_width_4:
1313		AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4);
1314		break;
1315	case bus_width_8:
1316		AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8);
1317		break;
1318	}
1319
1320	switch (ios->power_mode) {
1321	case power_on:
1322		break;
1323	case power_off:
1324		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1325			device_printf(sc->aw_dev, "Powering down sd/mmc\n");
1326
1327		if (sc->mmc_helper.vmmc_supply) {
1328			rv = regulator_status(sc->mmc_helper.vmmc_supply, &reg_status);
1329			if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1330				regulator_disable(sc->mmc_helper.vmmc_supply);
1331		}
1332		if (sc->mmc_helper.vqmmc_supply) {
1333			rv = regulator_status(sc->mmc_helper.vqmmc_supply, &reg_status);
1334			if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED)
1335				regulator_disable(sc->mmc_helper.vqmmc_supply);
1336		}
1337
1338		if (sc->mmc_helper.mmc_pwrseq)
1339			MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, false);
1340
1341		aw_mmc_reset(sc);
1342		break;
1343	case power_up:
1344		if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD))
1345			device_printf(sc->aw_dev, "Powering up sd/mmc\n");
1346
1347		if (sc->mmc_helper.vmmc_supply) {
1348			rv = regulator_status(sc->mmc_helper.vmmc_supply, &reg_status);
1349			if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1350				regulator_enable(sc->mmc_helper.vmmc_supply);
1351		}
1352		if (sc->mmc_helper.vqmmc_supply) {
1353			rv = regulator_status(sc->mmc_helper.vqmmc_supply, &reg_status);
1354			if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED)
1355				regulator_enable(sc->mmc_helper.vqmmc_supply);
1356		}
1357
1358		if (sc->mmc_helper.mmc_pwrseq)
1359			MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, true);
1360		aw_mmc_init(sc);
1361		break;
1362	};
1363
1364	/* Enable ddr mode if needed */
1365	reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
1366	if (ios->timing == bus_timing_uhs_ddr50 ||
1367	  ios->timing == bus_timing_mmc_ddr52)
1368		reg |= AW_MMC_GCTL_DDR_MOD_SEL;
1369	else
1370		reg &= ~AW_MMC_GCTL_DDR_MOD_SEL;
1371	AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg);
1372
1373	if (ios->clock && ios->clock != sc->aw_clock) {
1374		sc->aw_clock = clock = ios->clock;
1375
1376		/* Disable clock */
1377		error = aw_mmc_update_clock(sc, 0);
1378		if (error != 0)
1379			return (error);
1380
1381		if (ios->timing == bus_timing_mmc_ddr52 &&
1382		    (sc->aw_mmc_conf->new_timing ||
1383		    ios->bus_width == bus_width_8)) {
1384			div = 2;
1385			clock <<= 1;
1386		}
1387
1388		/* Reset the divider. */
1389		reg = AW_MMC_READ_4(sc, AW_MMC_CKCR);
1390		reg &= ~AW_MMC_CKCR_DIV;
1391		reg |= div - 1;
1392		AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg);
1393
1394		/* New timing mode if needed */
1395		if (sc->aw_mmc_conf->new_timing) {
1396			reg = AW_MMC_READ_4(sc, AW_MMC_NTSR);
1397			reg |= AW_MMC_NTSR_MODE_SELECT;
1398			AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg);
1399		}
1400
1401		/* Set the MMC clock. */
1402		error = clk_disable(sc->aw_clk_mmc);
1403		if (error != 0 && bootverbose)
1404			device_printf(sc->aw_dev,
1405			  "failed to disable mmc clock: %d\n", error);
1406		error = clk_set_freq(sc->aw_clk_mmc, clock,
1407		    CLK_SET_ROUND_DOWN);
1408		if (error != 0) {
1409			device_printf(sc->aw_dev,
1410			    "failed to set frequency to %u Hz: %d\n",
1411			    clock, error);
1412			return (error);
1413		}
1414		error = clk_enable(sc->aw_clk_mmc);
1415		if (error != 0 && bootverbose)
1416			device_printf(sc->aw_dev,
1417			  "failed to re-enable mmc clock: %d\n", error);
1418
1419		if (sc->aw_mmc_conf->can_calibrate)
1420			AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN);
1421
1422		/* Enable clock. */
1423		error = aw_mmc_update_clock(sc, 1);
1424		if (error != 0)
1425			return (error);
1426	}
1427
1428	return (0);
1429}
1430
1431#ifndef MMCCAM
1432static int
1433aw_mmc_get_ro(device_t bus, device_t child)
1434{
1435	struct aw_mmc_softc *sc;
1436
1437	sc = device_get_softc(bus);
1438
1439	return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper));
1440}
1441
1442static int
1443aw_mmc_acquire_host(device_t bus, device_t child)
1444{
1445	struct aw_mmc_softc *sc;
1446	int error;
1447
1448	sc = device_get_softc(bus);
1449	AW_MMC_LOCK(sc);
1450	while (sc->aw_bus_busy) {
1451		error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0);
1452		if (error != 0) {
1453			AW_MMC_UNLOCK(sc);
1454			return (error);
1455		}
1456	}
1457	sc->aw_bus_busy++;
1458	AW_MMC_UNLOCK(sc);
1459
1460	return (0);
1461}
1462
1463static int
1464aw_mmc_release_host(device_t bus, device_t child)
1465{
1466	struct aw_mmc_softc *sc;
1467
1468	sc = device_get_softc(bus);
1469	AW_MMC_LOCK(sc);
1470	sc->aw_bus_busy--;
1471	wakeup(sc);
1472	AW_MMC_UNLOCK(sc);
1473
1474	return (0);
1475}
1476#endif
1477
1478static device_method_t aw_mmc_methods[] = {
1479	/* Device interface */
1480	DEVMETHOD(device_probe,		aw_mmc_probe),
1481	DEVMETHOD(device_attach,	aw_mmc_attach),
1482	DEVMETHOD(device_detach,	aw_mmc_detach),
1483
1484	/* Bus interface */
1485	DEVMETHOD(bus_read_ivar,	aw_mmc_read_ivar),
1486	DEVMETHOD(bus_write_ivar,	aw_mmc_write_ivar),
1487	DEVMETHOD(bus_add_child,        bus_generic_add_child),
1488
1489#ifndef MMCCAM
1490	/* MMC bridge interface */
1491	DEVMETHOD(mmcbr_update_ios,	aw_mmc_update_ios),
1492	DEVMETHOD(mmcbr_request,	aw_mmc_request),
1493	DEVMETHOD(mmcbr_get_ro,		aw_mmc_get_ro),
1494	DEVMETHOD(mmcbr_switch_vccq,	aw_mmc_switch_vccq),
1495	DEVMETHOD(mmcbr_acquire_host,	aw_mmc_acquire_host),
1496	DEVMETHOD(mmcbr_release_host,	aw_mmc_release_host),
1497#endif
1498
1499#ifdef MMCCAM
1500	/* MMCCAM interface */
1501	DEVMETHOD(mmc_sim_get_tran_settings,	aw_mmc_get_tran_settings),
1502	DEVMETHOD(mmc_sim_set_tran_settings,	aw_mmc_set_tran_settings),
1503	DEVMETHOD(mmc_sim_cam_request,		aw_mmc_cam_request),
1504	DEVMETHOD(mmc_sim_cam_poll,		aw_mmc_cam_poll),
1505#endif
1506
1507	DEVMETHOD_END
1508};
1509
1510static driver_t aw_mmc_driver = {
1511	"aw_mmc",
1512	aw_mmc_methods,
1513	sizeof(struct aw_mmc_softc),
1514};
1515
1516DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, NULL, NULL);
1517#ifndef MMCCAM
1518MMC_DECLARE_BRIDGE(aw_mmc);
1519#endif
1520SIMPLEBUS_PNP_INFO(compat_data);
1521